Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	456	1			T2	2		T7	1		T9	6
auto[ReadAddrCrossIntoMailbox]	308	1			T2	2		T7	1		T9	2
auto[ReadAddrCrossOutOfMailbox]	353	1			T2	3		T37	3		T38	3
auto[ReadAddrCrossAllMailbox]	240	1			T7	1		T37	4		T47	1
auto[ReadAddrOutsideMailbox]	4074	1			T2	34		T3	6		T7	17

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2683

1

T2

23

T3

3

T7

9

auto[1]

2748

1

T2

18

T3

3

T7

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	916	1			T2	7		T7	4		T9	6
read_ops[0x0b]	912	1			T2	7		T3	2		T7	2
read_ops[0x3b]	896	1			T2	4		T7	3		T45	1
read_ops[0x6b]	933	1			T2	9		T3	4		T7	4
read_ops[0xbb]	873	1			T2	9		T7	3		T9	2
read_ops[0xeb]	901	1			T2	5		T7	4		T9	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T9	3		T48	1		T202	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T9	3		T37	1		T38	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T2	1		T38	1		T210	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T37	1		T38	1		T50	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T38	1		T48	1		T50	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T37	1		T38	1		T15	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T37	1		T50	1		T75	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T209	1		T204	1		T188	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	331	1			T2	6		T7	4		T46	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	355	1			T46	1		T37	1		T38	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T38	1		T48	1		T17	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T170	1		T195	2		T212	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T195	2		T203	1		T160	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T2	1		T50	1		T51	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T50	3		T216	2		T205	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T15	1		T50	1		T51	3
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T48	2		T216	1		T213	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T37	1		T15	1		T212	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	351	1			T2	2		T3	1		T46	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	339	1			T2	4		T3	1		T7	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	47	1			T38	1		T48	1		T15	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T211	1		T195	1		T216	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T38	1		T193	1		T160	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T37	1		T38	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T48	1		T17	1		T50	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T37	1		T17	1		T195	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T203	1		T222	1		T256	3
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T48	1		T212	1		T216	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	327	1			T7	1		T46	2		T37	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T2	4		T7	2		T45	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T38	1		T170	1		T219	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T2	1		T51	1		T216	3
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T38	1		T170	1		T201	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T7	1		T37	2		T38	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T17	2		T170	2		T257	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T48	1		T17	2		T160	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T49	1		T209	1		T205	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T37	1		T48	1		T209	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	380	1			T2	4		T3	2		T7	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	345	1			T2	4		T3	2		T7	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T2	1		T38	1		T193	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T48	1		T17	1		T195	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	30	1			T9	1		T50	1		T219	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	37	1			T9	1		T37	2		T38	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T2	3		T50	1		T212	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T37	1		T48	1		T75	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T222	1		T213	1		T258	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T37	1		T50	1		T202	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	338	1			T2	4		T7	2		T13	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	312	1			T2	1		T7	1		T13	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T90	1		T17	1		T212	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T7	1		T38	2		T90	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T37	1		T38	1		T47	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T37	1		T51	1		T197	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T38	1		T48	1		T15	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T50	1		T51	3		T203	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T47	1		T48	1		T17	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T7	1		T17	1		T50	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	309	1			T2	2		T9	1		T43	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	354	1			T2	3		T7	2		T9	1