Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3891	1			T2	20		T6	2		T45	20
values[1]	4723	1			T2	60		T94	20		T37	20
values[2]	4741	1			T2	20		T232	14		T45	52
values[3]	4442	1			T2	60		T37	40		T38	69
values[4]	4724	1			T2	20		T37	40		T38	82
values[5]	4195	1			T2	20		T7	22		T14	16
values[6]	4490	1			T3	10		T7	22		T11	30
values[7]	3857	1			T2	40		T7	42		T9	14

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3810	1			T2	60		T7	22		T37	20
values[1]	4598	1			T2	20		T7	20		T13	20
values[2]	4002	1			T7	22		T11	30		T38	20
values[3]	4411	1			T2	20		T3	10		T89	10
values[4]	4665	1			T2	40		T9	14		T45	20
values[5]	3973	1			T2	60		T7	22		T94	20
values[6]	4750	1			T43	10		T37	20		T53	59
values[7]	4854	1			T2	40		T6	2		T14	16

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34234

1

T2

231

T3

10

T6

2

auto[1]

829

1

T2

9

T7

3

T94

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	426	1			T236	4		T48	80		T51	20
auto[0]	values[0]	values[1]	465	1			T15	20		T50	54		T51	20
auto[0]	values[0]	values[2]	558	1			T51	20		T79	4		T216	18
auto[0]	values[0]	values[3]	500	1			T37	20		T185	19		T225	20
auto[0]	values[0]	values[4]	474	1			T45	20		T81	18		T209	20
auto[0]	values[0]	values[5]	622	1			T204	37		T216	17		T160	71
auto[0]	values[0]	values[6]	415	1			T51	20		T193	27		T198	21
auto[0]	values[0]	values[7]	334	1			T2	18		T6	2		T38	20
auto[0]	values[1]	values[0]	334	1			T50	65		T238	6		T174	20
auto[0]	values[1]	values[1]	712	1			T2	19		T242	2		T231	22
auto[0]	values[1]	values[2]	582	1			T49	20		T259	4		T174	20
auto[0]	values[1]	values[3]	303	1			T254	16		T251	20		T205	66
auto[0]	values[1]	values[4]	455	1			T51	16		T174	31		T170	19
auto[0]	values[1]	values[5]	616	1			T2	40		T94	19		T37	20
auto[0]	values[1]	values[6]	586	1			T53	59		T15	23		T202	22
auto[0]	values[1]	values[7]	1028	1			T48	36		T193	75		T211	29
auto[0]	values[2]	values[0]	458	1			T2	20		T37	20		T38	57
auto[0]	values[2]	values[1]	684	1			T45	52		T17	41		T51	20
auto[0]	values[2]	values[2]	552	1			T47	22		T202	31		T195	63
auto[0]	values[2]	values[3]	453	1			T49	20		T90	6		T51	19
auto[0]	values[2]	values[4]	772	1			T170	38		T260	20		T261	4
auto[0]	values[2]	values[5]	412	1			T38	19		T48	20		T197	22
auto[0]	values[2]	values[6]	731	1			T51	19		T174	29		T245	6
auto[0]	values[2]	values[7]	566	1			T232	14		T49	20		T209	23
auto[0]	values[3]	values[0]	400	1			T44	10		T17	76		T262	20
auto[0]	values[3]	values[1]	674	1			T37	20		T174	32		T170	68
auto[0]	values[3]	values[2]	507	1			T38	20		T50	56		T221	20
auto[0]	values[3]	values[3]	655	1			T105	26		T170	20		T219	20
auto[0]	values[3]	values[4]	624	1			T2	39		T37	19		T17	93
auto[0]	values[3]	values[5]	515	1			T49	19		T17	24		T174	19
auto[0]	values[3]	values[6]	481	1			T38	47		T50	19		T170	29
auto[0]	values[3]	values[7]	487	1			T2	17		T50	19		T197	37
auto[0]	values[4]	values[0]	693	1			T2	20		T49	20		T209	40
auto[0]	values[4]	values[1]	719	1			T38	56		T170	19		T248	6
auto[0]	values[4]	values[2]	364	1			T17	23		T205	25		T263	12
auto[0]	values[4]	values[3]	540	1			T51	18		T212	25		T203	33
auto[0]	values[4]	values[4]	635	1			T37	20		T96	12		T203	20
auto[0]	values[4]	values[5]	461	1			T38	23		T48	31		T213	35
auto[0]	values[4]	values[6]	310	1			T264	6		T265	12		T266	20
auto[0]	values[4]	values[7]	869	1			T37	18		T80	8		T202	20
auto[0]	values[5]	values[0]	426	1			T7	20		T38	25		T211	45
auto[0]	values[5]	values[1]	423	1			T48	37		T15	35		T209	27
auto[0]	values[5]	values[2]	216	1			T209	21		T195	19		T216	20
auto[0]	values[5]	values[3]	591	1			T2	20		T120	6		T15	20
auto[0]	values[5]	values[4]	639	1			T50	36		T216	57		T225	42
auto[0]	values[5]	values[5]	384	1			T37	19		T15	20		T193	20
auto[0]	values[5]	values[6]	988	1			T38	119		T48	46		T170	20
auto[0]	values[5]	values[7]	452	1			T14	16		T50	20		T51	20
auto[0]	values[6]	values[0]	474	1			T51	20		T210	20		T203	156
auto[0]	values[6]	values[1]	401	1			T13	20		T243	4		T91	4
auto[0]	values[6]	values[2]	756	1			T11	30		T15	40		T267	2
auto[0]	values[6]	values[3]	783	1			T3	10		T89	10		T38	20
auto[0]	values[6]	values[4]	530	1			T38	29		T49	19		T50	58
auto[0]	values[6]	values[5]	397	1			T7	22		T95	16		T201	19
auto[0]	values[6]	values[6]	621	1			T209	20		T212	20		T203	164
auto[0]	values[6]	values[7]	424	1			T38	20		T48	24		T75	34
auto[0]	values[7]	values[0]	501	1			T2	18		T47	20		T206	8
auto[0]	values[7]	values[1]	412	1			T7	20		T193	19		T219	19
auto[0]	values[7]	values[2]	370	1			T7	21		T17	20		T193	40
auto[0]	values[7]	values[3]	474	1			T46	14		T48	85		T209	24
auto[0]	values[7]	values[4]	427	1			T9	14		T187	4		T50	24
auto[0]	values[7]	values[5]	478	1			T2	20		T225	47		T186	20
auto[0]	values[7]	values[6]	517	1			T43	10		T37	20		T106	8
auto[0]	values[7]	values[7]	578	1			T51	20		T193	23		T233	10
auto[1]	values[0]	values[0]	10	1			T170	2		T212	4		T250	2
auto[1]	values[0]	values[1]	16	1			T50	3		T185	3		T268	2
auto[1]	values[0]	values[2]	14	1			T216	2		T198	3		T234	2
auto[1]	values[0]	values[3]	14	1			T185	1		T205	2		T191	1
auto[1]	values[0]	values[4]	12	1			T201	1		T186	1		T269	2
auto[1]	values[0]	values[5]	10	1			T216	3		T144	1		T270	3
auto[1]	values[0]	values[6]	17	1			T193	1		T266	4		T271	1
auto[1]	values[0]	values[7]	4	1			T2	2		T163	2		-	-
auto[1]	values[1]	values[0]	12	1			T50	2		T186	1		T272	4
auto[1]	values[1]	values[1]	15	1			T2	1		T252	1		T273	4
auto[1]	values[1]	values[2]	12	1			T170	2		T257	1		T198	1
auto[1]	values[1]	values[3]	10	1			T254	2		T251	1		T205	3
auto[1]	values[1]	values[4]	13	1			T51	4		T174	1		T170	1
auto[1]	values[1]	values[5]	6	1			T94	1		T274	1		T145	1
auto[1]	values[1]	values[6]	15	1			T202	1		T251	2		T163	6
auto[1]	values[1]	values[7]	24	1			T193	4		T211	1		T205	8
auto[1]	values[2]	values[0]	9	1			T50	3		T257	2		T226	2
auto[1]	values[2]	values[1]	16	1			T216	2		T54	5		T194	2
auto[1]	values[2]	values[2]	17	1			T47	2		T202	2		T195	1
auto[1]	values[2]	values[3]	16	1			T51	1		T195	1		T216	3
auto[1]	values[2]	values[4]	17	1			T67	4		T275	2		T250	1
auto[1]	values[2]	values[5]	9	1			T38	1		T54	4		T276	1
auto[1]	values[2]	values[6]	14	1			T51	1		T277	1		T234	2
auto[1]	values[2]	values[7]	15	1			T190	4		T191	2		T270	1
auto[1]	values[3]	values[0]	12	1			T278	3		T218	2		T279	3
auto[1]	values[3]	values[1]	4	1			T170	1		T160	2		T280	1
auto[1]	values[3]	values[2]	15	1			T50	1		T221	2		T249	1
auto[1]	values[3]	values[3]	13	1			T219	4		T216	1		T188	2
auto[1]	values[3]	values[4]	22	1			T2	1		T37	1		T17	3
auto[1]	values[3]	values[5]	14	1			T49	1		T17	1		T174	1
auto[1]	values[3]	values[6]	10	1			T38	2		T50	1		T170	1
auto[1]	values[3]	values[7]	9	1			T2	3		T50	1		T197	1
auto[1]	values[4]	values[0]	12	1			T209	1		T216	3		T213	1
auto[1]	values[4]	values[1]	22	1			T38	2		T170	1		T203	2
auto[1]	values[4]	values[2]	7	1			T205	1		T277	1		T271	1
auto[1]	values[4]	values[3]	21	1			T51	2		T212	2		T203	2
auto[1]	values[4]	values[4]	6	1			T274	1		T281	2		T282	3
auto[1]	values[4]	values[5]	17	1			T38	1		T48	4		T213	5
auto[1]	values[4]	values[6]	9	1			T283	1		T284	1		T285	1
auto[1]	values[4]	values[7]	39	1			T37	2		T211	2		T194	3
auto[1]	values[5]	values[0]	12	1			T7	2		T38	2		T211	1
auto[1]	values[5]	values[1]	12	1			T48	1		T186	2		T244	1
auto[1]	values[5]	values[2]	6	1			T195	1		T191	3		T286	2
auto[1]	values[5]	values[3]	13	1			T185	1		T226	3		T144	3
auto[1]	values[5]	values[4]	13	1			T50	1		T191	1		T278	1
auto[1]	values[5]	values[5]	4	1			T37	1		T235	1		T67	1
auto[1]	values[5]	values[6]	12	1			T38	1		T234	2		T252	1
auto[1]	values[5]	values[7]	4	1			T216	1		T287	1		T288	1
auto[1]	values[6]	values[0]	14	1			T203	3		T234	4		T289	1
auto[1]	values[6]	values[1]	10	1			T197	4		T218	2		T290	1
auto[1]	values[6]	values[2]	22	1			T234	3		T252	1		T218	4
auto[1]	values[6]	values[3]	13	1			T185	4		T186	2		T198	1
auto[1]	values[6]	values[4]	17	1			T49	1		T50	4		T291	2
auto[1]	values[6]	values[5]	10	1			T201	1		T216	1		T67	1
auto[1]	values[6]	values[6]	7	1			T203	3		T191	1		T292	1
auto[1]	values[6]	values[7]	11	1			T54	1		T198	2		T293	2
auto[1]	values[7]	values[0]	17	1			T2	2		T47	1		T203	2
auto[1]	values[7]	values[1]	13	1			T193	1		T219	1		T185	1
auto[1]	values[7]	values[2]	4	1			T7	1		T202	1		T275	1
auto[1]	values[7]	values[3]	12	1			T48	1		T209	2		T203	1
auto[1]	values[7]	values[4]	9	1			T50	1		T294	1		T295	2
auto[1]	values[7]	values[5]	18	1			T189	4		T292	3		T250	1
auto[1]	values[7]	values[6]	17	1			T17	1		T197	2		T67	2
auto[1]	values[7]	values[7]	10	1			T193	5		T277	2		T296	2