Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	830	1			T8	14		T16	8		T17	17
all_values[1]	830	1			T8	14		T16	8		T17	17
all_values[2]	830	1			T8	14		T16	8		T17	17
all_values[3]	830	1			T8	14		T16	8		T17	17
all_values[4]	830	1			T8	14		T16	8		T17	17
all_values[5]	830	1			T8	14		T16	8		T17	17
all_values[6]	830	1			T8	14		T16	8		T17	17
all_values[7]	830	1			T8	14		T16	8		T17	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3616

1

T8

60

T16

38

T17

76

auto[1]

3024

1

T8

52

T16

26

T17

60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2792

1

T8

44

T16

34

T17

48

auto[1]

3848

1

T8

68

T16

30

T17

88

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3872

1

T8

62

T16

44

T17

80

auto[1]

2768

1

T8

50

T16

20

T17

56

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	186	1			T8	1		T16	4		T17	2
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T8	2		T16	1		T17	2
all_values[0]	auto[0]	auto[1]	auto[0]	139	1			T8	3		T16	1		T17	5
all_values[0]	auto[0]	auto[1]	auto[1]	72	1			T8	1		T17	3		T22	1
all_values[0]	auto[1]	auto[0]	auto[1]	185	1			T8	6		T16	2		T17	3
all_values[0]	auto[1]	auto[1]	auto[1]	161	1			T8	1		T17	2		T19	1
all_values[1]	auto[0]	auto[0]	auto[0]	171	1			T8	2		T16	2		T17	4
all_values[1]	auto[0]	auto[0]	auto[1]	75	1			T8	2		T17	3		T20	1
all_values[1]	auto[0]	auto[1]	auto[0]	156	1			T8	4		T16	2		T17	1
all_values[1]	auto[0]	auto[1]	auto[1]	69	1			T16	2		T17	2		T19	1
all_values[1]	auto[1]	auto[0]	auto[1]	201	1			T8	2		T17	3		T19	2
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T8	4		T16	2		T17	4
all_values[2]	auto[0]	auto[0]	auto[0]	185	1			T8	3		T16	6		T17	3
all_values[2]	auto[0]	auto[0]	auto[1]	81	1			T8	2		T16	1		T17	2
all_values[2]	auto[0]	auto[1]	auto[0]	144	1			T8	1		T17	2		T19	3
all_values[2]	auto[0]	auto[1]	auto[1]	71	1			T8	1		T17	1		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	196	1			T8	5		T16	1		T17	6
all_values[2]	auto[1]	auto[1]	auto[1]	153	1			T8	2		T17	3		T20	1
all_values[3]	auto[0]	auto[0]	auto[0]	165	1			T8	2		T16	3		T17	2
all_values[3]	auto[0]	auto[0]	auto[1]	83	1			T17	1		T20	3		T21	1
all_values[3]	auto[0]	auto[1]	auto[0]	160	1			T8	1		T16	3		T17	1
all_values[3]	auto[0]	auto[1]	auto[1]	74	1			T8	4		T17	5		T19	1
all_values[3]	auto[1]	auto[0]	auto[1]	183	1			T8	4		T16	1		T17	6
all_values[3]	auto[1]	auto[1]	auto[1]	165	1			T8	3		T16	1		T17	2
all_values[4]	auto[0]	auto[0]	auto[0]	189	1			T8	5		T20	2		T21	1
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T16	1		T17	3		T19	2
all_values[4]	auto[0]	auto[1]	auto[0]	139	1			T8	3		T16	1		T17	6
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T8	1		T16	2		T19	2
all_values[4]	auto[1]	auto[0]	auto[1]	192	1			T8	3		T16	1		T17	4
all_values[4]	auto[1]	auto[1]	auto[1]	151	1			T8	2		T16	3		T17	4
all_values[5]	auto[0]	auto[0]	auto[0]	275	1			T8	3		T16	6		T17	7
all_values[5]	auto[0]	auto[1]	auto[0]	229	1			T8	4		T17	4		T19	4
all_values[5]	auto[1]	auto[0]	auto[1]	187	1			T8	6		T16	2		T17	4
all_values[5]	auto[1]	auto[1]	auto[1]	139	1			T8	1		T17	2		T19	2
all_values[6]	auto[0]	auto[0]	auto[0]	159	1			T8	2		T16	2		T17	3
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T16	1		T17	4		T20	2
all_values[6]	auto[0]	auto[1]	auto[0]	143	1			T8	2		T16	1		T17	5
all_values[6]	auto[0]	auto[1]	auto[1]	93	1			T8	3		T16	1		T17	1
all_values[6]	auto[1]	auto[0]	auto[1]	190	1			T8	2		T16	1		T17	2
all_values[6]	auto[1]	auto[1]	auto[1]	171	1			T8	5		T16	2		T17	2
all_values[7]	auto[0]	auto[0]	auto[0]	213	1			T8	4		T17	3		T19	5
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T8	2		T17	3		T20	2
all_values[7]	auto[0]	auto[1]	auto[0]	139	1			T8	4		T16	3		T20	2
all_values[7]	auto[0]	auto[1]	auto[1]	69	1			T16	1		T17	2		T19	1
all_values[7]	auto[1]	auto[0]	auto[1]	188	1			T8	2		T16	3		T17	6
all_values[7]	auto[1]	auto[1]	auto[1]	148	1			T8	2		T16	1		T17	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal