Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1640

1

T4

7

T7

4

T10

20

auto[1]

1653

1

T4

11

T7

5

T10

16

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1692

1

T4

18

T7

9

T12

7

auto[1]

1601

1

T10

36

T25

19

T27

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2625

1

T4

10

T7

5

T10

36

auto[1]

668

1

T4

8

T7

4

T12

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	645	1			T4	5		T7	1		T10	8
valid[1]	649	1			T4	2		T7	3		T10	6
valid[2]	669	1			T4	5		T7	2		T10	9
valid[3]	668	1			T4	4		T7	1		T10	9
valid[4]	662	1			T4	2		T7	2		T10	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	107	1			T4	1		T7	1		T12	1
auto[0]	auto[0]	valid[0]	auto[1]	142	1			T10	5		T27	1		T30	1
auto[0]	auto[0]	valid[1]	auto[0]	98	1			T4	1		T26	1		T88	1
auto[0]	auto[0]	valid[1]	auto[1]	165	1			T10	3		T25	3		T52	1
auto[0]	auto[0]	valid[2]	auto[0]	103	1			T4	1		T28	1		T29	2
auto[0]	auto[0]	valid[2]	auto[1]	163	1			T10	7		T25	2		T28	2
auto[0]	auto[0]	valid[3]	auto[0]	105	1			T7	1		T28	2		T29	1
auto[0]	auto[0]	valid[3]	auto[1]	150	1			T10	3		T25	1		T317	3
auto[0]	auto[0]	valid[4]	auto[0]	104	1			T4	1		T12	1		T26	1
auto[0]	auto[0]	valid[4]	auto[1]	163	1			T10	2		T25	2		T29	1
auto[0]	auto[1]	valid[0]	auto[0]	102	1			T4	2		T52	1		T15	1
auto[0]	auto[1]	valid[0]	auto[1]	164	1			T10	3		T25	4		T28	1
auto[0]	auto[1]	valid[1]	auto[0]	95	1			T7	2		T52	1		T88	1
auto[0]	auto[1]	valid[1]	auto[1]	176	1			T10	3		T25	1		T30	1
auto[0]	auto[1]	valid[2]	auto[0]	90	1			T4	2		T29	1		T88	2
auto[0]	auto[1]	valid[2]	auto[1]	170	1			T10	2		T25	3		T28	1
auto[0]	auto[1]	valid[3]	auto[0]	113	1			T4	1		T12	3		T28	1
auto[0]	auto[1]	valid[3]	auto[1]	158	1			T10	6		T317	1		T104	3
auto[0]	auto[1]	valid[4]	auto[0]	107	1			T4	1		T7	1		T88	1
auto[0]	auto[1]	valid[4]	auto[1]	150	1			T10	2		T25	3		T28	1
auto[1]	auto[0]	valid[0]	auto[0]	74	1			T4	1		T28	1		T52	1
auto[1]	auto[0]	valid[1]	auto[0]	60	1			T7	1		T27	1		T29	1
auto[1]	auto[0]	valid[2]	auto[0]	77	1			T4	1		T28	2		T47	1
auto[1]	auto[0]	valid[3]	auto[0]	60	1			T4	1		T29	2		T47	1
auto[1]	auto[0]	valid[4]	auto[0]	69	1			T7	1		T27	2		T29	2
auto[1]	auto[1]	valid[0]	auto[0]	56	1			T4	1		T28	1		T29	2
auto[1]	auto[1]	valid[1]	auto[0]	55	1			T4	1		T26	2		T174	2
auto[1]	auto[1]	valid[2]	auto[0]	66	1			T4	1		T7	2		T28	1
auto[1]	auto[1]	valid[3]	auto[0]	82	1			T4	2		T27	1		T28	1
auto[1]	auto[1]	valid[4]	auto[0]	69	1			T12	2		T29	1		T48	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal