Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43629

1

T4

310

T7

139

T12

134

auto[1]

15857

1

T4

47

T7

19

T10

331

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43466

1

T4

233

T7

100

T10

331

auto[1]

16020

1

T4

124

T7

58

T12

40

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	30512	1			T4	192		T7	77		T10	171
others[1]	5038	1			T4	22		T7	16		T10	24
others[2]	5050	1			T4	39		T7	10		T10	34
others[3]	5709	1			T4	31		T7	18		T10	32
interest[1]	3270	1			T4	27		T7	10		T10	19
interest[4]	19991	1			T4	130		T7	49		T10	108
interest[64]	9907	1			T4	46		T7	27		T10	51

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14083	1			T4	100		T7	39		T12	40
auto[0]	auto[0]	others[1]	2318	1			T4	11		T7	10		T12	9
auto[0]	auto[0]	others[2]	2427	1			T4	20		T7	5		T12	8
auto[0]	auto[0]	others[3]	2668	1			T4	17		T7	8		T12	14
auto[0]	auto[0]	interest[1]	1514	1			T4	14		T7	6		T12	4
auto[0]	auto[0]	interest[4]	9162	1			T4	67		T7	27		T12	29
auto[0]	auto[0]	interest[64]	4599	1			T4	24		T7	13		T12	19
auto[0]	auto[1]	others[0]	8271	1			T4	25		T7	11		T10	171
auto[0]	auto[1]	others[1]	1330	1			T4	5		T7	2		T10	24
auto[0]	auto[1]	others[2]	1315	1			T4	6		T7	1		T10	34
auto[0]	auto[1]	others[3]	1468	1			T4	3		T10	32		T25	23
auto[0]	auto[1]	interest[1]	857	1			T4	2		T7	1		T10	19
auto[0]	auto[1]	interest[4]	5502	1			T4	16		T7	7		T10	108
auto[0]	auto[1]	interest[64]	2616	1			T4	6		T7	4		T10	51
auto[1]	auto[0]	others[0]	8158	1			T4	67		T7	27		T12	20
auto[1]	auto[0]	others[1]	1390	1			T4	6		T7	4		T12	4
auto[1]	auto[0]	others[2]	1308	1			T4	13		T7	4		T12	4
auto[1]	auto[0]	others[3]	1573	1			T4	11		T7	10		T12	4
auto[1]	auto[0]	interest[1]	899	1			T4	11		T7	3		T12	2
auto[1]	auto[0]	interest[4]	5327	1			T4	47		T7	15		T12	11
auto[1]	auto[0]	interest[64]	2692	1			T4	16		T7	10		T12	6

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal