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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1150
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T127 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3549178044 Aug 14 04:42:33 PM PDT 24 Aug 14 04:42:34 PM PDT 24 38059075 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2988461395 Aug 14 04:42:44 PM PDT 24 Aug 14 04:42:45 PM PDT 24 11981461 ps
T128 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2216083426 Aug 14 04:42:34 PM PDT 24 Aug 14 04:42:59 PM PDT 24 7503320148 ps
T1039 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2501274788 Aug 14 04:43:05 PM PDT 24 Aug 14 04:43:06 PM PDT 24 11570726 ps
T108 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.299713457 Aug 14 04:42:48 PM PDT 24 Aug 14 04:42:50 PM PDT 24 860537750 ps
T102 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2964943273 Aug 14 04:42:58 PM PDT 24 Aug 14 04:43:04 PM PDT 24 389976385 ps
T1040 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2905045391 Aug 14 04:42:48 PM PDT 24 Aug 14 04:42:49 PM PDT 24 39747819 ps
T1041 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.717431349 Aug 14 04:42:47 PM PDT 24 Aug 14 04:42:48 PM PDT 24 107191188 ps
T117 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3874174677 Aug 14 04:42:50 PM PDT 24 Aug 14 04:42:54 PM PDT 24 449389619 ps
T1042 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4094665225 Aug 14 04:42:44 PM PDT 24 Aug 14 04:42:45 PM PDT 24 199935122 ps
T119 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4183258639 Aug 14 04:42:37 PM PDT 24 Aug 14 04:42:40 PM PDT 24 96037764 ps
T1043 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4154089600 Aug 14 04:43:10 PM PDT 24 Aug 14 04:43:11 PM PDT 24 16690345 ps
T1044 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2406494713 Aug 14 04:42:59 PM PDT 24 Aug 14 04:43:00 PM PDT 24 53443275 ps
T1045 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2058987935 Aug 14 04:42:53 PM PDT 24 Aug 14 04:42:54 PM PDT 24 14377609 ps
T103 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.159270476 Aug 14 04:42:30 PM PDT 24 Aug 14 04:42:52 PM PDT 24 2050799552 ps
T85 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3455385626 Aug 14 04:42:55 PM PDT 24 Aug 14 04:42:56 PM PDT 24 127814777 ps
T109 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1516727622 Aug 14 04:42:21 PM PDT 24 Aug 14 04:42:25 PM PDT 24 244069508 ps
T129 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1443800011 Aug 14 04:42:56 PM PDT 24 Aug 14 04:42:59 PM PDT 24 41481977 ps
T116 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.342151709 Aug 14 04:42:30 PM PDT 24 Aug 14 04:42:33 PM PDT 24 94774695 ps
T155 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1053924636 Aug 14 04:42:55 PM PDT 24 Aug 14 04:42:56 PM PDT 24 263805949 ps
T1046 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2673865397 Aug 14 04:42:53 PM PDT 24 Aug 14 04:42:53 PM PDT 24 40019876 ps
T130 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1567459324 Aug 14 04:42:22 PM PDT 24 Aug 14 04:42:25 PM PDT 24 1382607400 ps
T156 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3653441112 Aug 14 04:42:39 PM PDT 24 Aug 14 04:42:40 PM PDT 24 57961090 ps
T1047 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.161695118 Aug 14 04:42:57 PM PDT 24 Aug 14 04:42:58 PM PDT 24 87392848 ps
T133 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3621497057 Aug 14 04:42:39 PM PDT 24 Aug 14 04:43:01 PM PDT 24 1236571996 ps
T110 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3178862421 Aug 14 04:42:25 PM PDT 24 Aug 14 04:42:30 PM PDT 24 1329204688 ps
T1048 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.453492166 Aug 14 04:42:44 PM PDT 24 Aug 14 04:42:48 PM PDT 24 77746872 ps
T1049 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.24365220 Aug 14 04:42:35 PM PDT 24 Aug 14 04:42:39 PM PDT 24 154812580 ps
T131 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2114916202 Aug 14 04:42:55 PM PDT 24 Aug 14 04:42:57 PM PDT 24 29641777 ps
T1050 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2616547275 Aug 14 04:42:55 PM PDT 24 Aug 14 04:42:56 PM PDT 24 17611814 ps
T1051 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.173545974 Aug 14 04:43:03 PM PDT 24 Aug 14 04:43:04 PM PDT 24 22817478 ps
T1052 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3471954559 Aug 14 04:42:57 PM PDT 24 Aug 14 04:42:58 PM PDT 24 46855315 ps
T1053 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1681169348 Aug 14 04:42:46 PM PDT 24 Aug 14 04:42:47 PM PDT 24 18071218 ps
T132 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4251919489 Aug 14 04:42:21 PM PDT 24 Aug 14 04:42:24 PM PDT 24 85361787 ps
T1054 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1632877661 Aug 14 04:43:01 PM PDT 24 Aug 14 04:43:01 PM PDT 24 70982254 ps
T157 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3920311190 Aug 14 04:42:47 PM PDT 24 Aug 14 04:42:50 PM PDT 24 122145922 ps
T1055 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2872649246 Aug 14 04:43:01 PM PDT 24 Aug 14 04:43:02 PM PDT 24 33652174 ps
T158 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3647081724 Aug 14 04:43:03 PM PDT 24 Aug 14 04:43:07 PM PDT 24 567838146 ps
T86 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2031850677 Aug 14 04:42:48 PM PDT 24 Aug 14 04:42:49 PM PDT 24 111226126 ps
T111 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.866178357 Aug 14 04:42:45 PM PDT 24 Aug 14 04:42:49 PM PDT 24 524674742 ps
T1056 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3003276145 Aug 14 04:43:03 PM PDT 24 Aug 14 04:43:04 PM PDT 24 34183026 ps
T159 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1651518833 Aug 14 04:42:52 PM PDT 24 Aug 14 04:42:54 PM PDT 24 258965736 ps
T1057 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1078719928 Aug 14 04:43:09 PM PDT 24 Aug 14 04:43:11 PM PDT 24 66265354 ps
T1058 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1814906010 Aug 14 04:42:45 PM PDT 24 Aug 14 04:42:47 PM PDT 24 709529301 ps
T172 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1937569200 Aug 14 04:42:22 PM PDT 24 Aug 14 04:43:00 PM PDT 24 2858498441 ps
T178 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3110301727 Aug 14 04:42:54 PM PDT 24 Aug 14 04:43:17 PM PDT 24 7162113359 ps
T1059 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3882198244 Aug 14 04:42:53 PM PDT 24 Aug 14 04:42:54 PM PDT 24 88805404 ps
T1060 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3780672473 Aug 14 04:42:43 PM PDT 24 Aug 14 04:42:57 PM PDT 24 1430439788 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2242148842 Aug 14 04:42:51 PM PDT 24 Aug 14 04:42:53 PM PDT 24 26399535 ps
T113 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2877375185 Aug 14 04:42:42 PM PDT 24 Aug 14 04:42:46 PM PDT 24 238200765 ps
T114 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3661806228 Aug 14 04:43:05 PM PDT 24 Aug 14 04:43:15 PM PDT 24 299567056 ps
T1062 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.933049246 Aug 14 04:42:44 PM PDT 24 Aug 14 04:42:45 PM PDT 24 13814190 ps
T1063 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3360529866 Aug 14 04:42:43 PM PDT 24 Aug 14 04:42:44 PM PDT 24 38747916 ps
T1064 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1320924673 Aug 14 04:42:42 PM PDT 24 Aug 14 04:42:45 PM PDT 24 57953736 ps
T115 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4033258835 Aug 14 04:42:56 PM PDT 24 Aug 14 04:42:59 PM PDT 24 198053935 ps
T1065 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2555910832 Aug 14 04:42:22 PM PDT 24 Aug 14 04:42:23 PM PDT 24 13976173 ps
T182 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1959581187 Aug 14 04:42:36 PM PDT 24 Aug 14 04:42:54 PM PDT 24 1261927008 ps
T1066 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2611773798 Aug 14 04:42:49 PM PDT 24 Aug 14 04:42:52 PM PDT 24 195399094 ps
T1067 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2189657879 Aug 14 04:42:36 PM PDT 24 Aug 14 04:42:38 PM PDT 24 54807867 ps
T1068 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3109544029 Aug 14 04:42:22 PM PDT 24 Aug 14 04:42:23 PM PDT 24 48592837 ps
T1069 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.388922220 Aug 14 04:42:55 PM PDT 24 Aug 14 04:42:59 PM PDT 24 236051264 ps
T183 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2921888160 Aug 14 04:42:49 PM PDT 24 Aug 14 04:43:07 PM PDT 24 303307183 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.828818509 Aug 14 04:43:01 PM PDT 24 Aug 14 04:43:02 PM PDT 24 10278580 ps
T1071 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1561757622 Aug 14 04:42:56 PM PDT 24 Aug 14 04:42:57 PM PDT 24 23254827 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3524786542 Aug 14 04:43:05 PM PDT 24 Aug 14 04:43:07 PM PDT 24 19453719 ps
T1073 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1504740475 Aug 14 04:42:23 PM PDT 24 Aug 14 04:42:42 PM PDT 24 1224280188 ps
T1074 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2860986132 Aug 14 04:42:32 PM PDT 24 Aug 14 04:42:40 PM PDT 24 115268989 ps
T1075 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3569904916 Aug 14 04:42:45 PM PDT 24 Aug 14 04:42:45 PM PDT 24 16220866 ps
T1076 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2763081978 Aug 14 04:42:20 PM PDT 24 Aug 14 04:42:21 PM PDT 24 37777981 ps
T179 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2071656753 Aug 14 04:42:38 PM PDT 24 Aug 14 04:42:52 PM PDT 24 2106511289 ps
T1077 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.128943169 Aug 14 04:42:53 PM PDT 24 Aug 14 04:42:56 PM PDT 24 95371953 ps
T1078 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2375310743 Aug 14 04:42:53 PM PDT 24 Aug 14 04:42:54 PM PDT 24 39632314 ps
T1079 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1168306949 Aug 14 04:42:48 PM PDT 24 Aug 14 04:42:53 PM PDT 24 1623641755 ps
T112 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2569148896 Aug 14 04:42:34 PM PDT 24 Aug 14 04:42:39 PM PDT 24 653321823 ps
T1080 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3069182351 Aug 14 04:42:43 PM PDT 24 Aug 14 04:42:44 PM PDT 24 14742318 ps
T1081 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.731984518 Aug 14 04:42:53 PM PDT 24 Aug 14 04:42:56 PM PDT 24 226850367 ps
T1082 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4234834388 Aug 14 04:42:45 PM PDT 24 Aug 14 04:42:49 PM PDT 24 138088431 ps
T1083 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3794970625 Aug 14 04:42:23 PM PDT 24 Aug 14 04:42:31 PM PDT 24 241535884 ps
T1084 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3273501963 Aug 14 04:42:53 PM PDT 24 Aug 14 04:42:54 PM PDT 24 24235725 ps
T1085 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3422073007 Aug 14 04:43:00 PM PDT 24 Aug 14 04:43:02 PM PDT 24 295248467 ps
T1086 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3763366175 Aug 14 04:42:57 PM PDT 24 Aug 14 04:42:58 PM PDT 24 11295980 ps
T1087 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2628722218 Aug 14 04:42:48 PM PDT 24 Aug 14 04:43:14 PM PDT 24 8214762041 ps
T1088 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2641578785 Aug 14 04:42:28 PM PDT 24 Aug 14 04:42:28 PM PDT 24 62427910 ps
T1089 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.575510787 Aug 14 04:42:52 PM PDT 24 Aug 14 04:42:54 PM PDT 24 150240436 ps
T1090 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3854323704 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:11 PM PDT 24 104488795 ps
T184 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1324297865 Aug 14 04:43:05 PM PDT 24 Aug 14 04:43:12 PM PDT 24 2862973342 ps
T1091 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2280024130 Aug 14 04:43:02 PM PDT 24 Aug 14 04:43:03 PM PDT 24 17893746 ps
T1092 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1681593312 Aug 14 04:42:58 PM PDT 24 Aug 14 04:42:58 PM PDT 24 31383830 ps
T176 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2154525061 Aug 14 04:43:03 PM PDT 24 Aug 14 04:43:23 PM PDT 24 6699462541 ps
T1093 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1987089705 Aug 14 04:42:39 PM PDT 24 Aug 14 04:42:47 PM PDT 24 89526240 ps
T1094 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2481280495 Aug 14 04:42:22 PM PDT 24 Aug 14 04:42:26 PM PDT 24 278255796 ps
T1095 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2439274144 Aug 14 04:42:53 PM PDT 24 Aug 14 04:42:57 PM PDT 24 241256698 ps
T1096 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3749452270 Aug 14 04:42:22 PM PDT 24 Aug 14 04:42:24 PM PDT 24 160763927 ps
T1097 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.889658590 Aug 14 04:42:37 PM PDT 24 Aug 14 04:42:39 PM PDT 24 83544286 ps
T1098 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2764064544 Aug 14 04:42:49 PM PDT 24 Aug 14 04:42:51 PM PDT 24 59405576 ps
T1099 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.977804973 Aug 14 04:42:55 PM PDT 24 Aug 14 04:43:01 PM PDT 24 220331907 ps
T1100 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2150712516 Aug 14 04:42:40 PM PDT 24 Aug 14 04:42:48 PM PDT 24 110878902 ps
T1101 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4240454670 Aug 14 04:42:42 PM PDT 24 Aug 14 04:42:43 PM PDT 24 16131086 ps
T1102 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1677000590 Aug 14 04:42:58 PM PDT 24 Aug 14 04:42:59 PM PDT 24 144534026 ps
T1103 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2691142345 Aug 14 04:42:52 PM PDT 24 Aug 14 04:42:53 PM PDT 24 13708196 ps
T1104 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3608896745 Aug 14 04:42:29 PM PDT 24 Aug 14 04:42:32 PM PDT 24 319850329 ps
T1105 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3898494620 Aug 14 04:42:40 PM PDT 24 Aug 14 04:42:43 PM PDT 24 144387433 ps
T1106 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1371204008 Aug 14 04:42:38 PM PDT 24 Aug 14 04:42:40 PM PDT 24 23913531 ps
T1107 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1424962852 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:06 PM PDT 24 44884687 ps
T1108 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3769428781 Aug 14 04:42:46 PM PDT 24 Aug 14 04:42:47 PM PDT 24 13888848 ps
T1109 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3996904183 Aug 14 04:42:52 PM PDT 24 Aug 14 04:42:54 PM PDT 24 94267015 ps
T1110 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1544840789 Aug 14 04:42:56 PM PDT 24 Aug 14 04:42:57 PM PDT 24 13489246 ps
T1111 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1710355841 Aug 14 04:42:59 PM PDT 24 Aug 14 04:43:00 PM PDT 24 41523999 ps
T1112 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.242023610 Aug 14 04:42:51 PM PDT 24 Aug 14 04:42:52 PM PDT 24 14159900 ps
T1113 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2941841116 Aug 14 04:42:56 PM PDT 24 Aug 14 04:43:01 PM PDT 24 1648650579 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.87544303 Aug 14 04:42:45 PM PDT 24 Aug 14 04:42:47 PM PDT 24 102685192 ps
T1115 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3179984693 Aug 14 04:42:32 PM PDT 24 Aug 14 04:42:33 PM PDT 24 18926797 ps
T1116 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.408759799 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:17 PM PDT 24 881010117 ps
T180 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1853942314 Aug 14 04:42:46 PM PDT 24 Aug 14 04:43:04 PM PDT 24 474808533 ps
T1117 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.429008044 Aug 14 04:42:51 PM PDT 24 Aug 14 04:42:52 PM PDT 24 37876951 ps
T1118 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.564170968 Aug 14 04:42:22 PM PDT 24 Aug 14 04:42:23 PM PDT 24 73618196 ps
T1119 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2838509133 Aug 14 04:42:38 PM PDT 24 Aug 14 04:42:46 PM PDT 24 363125704 ps
T1120 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2572957133 Aug 14 04:42:38 PM PDT 24 Aug 14 04:42:59 PM PDT 24 4257456786 ps
T1121 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3751067822 Aug 14 04:42:46 PM PDT 24 Aug 14 04:42:50 PM PDT 24 249920545 ps
T1122 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.233572823 Aug 14 04:42:35 PM PDT 24 Aug 14 04:42:41 PM PDT 24 250842765 ps
T1123 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3984341900 Aug 14 04:42:51 PM PDT 24 Aug 14 04:42:51 PM PDT 24 10609004 ps
T1124 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2187070032 Aug 14 04:42:56 PM PDT 24 Aug 14 04:42:57 PM PDT 24 58359737 ps
T1125 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2735451368 Aug 14 04:42:49 PM PDT 24 Aug 14 04:43:09 PM PDT 24 1871585237 ps
T1126 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3452408631 Aug 14 04:43:10 PM PDT 24 Aug 14 04:43:11 PM PDT 24 48824454 ps
T1127 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3509096521 Aug 14 04:42:45 PM PDT 24 Aug 14 04:42:48 PM PDT 24 139822044 ps
T177 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1284693380 Aug 14 04:42:50 PM PDT 24 Aug 14 04:42:59 PM PDT 24 1313186830 ps
T1128 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3854746620 Aug 14 04:42:59 PM PDT 24 Aug 14 04:43:06 PM PDT 24 112128967 ps
T1129 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2779179533 Aug 14 04:42:43 PM PDT 24 Aug 14 04:42:45 PM PDT 24 280808292 ps
T1130 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3210185758 Aug 14 04:42:57 PM PDT 24 Aug 14 04:43:00 PM PDT 24 813789601 ps
T1131 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2739667798 Aug 14 04:42:55 PM PDT 24 Aug 14 04:42:59 PM PDT 24 367071975 ps
T1132 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4116370106 Aug 14 04:42:22 PM PDT 24 Aug 14 04:42:24 PM PDT 24 105712640 ps
T1133 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2269962911 Aug 14 04:42:21 PM PDT 24 Aug 14 04:42:22 PM PDT 24 18586339 ps
T1134 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1661147666 Aug 14 04:42:23 PM PDT 24 Aug 14 04:42:46 PM PDT 24 2760886968 ps
T181 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2991176297 Aug 14 04:42:34 PM PDT 24 Aug 14 04:42:48 PM PDT 24 571094116 ps
T1135 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.140315379 Aug 14 04:43:02 PM PDT 24 Aug 14 04:43:03 PM PDT 24 15600254 ps
T1136 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2921736722 Aug 14 04:42:29 PM PDT 24 Aug 14 04:42:30 PM PDT 24 29757148 ps
T1137 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.488127004 Aug 14 04:42:46 PM PDT 24 Aug 14 04:42:47 PM PDT 24 31048997 ps
T1138 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.290705918 Aug 14 04:42:23 PM PDT 24 Aug 14 04:42:27 PM PDT 24 129714818 ps
T1139 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3247643798 Aug 14 04:42:53 PM PDT 24 Aug 14 04:42:54 PM PDT 24 22448382 ps
T1140 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2185995573 Aug 14 04:43:04 PM PDT 24 Aug 14 04:43:05 PM PDT 24 36488795 ps
T1141 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1368559168 Aug 14 04:42:57 PM PDT 24 Aug 14 04:43:00 PM PDT 24 46729876 ps
T1142 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3982421439 Aug 14 04:43:03 PM PDT 24 Aug 14 04:43:08 PM PDT 24 495796099 ps
T1143 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.212629164 Aug 14 04:42:36 PM PDT 24 Aug 14 04:42:37 PM PDT 24 210058147 ps
T1144 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2625025531 Aug 14 04:42:47 PM PDT 24 Aug 14 04:43:00 PM PDT 24 393503268 ps
T1145 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.63968531 Aug 14 04:42:53 PM PDT 24 Aug 14 04:42:55 PM PDT 24 277114393 ps
T1146 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2254966570 Aug 14 04:42:39 PM PDT 24 Aug 14 04:42:46 PM PDT 24 763365446 ps
T1147 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.486465090 Aug 14 04:43:01 PM PDT 24 Aug 14 04:43:02 PM PDT 24 51439121 ps
T1148 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1079550087 Aug 14 04:42:48 PM PDT 24 Aug 14 04:42:51 PM PDT 24 393344365 ps
T1149 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2488126599 Aug 14 04:42:43 PM PDT 24 Aug 14 04:43:05 PM PDT 24 3486050342 ps
T1150 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3420211201 Aug 14 04:42:25 PM PDT 24 Aug 14 04:42:39 PM PDT 24 3774828351 ps

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2059790797
Short name T7
Test name
Test status
Simulation time 43030982382 ps
CPU time 132.82 seconds
Started Aug 14 05:27:06 PM PDT 24
Finished Aug 14 05:29:19 PM PDT 24
Peak memory 257040 kb
Host smart-6821266e-7ed7-4c20-af4b-44572cb95104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059790797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2059790797
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1552008192
Short name T17
Test name
Test status
Simulation time 54002973313 ps
CPU time 264.58 seconds
Started Aug 14 05:27:04 PM PDT 24
Finished Aug 14 05:31:29 PM PDT 24
Peak memory 262368 kb
Host smart-286ef852-602e-465d-8f5f-c5d1ca33d3a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552008192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1552008192
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1129735136
Short name T83
Test name
Test status
Simulation time 3806753419 ps
CPU time 92.28 seconds
Started Aug 14 05:27:26 PM PDT 24
Finished Aug 14 05:28:59 PM PDT 24
Peak memory 249528 kb
Host smart-dd1b2cd2-9365-48fd-b44a-2e7cf94b5492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129735136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1129735136
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.159270476
Short name T103
Test name
Test status
Simulation time 2050799552 ps
CPU time 21.83 seconds
Started Aug 14 04:42:30 PM PDT 24
Finished Aug 14 04:42:52 PM PDT 24
Peak memory 215972 kb
Host smart-142023ea-27ff-4021-b3db-0efa6c83fe4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159270476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.159270476
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3920702335
Short name T197
Test name
Test status
Simulation time 64258086208 ps
CPU time 388.24 seconds
Started Aug 14 05:28:52 PM PDT 24
Finished Aug 14 05:35:21 PM PDT 24
Peak memory 269480 kb
Host smart-3d6a12d9-03c5-45f5-b0a0-27dd6980b7cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920702335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3920702335
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3695814444
Short name T38
Test name
Test status
Simulation time 194907865748 ps
CPU time 323.89 seconds
Started Aug 14 05:28:47 PM PDT 24
Finished Aug 14 05:34:11 PM PDT 24
Peak memory 252572 kb
Host smart-b618c97b-108c-4fe2-b49b-06d74fdfb60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695814444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3695814444
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.255806817
Short name T70
Test name
Test status
Simulation time 34860410 ps
CPU time 0.74 seconds
Started Aug 14 05:25:28 PM PDT 24
Finished Aug 14 05:25:29 PM PDT 24
Peak memory 216264 kb
Host smart-c735e87a-a183-4ca4-bbf6-9884af0fa779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255806817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.255806817
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4266457593
Short name T4
Test name
Test status
Simulation time 11581705649 ps
CPU time 78.76 seconds
Started Aug 14 05:29:06 PM PDT 24
Finished Aug 14 05:30:25 PM PDT 24
Peak memory 272028 kb
Host smart-563e6999-060a-47ef-8654-31ab33da0261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266457593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4266457593
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2669707568
Short name T216
Test name
Test status
Simulation time 399188903329 ps
CPU time 512.58 seconds
Started Aug 14 05:28:05 PM PDT 24
Finished Aug 14 05:36:37 PM PDT 24
Peak memory 282172 kb
Host smart-b68b7aab-f8b3-4e1a-b803-a36332b3a077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669707568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2669707568
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3042733987
Short name T101
Test name
Test status
Simulation time 162969746 ps
CPU time 5.1 seconds
Started Aug 14 04:42:56 PM PDT 24
Finished Aug 14 04:43:02 PM PDT 24
Peak memory 216104 kb
Host smart-32580d16-febd-43f8-8b62-a96cfc95cae7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042733987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
042733987
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3680433306
Short name T50
Test name
Test status
Simulation time 18510194326 ps
CPU time 151.64 seconds
Started Aug 14 05:29:11 PM PDT 24
Finished Aug 14 05:31:43 PM PDT 24
Peak memory 251688 kb
Host smart-ada4c622-334d-47bd-821e-7bd436ad659f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680433306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3680433306
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3903867701
Short name T18
Test name
Test status
Simulation time 38219118 ps
CPU time 1.01 seconds
Started Aug 14 05:25:41 PM PDT 24
Finished Aug 14 05:25:42 PM PDT 24
Peak memory 235976 kb
Host smart-b4dcf5cf-5dc4-4d68-9c71-43552fd9b43c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903867701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3903867701
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.943676035
Short name T160
Test name
Test status
Simulation time 12413591576 ps
CPU time 199.21 seconds
Started Aug 14 05:27:35 PM PDT 24
Finished Aug 14 05:30:54 PM PDT 24
Peak memory 268624 kb
Host smart-df2b73c1-abe0-4608-8000-e005508da121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943676035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.943676035
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.283676823
Short name T48
Test name
Test status
Simulation time 58749388520 ps
CPU time 98.03 seconds
Started Aug 14 05:26:48 PM PDT 24
Finished Aug 14 05:28:26 PM PDT 24
Peak memory 256008 kb
Host smart-9e3d30bc-aa7a-42f2-95a6-f2c68bb5b591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283676823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.283676823
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1055680685
Short name T151
Test name
Test status
Simulation time 4389386087 ps
CPU time 8.13 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:29:12 PM PDT 24
Peak memory 222560 kb
Host smart-73741386-0e6a-4227-834e-e22f88b22b8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1055680685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1055680685
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2048073182
Short name T88
Test name
Test status
Simulation time 46034221437 ps
CPU time 371.94 seconds
Started Aug 14 05:28:00 PM PDT 24
Finished Aug 14 05:34:12 PM PDT 24
Peak memory 256156 kb
Host smart-6b6ca834-bf0d-4fea-80bf-a7a5b801f0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048073182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2048073182
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3369762139
Short name T191
Test name
Test status
Simulation time 49032600484 ps
CPU time 466.2 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:33:44 PM PDT 24
Peak memory 271160 kb
Host smart-95813af5-800b-4f63-a55d-f96efcef10a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369762139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3369762139
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4247761647
Short name T122
Test name
Test status
Simulation time 134877475 ps
CPU time 1.26 seconds
Started Aug 14 04:42:29 PM PDT 24
Finished Aug 14 04:42:35 PM PDT 24
Peak memory 215996 kb
Host smart-5feb0e7d-2f82-4daf-b903-f177c74e71b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247761647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
247761647
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1454537363
Short name T51
Test name
Test status
Simulation time 30425631646 ps
CPU time 104.82 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:29:19 PM PDT 24
Peak memory 251416 kb
Host smart-9dfefd7f-53d6-42dd-a11a-ae577d1f62a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454537363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1454537363
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1271894060
Short name T2
Test name
Test status
Simulation time 11739260797 ps
CPU time 152.34 seconds
Started Aug 14 05:25:47 PM PDT 24
Finished Aug 14 05:28:20 PM PDT 24
Peak memory 266088 kb
Host smart-17dc35ec-730b-4611-8b9d-7e70ce50a1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271894060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1271894060
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2957045944
Short name T202
Test name
Test status
Simulation time 21787595220 ps
CPU time 104.43 seconds
Started Aug 14 05:26:18 PM PDT 24
Finished Aug 14 05:28:05 PM PDT 24
Peak memory 253560 kb
Host smart-70fba19e-0757-41ac-b62f-d1cf7034fdc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957045944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2957045944
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2092222699
Short name T491
Test name
Test status
Simulation time 34548120 ps
CPU time 1.05 seconds
Started Aug 14 05:26:50 PM PDT 24
Finished Aug 14 05:26:51 PM PDT 24
Peak memory 216752 kb
Host smart-b60274cf-1967-4102-bc6a-5ebef23b29ea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092222699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2092222699
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3205438103
Short name T15
Test name
Test status
Simulation time 136860235191 ps
CPU time 294.43 seconds
Started Aug 14 05:29:20 PM PDT 24
Finished Aug 14 05:34:15 PM PDT 24
Peak memory 256496 kb
Host smart-708d9ce1-19df-48cc-bebe-310ca0aed68f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205438103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3205438103
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1951562686
Short name T186
Test name
Test status
Simulation time 17277754006 ps
CPU time 83.98 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:30:19 PM PDT 24
Peak memory 262484 kb
Host smart-ce1b44d7-5e44-41be-849e-fe30e2042ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951562686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1951562686
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1013593406
Short name T16
Test name
Test status
Simulation time 89322046704 ps
CPU time 151.34 seconds
Started Aug 14 05:28:34 PM PDT 24
Finished Aug 14 05:31:06 PM PDT 24
Peak memory 249340 kb
Host smart-42a7e788-76aa-4d6e-a298-ca24bd4e77c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013593406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1013593406
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2674619185
Short name T203
Test name
Test status
Simulation time 45699581920 ps
CPU time 148.31 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:28:37 PM PDT 24
Peak memory 264732 kb
Host smart-3c7a5dff-6134-4a1c-a37c-1c64a6a046f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674619185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2674619185
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2924116131
Short name T193
Test name
Test status
Simulation time 6997347494 ps
CPU time 101.94 seconds
Started Aug 14 05:28:57 PM PDT 24
Finished Aug 14 05:30:39 PM PDT 24
Peak memory 255832 kb
Host smart-a946c587-afb7-46fb-90b8-f3dd950cda54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924116131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2924116131
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3538261905
Short name T185
Test name
Test status
Simulation time 95216579871 ps
CPU time 203.26 seconds
Started Aug 14 05:26:13 PM PDT 24
Finished Aug 14 05:29:37 PM PDT 24
Peak memory 264616 kb
Host smart-69895fa0-e237-4993-996e-f70893ac676a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538261905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3538261905
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.12681130
Short name T54
Test name
Test status
Simulation time 24598728694 ps
CPU time 127.31 seconds
Started Aug 14 05:28:29 PM PDT 24
Finished Aug 14 05:30:36 PM PDT 24
Peak memory 273748 kb
Host smart-fe43dfd5-6f14-44f0-a82c-bf2b9b118bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12681130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.12681130
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1658974902
Short name T326
Test name
Test status
Simulation time 11830556 ps
CPU time 0.71 seconds
Started Aug 14 05:26:56 PM PDT 24
Finished Aug 14 05:26:57 PM PDT 24
Peak memory 205556 kb
Host smart-462c14fe-7aba-4f20-8eb1-3492e855c6e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658974902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1658974902
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2991176297
Short name T181
Test name
Test status
Simulation time 571094116 ps
CPU time 14.05 seconds
Started Aug 14 04:42:34 PM PDT 24
Finished Aug 14 04:42:48 PM PDT 24
Peak memory 215988 kb
Host smart-1d5ea37a-8ba2-4978-b102-f0ccc7c9526f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991176297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2991176297
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2687865125
Short name T778
Test name
Test status
Simulation time 27723462887 ps
CPU time 202.29 seconds
Started Aug 14 05:28:03 PM PDT 24
Finished Aug 14 05:31:26 PM PDT 24
Peak memory 265832 kb
Host smart-882c5db8-15cc-41e4-a3aa-c50fccd0f392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687865125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2687865125
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1727089640
Short name T317
Test name
Test status
Simulation time 503267098 ps
CPU time 3.83 seconds
Started Aug 14 05:27:13 PM PDT 24
Finished Aug 14 05:27:17 PM PDT 24
Peak memory 216460 kb
Host smart-659c62aa-19fb-468f-9cad-f9b1a177a8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727089640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1727089640
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2700919359
Short name T283
Test name
Test status
Simulation time 6473861201 ps
CPU time 135.77 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:28:06 PM PDT 24
Peak memory 261896 kb
Host smart-c46e0341-ab12-44ff-8aa7-d7c3c615f13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700919359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2700919359
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4203830810
Short name T300
Test name
Test status
Simulation time 445689966 ps
CPU time 8.02 seconds
Started Aug 14 05:27:51 PM PDT 24
Finished Aug 14 05:28:00 PM PDT 24
Peak memory 241124 kb
Host smart-571b5d1a-afc3-45d6-8c0a-1cffeafc6c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203830810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4203830810
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3661806228
Short name T114
Test name
Test status
Simulation time 299567056 ps
CPU time 5.08 seconds
Started Aug 14 04:43:05 PM PDT 24
Finished Aug 14 04:43:15 PM PDT 24
Peak memory 217208 kb
Host smart-45d119b5-1f6e-4f84-baed-89bff8ef936e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661806228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3661806228
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.620867733
Short name T274
Test name
Test status
Simulation time 21437243802 ps
CPU time 132.45 seconds
Started Aug 14 05:26:46 PM PDT 24
Finished Aug 14 05:28:58 PM PDT 24
Peak memory 251844 kb
Host smart-7ed355bf-b06e-4364-846e-91561281d116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620867733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.620867733
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2488126599
Short name T1149
Test name
Test status
Simulation time 3486050342 ps
CPU time 21.84 seconds
Started Aug 14 04:42:43 PM PDT 24
Finished Aug 14 04:43:05 PM PDT 24
Peak memory 215212 kb
Host smart-e0d672a0-6cef-4a79-9d88-71f10585e59c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488126599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2488126599
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1621695106
Short name T144
Test name
Test status
Simulation time 41774861325 ps
CPU time 155.77 seconds
Started Aug 14 05:25:40 PM PDT 24
Finished Aug 14 05:28:16 PM PDT 24
Peak memory 260412 kb
Host smart-c3f41073-1ae9-41e6-941b-8609949af3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621695106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1621695106
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.85770767
Short name T279
Test name
Test status
Simulation time 63879584746 ps
CPU time 106.08 seconds
Started Aug 14 05:26:36 PM PDT 24
Finished Aug 14 05:28:22 PM PDT 24
Peak memory 256320 kb
Host smart-b4d6833d-1205-4bab-9cfe-e07f1f572e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85770767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.85770767
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2815747085
Short name T318
Test name
Test status
Simulation time 56634677604 ps
CPU time 543.25 seconds
Started Aug 14 05:26:37 PM PDT 24
Finished Aug 14 05:35:40 PM PDT 24
Peak memory 265988 kb
Host smart-159a5d46-b007-459a-99f3-8f79165f8dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815747085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2815747085
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3250312003
Short name T711
Test name
Test status
Simulation time 558563904 ps
CPU time 14.83 seconds
Started Aug 14 05:27:33 PM PDT 24
Finished Aug 14 05:27:48 PM PDT 24
Peak memory 234392 kb
Host smart-d7976813-d76d-4b22-b1e5-c159d57f7674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250312003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3250312003
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.85982867
Short name T33
Test name
Test status
Simulation time 200327380426 ps
CPU time 447.76 seconds
Started Aug 14 05:26:48 PM PDT 24
Finished Aug 14 05:34:16 PM PDT 24
Peak memory 284800 kb
Host smart-a2e3ffe1-575a-4349-b2c8-1598f4609258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85982867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress
_all.85982867
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.758660504
Short name T121
Test name
Test status
Simulation time 733486954 ps
CPU time 13.66 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:29:08 PM PDT 24
Peak memory 237600 kb
Host smart-72778a1e-abe2-4fe7-a5cd-6162f0782519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758660504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.758660504
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2154525061
Short name T176
Test name
Test status
Simulation time 6699462541 ps
CPU time 20.52 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:43:23 PM PDT 24
Peak memory 216036 kb
Host smart-307b4748-edbd-4283-8d99-984d982c7e8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154525061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2154525061
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.365708060
Short name T273
Test name
Test status
Simulation time 10019415633 ps
CPU time 97.01 seconds
Started Aug 14 05:25:30 PM PDT 24
Finished Aug 14 05:27:07 PM PDT 24
Peak memory 265780 kb
Host smart-588c012c-6989-4baf-8df6-b530481de719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365708060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.365708060
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2430696069
Short name T301
Test name
Test status
Simulation time 377615965 ps
CPU time 10.83 seconds
Started Aug 14 05:26:39 PM PDT 24
Finished Aug 14 05:26:50 PM PDT 24
Peak memory 241088 kb
Host smart-48393a7c-c12e-42f6-a55c-e8cc43f904b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430696069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2430696069
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.981956712
Short name T914
Test name
Test status
Simulation time 189569396 ps
CPU time 5.65 seconds
Started Aug 14 05:26:51 PM PDT 24
Finished Aug 14 05:26:56 PM PDT 24
Peak memory 224744 kb
Host smart-1351befa-8a4f-469d-afcc-c0d16204955c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981956712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.981956712
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3301878391
Short name T657
Test name
Test status
Simulation time 69784214426 ps
CPU time 82.83 seconds
Started Aug 14 05:25:29 PM PDT 24
Finished Aug 14 05:26:52 PM PDT 24
Peak memory 224720 kb
Host smart-ed812aa0-3d74-44b6-ba43-2990ba122f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301878391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3301878391
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.710490462
Short name T95
Test name
Test status
Simulation time 1038664018 ps
CPU time 4.37 seconds
Started Aug 14 05:25:28 PM PDT 24
Finished Aug 14 05:25:33 PM PDT 24
Peak memory 224696 kb
Host smart-0f390493-d68c-49b7-9afe-64c1f6fe54c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710490462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
710490462
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2645997613
Short name T84
Test name
Test status
Simulation time 36979694 ps
CPU time 1.17 seconds
Started Aug 14 04:42:44 PM PDT 24
Finished Aug 14 04:42:45 PM PDT 24
Peak memory 207624 kb
Host smart-83f91e9a-0da5-4a54-9908-139ee4716fb4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645997613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2645997613
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1987089705
Short name T1093
Test name
Test status
Simulation time 89526240 ps
CPU time 2.41 seconds
Started Aug 14 04:42:39 PM PDT 24
Finished Aug 14 04:42:47 PM PDT 24
Peak memory 216188 kb
Host smart-364948c4-bb58-4dc3-8d69-eaa0eb8b2ffc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987089705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1987089705
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2860986132
Short name T1074
Test name
Test status
Simulation time 115268989 ps
CPU time 8 seconds
Started Aug 14 04:42:32 PM PDT 24
Finished Aug 14 04:42:40 PM PDT 24
Peak memory 207620 kb
Host smart-d927aaa8-bd03-4e92-9e7e-49e100c010b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860986132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2860986132
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1937569200
Short name T172
Test name
Test status
Simulation time 2858498441 ps
CPU time 37.8 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:43:00 PM PDT 24
Peak memory 207664 kb
Host smart-cfd0f331-9337-4409-a24b-abbf620bde36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937569200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1937569200
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.24365220
Short name T1049
Test name
Test status
Simulation time 154812580 ps
CPU time 3.45 seconds
Started Aug 14 04:42:35 PM PDT 24
Finished Aug 14 04:42:39 PM PDT 24
Peak memory 217676 kb
Host smart-14ec4af6-6be8-4636-9cc5-452f1a5564c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24365220 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.24365220
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4251919489
Short name T132
Test name
Test status
Simulation time 85361787 ps
CPU time 2.17 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 215928 kb
Host smart-c3d91e18-1210-419a-8193-a6fd9df4ba53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251919489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
251919489
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.4240454670
Short name T1101
Test name
Test status
Simulation time 16131086 ps
CPU time 0.73 seconds
Started Aug 14 04:42:42 PM PDT 24
Finished Aug 14 04:42:43 PM PDT 24
Peak memory 204564 kb
Host smart-6730a7c0-5b5a-4d98-b03e-d11d41f2b06e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240454670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.4
240454670
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.888739463
Short name T123
Test name
Test status
Simulation time 27879259 ps
CPU time 2.13 seconds
Started Aug 14 04:42:38 PM PDT 24
Finished Aug 14 04:42:40 PM PDT 24
Peak memory 215824 kb
Host smart-5dbe8d7a-2fd3-4709-b959-19e3066ded54
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888739463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.888739463
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2570400832
Short name T1037
Test name
Test status
Simulation time 11056302 ps
CPU time 0.68 seconds
Started Aug 14 04:42:59 PM PDT 24
Finished Aug 14 04:43:00 PM PDT 24
Peak memory 204300 kb
Host smart-ae46d531-fb2a-4315-8b8a-e3acd6b2bef3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570400832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2570400832
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3608896745
Short name T1104
Test name
Test status
Simulation time 319850329 ps
CPU time 2.96 seconds
Started Aug 14 04:42:29 PM PDT 24
Finished Aug 14 04:42:32 PM PDT 24
Peak memory 215856 kb
Host smart-8a3534b7-04a2-4689-97f7-9394baca76af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608896745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3608896745
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1516727622
Short name T109
Test name
Test status
Simulation time 244069508 ps
CPU time 3.08 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 216208 kb
Host smart-7e28af79-a289-4288-b646-0858eeddfd35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516727622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
516727622
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2838509133
Short name T1119
Test name
Test status
Simulation time 363125704 ps
CPU time 8.02 seconds
Started Aug 14 04:42:38 PM PDT 24
Finished Aug 14 04:42:46 PM PDT 24
Peak memory 215952 kb
Host smart-e53a6473-c83c-4007-b563-39463e35a15b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838509133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2838509133
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1661147666
Short name T1134
Test name
Test status
Simulation time 2760886968 ps
CPU time 23 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:46 PM PDT 24
Peak memory 216076 kb
Host smart-2fafc6bb-6ca4-4a43-9a17-a9fd91edc94c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661147666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1661147666
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2628722218
Short name T1087
Test name
Test status
Simulation time 8214762041 ps
CPU time 26.26 seconds
Started Aug 14 04:42:48 PM PDT 24
Finished Aug 14 04:43:14 PM PDT 24
Peak memory 207916 kb
Host smart-0353f3e8-856a-41b0-bdf9-c6e7ff9a16bc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628722218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2628722218
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.488127004
Short name T1137
Test name
Test status
Simulation time 31048997 ps
CPU time 0.95 seconds
Started Aug 14 04:42:46 PM PDT 24
Finished Aug 14 04:42:47 PM PDT 24
Peak memory 207416 kb
Host smart-348710a7-4d74-45c8-8ec2-e80dbde4a004
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488127004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.488127004
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.127768170
Short name T118
Test name
Test status
Simulation time 64290820 ps
CPU time 1.73 seconds
Started Aug 14 04:42:24 PM PDT 24
Finished Aug 14 04:42:26 PM PDT 24
Peak memory 215916 kb
Host smart-0d394873-4cb6-43dd-a400-d768654e3150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127768170 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.127768170
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3996904183
Short name T1109
Test name
Test status
Simulation time 94267015 ps
CPU time 2.13 seconds
Started Aug 14 04:42:52 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 215896 kb
Host smart-0ec28807-9a6d-42de-98a4-81a9ae170152
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996904183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
996904183
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2555910832
Short name T1065
Test name
Test status
Simulation time 13976173 ps
CPU time 0.69 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 204316 kb
Host smart-c2b66c59-7d67-42e8-8780-6293f3ed410a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555910832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
555910832
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2242148842
Short name T1061
Test name
Test status
Simulation time 26399535 ps
CPU time 2.05 seconds
Started Aug 14 04:42:51 PM PDT 24
Finished Aug 14 04:42:53 PM PDT 24
Peak memory 215808 kb
Host smart-f178ad88-7cd6-4b27-9655-55a1062cb722
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242148842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2242148842
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2269962911
Short name T1133
Test name
Test status
Simulation time 18586339 ps
CPU time 0.66 seconds
Started Aug 14 04:42:21 PM PDT 24
Finished Aug 14 04:42:22 PM PDT 24
Peak memory 204204 kb
Host smart-89998a20-267d-4ab6-a025-982b175a20f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269962911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2269962911
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3751067822
Short name T1121
Test name
Test status
Simulation time 249920545 ps
CPU time 3.02 seconds
Started Aug 14 04:42:46 PM PDT 24
Finished Aug 14 04:42:50 PM PDT 24
Peak memory 215888 kb
Host smart-d3534606-f254-44dc-af9e-7dcd97c665d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751067822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3751067822
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1637138800
Short name T100
Test name
Test status
Simulation time 77272904 ps
CPU time 2.66 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 216132 kb
Host smart-dde086fd-b019-41a4-91c0-3144e658405c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637138800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
637138800
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1504740475
Short name T1073
Test name
Test status
Simulation time 1224280188 ps
CPU time 18.41 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:42 PM PDT 24
Peak memory 216164 kb
Host smart-427da442-5898-4324-9c7c-82cf695985f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504740475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1504740475
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3647081724
Short name T158
Test name
Test status
Simulation time 567838146 ps
CPU time 3.83 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:43:07 PM PDT 24
Peak memory 217796 kb
Host smart-b65c6b30-4993-436f-8dcb-a35d3536e37e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647081724 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3647081724
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.663687448
Short name T125
Test name
Test status
Simulation time 231657745 ps
CPU time 1.23 seconds
Started Aug 14 04:43:02 PM PDT 24
Finished Aug 14 04:43:03 PM PDT 24
Peak memory 215828 kb
Host smart-7252f95b-bdbe-4480-bbb8-a4b8fbaef7b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663687448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.663687448
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2412332167
Short name T1030
Test name
Test status
Simulation time 13824068 ps
CPU time 0.72 seconds
Started Aug 14 04:42:50 PM PDT 24
Finished Aug 14 04:42:51 PM PDT 24
Peak memory 204320 kb
Host smart-0d25922a-514d-400c-b104-e791085007b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412332167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2412332167
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2405108038
Short name T147
Test name
Test status
Simulation time 486793428 ps
CPU time 3.7 seconds
Started Aug 14 04:42:43 PM PDT 24
Finished Aug 14 04:42:47 PM PDT 24
Peak memory 216016 kb
Host smart-98861cdd-eb0c-4a5b-be68-05415cfb862f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405108038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2405108038
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.575510787
Short name T1089
Test name
Test status
Simulation time 150240436 ps
CPU time 2.34 seconds
Started Aug 14 04:42:52 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 216136 kb
Host smart-44f6624a-4390-4d9a-a46f-68c2a992fa8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575510787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.575510787
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1853942314
Short name T180
Test name
Test status
Simulation time 474808533 ps
CPU time 17.69 seconds
Started Aug 14 04:42:46 PM PDT 24
Finished Aug 14 04:43:04 PM PDT 24
Peak memory 215792 kb
Host smart-194e8cd3-bf7e-4462-8f8c-a30010596660
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853942314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1853942314
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2455524734
Short name T98
Test name
Test status
Simulation time 47338251 ps
CPU time 1.92 seconds
Started Aug 14 04:42:55 PM PDT 24
Finished Aug 14 04:42:57 PM PDT 24
Peak memory 215936 kb
Host smart-77b9bf8e-7006-4314-91bb-a6fa71806d03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455524734 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2455524734
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2254966570
Short name T1146
Test name
Test status
Simulation time 763365446 ps
CPU time 1.89 seconds
Started Aug 14 04:42:39 PM PDT 24
Finished Aug 14 04:42:46 PM PDT 24
Peak memory 215948 kb
Host smart-8a41945a-25f7-4eb5-bbfb-ca9e47fcab63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254966570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2254966570
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3569904916
Short name T1075
Test name
Test status
Simulation time 16220866 ps
CPU time 0.72 seconds
Started Aug 14 04:42:45 PM PDT 24
Finished Aug 14 04:42:45 PM PDT 24
Peak memory 204372 kb
Host smart-a677855f-1fcc-441e-a9fa-89eed293e9f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569904916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3569904916
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1320924673
Short name T1064
Test name
Test status
Simulation time 57953736 ps
CPU time 3.54 seconds
Started Aug 14 04:42:42 PM PDT 24
Finished Aug 14 04:42:45 PM PDT 24
Peak memory 215900 kb
Host smart-c473b8e1-3a94-4811-9dc1-0fab20dd0412
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320924673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1320924673
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4234834388
Short name T1082
Test name
Test status
Simulation time 138088431 ps
CPU time 4.41 seconds
Started Aug 14 04:42:45 PM PDT 24
Finished Aug 14 04:42:49 PM PDT 24
Peak memory 216044 kb
Host smart-c01c0136-88fa-4412-bc8c-81698573cb11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234834388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4234834388
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2625025531
Short name T1144
Test name
Test status
Simulation time 393503268 ps
CPU time 12.44 seconds
Started Aug 14 04:42:47 PM PDT 24
Finished Aug 14 04:43:00 PM PDT 24
Peak memory 216048 kb
Host smart-d0d7d3f7-e5d8-43c1-8382-bd2e8d534647
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625025531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2625025531
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.128943169
Short name T1077
Test name
Test status
Simulation time 95371953 ps
CPU time 3.26 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:42:56 PM PDT 24
Peak memory 217840 kb
Host smart-138b9234-2e85-47d7-b4c4-23ec9e1d2e05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128943169 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.128943169
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4116370106
Short name T1132
Test name
Test status
Simulation time 105712640 ps
CPU time 1.67 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 207748 kb
Host smart-5a0d6056-65ef-40b4-a64c-7ce2b72d1093
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116370106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4116370106
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.271539720
Short name T1029
Test name
Test status
Simulation time 28657235 ps
CPU time 0.79 seconds
Started Aug 14 04:42:50 PM PDT 24
Finished Aug 14 04:42:51 PM PDT 24
Peak memory 204336 kb
Host smart-0359d4f3-6f81-4769-add1-6569f80f3003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271539720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.271539720
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1168306949
Short name T1079
Test name
Test status
Simulation time 1623641755 ps
CPU time 4.4 seconds
Started Aug 14 04:42:48 PM PDT 24
Finished Aug 14 04:42:53 PM PDT 24
Peak memory 215984 kb
Host smart-9af1e29d-5853-428f-93f7-89d293ad74e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168306949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1168306949
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1959581187
Short name T182
Test name
Test status
Simulation time 1261927008 ps
CPU time 17.78 seconds
Started Aug 14 04:42:36 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 215860 kb
Host smart-5ea1658a-9a68-422a-95b9-a226b997254f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959581187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1959581187
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1079550087
Short name T1148
Test name
Test status
Simulation time 393344365 ps
CPU time 3.89 seconds
Started Aug 14 04:42:48 PM PDT 24
Finished Aug 14 04:42:51 PM PDT 24
Peak memory 219236 kb
Host smart-a748c647-7479-4143-b38e-4d16f3d82a78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079550087 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1079550087
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3452408631
Short name T1126
Test name
Test status
Simulation time 48824454 ps
CPU time 1.24 seconds
Started Aug 14 04:43:10 PM PDT 24
Finished Aug 14 04:43:11 PM PDT 24
Peak memory 215916 kb
Host smart-d9e0fbb8-1515-4038-9f6a-0b2758c51bb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452408631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3452408631
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2905045391
Short name T1040
Test name
Test status
Simulation time 39747819 ps
CPU time 0.75 seconds
Started Aug 14 04:42:48 PM PDT 24
Finished Aug 14 04:42:49 PM PDT 24
Peak memory 204560 kb
Host smart-def8a5fa-94ba-487d-a84a-d7411c22ed42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905045391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2905045391
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3210185758
Short name T1130
Test name
Test status
Simulation time 813789601 ps
CPU time 2.97 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:43:00 PM PDT 24
Peak memory 215812 kb
Host smart-56bf9835-2409-4101-954f-1246f2976e13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210185758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3210185758
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.866178357
Short name T111
Test name
Test status
Simulation time 524674742 ps
CPU time 3.62 seconds
Started Aug 14 04:42:45 PM PDT 24
Finished Aug 14 04:42:49 PM PDT 24
Peak memory 216112 kb
Host smart-72854d8f-1513-4127-9449-f94f4d5e3973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866178357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.866178357
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3854323704
Short name T1090
Test name
Test status
Simulation time 104488795 ps
CPU time 6.74 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:11 PM PDT 24
Peak memory 216600 kb
Host smart-09b68993-9970-4b0f-8eb7-1bfec6f51ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854323704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3854323704
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3794970625
Short name T1083
Test name
Test status
Simulation time 241535884 ps
CPU time 3.54 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:31 PM PDT 24
Peak memory 217700 kb
Host smart-4b5eb570-6018-46af-8a33-58ac44508e10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794970625 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3794970625
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2189657879
Short name T1067
Test name
Test status
Simulation time 54807867 ps
CPU time 1.79 seconds
Started Aug 14 04:42:36 PM PDT 24
Finished Aug 14 04:42:38 PM PDT 24
Peak memory 215884 kb
Host smart-152d4a52-4209-44ab-b249-4a6e23668c70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189657879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2189657879
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2641578785
Short name T1088
Test name
Test status
Simulation time 62427910 ps
CPU time 0.75 seconds
Started Aug 14 04:42:28 PM PDT 24
Finished Aug 14 04:42:28 PM PDT 24
Peak memory 204252 kb
Host smart-9a6bd1a5-2721-42a4-a4fd-b327f40fc3bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641578785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2641578785
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.388922220
Short name T1069
Test name
Test status
Simulation time 236051264 ps
CPU time 3.93 seconds
Started Aug 14 04:42:55 PM PDT 24
Finished Aug 14 04:42:59 PM PDT 24
Peak memory 215812 kb
Host smart-2399c54c-dd1e-41c1-b50f-7842501098a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388922220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.388922220
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.977804973
Short name T1099
Test name
Test status
Simulation time 220331907 ps
CPU time 5.28 seconds
Started Aug 14 04:42:55 PM PDT 24
Finished Aug 14 04:43:01 PM PDT 24
Peak memory 216172 kb
Host smart-4e7cbcb3-1d38-44e6-9bed-39e2f0155900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977804973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.977804973
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2764064544
Short name T1098
Test name
Test status
Simulation time 59405576 ps
CPU time 1.81 seconds
Started Aug 14 04:42:49 PM PDT 24
Finished Aug 14 04:42:51 PM PDT 24
Peak memory 217084 kb
Host smart-d0b615e1-fbae-492a-af67-60618ac23a53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764064544 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2764064544
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.717431349
Short name T1041
Test name
Test status
Simulation time 107191188 ps
CPU time 1.28 seconds
Started Aug 14 04:42:47 PM PDT 24
Finished Aug 14 04:42:48 PM PDT 24
Peak memory 215884 kb
Host smart-a9760e27-76fb-4a34-bef6-a2caf3f4e3ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717431349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.717431349
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3769428781
Short name T1108
Test name
Test status
Simulation time 13888848 ps
CPU time 0.74 seconds
Started Aug 14 04:42:46 PM PDT 24
Finished Aug 14 04:42:47 PM PDT 24
Peak memory 204692 kb
Host smart-7c3655eb-67c1-4f36-8531-2a83a70efe1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769428781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3769428781
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1424962852
Short name T1107
Test name
Test status
Simulation time 44884687 ps
CPU time 2.69 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:06 PM PDT 24
Peak memory 215900 kb
Host smart-5058e73a-9f2f-4d3e-80eb-e5f1c61c2bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424962852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1424962852
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2569148896
Short name T112
Test name
Test status
Simulation time 653321823 ps
CPU time 4.38 seconds
Started Aug 14 04:42:34 PM PDT 24
Finished Aug 14 04:42:39 PM PDT 24
Peak memory 216988 kb
Host smart-ca54c2ca-20a2-437c-86af-6ca0251435a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569148896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2569148896
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2921888160
Short name T183
Test name
Test status
Simulation time 303307183 ps
CPU time 18.52 seconds
Started Aug 14 04:42:49 PM PDT 24
Finished Aug 14 04:43:07 PM PDT 24
Peak memory 215968 kb
Host smart-9193506d-830e-4e1a-9d28-33da164327fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921888160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2921888160
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2611773798
Short name T1066
Test name
Test status
Simulation time 195399094 ps
CPU time 2.6 seconds
Started Aug 14 04:42:49 PM PDT 24
Finished Aug 14 04:42:52 PM PDT 24
Peak memory 217492 kb
Host smart-c920bf80-62a9-47d8-99c8-37549ddbd60c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611773798 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2611773798
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1567459324
Short name T130
Test name
Test status
Simulation time 1382607400 ps
CPU time 2.51 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 215828 kb
Host smart-e999828b-5d0e-4982-adb3-4fc969e0d296
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567459324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1567459324
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2188846295
Short name T1027
Test name
Test status
Simulation time 51572388 ps
CPU time 0.74 seconds
Started Aug 14 04:42:52 PM PDT 24
Finished Aug 14 04:42:52 PM PDT 24
Peak memory 204580 kb
Host smart-b51b35f9-b65f-49f3-92a1-0c84c594e6b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188846295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2188846295
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3108916230
Short name T1036
Test name
Test status
Simulation time 113646130 ps
CPU time 3.98 seconds
Started Aug 14 04:42:37 PM PDT 24
Finished Aug 14 04:42:41 PM PDT 24
Peak memory 216016 kb
Host smart-15014069-ac91-4f30-8948-668877960eb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108916230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3108916230
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.233572823
Short name T1122
Test name
Test status
Simulation time 250842765 ps
CPU time 5.69 seconds
Started Aug 14 04:42:35 PM PDT 24
Finished Aug 14 04:42:41 PM PDT 24
Peak memory 216352 kb
Host smart-4eef4f76-a555-4b8c-90b0-3771c63202cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233572823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.233572823
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2964943273
Short name T102
Test name
Test status
Simulation time 389976385 ps
CPU time 6.53 seconds
Started Aug 14 04:42:58 PM PDT 24
Finished Aug 14 04:43:04 PM PDT 24
Peak memory 215932 kb
Host smart-0fbf0e57-8185-43cf-a3df-7c8e81df9b4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964943273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2964943273
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3509096521
Short name T1127
Test name
Test status
Simulation time 139822044 ps
CPU time 3.21 seconds
Started Aug 14 04:42:45 PM PDT 24
Finished Aug 14 04:42:48 PM PDT 24
Peak memory 218716 kb
Host smart-b1ee8249-01f9-4499-9606-b6feb4e873e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509096521 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3509096521
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.429008044
Short name T1117
Test name
Test status
Simulation time 37876951 ps
CPU time 1.38 seconds
Started Aug 14 04:42:51 PM PDT 24
Finished Aug 14 04:42:52 PM PDT 24
Peak memory 216004 kb
Host smart-72bfe55d-7f8d-437f-a12e-4809713e0ca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429008044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.429008044
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2187070032
Short name T1124
Test name
Test status
Simulation time 58359737 ps
CPU time 0.76 seconds
Started Aug 14 04:42:56 PM PDT 24
Finished Aug 14 04:42:57 PM PDT 24
Peak memory 204320 kb
Host smart-4aff0d32-16c7-43a3-9282-69e945f10341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187070032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2187070032
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3898494620
Short name T1105
Test name
Test status
Simulation time 144387433 ps
CPU time 3.12 seconds
Started Aug 14 04:42:40 PM PDT 24
Finished Aug 14 04:42:43 PM PDT 24
Peak memory 215784 kb
Host smart-1c68f7ef-f7a0-493a-a103-8b2f0919c0ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898494620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3898494620
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2735451368
Short name T1125
Test name
Test status
Simulation time 1871585237 ps
CPU time 20.37 seconds
Started Aug 14 04:42:49 PM PDT 24
Finished Aug 14 04:43:09 PM PDT 24
Peak memory 216732 kb
Host smart-246b7e4b-f823-47d2-9218-4b58f2166fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735451368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2735451368
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.731984518
Short name T1081
Test name
Test status
Simulation time 226850367 ps
CPU time 2.82 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:42:56 PM PDT 24
Peak memory 217076 kb
Host smart-c37f99cc-d76c-435c-9c79-1d8d0ff6f654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731984518 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.731984518
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1443800011
Short name T129
Test name
Test status
Simulation time 41481977 ps
CPU time 2.66 seconds
Started Aug 14 04:42:56 PM PDT 24
Finished Aug 14 04:42:59 PM PDT 24
Peak memory 207604 kb
Host smart-ca570063-cf1b-4078-9386-db6178e1e022
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443800011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1443800011
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2763081978
Short name T1076
Test name
Test status
Simulation time 37777981 ps
CPU time 0.68 seconds
Started Aug 14 04:42:20 PM PDT 24
Finished Aug 14 04:42:21 PM PDT 24
Peak memory 204680 kb
Host smart-ff5b888d-46f5-4a2f-ac27-5e4587308794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763081978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2763081978
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.212629164
Short name T1143
Test name
Test status
Simulation time 210058147 ps
CPU time 1.63 seconds
Started Aug 14 04:42:36 PM PDT 24
Finished Aug 14 04:42:37 PM PDT 24
Peak memory 215900 kb
Host smart-633343ae-6dfc-4834-9b7b-355cf7539919
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212629164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.212629164
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2877375185
Short name T113
Test name
Test status
Simulation time 238200765 ps
CPU time 3.68 seconds
Started Aug 14 04:42:42 PM PDT 24
Finished Aug 14 04:42:46 PM PDT 24
Peak memory 216144 kb
Host smart-6b304c8f-6dd0-4fad-9d1a-841d00fdcdc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877375185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2877375185
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2572957133
Short name T1120
Test name
Test status
Simulation time 4257456786 ps
CPU time 20.38 seconds
Started Aug 14 04:42:38 PM PDT 24
Finished Aug 14 04:42:59 PM PDT 24
Peak memory 216092 kb
Host smart-a764bf1f-b521-4acb-8b2e-16c115d63b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572957133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2572957133
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2439274144
Short name T1095
Test name
Test status
Simulation time 241256698 ps
CPU time 3.45 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:42:57 PM PDT 24
Peak memory 218640 kb
Host smart-a9d5ecab-5b66-4b62-b941-46517ec1d9f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439274144 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2439274144
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1053924636
Short name T155
Test name
Test status
Simulation time 263805949 ps
CPU time 1.37 seconds
Started Aug 14 04:42:55 PM PDT 24
Finished Aug 14 04:42:56 PM PDT 24
Peak memory 207692 kb
Host smart-992d9320-47b2-4fd2-b14c-d748b4eef906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053924636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1053924636
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2872649246
Short name T1055
Test name
Test status
Simulation time 33652174 ps
CPU time 0.72 seconds
Started Aug 14 04:43:01 PM PDT 24
Finished Aug 14 04:43:02 PM PDT 24
Peak memory 204676 kb
Host smart-6f2d9cee-8dd0-428f-b256-e2de72ce429c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872649246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2872649246
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2941841116
Short name T1113
Test name
Test status
Simulation time 1648650579 ps
CPU time 4.27 seconds
Started Aug 14 04:42:56 PM PDT 24
Finished Aug 14 04:43:01 PM PDT 24
Peak memory 215892 kb
Host smart-ada06d33-2c3e-44d0-83d1-a8c5dafab330
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941841116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2941841116
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.755603442
Short name T97
Test name
Test status
Simulation time 53509838 ps
CPU time 1.59 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:43:05 PM PDT 24
Peak memory 216116 kb
Host smart-b7fdcfa1-bdda-4a0b-a023-d99b4bf79dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755603442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.755603442
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1324297865
Short name T184
Test name
Test status
Simulation time 2862973342 ps
CPU time 6.9 seconds
Started Aug 14 04:43:05 PM PDT 24
Finished Aug 14 04:43:12 PM PDT 24
Peak memory 215916 kb
Host smart-63811b1b-5177-450b-ba8c-50e75e67a7c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324297865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1324297865
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.408759799
Short name T1116
Test name
Test status
Simulation time 881010117 ps
CPU time 13.34 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:17 PM PDT 24
Peak memory 215816 kb
Host smart-2fe4bd82-b282-43a9-82ec-a3476d264783
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408759799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.408759799
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2216083426
Short name T128
Test name
Test status
Simulation time 7503320148 ps
CPU time 25.5 seconds
Started Aug 14 04:42:34 PM PDT 24
Finished Aug 14 04:42:59 PM PDT 24
Peak memory 207824 kb
Host smart-ed9f1e9b-2374-4773-b712-653d5af62d02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216083426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2216083426
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.564170968
Short name T1118
Test name
Test status
Simulation time 73618196 ps
CPU time 1.13 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 207568 kb
Host smart-a4cbb026-8dee-45bb-b5b9-322d649be963
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564170968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.564170968
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.63968531
Short name T1145
Test name
Test status
Simulation time 277114393 ps
CPU time 2.38 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:42:55 PM PDT 24
Peak memory 218456 kb
Host smart-e79aacb1-b2ad-47b5-b375-94427b391cd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63968531 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.63968531
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3109544029
Short name T1068
Test name
Test status
Simulation time 48592837 ps
CPU time 0.74 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:23 PM PDT 24
Peak memory 204256 kb
Host smart-68ce0a2b-544c-4f32-a42a-e0a4b9a93de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109544029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
109544029
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.59667616
Short name T126
Test name
Test status
Simulation time 34468748 ps
CPU time 1.28 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:25 PM PDT 24
Peak memory 215892 kb
Host smart-6bc5959d-f549-447e-a9ee-381a86c66760
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59667616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_d
evice_mem_partial_access.59667616
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3179984693
Short name T1115
Test name
Test status
Simulation time 18926797 ps
CPU time 0.64 seconds
Started Aug 14 04:42:32 PM PDT 24
Finished Aug 14 04:42:33 PM PDT 24
Peak memory 204212 kb
Host smart-a500b5fb-9566-431c-9765-a453b57f11e8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179984693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3179984693
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.889658590
Short name T1097
Test name
Test status
Simulation time 83544286 ps
CPU time 1.89 seconds
Started Aug 14 04:42:37 PM PDT 24
Finished Aug 14 04:42:39 PM PDT 24
Peak memory 215964 kb
Host smart-67957e50-254b-4696-8db8-d57cad3b5731
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889658590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.889658590
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2481280495
Short name T1094
Test name
Test status
Simulation time 278255796 ps
CPU time 3.98 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:26 PM PDT 24
Peak memory 217076 kb
Host smart-540f4689-af97-4c12-9fdf-889864e42f48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481280495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
481280495
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1866071998
Short name T1028
Test name
Test status
Simulation time 15129934 ps
CPU time 0.76 seconds
Started Aug 14 04:42:54 PM PDT 24
Finished Aug 14 04:42:55 PM PDT 24
Peak memory 204316 kb
Host smart-4983f753-0281-40d5-a41a-0e8081622289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866071998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1866071998
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.103300086
Short name T1033
Test name
Test status
Simulation time 107273961 ps
CPU time 0.71 seconds
Started Aug 14 04:43:02 PM PDT 24
Finished Aug 14 04:43:03 PM PDT 24
Peak memory 204676 kb
Host smart-b9b27465-1e19-4ea6-9be4-de47e659bfe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103300086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.103300086
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1632877661
Short name T1054
Test name
Test status
Simulation time 70982254 ps
CPU time 0.75 seconds
Started Aug 14 04:43:01 PM PDT 24
Finished Aug 14 04:43:01 PM PDT 24
Peak memory 204676 kb
Host smart-8f0e76f5-7a4c-428b-a662-f2da594bfb14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632877661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1632877661
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2280024130
Short name T1091
Test name
Test status
Simulation time 17893746 ps
CPU time 0.73 seconds
Started Aug 14 04:43:02 PM PDT 24
Finished Aug 14 04:43:03 PM PDT 24
Peak memory 204348 kb
Host smart-edaa7d80-12cb-40ef-b316-3b86066e455d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280024130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2280024130
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3003276145
Short name T1056
Test name
Test status
Simulation time 34183026 ps
CPU time 0.76 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:43:04 PM PDT 24
Peak memory 204252 kb
Host smart-44eae9e5-d393-465b-8858-2c3552369c41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003276145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3003276145
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.161695118
Short name T1047
Test name
Test status
Simulation time 87392848 ps
CPU time 0.74 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:42:58 PM PDT 24
Peak memory 204656 kb
Host smart-bf191040-b298-4abe-b3d6-34ae1d3e0f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161695118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.161695118
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3247643798
Short name T1139
Test name
Test status
Simulation time 22448382 ps
CPU time 0.7 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 204208 kb
Host smart-19a4b886-f830-453f-82c8-f0a4813d8d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247643798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3247643798
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2185995573
Short name T1140
Test name
Test status
Simulation time 36488795 ps
CPU time 0.68 seconds
Started Aug 14 04:43:04 PM PDT 24
Finished Aug 14 04:43:05 PM PDT 24
Peak memory 204236 kb
Host smart-1b549cff-8372-42c1-b24c-8fcb2da96520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185995573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2185995573
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.486465090
Short name T1147
Test name
Test status
Simulation time 51439121 ps
CPU time 0.78 seconds
Started Aug 14 04:43:01 PM PDT 24
Finished Aug 14 04:43:02 PM PDT 24
Peak memory 204356 kb
Host smart-221b6bfe-a022-4bb3-95d7-20e5ce6643c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486465090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.486465090
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2058987935
Short name T1045
Test name
Test status
Simulation time 14377609 ps
CPU time 0.71 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 204284 kb
Host smart-c3c53b07-efd4-4747-a4fd-53af81913750
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058987935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2058987935
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2150712516
Short name T1100
Test name
Test status
Simulation time 110878902 ps
CPU time 7.81 seconds
Started Aug 14 04:42:40 PM PDT 24
Finished Aug 14 04:42:48 PM PDT 24
Peak memory 207736 kb
Host smart-9c93f443-e9b1-433d-94ea-c45d9365333a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150712516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2150712516
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3621497057
Short name T133
Test name
Test status
Simulation time 1236571996 ps
CPU time 22.59 seconds
Started Aug 14 04:42:39 PM PDT 24
Finished Aug 14 04:43:01 PM PDT 24
Peak memory 207692 kb
Host smart-0480d12b-372a-469a-96f4-c29f873852e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621497057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3621497057
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3455385626
Short name T85
Test name
Test status
Simulation time 127814777 ps
CPU time 1.19 seconds
Started Aug 14 04:42:55 PM PDT 24
Finished Aug 14 04:42:56 PM PDT 24
Peak memory 207576 kb
Host smart-0fc7003c-1dfd-40f4-947f-2e188457e4bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455385626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3455385626
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3874174677
Short name T117
Test name
Test status
Simulation time 449389619 ps
CPU time 2.86 seconds
Started Aug 14 04:42:50 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 217496 kb
Host smart-59f14194-8d31-413f-920d-8d778ae20948
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874174677 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3874174677
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.968494680
Short name T124
Test name
Test status
Simulation time 63107042 ps
CPU time 1.3 seconds
Started Aug 14 04:42:56 PM PDT 24
Finished Aug 14 04:42:57 PM PDT 24
Peak memory 207788 kb
Host smart-a5c6f9cd-77bb-49f4-82d3-8aa0056fe5ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968494680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.968494680
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.933049246
Short name T1062
Test name
Test status
Simulation time 13814190 ps
CPU time 0.73 seconds
Started Aug 14 04:42:44 PM PDT 24
Finished Aug 14 04:42:45 PM PDT 24
Peak memory 204236 kb
Host smart-315f03c3-9412-41a5-bf73-5714f974ac10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933049246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.933049246
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3524786542
Short name T1072
Test name
Test status
Simulation time 19453719 ps
CPU time 1.35 seconds
Started Aug 14 04:43:05 PM PDT 24
Finished Aug 14 04:43:07 PM PDT 24
Peak memory 215904 kb
Host smart-d6495485-3511-4ba8-9500-17dd9ec687c9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524786542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3524786542
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.828818509
Short name T1070
Test name
Test status
Simulation time 10278580 ps
CPU time 0.67 seconds
Started Aug 14 04:43:01 PM PDT 24
Finished Aug 14 04:43:02 PM PDT 24
Peak memory 204336 kb
Host smart-57ed75e2-a34f-4b1e-b932-3162a7f6e291
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828818509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.828818509
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1814906010
Short name T1058
Test name
Test status
Simulation time 709529301 ps
CPU time 1.84 seconds
Started Aug 14 04:42:45 PM PDT 24
Finished Aug 14 04:42:47 PM PDT 24
Peak memory 215944 kb
Host smart-deb9c801-f899-4350-9476-69c64fe63b0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814906010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1814906010
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.342151709
Short name T116
Test name
Test status
Simulation time 94774695 ps
CPU time 2.51 seconds
Started Aug 14 04:42:30 PM PDT 24
Finished Aug 14 04:42:33 PM PDT 24
Peak memory 216132 kb
Host smart-86f4ade5-0f65-478a-b0c8-768e45155568
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342151709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.342151709
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1681593312
Short name T1092
Test name
Test status
Simulation time 31383830 ps
CPU time 0.68 seconds
Started Aug 14 04:42:58 PM PDT 24
Finished Aug 14 04:42:58 PM PDT 24
Peak memory 204552 kb
Host smart-2cceb678-bb52-48bd-8ee9-83eac4d3b168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681593312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1681593312
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1677000590
Short name T1102
Test name
Test status
Simulation time 144534026 ps
CPU time 0.78 seconds
Started Aug 14 04:42:58 PM PDT 24
Finished Aug 14 04:42:59 PM PDT 24
Peak memory 204348 kb
Host smart-9952b5ca-45c7-4030-bd79-a15df431bbbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677000590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1677000590
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4152421445
Short name T1034
Test name
Test status
Simulation time 35315760 ps
CPU time 0.71 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:42:58 PM PDT 24
Peak memory 204256 kb
Host smart-380de784-4ab9-44f9-b1d2-33acf59b99b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152421445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
4152421445
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.173545974
Short name T1051
Test name
Test status
Simulation time 22817478 ps
CPU time 0.7 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:43:04 PM PDT 24
Peak memory 204348 kb
Host smart-174b7f09-18e7-4556-b0ba-4084a2976e8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173545974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.173545974
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1561757622
Short name T1071
Test name
Test status
Simulation time 23254827 ps
CPU time 0.69 seconds
Started Aug 14 04:42:56 PM PDT 24
Finished Aug 14 04:42:57 PM PDT 24
Peak memory 204368 kb
Host smart-ba1cc833-0584-4af2-8ea5-c5862ac596fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561757622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1561757622
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2406494713
Short name T1044
Test name
Test status
Simulation time 53443275 ps
CPU time 0.72 seconds
Started Aug 14 04:42:59 PM PDT 24
Finished Aug 14 04:43:00 PM PDT 24
Peak memory 204316 kb
Host smart-5c4be6f6-a3e4-444d-b15b-52515c43769d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406494713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2406494713
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2375310743
Short name T1078
Test name
Test status
Simulation time 39632314 ps
CPU time 0.69 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 204348 kb
Host smart-edd793d1-51ab-4b3d-814a-c633b9804574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375310743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2375310743
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3984341900
Short name T1123
Test name
Test status
Simulation time 10609004 ps
CPU time 0.7 seconds
Started Aug 14 04:42:51 PM PDT 24
Finished Aug 14 04:42:51 PM PDT 24
Peak memory 204664 kb
Host smart-8ec3071a-57c6-4ef0-a028-39e1a818661c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984341900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3984341900
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2616547275
Short name T1050
Test name
Test status
Simulation time 17611814 ps
CPU time 0.76 seconds
Started Aug 14 04:42:55 PM PDT 24
Finished Aug 14 04:42:56 PM PDT 24
Peak memory 204264 kb
Host smart-fa42a7ba-04b0-4090-98ef-380b0b4a7097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616547275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2616547275
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.592681348
Short name T1032
Test name
Test status
Simulation time 32286525 ps
CPU time 0.73 seconds
Started Aug 14 04:42:51 PM PDT 24
Finished Aug 14 04:42:51 PM PDT 24
Peak memory 204332 kb
Host smart-22ae343e-db6f-4b98-bc49-f0e57538ad68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592681348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.592681348
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3854746620
Short name T1128
Test name
Test status
Simulation time 112128967 ps
CPU time 7.27 seconds
Started Aug 14 04:42:59 PM PDT 24
Finished Aug 14 04:43:06 PM PDT 24
Peak memory 207788 kb
Host smart-42d18362-e065-4d97-afc2-d7c4d69fb70e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854746620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3854746620
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3420211201
Short name T1150
Test name
Test status
Simulation time 3774828351 ps
CPU time 13.8 seconds
Started Aug 14 04:42:25 PM PDT 24
Finished Aug 14 04:42:39 PM PDT 24
Peak memory 207816 kb
Host smart-0c220101-f83d-450d-8395-615f40c7a2c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420211201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3420211201
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2031850677
Short name T86
Test name
Test status
Simulation time 111226126 ps
CPU time 1.21 seconds
Started Aug 14 04:42:48 PM PDT 24
Finished Aug 14 04:42:49 PM PDT 24
Peak memory 216964 kb
Host smart-4dd43523-57a2-4b82-b174-b5f0414420e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031850677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2031850677
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3653441112
Short name T156
Test name
Test status
Simulation time 57961090 ps
CPU time 1.71 seconds
Started Aug 14 04:42:39 PM PDT 24
Finished Aug 14 04:42:40 PM PDT 24
Peak memory 216040 kb
Host smart-324c76af-11d8-44b1-909c-c56f2848f6c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653441112 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3653441112
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3549178044
Short name T127
Test name
Test status
Simulation time 38059075 ps
CPU time 1.26 seconds
Started Aug 14 04:42:33 PM PDT 24
Finished Aug 14 04:42:34 PM PDT 24
Peak memory 207680 kb
Host smart-54ef8afe-7f34-4447-8a7c-8ef497196106
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549178044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
549178044
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2988461395
Short name T1038
Test name
Test status
Simulation time 11981461 ps
CPU time 0.7 seconds
Started Aug 14 04:42:44 PM PDT 24
Finished Aug 14 04:42:45 PM PDT 24
Peak memory 204256 kb
Host smart-7e429e92-7e1f-4b7a-85d6-3ef356015e5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988461395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
988461395
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.87544303
Short name T1114
Test name
Test status
Simulation time 102685192 ps
CPU time 1.73 seconds
Started Aug 14 04:42:45 PM PDT 24
Finished Aug 14 04:42:47 PM PDT 24
Peak memory 215868 kb
Host smart-d4c4f1b9-6b30-4850-9bb5-9dc49b786ba1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87544303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_d
evice_mem_partial_access.87544303
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2921736722
Short name T1136
Test name
Test status
Simulation time 29757148 ps
CPU time 0.66 seconds
Started Aug 14 04:42:29 PM PDT 24
Finished Aug 14 04:42:30 PM PDT 24
Peak memory 204312 kb
Host smart-301d74af-c140-45d9-acc2-f6619e6e08ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921736722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2921736722
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3422073007
Short name T1085
Test name
Test status
Simulation time 295248467 ps
CPU time 2.02 seconds
Started Aug 14 04:43:00 PM PDT 24
Finished Aug 14 04:43:02 PM PDT 24
Peak memory 215936 kb
Host smart-0fa18539-8862-4a29-b018-a9487c331181
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422073007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3422073007
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1284693380
Short name T177
Test name
Test status
Simulation time 1313186830 ps
CPU time 7.93 seconds
Started Aug 14 04:42:50 PM PDT 24
Finished Aug 14 04:42:59 PM PDT 24
Peak memory 215772 kb
Host smart-f5c51d46-08dc-4d5d-bd75-2ed84d1118c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284693380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1284693380
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3763366175
Short name T1086
Test name
Test status
Simulation time 11295980 ps
CPU time 0.73 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:42:58 PM PDT 24
Peak memory 204328 kb
Host smart-04ec2d95-5243-46e4-b7a5-63ce9b6dd052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763366175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3763366175
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1710355841
Short name T1111
Test name
Test status
Simulation time 41523999 ps
CPU time 0.74 seconds
Started Aug 14 04:42:59 PM PDT 24
Finished Aug 14 04:43:00 PM PDT 24
Peak memory 203280 kb
Host smart-a01dd60f-8ad7-4e9f-a329-846464092489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710355841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1710355841
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.140315379
Short name T1135
Test name
Test status
Simulation time 15600254 ps
CPU time 0.74 seconds
Started Aug 14 04:43:02 PM PDT 24
Finished Aug 14 04:43:03 PM PDT 24
Peak memory 204336 kb
Host smart-9e6edff6-d16d-44a1-b0b9-33ff605dbc78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140315379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.140315379
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2501274788
Short name T1039
Test name
Test status
Simulation time 11570726 ps
CPU time 0.7 seconds
Started Aug 14 04:43:05 PM PDT 24
Finished Aug 14 04:43:06 PM PDT 24
Peak memory 204356 kb
Host smart-37035a65-4abc-482d-b490-2378faeed7f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501274788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2501274788
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.242023610
Short name T1112
Test name
Test status
Simulation time 14159900 ps
CPU time 0.71 seconds
Started Aug 14 04:42:51 PM PDT 24
Finished Aug 14 04:42:52 PM PDT 24
Peak memory 204340 kb
Host smart-4f4bd5de-e4fb-47c6-a1b4-6ce7e1de9de7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242023610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.242023610
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2691142345
Short name T1103
Test name
Test status
Simulation time 13708196 ps
CPU time 0.78 seconds
Started Aug 14 04:42:52 PM PDT 24
Finished Aug 14 04:42:53 PM PDT 24
Peak memory 204360 kb
Host smart-39248c14-0644-4986-b131-70cb6a1d6e50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691142345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2691142345
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3471954559
Short name T1052
Test name
Test status
Simulation time 46855315 ps
CPU time 0.74 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:42:58 PM PDT 24
Peak memory 204528 kb
Host smart-ed1ccfc8-2018-4e08-b0e2-de39e9a9b8f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471954559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3471954559
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.722247573
Short name T1031
Test name
Test status
Simulation time 21875910 ps
CPU time 0.7 seconds
Started Aug 14 04:42:49 PM PDT 24
Finished Aug 14 04:42:50 PM PDT 24
Peak memory 204252 kb
Host smart-ed910b20-876b-4c72-a325-034d77d351b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722247573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.722247573
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4154089600
Short name T1043
Test name
Test status
Simulation time 16690345 ps
CPU time 0.74 seconds
Started Aug 14 04:43:10 PM PDT 24
Finished Aug 14 04:43:11 PM PDT 24
Peak memory 204336 kb
Host smart-4aca1b53-8ed4-46d2-9f12-8037aea999a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154089600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
4154089600
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3273501963
Short name T1084
Test name
Test status
Simulation time 24235725 ps
CPU time 0.75 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 204272 kb
Host smart-d7af013b-b3f1-4c81-8158-21ba93509919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273501963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3273501963
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4033258835
Short name T115
Test name
Test status
Simulation time 198053935 ps
CPU time 2.87 seconds
Started Aug 14 04:42:56 PM PDT 24
Finished Aug 14 04:42:59 PM PDT 24
Peak memory 217308 kb
Host smart-76c087db-de2f-45f3-a8e3-3a4a310e9ff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033258835 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4033258835
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2114916202
Short name T131
Test name
Test status
Simulation time 29641777 ps
CPU time 1.91 seconds
Started Aug 14 04:42:55 PM PDT 24
Finished Aug 14 04:42:57 PM PDT 24
Peak memory 215812 kb
Host smart-02e8312f-2b78-40cd-91dc-fc13a79a9273
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114916202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
114916202
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3360529866
Short name T1063
Test name
Test status
Simulation time 38747916 ps
CPU time 0.66 seconds
Started Aug 14 04:42:43 PM PDT 24
Finished Aug 14 04:42:44 PM PDT 24
Peak memory 204364 kb
Host smart-ec4a2430-a806-4d2d-b07b-8951b9b05dd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360529866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
360529866
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4094665225
Short name T1042
Test name
Test status
Simulation time 199935122 ps
CPU time 1.71 seconds
Started Aug 14 04:42:44 PM PDT 24
Finished Aug 14 04:42:45 PM PDT 24
Peak memory 216004 kb
Host smart-92b21a07-8d89-4190-9762-c88cde45a238
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094665225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4094665225
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3178862421
Short name T110
Test name
Test status
Simulation time 1329204688 ps
CPU time 5.29 seconds
Started Aug 14 04:42:25 PM PDT 24
Finished Aug 14 04:42:30 PM PDT 24
Peak memory 216252 kb
Host smart-f291793b-82c7-4f74-9135-fa322180b602
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178862421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
178862421
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2071656753
Short name T179
Test name
Test status
Simulation time 2106511289 ps
CPU time 13.63 seconds
Started Aug 14 04:42:38 PM PDT 24
Finished Aug 14 04:42:52 PM PDT 24
Peak memory 216628 kb
Host smart-ba3f6921-eb0b-4e5a-b788-39d6ce2874ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071656753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2071656753
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3882198244
Short name T1059
Test name
Test status
Simulation time 88805404 ps
CPU time 1.66 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 215980 kb
Host smart-af98d082-ce39-43d7-bedc-9f4872a6ec3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882198244 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3882198244
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3920311190
Short name T157
Test name
Test status
Simulation time 122145922 ps
CPU time 2.8 seconds
Started Aug 14 04:42:47 PM PDT 24
Finished Aug 14 04:42:50 PM PDT 24
Peak memory 215928 kb
Host smart-7e053d7c-1421-4e6f-aa09-ff6802d963a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920311190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
920311190
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1681169348
Short name T1053
Test name
Test status
Simulation time 18071218 ps
CPU time 0.76 seconds
Started Aug 14 04:42:46 PM PDT 24
Finished Aug 14 04:42:47 PM PDT 24
Peak memory 204228 kb
Host smart-dde79c24-6459-4efd-b403-052606420c4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681169348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
681169348
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3257637997
Short name T1035
Test name
Test status
Simulation time 62292047 ps
CPU time 3.94 seconds
Started Aug 14 04:42:46 PM PDT 24
Finished Aug 14 04:42:50 PM PDT 24
Peak memory 215896 kb
Host smart-48824664-3fe3-45c8-9f9c-5715bd3208a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257637997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3257637997
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1078719928
Short name T1057
Test name
Test status
Simulation time 66265354 ps
CPU time 1.89 seconds
Started Aug 14 04:43:09 PM PDT 24
Finished Aug 14 04:43:11 PM PDT 24
Peak memory 216024 kb
Host smart-9b942313-efa1-46f0-9fc0-8f548cc55356
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078719928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
078719928
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3780672473
Short name T1060
Test name
Test status
Simulation time 1430439788 ps
CPU time 13.85 seconds
Started Aug 14 04:42:43 PM PDT 24
Finished Aug 14 04:42:57 PM PDT 24
Peak memory 215856 kb
Host smart-460b583d-5edc-43b0-83ed-16f949276457
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780672473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3780672473
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.453492166
Short name T1048
Test name
Test status
Simulation time 77746872 ps
CPU time 4.03 seconds
Started Aug 14 04:42:44 PM PDT 24
Finished Aug 14 04:42:48 PM PDT 24
Peak memory 219532 kb
Host smart-d79feaf6-e7b3-4e2e-9c09-d7fc9a9dcffc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453492166 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.453492166
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1371204008
Short name T1106
Test name
Test status
Simulation time 23913531 ps
CPU time 1.41 seconds
Started Aug 14 04:42:38 PM PDT 24
Finished Aug 14 04:42:40 PM PDT 24
Peak memory 215948 kb
Host smart-6336f6d5-d181-44d3-b9b0-849ba6ca48ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371204008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
371204008
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1544840789
Short name T1110
Test name
Test status
Simulation time 13489246 ps
CPU time 0.71 seconds
Started Aug 14 04:42:56 PM PDT 24
Finished Aug 14 04:42:57 PM PDT 24
Peak memory 204360 kb
Host smart-50ae8363-1dab-49e6-a9f5-1c629863d143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544840789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
544840789
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1152904502
Short name T148
Test name
Test status
Simulation time 45069266 ps
CPU time 2.69 seconds
Started Aug 14 04:42:43 PM PDT 24
Finished Aug 14 04:42:45 PM PDT 24
Peak memory 216000 kb
Host smart-cbf37c94-757a-4629-a976-45d0d231972a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152904502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1152904502
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.299713457
Short name T108
Test name
Test status
Simulation time 860537750 ps
CPU time 2.25 seconds
Started Aug 14 04:42:48 PM PDT 24
Finished Aug 14 04:42:50 PM PDT 24
Peak memory 216096 kb
Host smart-a1b112ca-d348-4b5c-943f-31afaaf0a3b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299713457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.299713457
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2739667798
Short name T1131
Test name
Test status
Simulation time 367071975 ps
CPU time 3.72 seconds
Started Aug 14 04:42:55 PM PDT 24
Finished Aug 14 04:42:59 PM PDT 24
Peak memory 217984 kb
Host smart-63c024c7-af0b-4f1e-bdb1-90cd7dcbf238
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739667798 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2739667798
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1651518833
Short name T159
Test name
Test status
Simulation time 258965736 ps
CPU time 1.77 seconds
Started Aug 14 04:42:52 PM PDT 24
Finished Aug 14 04:42:54 PM PDT 24
Peak memory 215828 kb
Host smart-ec4ef0e1-bcfe-433f-8f9a-f3dae31a11c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651518833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
651518833
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3069182351
Short name T1080
Test name
Test status
Simulation time 14742318 ps
CPU time 0.78 seconds
Started Aug 14 04:42:43 PM PDT 24
Finished Aug 14 04:42:44 PM PDT 24
Peak memory 204284 kb
Host smart-5aa4d45a-3756-491a-8fb5-c38c35287294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069182351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
069182351
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3982421439
Short name T1142
Test name
Test status
Simulation time 495796099 ps
CPU time 4.56 seconds
Started Aug 14 04:43:03 PM PDT 24
Finished Aug 14 04:43:08 PM PDT 24
Peak memory 215944 kb
Host smart-f52e6a5a-c7c6-416b-94ac-716e457394f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982421439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3982421439
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.290705918
Short name T1138
Test name
Test status
Simulation time 129714818 ps
CPU time 3.1 seconds
Started Aug 14 04:42:23 PM PDT 24
Finished Aug 14 04:42:27 PM PDT 24
Peak memory 216188 kb
Host smart-c75aacaa-7a79-4155-b6ce-da0473ee1abb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290705918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.290705918
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1586880646
Short name T99
Test name
Test status
Simulation time 292903359 ps
CPU time 16.88 seconds
Started Aug 14 04:42:51 PM PDT 24
Finished Aug 14 04:43:08 PM PDT 24
Peak memory 215964 kb
Host smart-b3f63a5a-1118-4f62-a765-e068ef25ca07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586880646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1586880646
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4183258639
Short name T119
Test name
Test status
Simulation time 96037764 ps
CPU time 2.78 seconds
Started Aug 14 04:42:37 PM PDT 24
Finished Aug 14 04:42:40 PM PDT 24
Peak memory 217940 kb
Host smart-0346cc90-2858-43ba-860f-d9502f28084d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183258639 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.4183258639
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3749452270
Short name T1096
Test name
Test status
Simulation time 160763927 ps
CPU time 1.25 seconds
Started Aug 14 04:42:22 PM PDT 24
Finished Aug 14 04:42:24 PM PDT 24
Peak memory 207788 kb
Host smart-58d3cc4d-3766-40f9-a066-be8d944b1edc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749452270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
749452270
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2673865397
Short name T1046
Test name
Test status
Simulation time 40019876 ps
CPU time 0.68 seconds
Started Aug 14 04:42:53 PM PDT 24
Finished Aug 14 04:42:53 PM PDT 24
Peak memory 204208 kb
Host smart-fa42f092-8cc6-4671-b871-54b19205c394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673865397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
673865397
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2779179533
Short name T1129
Test name
Test status
Simulation time 280808292 ps
CPU time 1.83 seconds
Started Aug 14 04:42:43 PM PDT 24
Finished Aug 14 04:42:45 PM PDT 24
Peak memory 215868 kb
Host smart-55e683d6-fa25-4dac-b465-0c40b7541ad4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779179533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2779179533
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1368559168
Short name T1141
Test name
Test status
Simulation time 46729876 ps
CPU time 3.1 seconds
Started Aug 14 04:42:57 PM PDT 24
Finished Aug 14 04:43:00 PM PDT 24
Peak memory 216132 kb
Host smart-a8a8e146-4c01-4a9a-8537-c26942cd95cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368559168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
368559168
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3110301727
Short name T178
Test name
Test status
Simulation time 7162113359 ps
CPU time 23.65 seconds
Started Aug 14 04:42:54 PM PDT 24
Finished Aug 14 04:43:17 PM PDT 24
Peak memory 216324 kb
Host smart-9446cbcb-686e-4232-bd53-cb3adcce01c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110301727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3110301727
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1119803930
Short name T371
Test name
Test status
Simulation time 13000670 ps
CPU time 0.75 seconds
Started Aug 14 05:25:29 PM PDT 24
Finished Aug 14 05:25:30 PM PDT 24
Peak memory 205932 kb
Host smart-a77044fd-5fc1-4705-94fe-21765aa999b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119803930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
119803930
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1491969355
Short name T89
Test name
Test status
Simulation time 409489810 ps
CPU time 5.17 seconds
Started Aug 14 05:25:34 PM PDT 24
Finished Aug 14 05:25:40 PM PDT 24
Peak memory 224644 kb
Host smart-8863194b-8d51-4fb9-a0c8-b0af36f2a269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491969355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1491969355
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1710555363
Short name T419
Test name
Test status
Simulation time 24247074 ps
CPU time 0.81 seconds
Started Aug 14 05:25:28 PM PDT 24
Finished Aug 14 05:25:29 PM PDT 24
Peak memory 206632 kb
Host smart-3b87294a-a1fe-4713-93b4-0ccbc57d0977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710555363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1710555363
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.838807187
Short name T47
Test name
Test status
Simulation time 9725853438 ps
CPU time 90.43 seconds
Started Aug 14 05:25:35 PM PDT 24
Finished Aug 14 05:27:06 PM PDT 24
Peak memory 249428 kb
Host smart-6765d0f4-0dde-4af5-8fb5-6862ffd429f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838807187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.838807187
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3044555864
Short name T31
Test name
Test status
Simulation time 13014047311 ps
CPU time 152.89 seconds
Started Aug 14 05:25:29 PM PDT 24
Finished Aug 14 05:28:02 PM PDT 24
Peak memory 254288 kb
Host smart-eac8d0de-1552-458e-a09c-6116cfb4f8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044555864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3044555864
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.945221705
Short name T298
Test name
Test status
Simulation time 7013377483 ps
CPU time 47.53 seconds
Started Aug 14 05:25:35 PM PDT 24
Finished Aug 14 05:26:23 PM PDT 24
Peak memory 234560 kb
Host smart-beaca97f-a251-4001-a775-f89fa4eb36d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945221705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.945221705
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1266334049
Short name T286
Test name
Test status
Simulation time 11484636829 ps
CPU time 70.24 seconds
Started Aug 14 05:25:29 PM PDT 24
Finished Aug 14 05:26:39 PM PDT 24
Peak memory 249384 kb
Host smart-f73bf35a-1b35-4aa7-9c0c-0da63e755947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266334049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1266334049
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1596523720
Short name T242
Test name
Test status
Simulation time 17759890185 ps
CPU time 16.8 seconds
Started Aug 14 05:25:27 PM PDT 24
Finished Aug 14 05:25:44 PM PDT 24
Peak memory 224720 kb
Host smart-78207f34-e1db-4546-b64e-62d3da0909f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596523720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1596523720
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.604959517
Short name T946
Test name
Test status
Simulation time 32333592 ps
CPU time 1.04 seconds
Started Aug 14 05:25:28 PM PDT 24
Finished Aug 14 05:25:29 PM PDT 24
Peak memory 218072 kb
Host smart-340c5213-0b84-41fe-9488-cebf108434a7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604959517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.604959517
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.84093945
Short name T230
Test name
Test status
Simulation time 282533289 ps
CPU time 2.95 seconds
Started Aug 14 05:25:30 PM PDT 24
Finished Aug 14 05:25:33 PM PDT 24
Peak memory 232860 kb
Host smart-f71fed01-8495-4f8f-a473-4dce125b9f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84093945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.84093945
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1486871367
Short name T597
Test name
Test status
Simulation time 1631028769 ps
CPU time 5.73 seconds
Started Aug 14 05:25:35 PM PDT 24
Finished Aug 14 05:25:41 PM PDT 24
Peak memory 219124 kb
Host smart-d34e8428-9a90-4895-9c81-a2cecc0773ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1486871367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1486871367
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3821195365
Short name T73
Test name
Test status
Simulation time 94874581 ps
CPU time 1.2 seconds
Started Aug 14 05:25:30 PM PDT 24
Finished Aug 14 05:25:32 PM PDT 24
Peak memory 235632 kb
Host smart-c2dcee59-550f-451c-8b42-758c86c9c0a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821195365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3821195365
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.614291302
Short name T165
Test name
Test status
Simulation time 4076208754 ps
CPU time 46.07 seconds
Started Aug 14 05:25:33 PM PDT 24
Finished Aug 14 05:26:19 PM PDT 24
Peak memory 249456 kb
Host smart-211f74a2-ebde-4dc2-ac7a-b0e56b4c0e8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614291302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.614291302
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4020743613
Short name T990
Test name
Test status
Simulation time 7759480020 ps
CPU time 5.73 seconds
Started Aug 14 05:25:29 PM PDT 24
Finished Aug 14 05:25:35 PM PDT 24
Peak memory 216588 kb
Host smart-f2eda131-25dd-4eb1-922b-fbfb215b02f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020743613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4020743613
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2029204698
Short name T885
Test name
Test status
Simulation time 144040593 ps
CPU time 1.02 seconds
Started Aug 14 05:25:35 PM PDT 24
Finished Aug 14 05:25:36 PM PDT 24
Peak memory 207932 kb
Host smart-6262bf9e-fae5-4606-af18-79e7f18282e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029204698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2029204698
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2532673221
Short name T932
Test name
Test status
Simulation time 16109546 ps
CPU time 0.73 seconds
Started Aug 14 05:25:27 PM PDT 24
Finished Aug 14 05:25:27 PM PDT 24
Peak memory 206144 kb
Host smart-b59afccb-5b39-4f22-9bc9-d27b19567844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532673221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2532673221
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.926351595
Short name T860
Test name
Test status
Simulation time 1212559777 ps
CPU time 1.01 seconds
Started Aug 14 05:25:29 PM PDT 24
Finished Aug 14 05:25:31 PM PDT 24
Peak memory 207156 kb
Host smart-60c577e8-53bb-4084-8832-8af411b64690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926351595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.926351595
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2605977044
Short name T334
Test name
Test status
Simulation time 75905799 ps
CPU time 2.61 seconds
Started Aug 14 05:25:28 PM PDT 24
Finished Aug 14 05:25:31 PM PDT 24
Peak memory 224316 kb
Host smart-703c202c-7713-464d-84c7-db12b78e881e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605977044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2605977044
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.402594397
Short name T1008
Test name
Test status
Simulation time 42798520 ps
CPU time 0.73 seconds
Started Aug 14 05:25:42 PM PDT 24
Finished Aug 14 05:25:42 PM PDT 24
Peak memory 205676 kb
Host smart-05d41d0d-325b-4993-8ba7-52c1d6bc535f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402594397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.402594397
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3712142104
Short name T913
Test name
Test status
Simulation time 1342102677 ps
CPU time 6.36 seconds
Started Aug 14 05:25:38 PM PDT 24
Finished Aug 14 05:25:44 PM PDT 24
Peak memory 224664 kb
Host smart-2a23fe3e-7cdc-41a0-9dc2-d3c6a48b7fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712142104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3712142104
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.85815689
Short name T891
Test name
Test status
Simulation time 19464223 ps
CPU time 0.81 seconds
Started Aug 14 05:25:28 PM PDT 24
Finished Aug 14 05:25:29 PM PDT 24
Peak memory 206660 kb
Host smart-95884aa7-00c2-4c8b-b670-5dbf1daa639e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85815689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.85815689
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1358350321
Short name T433
Test name
Test status
Simulation time 9527750281 ps
CPU time 99.67 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:27:18 PM PDT 24
Peak memory 256724 kb
Host smart-2136d7c3-6c62-4a32-ab09-f38c9b2bffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358350321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1358350321
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.340454731
Short name T292
Test name
Test status
Simulation time 235331371389 ps
CPU time 266.79 seconds
Started Aug 14 05:25:43 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 249832 kb
Host smart-cd10f1c7-55f7-4765-9ee5-cb11af163c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340454731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
340454731
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3071335017
Short name T514
Test name
Test status
Simulation time 1994652090 ps
CPU time 20.55 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:26:00 PM PDT 24
Peak memory 241128 kb
Host smart-37833f82-98cd-4e02-a563-ad60f667af47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071335017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3071335017
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.220342528
Short name T270
Test name
Test status
Simulation time 2394267698 ps
CPU time 63.44 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:26:43 PM PDT 24
Peak memory 252012 kb
Host smart-25eb21bf-37fb-4484-b5dd-6756bf54f6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220342528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
220342528
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2092623776
Short name T890
Test name
Test status
Simulation time 599795311 ps
CPU time 5.29 seconds
Started Aug 14 05:25:38 PM PDT 24
Finished Aug 14 05:25:44 PM PDT 24
Peak memory 232928 kb
Host smart-f31937b0-baa8-4fe7-8b50-12748a018ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092623776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2092623776
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.15839583
Short name T947
Test name
Test status
Simulation time 487965784 ps
CPU time 5.49 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:25:44 PM PDT 24
Peak memory 224568 kb
Host smart-3e8de78b-7add-46e8-9e37-6c742a805e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15839583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.15839583
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3958891455
Short name T900
Test name
Test status
Simulation time 28208173 ps
CPU time 1.1 seconds
Started Aug 14 05:25:38 PM PDT 24
Finished Aug 14 05:25:39 PM PDT 24
Peak memory 216756 kb
Host smart-ab412058-4670-46b3-9982-24cedf1103b5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958891455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3958891455
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1484820257
Short name T877
Test name
Test status
Simulation time 658297851 ps
CPU time 5.4 seconds
Started Aug 14 05:25:42 PM PDT 24
Finished Aug 14 05:25:48 PM PDT 24
Peak memory 232900 kb
Host smart-b038ab35-b561-448f-98e7-5b6afa599640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484820257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1484820257
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3037440500
Short name T387
Test name
Test status
Simulation time 232622518 ps
CPU time 2.49 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:25:42 PM PDT 24
Peak memory 232508 kb
Host smart-121503c7-9555-4e9b-a235-eb1f09fe0a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037440500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3037440500
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3084833095
Short name T500
Test name
Test status
Simulation time 7067101465 ps
CPU time 17.64 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:25:57 PM PDT 24
Peak memory 220116 kb
Host smart-916d6ece-3aa2-47dc-8a73-617e4c2f18de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3084833095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3084833095
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1036149650
Short name T145
Test name
Test status
Simulation time 2379003230185 ps
CPU time 1166.42 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:45:05 PM PDT 24
Peak memory 283680 kb
Host smart-c0c7e7c0-c5b7-4b59-a946-bbc2bf3d1e22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036149650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1036149650
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.92019275
Short name T482
Test name
Test status
Simulation time 706260645 ps
CPU time 5.37 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:25:44 PM PDT 24
Peak memory 218604 kb
Host smart-af18c909-ec72-40be-b972-4516575091da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92019275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.92019275
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2149675646
Short name T332
Test name
Test status
Simulation time 37164924345 ps
CPU time 15.34 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:25:54 PM PDT 24
Peak memory 216560 kb
Host smart-1b4a3de7-37ed-497c-9ba0-90f1641c028f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149675646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2149675646
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4043516538
Short name T935
Test name
Test status
Simulation time 1625722333 ps
CPU time 1.98 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:25:41 PM PDT 24
Peak memory 216412 kb
Host smart-2afc922f-c1ec-4440-a2c6-7063d0185b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043516538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4043516538
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3447634569
Short name T481
Test name
Test status
Simulation time 39641377 ps
CPU time 0.86 seconds
Started Aug 14 05:25:37 PM PDT 24
Finished Aug 14 05:25:38 PM PDT 24
Peak memory 207168 kb
Host smart-3b54dc23-2bcf-420e-86a4-6ee95db753b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447634569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3447634569
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1528621438
Short name T753
Test name
Test status
Simulation time 507337709 ps
CPU time 3.03 seconds
Started Aug 14 05:25:42 PM PDT 24
Finished Aug 14 05:25:45 PM PDT 24
Peak memory 224720 kb
Host smart-9dae0736-21f4-471e-b3fb-c11ee34d2d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528621438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1528621438
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3459144286
Short name T484
Test name
Test status
Simulation time 66718459 ps
CPU time 0.72 seconds
Started Aug 14 05:26:25 PM PDT 24
Finished Aug 14 05:26:26 PM PDT 24
Peak memory 204988 kb
Host smart-f3554b35-8f10-4166-9e95-fa034e7bfeda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459144286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3459144286
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3219179439
Short name T408
Test name
Test status
Simulation time 1282657079 ps
CPU time 4.72 seconds
Started Aug 14 05:26:29 PM PDT 24
Finished Aug 14 05:26:34 PM PDT 24
Peak memory 224684 kb
Host smart-b85d2be2-0e79-46ec-bb56-9a13b4c3200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219179439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3219179439
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1554028906
Short name T379
Test name
Test status
Simulation time 288966419 ps
CPU time 0.8 seconds
Started Aug 14 05:26:27 PM PDT 24
Finished Aug 14 05:26:28 PM PDT 24
Peak memory 206776 kb
Host smart-3f40ca90-ec28-4030-9603-7302b620a4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554028906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1554028906
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3566865673
Short name T771
Test name
Test status
Simulation time 524782152 ps
CPU time 5.77 seconds
Started Aug 14 05:26:27 PM PDT 24
Finished Aug 14 05:26:32 PM PDT 24
Peak memory 234772 kb
Host smart-9864e223-edfd-44ea-acea-2ec39c344c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566865673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3566865673
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1580368551
Short name T278
Test name
Test status
Simulation time 48316127256 ps
CPU time 482.85 seconds
Started Aug 14 05:26:25 PM PDT 24
Finished Aug 14 05:34:28 PM PDT 24
Peak memory 252220 kb
Host smart-d6349d5f-09be-4943-bfd9-d2366b7886d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580368551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1580368551
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1083066106
Short name T953
Test name
Test status
Simulation time 15257547180 ps
CPU time 127.02 seconds
Started Aug 14 05:26:25 PM PDT 24
Finished Aug 14 05:28:32 PM PDT 24
Peak memory 249676 kb
Host smart-9018c4d9-9a3e-48aa-a982-6478128d4d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083066106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1083066106
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2610105316
Short name T415
Test name
Test status
Simulation time 684648801 ps
CPU time 3.44 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:30 PM PDT 24
Peak memory 224680 kb
Host smart-59045cf4-47fd-45e9-94f1-a8ad55e55607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610105316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2610105316
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3624885475
Short name T293
Test name
Test status
Simulation time 15984573893 ps
CPU time 92.16 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:27:59 PM PDT 24
Peak memory 260596 kb
Host smart-c974c2ac-7605-4d13-a33a-996fa97b4b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624885475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3624885475
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3320836010
Short name T892
Test name
Test status
Simulation time 425847735 ps
CPU time 7.43 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:33 PM PDT 24
Peak memory 224672 kb
Host smart-dcc5ae06-0411-479d-baa7-96bffe3f6a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320836010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3320836010
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3036411873
Short name T138
Test name
Test status
Simulation time 4266080427 ps
CPU time 17.57 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:43 PM PDT 24
Peak memory 254144 kb
Host smart-ce346419-dfe7-4edd-ae63-084bba1dd4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036411873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3036411873
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.93812510
Short name T705
Test name
Test status
Simulation time 65445031 ps
CPU time 1.03 seconds
Started Aug 14 05:26:27 PM PDT 24
Finished Aug 14 05:26:28 PM PDT 24
Peak memory 216736 kb
Host smart-4047697e-5080-42de-92f7-e8864af53d67
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93812510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.93812510
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.693770496
Short name T608
Test name
Test status
Simulation time 2124189920 ps
CPU time 5.27 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:31 PM PDT 24
Peak memory 224724 kb
Host smart-41b10f3d-a874-425f-9f91-7318fbce648d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693770496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.693770496
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.467979028
Short name T105
Test name
Test status
Simulation time 597477313 ps
CPU time 6.64 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:33 PM PDT 24
Peak memory 224716 kb
Host smart-9b65e132-f823-493e-96c0-9f2002667504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467979028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.467979028
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3996980655
Short name T873
Test name
Test status
Simulation time 3972782122 ps
CPU time 8.76 seconds
Started Aug 14 05:26:25 PM PDT 24
Finished Aug 14 05:26:34 PM PDT 24
Peak memory 222128 kb
Host smart-4cd85070-b010-47a1-b76f-c69067234a3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3996980655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3996980655
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2744407441
Short name T198
Test name
Test status
Simulation time 11089515419 ps
CPU time 51.6 seconds
Started Aug 14 05:26:28 PM PDT 24
Finished Aug 14 05:27:20 PM PDT 24
Peak memory 256672 kb
Host smart-5ade4743-a59f-4d6e-9301-815bdf681343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744407441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2744407441
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4101706667
Short name T26
Test name
Test status
Simulation time 479858706 ps
CPU time 4.66 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:31 PM PDT 24
Peak memory 218472 kb
Host smart-b5a91279-a88a-404b-81f4-af68943c0fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101706667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4101706667
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2055052732
Short name T699
Test name
Test status
Simulation time 191985715 ps
CPU time 1.71 seconds
Started Aug 14 05:26:27 PM PDT 24
Finished Aug 14 05:26:28 PM PDT 24
Peak memory 208120 kb
Host smart-f86ab4b5-f402-479c-ac40-7b2a2ee4b0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055052732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2055052732
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3072599408
Short name T473
Test name
Test status
Simulation time 165588055 ps
CPU time 3.55 seconds
Started Aug 14 05:26:25 PM PDT 24
Finished Aug 14 05:26:29 PM PDT 24
Peak memory 216476 kb
Host smart-7e958a57-2c33-4197-a4d3-a89e59118657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072599408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3072599408
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.427933979
Short name T770
Test name
Test status
Simulation time 99934574 ps
CPU time 0.75 seconds
Started Aug 14 05:26:25 PM PDT 24
Finished Aug 14 05:26:26 PM PDT 24
Peak memory 206156 kb
Host smart-501f024b-6326-49d2-9fa1-6c6de66e7de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427933979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.427933979
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.569837049
Short name T1020
Test name
Test status
Simulation time 2761815760 ps
CPU time 10.3 seconds
Started Aug 14 05:26:30 PM PDT 24
Finished Aug 14 05:26:41 PM PDT 24
Peak memory 238276 kb
Host smart-1198930d-4168-4383-a09d-e811c70f6062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569837049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.569837049
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3864649642
Short name T703
Test name
Test status
Simulation time 35709619 ps
CPU time 0.71 seconds
Started Aug 14 05:26:37 PM PDT 24
Finished Aug 14 05:26:38 PM PDT 24
Peak memory 205552 kb
Host smart-ddd6ba48-bc34-4c86-804f-2323f25b464c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864649642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3864649642
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2777918912
Short name T985
Test name
Test status
Simulation time 554945412 ps
CPU time 3.36 seconds
Started Aug 14 05:26:36 PM PDT 24
Finished Aug 14 05:26:40 PM PDT 24
Peak memory 232764 kb
Host smart-b6cc2f95-e516-4f21-8059-e111841c5213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777918912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2777918912
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2894489622
Short name T478
Test name
Test status
Simulation time 18337301 ps
CPU time 0.77 seconds
Started Aug 14 05:26:29 PM PDT 24
Finished Aug 14 05:26:30 PM PDT 24
Peak memory 207004 kb
Host smart-96a331d2-0f7c-4d9c-8e1a-71e4a3a0a173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894489622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2894489622
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1793026516
Short name T257
Test name
Test status
Simulation time 205219845187 ps
CPU time 258.46 seconds
Started Aug 14 05:26:42 PM PDT 24
Finished Aug 14 05:31:00 PM PDT 24
Peak memory 264996 kb
Host smart-a9f583bc-0a6d-46e6-a4a0-e74eee2dd068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793026516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1793026516
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1152284005
Short name T269
Test name
Test status
Simulation time 10304887755 ps
CPU time 129.22 seconds
Started Aug 14 05:26:39 PM PDT 24
Finished Aug 14 05:28:48 PM PDT 24
Peak memory 252656 kb
Host smart-7509f68f-91f4-4aaf-a86b-12e73d3eb7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152284005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1152284005
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.505030666
Short name T580
Test name
Test status
Simulation time 73590798 ps
CPU time 3.56 seconds
Started Aug 14 05:26:36 PM PDT 24
Finished Aug 14 05:26:39 PM PDT 24
Peak memory 224724 kb
Host smart-135f6d9d-8285-4f94-9ba6-4ec4fedf3d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505030666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.505030666
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1215824055
Short name T614
Test name
Test status
Simulation time 105571062284 ps
CPU time 179.11 seconds
Started Aug 14 05:26:36 PM PDT 24
Finished Aug 14 05:29:36 PM PDT 24
Peak memory 249384 kb
Host smart-2bdc6691-5ffd-4412-a3b9-fe8456ab57ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215824055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1215824055
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.274483545
Short name T139
Test name
Test status
Simulation time 3529855445 ps
CPU time 9.08 seconds
Started Aug 14 05:26:36 PM PDT 24
Finished Aug 14 05:26:45 PM PDT 24
Peak memory 233008 kb
Host smart-505d79dc-87d8-4c4f-a32d-1eaf22b7b958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274483545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.274483545
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2583715248
Short name T583
Test name
Test status
Simulation time 264876126 ps
CPU time 7.34 seconds
Started Aug 14 05:26:37 PM PDT 24
Finished Aug 14 05:26:45 PM PDT 24
Peak memory 232904 kb
Host smart-77fbcafe-7ffb-4b5e-b5a0-793869afecc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583715248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2583715248
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.204810107
Short name T797
Test name
Test status
Simulation time 58133145 ps
CPU time 0.98 seconds
Started Aug 14 05:26:29 PM PDT 24
Finished Aug 14 05:26:30 PM PDT 24
Peak memory 217960 kb
Host smart-6fb3c2df-d56f-4a45-ada0-299754337e24
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204810107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.204810107
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2002365190
Short name T695
Test name
Test status
Simulation time 703538715 ps
CPU time 2.54 seconds
Started Aug 14 05:26:37 PM PDT 24
Finished Aug 14 05:26:39 PM PDT 24
Peak memory 224660 kb
Host smart-adc5c476-39c9-4771-8001-b130e3c5ff88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002365190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2002365190
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.440816933
Short name T340
Test name
Test status
Simulation time 1035343080 ps
CPU time 4.14 seconds
Started Aug 14 05:26:40 PM PDT 24
Finished Aug 14 05:26:45 PM PDT 24
Peak memory 224684 kb
Host smart-b5e96978-1f56-400d-a66f-0d1dd8988e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440816933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.440816933
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.728488924
Short name T153
Test name
Test status
Simulation time 1077201282 ps
CPU time 8.74 seconds
Started Aug 14 05:26:36 PM PDT 24
Finished Aug 14 05:26:45 PM PDT 24
Peak memory 219568 kb
Host smart-e67ae60a-f4e2-4bab-88cd-0774305e9c7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=728488924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.728488924
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4154456245
Short name T360
Test name
Test status
Simulation time 119904912 ps
CPU time 1.02 seconds
Started Aug 14 05:26:38 PM PDT 24
Finished Aug 14 05:26:39 PM PDT 24
Peak memory 206840 kb
Host smart-ebdfb06d-9139-4e90-9c68-f03d4d0e4bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154456245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4154456245
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3776900186
Short name T531
Test name
Test status
Simulation time 27480833010 ps
CPU time 34.9 seconds
Started Aug 14 05:26:24 PM PDT 24
Finished Aug 14 05:26:59 PM PDT 24
Peak memory 216544 kb
Host smart-33a29fc3-11c5-4a8a-a404-5f4228adc39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776900186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3776900186
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3026475764
Short name T626
Test name
Test status
Simulation time 1984212470 ps
CPU time 3.68 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:30 PM PDT 24
Peak memory 216484 kb
Host smart-8e5c6921-0195-4b1b-8367-93d84e0fd316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026475764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3026475764
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3031244908
Short name T316
Test name
Test status
Simulation time 159978034 ps
CPU time 1.84 seconds
Started Aug 14 05:26:38 PM PDT 24
Finished Aug 14 05:26:40 PM PDT 24
Peak memory 216480 kb
Host smart-6c11ac7d-2379-48c2-aa9a-933844520e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031244908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3031244908
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1490686262
Short name T410
Test name
Test status
Simulation time 60573777 ps
CPU time 0.87 seconds
Started Aug 14 05:26:37 PM PDT 24
Finished Aug 14 05:26:38 PM PDT 24
Peak memory 206164 kb
Host smart-5c0c7fd0-47bf-46c8-b94d-5f795c1b8b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490686262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1490686262
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3840795655
Short name T984
Test name
Test status
Simulation time 23945924801 ps
CPU time 22.49 seconds
Started Aug 14 05:26:39 PM PDT 24
Finished Aug 14 05:27:01 PM PDT 24
Peak memory 232948 kb
Host smart-509b0e66-05a1-4920-b51b-09c51f2b000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840795655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3840795655
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3736766465
Short name T582
Test name
Test status
Simulation time 34615038 ps
CPU time 0.77 seconds
Started Aug 14 05:26:37 PM PDT 24
Finished Aug 14 05:26:38 PM PDT 24
Peak memory 204992 kb
Host smart-0ef7895e-454f-45c5-a6f0-e4cdf268f3b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736766465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3736766465
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.943355426
Short name T366
Test name
Test status
Simulation time 479240147 ps
CPU time 3.75 seconds
Started Aug 14 05:26:38 PM PDT 24
Finished Aug 14 05:26:41 PM PDT 24
Peak memory 224664 kb
Host smart-e5b062f1-40f1-446a-addb-07ddbc1b6d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943355426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.943355426
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.838808709
Short name T924
Test name
Test status
Simulation time 21052740 ps
CPU time 0.8 seconds
Started Aug 14 05:26:36 PM PDT 24
Finished Aug 14 05:26:37 PM PDT 24
Peak memory 206632 kb
Host smart-efba71a4-c04d-4526-9f48-d72c3b8494f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838808709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.838808709
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3042393808
Short name T549
Test name
Test status
Simulation time 3218941551 ps
CPU time 17.89 seconds
Started Aug 14 05:26:35 PM PDT 24
Finished Aug 14 05:26:53 PM PDT 24
Peak memory 239228 kb
Host smart-7fa80660-8344-40dd-868f-11cb63092933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042393808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3042393808
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1852925095
Short name T250
Test name
Test status
Simulation time 12285556189 ps
CPU time 159.21 seconds
Started Aug 14 05:26:38 PM PDT 24
Finished Aug 14 05:29:17 PM PDT 24
Peak memory 273996 kb
Host smart-7ec2a1e7-778d-45ad-8c60-4e4420843e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852925095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1852925095
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2651119184
Short name T37
Test name
Test status
Simulation time 93097053255 ps
CPU time 202.21 seconds
Started Aug 14 05:26:39 PM PDT 24
Finished Aug 14 05:30:01 PM PDT 24
Peak memory 256416 kb
Host smart-81c568de-7b91-4c5f-a9ee-1c53dead9bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651119184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2651119184
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2877901673
Short name T247
Test name
Test status
Simulation time 3019213079 ps
CPU time 16.55 seconds
Started Aug 14 05:26:38 PM PDT 24
Finished Aug 14 05:26:55 PM PDT 24
Peak memory 232960 kb
Host smart-e7f9472c-bcd3-4ed5-a6bc-2c1e82b22327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877901673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2877901673
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3660201917
Short name T214
Test name
Test status
Simulation time 70144998426 ps
CPU time 92.98 seconds
Started Aug 14 05:26:37 PM PDT 24
Finished Aug 14 05:28:10 PM PDT 24
Peak memory 249456 kb
Host smart-431561a0-016a-469d-b481-01ad34a14277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660201917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3660201917
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3606509643
Short name T526
Test name
Test status
Simulation time 24951099 ps
CPU time 1.01 seconds
Started Aug 14 05:26:36 PM PDT 24
Finished Aug 14 05:26:37 PM PDT 24
Peak memory 218052 kb
Host smart-4eea41a5-77f7-44ae-9fbd-901254ccf15b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606509643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3606509643
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4141741664
Short name T422
Test name
Test status
Simulation time 719128112 ps
CPU time 8.22 seconds
Started Aug 14 05:26:37 PM PDT 24
Finished Aug 14 05:26:45 PM PDT 24
Peak memory 224728 kb
Host smart-ed566f69-f08e-4965-89a4-f61551dba2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141741664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4141741664
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2218110540
Short name T612
Test name
Test status
Simulation time 110516847 ps
CPU time 4.07 seconds
Started Aug 14 05:26:36 PM PDT 24
Finished Aug 14 05:26:40 PM PDT 24
Peak memory 232916 kb
Host smart-76d531f5-e3d3-4574-9b00-6158e0787038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218110540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2218110540
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4087692076
Short name T603
Test name
Test status
Simulation time 202182000 ps
CPU time 4.91 seconds
Started Aug 14 05:26:39 PM PDT 24
Finished Aug 14 05:26:44 PM PDT 24
Peak memory 222672 kb
Host smart-ba6e62c7-285e-492f-a747-fee1fc11ff9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4087692076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4087692076
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3133405979
Short name T22
Test name
Test status
Simulation time 8781333782 ps
CPU time 47.12 seconds
Started Aug 14 05:26:39 PM PDT 24
Finished Aug 14 05:27:26 PM PDT 24
Peak memory 249456 kb
Host smart-86aefafb-3e56-4f37-a809-cbd22fa6ef1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133405979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3133405979
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3448576032
Short name T312
Test name
Test status
Simulation time 6111888438 ps
CPU time 37.36 seconds
Started Aug 14 05:26:38 PM PDT 24
Finished Aug 14 05:27:16 PM PDT 24
Peak memory 216352 kb
Host smart-b7b8d576-f04f-4e1c-bb92-ec75adc4626d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448576032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3448576032
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.598738254
Short name T825
Test name
Test status
Simulation time 2502355421 ps
CPU time 5.25 seconds
Started Aug 14 05:26:38 PM PDT 24
Finished Aug 14 05:26:43 PM PDT 24
Peak memory 216612 kb
Host smart-65c73b58-5db9-46f8-82c3-bf8166b701bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598738254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.598738254
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3922444076
Short name T998
Test name
Test status
Simulation time 1253190598 ps
CPU time 3 seconds
Started Aug 14 05:26:37 PM PDT 24
Finished Aug 14 05:26:40 PM PDT 24
Peak memory 216548 kb
Host smart-d3a900aa-9551-4899-be37-2d53571b5689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922444076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3922444076
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1037564391
Short name T65
Test name
Test status
Simulation time 152618007 ps
CPU time 1.02 seconds
Started Aug 14 05:26:36 PM PDT 24
Finished Aug 14 05:26:37 PM PDT 24
Peak memory 207072 kb
Host smart-4be0a4bb-d36d-4f25-bf57-182580b94c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037564391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1037564391
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.965355098
Short name T1003
Test name
Test status
Simulation time 30208753685 ps
CPU time 26.1 seconds
Started Aug 14 05:26:38 PM PDT 24
Finished Aug 14 05:27:04 PM PDT 24
Peak memory 234356 kb
Host smart-ba1acddf-43a4-4da9-b4e5-ffd479e7a881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965355098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.965355098
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2525655983
Short name T902
Test name
Test status
Simulation time 31073490 ps
CPU time 0.73 seconds
Started Aug 14 05:26:48 PM PDT 24
Finished Aug 14 05:26:49 PM PDT 24
Peak memory 205936 kb
Host smart-10e6cd3e-a64c-4b4e-b0dc-a1e4e5a0fdfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525655983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2525655983
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.877836348
Short name T646
Test name
Test status
Simulation time 2735249671 ps
CPU time 10.86 seconds
Started Aug 14 05:26:46 PM PDT 24
Finished Aug 14 05:26:57 PM PDT 24
Peak memory 224684 kb
Host smart-36617120-db13-4ad8-b408-4ae217cd8890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877836348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.877836348
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1545820378
Short name T871
Test name
Test status
Simulation time 21744904 ps
CPU time 0.79 seconds
Started Aug 14 05:26:38 PM PDT 24
Finished Aug 14 05:26:39 PM PDT 24
Peak memory 206588 kb
Host smart-832aeab4-4d3d-4097-a0a6-c66f8d433e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545820378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1545820378
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4023136661
Short name T418
Test name
Test status
Simulation time 6995688352 ps
CPU time 46.56 seconds
Started Aug 14 05:26:46 PM PDT 24
Finished Aug 14 05:27:33 PM PDT 24
Peak memory 249380 kb
Host smart-85354bf0-075a-489b-89ed-baee733d8cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023136661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4023136661
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2677695557
Short name T755
Test name
Test status
Simulation time 23548272469 ps
CPU time 195.65 seconds
Started Aug 14 05:26:47 PM PDT 24
Finished Aug 14 05:30:03 PM PDT 24
Peak memory 264436 kb
Host smart-f66c1622-8d46-4570-b09f-3b6a60716d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677695557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2677695557
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1218707096
Short name T1002
Test name
Test status
Simulation time 99492799629 ps
CPU time 321.97 seconds
Started Aug 14 05:26:46 PM PDT 24
Finished Aug 14 05:32:08 PM PDT 24
Peak memory 274000 kb
Host smart-463c82f6-5d3b-464b-90b2-fbf80e9ee18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218707096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1218707096
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2121351108
Short name T954
Test name
Test status
Simulation time 16390526472 ps
CPU time 172.03 seconds
Started Aug 14 05:26:47 PM PDT 24
Finished Aug 14 05:29:39 PM PDT 24
Peak memory 265684 kb
Host smart-1ff78618-ab64-4550-8c11-0bbd0f35171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121351108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2121351108
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1455242912
Short name T821
Test name
Test status
Simulation time 1089946146 ps
CPU time 4.34 seconds
Started Aug 14 05:26:48 PM PDT 24
Finished Aug 14 05:26:52 PM PDT 24
Peak memory 224668 kb
Host smart-2d80aa9c-43f8-47f2-a9b8-83e31a4cca20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455242912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1455242912
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1386340122
Short name T210
Test name
Test status
Simulation time 46337156181 ps
CPU time 82.03 seconds
Started Aug 14 05:26:46 PM PDT 24
Finished Aug 14 05:28:08 PM PDT 24
Peak memory 240948 kb
Host smart-447c0a1c-f68b-4119-afff-287e71665cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386340122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1386340122
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3601587337
Short name T679
Test name
Test status
Simulation time 418250365 ps
CPU time 1.1 seconds
Started Aug 14 05:26:37 PM PDT 24
Finished Aug 14 05:26:39 PM PDT 24
Peak memory 216724 kb
Host smart-559c8672-b59c-4cd1-a2bf-2b581c037aa4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601587337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3601587337
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2561336615
Short name T255
Test name
Test status
Simulation time 3049217023 ps
CPU time 6.53 seconds
Started Aug 14 05:26:47 PM PDT 24
Finished Aug 14 05:26:53 PM PDT 24
Peak memory 240908 kb
Host smart-1ed1b05e-fd93-4866-aff0-6a81fa4e2ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561336615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2561336615
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3909107539
Short name T46
Test name
Test status
Simulation time 1711865486 ps
CPU time 6 seconds
Started Aug 14 05:26:46 PM PDT 24
Finished Aug 14 05:26:53 PM PDT 24
Peak memory 224644 kb
Host smart-a98afef2-3019-41e4-ac27-38aea27f6111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909107539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3909107539
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3538323369
Short name T447
Test name
Test status
Simulation time 478616691 ps
CPU time 4.64 seconds
Started Aug 14 05:26:51 PM PDT 24
Finished Aug 14 05:26:56 PM PDT 24
Peak memory 219036 kb
Host smart-c7b38a7f-3b28-4a0f-8f4d-b5df215827e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3538323369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3538323369
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1099301569
Short name T730
Test name
Test status
Simulation time 21451118616 ps
CPU time 29.64 seconds
Started Aug 14 05:26:47 PM PDT 24
Finished Aug 14 05:27:17 PM PDT 24
Peak memory 216556 kb
Host smart-e153d1ad-1ab2-4d33-a416-3bd760b4905c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099301569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1099301569
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4258677250
Short name T396
Test name
Test status
Simulation time 13863172 ps
CPU time 0.7 seconds
Started Aug 14 05:26:38 PM PDT 24
Finished Aug 14 05:26:39 PM PDT 24
Peak memory 205764 kb
Host smart-ea21b475-1dfe-4f25-a2b7-87d8dd05e8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258677250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4258677250
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.130126431
Short name T952
Test name
Test status
Simulation time 27191420 ps
CPU time 1.22 seconds
Started Aug 14 05:26:45 PM PDT 24
Finished Aug 14 05:26:47 PM PDT 24
Peak memory 216500 kb
Host smart-f90e74e1-9df9-4779-b6f7-deec04213dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130126431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.130126431
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1615856313
Short name T802
Test name
Test status
Simulation time 38224062 ps
CPU time 0.74 seconds
Started Aug 14 05:26:46 PM PDT 24
Finished Aug 14 05:26:47 PM PDT 24
Peak memory 206148 kb
Host smart-97d6363b-b6de-489a-abdc-ec113a06df40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615856313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1615856313
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3031003234
Short name T53
Test name
Test status
Simulation time 562291411 ps
CPU time 5.52 seconds
Started Aug 14 05:26:47 PM PDT 24
Finished Aug 14 05:26:53 PM PDT 24
Peak memory 224644 kb
Host smart-bb1c4bd0-5874-48b3-b614-66870773325c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031003234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3031003234
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3040499775
Short name T337
Test name
Test status
Simulation time 16038079 ps
CPU time 0.69 seconds
Started Aug 14 05:26:46 PM PDT 24
Finished Aug 14 05:26:47 PM PDT 24
Peak memory 204996 kb
Host smart-20037b34-6a58-4388-a3a0-116b821d7feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040499775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3040499775
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2552736586
Short name T901
Test name
Test status
Simulation time 3028151124 ps
CPU time 10.15 seconds
Started Aug 14 05:26:48 PM PDT 24
Finished Aug 14 05:26:58 PM PDT 24
Peak memory 224744 kb
Host smart-fc8febb0-30f1-4535-9dfc-3ba8910c6bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552736586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2552736586
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4176987523
Short name T788
Test name
Test status
Simulation time 33279894 ps
CPU time 0.77 seconds
Started Aug 14 05:26:46 PM PDT 24
Finished Aug 14 05:26:47 PM PDT 24
Peak memory 206640 kb
Host smart-59f0b5e7-e43a-48ba-bedf-3b5093e0585f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176987523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4176987523
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3408992446
Short name T169
Test name
Test status
Simulation time 4021366319 ps
CPU time 62.2 seconds
Started Aug 14 05:26:49 PM PDT 24
Finished Aug 14 05:27:51 PM PDT 24
Peak memory 249112 kb
Host smart-3d177a5a-bd30-46a9-87e9-bf9e88719e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408992446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3408992446
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.384554468
Short name T297
Test name
Test status
Simulation time 1772937013 ps
CPU time 12.28 seconds
Started Aug 14 05:26:46 PM PDT 24
Finished Aug 14 05:26:58 PM PDT 24
Peak memory 232948 kb
Host smart-6888d841-d73b-4bf4-9995-f00613e9361a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384554468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.384554468
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3245096091
Short name T855
Test name
Test status
Simulation time 1876606414 ps
CPU time 27.26 seconds
Started Aug 14 05:26:48 PM PDT 24
Finished Aug 14 05:27:16 PM PDT 24
Peak memory 241028 kb
Host smart-2240b45c-e1e8-4669-a27e-7730aed761c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245096091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3245096091
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1688999422
Short name T90
Test name
Test status
Simulation time 1400180811 ps
CPU time 3.95 seconds
Started Aug 14 05:26:52 PM PDT 24
Finished Aug 14 05:26:56 PM PDT 24
Peak memory 224788 kb
Host smart-61f40667-a851-445c-8e7d-7b6ce1cb4d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688999422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1688999422
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2521623748
Short name T222
Test name
Test status
Simulation time 1424409153 ps
CPU time 15.67 seconds
Started Aug 14 05:26:49 PM PDT 24
Finished Aug 14 05:27:05 PM PDT 24
Peak memory 224720 kb
Host smart-3aa0fdeb-2e61-4ff0-9bfa-898021768e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521623748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2521623748
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.280393951
Short name T956
Test name
Test status
Simulation time 4933018543 ps
CPU time 15.5 seconds
Started Aug 14 05:26:54 PM PDT 24
Finished Aug 14 05:27:09 PM PDT 24
Peak memory 240204 kb
Host smart-8ec9c276-3434-4767-aebd-785a03618ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280393951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.280393951
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1554981318
Short name T918
Test name
Test status
Simulation time 7460625619 ps
CPU time 10.49 seconds
Started Aug 14 05:26:51 PM PDT 24
Finished Aug 14 05:27:02 PM PDT 24
Peak memory 232856 kb
Host smart-f90e4a2c-a5bc-4690-b365-d8784f1e66e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554981318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1554981318
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.111456261
Short name T1011
Test name
Test status
Simulation time 1224568045 ps
CPU time 15.82 seconds
Started Aug 14 05:26:50 PM PDT 24
Finished Aug 14 05:27:06 PM PDT 24
Peak memory 222080 kb
Host smart-9ca853c2-14ac-4005-a327-1a64c81e0e7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=111456261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.111456261
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3154602699
Short name T921
Test name
Test status
Simulation time 133101435397 ps
CPU time 209.58 seconds
Started Aug 14 05:26:51 PM PDT 24
Finished Aug 14 05:30:21 PM PDT 24
Peak memory 262476 kb
Host smart-b6374115-97d5-4cfc-b04d-f6acb6d1b085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154602699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3154602699
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1145054582
Short name T402
Test name
Test status
Simulation time 22992772343 ps
CPU time 7.17 seconds
Started Aug 14 05:26:50 PM PDT 24
Finished Aug 14 05:26:57 PM PDT 24
Peak memory 216612 kb
Host smart-cf6b6cfc-93a2-4760-b8fa-0adeb123f6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145054582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1145054582
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3063840726
Short name T715
Test name
Test status
Simulation time 17942426680 ps
CPU time 11.42 seconds
Started Aug 14 05:26:49 PM PDT 24
Finished Aug 14 05:27:01 PM PDT 24
Peak memory 217620 kb
Host smart-277d4ac2-941b-466e-9013-f3870c8f828e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063840726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3063840726
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2027996418
Short name T452
Test name
Test status
Simulation time 294743072 ps
CPU time 1.36 seconds
Started Aug 14 05:26:47 PM PDT 24
Finished Aug 14 05:26:48 PM PDT 24
Peak memory 216484 kb
Host smart-b770fff9-cdf7-45bc-811c-c1a5aaa63bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027996418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2027996418
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4219160836
Short name T359
Test name
Test status
Simulation time 219855342 ps
CPU time 0.88 seconds
Started Aug 14 05:26:52 PM PDT 24
Finished Aug 14 05:26:53 PM PDT 24
Peak memory 207244 kb
Host smart-4f0293bd-f5e6-41d2-a314-78bf729297f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219160836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4219160836
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1371164709
Short name T6
Test name
Test status
Simulation time 85157648 ps
CPU time 2.24 seconds
Started Aug 14 05:26:46 PM PDT 24
Finished Aug 14 05:26:49 PM PDT 24
Peak memory 224724 kb
Host smart-d10e3714-4ede-40c4-9440-31676b9d5f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371164709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1371164709
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1094689844
Short name T324
Test name
Test status
Simulation time 114059427 ps
CPU time 2.59 seconds
Started Aug 14 05:26:56 PM PDT 24
Finished Aug 14 05:26:59 PM PDT 24
Peak memory 232448 kb
Host smart-8c320f65-ca1f-44ea-93f2-ed34999ab291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094689844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1094689844
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.643810345
Short name T734
Test name
Test status
Simulation time 16695612 ps
CPU time 0.73 seconds
Started Aug 14 05:26:57 PM PDT 24
Finished Aug 14 05:26:57 PM PDT 24
Peak memory 205884 kb
Host smart-ddf73b03-dff0-4487-a942-1f6538dcfc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643810345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.643810345
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2291913114
Short name T294
Test name
Test status
Simulation time 507264956767 ps
CPU time 269.96 seconds
Started Aug 14 05:26:55 PM PDT 24
Finished Aug 14 05:31:25 PM PDT 24
Peak memory 265084 kb
Host smart-beaf413e-63ef-46a6-9c9e-374ae1c20b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291913114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2291913114
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.995255482
Short name T815
Test name
Test status
Simulation time 1738560749 ps
CPU time 11.77 seconds
Started Aug 14 05:26:54 PM PDT 24
Finished Aug 14 05:27:06 PM PDT 24
Peak memory 217708 kb
Host smart-0440a853-b557-4839-aa3d-302d61bd1dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995255482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.995255482
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3682618792
Short name T594
Test name
Test status
Simulation time 10159349892 ps
CPU time 36.4 seconds
Started Aug 14 05:26:54 PM PDT 24
Finished Aug 14 05:27:30 PM PDT 24
Peak memory 236708 kb
Host smart-a480dcf5-46a9-48d6-ad06-a6d471076af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682618792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3682618792
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.76926740
Short name T474
Test name
Test status
Simulation time 1804398020 ps
CPU time 8.25 seconds
Started Aug 14 05:26:56 PM PDT 24
Finished Aug 14 05:27:05 PM PDT 24
Peak memory 224656 kb
Host smart-0af1be69-3d44-4e3f-9365-520cdc0fc994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76926740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.76926740
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1360486401
Short name T196
Test name
Test status
Simulation time 61628106045 ps
CPU time 104.81 seconds
Started Aug 14 05:26:54 PM PDT 24
Finished Aug 14 05:28:39 PM PDT 24
Peak memory 234996 kb
Host smart-8535341c-2401-4099-a914-9cf7a47a358a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360486401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1360486401
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3576858865
Short name T267
Test name
Test status
Simulation time 1964845863 ps
CPU time 5.16 seconds
Started Aug 14 05:26:55 PM PDT 24
Finished Aug 14 05:27:00 PM PDT 24
Peak memory 224668 kb
Host smart-6bd96a2f-0f5d-4e3f-a5f6-f9acf9cb1ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576858865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3576858865
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3599647694
Short name T640
Test name
Test status
Simulation time 4956282493 ps
CPU time 21.58 seconds
Started Aug 14 05:26:56 PM PDT 24
Finished Aug 14 05:27:17 PM PDT 24
Peak memory 232988 kb
Host smart-0e3db465-102f-4352-b78e-6385ffc95389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599647694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3599647694
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1273599746
Short name T34
Test name
Test status
Simulation time 16562443 ps
CPU time 1.04 seconds
Started Aug 14 05:26:56 PM PDT 24
Finished Aug 14 05:26:57 PM PDT 24
Peak memory 216768 kb
Host smart-887ff5d5-a772-437e-8b0e-62c32153b426
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273599746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1273599746
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4273248164
Short name T554
Test name
Test status
Simulation time 7664184941 ps
CPU time 24.18 seconds
Started Aug 14 05:26:55 PM PDT 24
Finished Aug 14 05:27:19 PM PDT 24
Peak memory 232968 kb
Host smart-13b956cb-5191-4c23-bffe-5a5bd22251bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273248164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4273248164
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1083323270
Short name T365
Test name
Test status
Simulation time 201014521 ps
CPU time 2.18 seconds
Started Aug 14 05:26:54 PM PDT 24
Finished Aug 14 05:26:56 PM PDT 24
Peak memory 224544 kb
Host smart-e4d53321-4eba-423f-b480-fe3cad48f9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083323270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1083323270
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1777529664
Short name T671
Test name
Test status
Simulation time 2064100800 ps
CPU time 7.66 seconds
Started Aug 14 05:26:55 PM PDT 24
Finished Aug 14 05:27:03 PM PDT 24
Peak memory 219440 kb
Host smart-db3c827b-71cd-4bc0-b4b6-ac662f18d04d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1777529664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1777529664
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3549094186
Short name T272
Test name
Test status
Simulation time 41115532179 ps
CPU time 442.69 seconds
Started Aug 14 05:26:57 PM PDT 24
Finished Aug 14 05:34:20 PM PDT 24
Peak memory 282452 kb
Host smart-80d7f1cd-137d-49b4-8f4b-a90766316ed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549094186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3549094186
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1722240489
Short name T27
Test name
Test status
Simulation time 12060262045 ps
CPU time 14.34 seconds
Started Aug 14 05:26:57 PM PDT 24
Finished Aug 14 05:27:11 PM PDT 24
Peak memory 216604 kb
Host smart-178a81f8-1d2c-4dba-9f5b-fed2db8e0ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722240489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1722240489
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3811726089
Short name T463
Test name
Test status
Simulation time 360047475 ps
CPU time 1.46 seconds
Started Aug 14 05:26:56 PM PDT 24
Finished Aug 14 05:26:58 PM PDT 24
Peak memory 208132 kb
Host smart-ff8885fe-7b62-4d5d-9824-bb71fcbee7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811726089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3811726089
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3571157944
Short name T895
Test name
Test status
Simulation time 466245322 ps
CPU time 2.07 seconds
Started Aug 14 05:26:58 PM PDT 24
Finished Aug 14 05:27:00 PM PDT 24
Peak memory 216636 kb
Host smart-2fa5945c-30a7-4345-aa7e-f304e79e8cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571157944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3571157944
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3754539355
Short name T757
Test name
Test status
Simulation time 360479238 ps
CPU time 0.97 seconds
Started Aug 14 05:26:55 PM PDT 24
Finished Aug 14 05:26:56 PM PDT 24
Peak memory 207184 kb
Host smart-bf9a7737-c9c3-4d2e-a2b2-caae7f8e096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754539355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3754539355
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4171420188
Short name T248
Test name
Test status
Simulation time 1992388670 ps
CPU time 4.72 seconds
Started Aug 14 05:26:56 PM PDT 24
Finished Aug 14 05:27:01 PM PDT 24
Peak memory 234308 kb
Host smart-fcc90259-9008-45fb-a4db-4ef58b3fe53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171420188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4171420188
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.219796366
Short name T335
Test name
Test status
Simulation time 46419970 ps
CPU time 0.79 seconds
Started Aug 14 05:27:06 PM PDT 24
Finished Aug 14 05:27:07 PM PDT 24
Peak memory 205936 kb
Host smart-40569dc6-3f1b-4fa1-b879-bde64ae65651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219796366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.219796366
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3294087682
Short name T486
Test name
Test status
Simulation time 204190398 ps
CPU time 2.6 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:08 PM PDT 24
Peak memory 224688 kb
Host smart-2d760f85-c69d-4af3-9611-726bc200d592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294087682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3294087682
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.699354232
Short name T564
Test name
Test status
Simulation time 32659029 ps
CPU time 0.78 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:06 PM PDT 24
Peak memory 206660 kb
Host smart-e1cb2db4-5250-4dde-a435-1b1639833370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699354232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.699354232
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3636616800
Short name T894
Test name
Test status
Simulation time 37013500294 ps
CPU time 269.22 seconds
Started Aug 14 05:27:04 PM PDT 24
Finished Aug 14 05:31:33 PM PDT 24
Peak memory 257292 kb
Host smart-cabccaa7-fa94-4279-962a-5b321324f7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636616800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3636616800
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4130708717
Short name T741
Test name
Test status
Simulation time 3460873966 ps
CPU time 32.73 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:38 PM PDT 24
Peak memory 241424 kb
Host smart-65e3a2ec-3f07-4b21-b538-7c95ca6dc8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130708717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4130708717
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2254503018
Short name T416
Test name
Test status
Simulation time 38236197739 ps
CPU time 210.52 seconds
Started Aug 14 05:27:04 PM PDT 24
Finished Aug 14 05:30:35 PM PDT 24
Peak memory 257596 kb
Host smart-31ac4fa7-f93e-44f2-804c-ac4f68f28384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254503018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2254503018
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2271666867
Short name T308
Test name
Test status
Simulation time 2714976089 ps
CPU time 9.4 seconds
Started Aug 14 05:27:04 PM PDT 24
Finished Aug 14 05:27:14 PM PDT 24
Peak memory 240428 kb
Host smart-97ea1f10-4776-4856-a682-96ea6e8e6d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271666867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2271666867
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3326870649
Short name T295
Test name
Test status
Simulation time 9103924761 ps
CPU time 19.7 seconds
Started Aug 14 05:27:06 PM PDT 24
Finished Aug 14 05:27:26 PM PDT 24
Peak memory 241200 kb
Host smart-c27379b7-5ff1-4bbb-946b-109d921e5b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326870649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3326870649
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2095596064
Short name T659
Test name
Test status
Simulation time 6262443398 ps
CPU time 8.69 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:14 PM PDT 24
Peak memory 224704 kb
Host smart-0d49a7ac-ec57-4f83-94fe-0634ff4a2d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095596064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2095596064
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3625963202
Short name T9
Test name
Test status
Simulation time 1340375880 ps
CPU time 8.51 seconds
Started Aug 14 05:27:06 PM PDT 24
Finished Aug 14 05:27:14 PM PDT 24
Peak memory 238924 kb
Host smart-e2f8a116-e0c7-461b-9ea0-406e4dd3962a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625963202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3625963202
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2825212118
Short name T633
Test name
Test status
Simulation time 35654290 ps
CPU time 1.12 seconds
Started Aug 14 05:26:54 PM PDT 24
Finished Aug 14 05:26:55 PM PDT 24
Peak memory 216744 kb
Host smart-90810a1a-0086-4d7e-b411-6b12dcdeec14
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825212118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2825212118
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3402857818
Short name T96
Test name
Test status
Simulation time 785593737 ps
CPU time 6.22 seconds
Started Aug 14 05:27:06 PM PDT 24
Finished Aug 14 05:27:12 PM PDT 24
Peak memory 239716 kb
Host smart-eb6f6df2-57c8-4b47-a07f-8ae9633ff715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402857818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3402857818
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2701099686
Short name T696
Test name
Test status
Simulation time 278058122 ps
CPU time 2.91 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:08 PM PDT 24
Peak memory 224680 kb
Host smart-3f7176c6-0c84-4995-b785-e00116d9eced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701099686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2701099686
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4023466293
Short name T395
Test name
Test status
Simulation time 1186848809 ps
CPU time 10.17 seconds
Started Aug 14 05:27:07 PM PDT 24
Finished Aug 14 05:27:17 PM PDT 24
Peak memory 221224 kb
Host smart-60ba2590-6508-496d-802c-fc955f5f085e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4023466293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4023466293
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3985391669
Short name T906
Test name
Test status
Simulation time 1657130190 ps
CPU time 25.45 seconds
Started Aug 14 05:26:55 PM PDT 24
Finished Aug 14 05:27:20 PM PDT 24
Peak memory 216456 kb
Host smart-8d76d7b9-5002-4d19-8a7f-ef65d037778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985391669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3985391669
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.653704268
Short name T449
Test name
Test status
Simulation time 794626605 ps
CPU time 2.32 seconds
Started Aug 14 05:26:55 PM PDT 24
Finished Aug 14 05:26:58 PM PDT 24
Peak memory 216520 kb
Host smart-aa2c5a4a-ead6-4d92-8f45-55ab3854289f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653704268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.653704268
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3204208432
Short name T407
Test name
Test status
Simulation time 25125110 ps
CPU time 1.15 seconds
Started Aug 14 05:26:57 PM PDT 24
Finished Aug 14 05:26:59 PM PDT 24
Peak memory 207504 kb
Host smart-9d05687d-3c71-4674-a5e2-018302df4113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204208432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3204208432
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4239939769
Short name T499
Test name
Test status
Simulation time 75377142 ps
CPU time 0.9 seconds
Started Aug 14 05:26:55 PM PDT 24
Finished Aug 14 05:26:56 PM PDT 24
Peak memory 206144 kb
Host smart-33b659bc-d31e-4146-bd7c-693b04b15614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239939769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4239939769
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1295257955
Short name T752
Test name
Test status
Simulation time 1142779168 ps
CPU time 7.26 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:12 PM PDT 24
Peak memory 224696 kb
Host smart-2ccc73be-9357-4f34-97a3-5f293176b668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295257955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1295257955
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2127988298
Short name T320
Test name
Test status
Simulation time 29861880 ps
CPU time 0.7 seconds
Started Aug 14 05:27:04 PM PDT 24
Finished Aug 14 05:27:05 PM PDT 24
Peak memory 205492 kb
Host smart-5c1b8203-0dc3-4026-b4ff-117c8721a128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127988298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2127988298
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2647901858
Short name T458
Test name
Test status
Simulation time 161826259 ps
CPU time 2.61 seconds
Started Aug 14 05:27:03 PM PDT 24
Finished Aug 14 05:27:06 PM PDT 24
Peak memory 232848 kb
Host smart-4bb325a7-047c-4e84-bf5d-919d460bb56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647901858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2647901858
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1712974743
Short name T555
Test name
Test status
Simulation time 21559272 ps
CPU time 0.79 seconds
Started Aug 14 05:27:04 PM PDT 24
Finished Aug 14 05:27:05 PM PDT 24
Peak memory 206640 kb
Host smart-2be06046-8d15-485d-acca-8b69b5627e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712974743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1712974743
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.689841938
Short name T881
Test name
Test status
Simulation time 1174744838 ps
CPU time 20.5 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:26 PM PDT 24
Peak memory 238236 kb
Host smart-57902007-f904-4542-ae85-2f4821e0f727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689841938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.689841938
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1253273948
Short name T648
Test name
Test status
Simulation time 4893352324 ps
CPU time 33.12 seconds
Started Aug 14 05:27:06 PM PDT 24
Finished Aug 14 05:27:39 PM PDT 24
Peak memory 251448 kb
Host smart-8467be5d-c725-4df2-bd46-02f71712ff35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253273948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1253273948
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3497266793
Short name T546
Test name
Test status
Simulation time 749893368 ps
CPU time 7.87 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:13 PM PDT 24
Peak memory 224732 kb
Host smart-eab4e65b-ae54-4679-a3cd-82411e86272f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497266793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3497266793
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3478778446
Short name T439
Test name
Test status
Simulation time 3327477688 ps
CPU time 16.72 seconds
Started Aug 14 05:27:04 PM PDT 24
Finished Aug 14 05:27:21 PM PDT 24
Peak memory 239400 kb
Host smart-32ad6c6a-9641-41b0-a03b-a14462273d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478778446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3478778446
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.580108357
Short name T658
Test name
Test status
Simulation time 286837933 ps
CPU time 3.5 seconds
Started Aug 14 05:27:08 PM PDT 24
Finished Aug 14 05:27:12 PM PDT 24
Peak memory 232952 kb
Host smart-640d63d7-3491-4f05-b9fa-9b058d50286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580108357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.580108357
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2539274694
Short name T498
Test name
Test status
Simulation time 2164425801 ps
CPU time 14.46 seconds
Started Aug 14 05:27:06 PM PDT 24
Finished Aug 14 05:27:20 PM PDT 24
Peak memory 249080 kb
Host smart-cce29aba-d1b1-4423-8311-01f104196361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539274694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2539274694
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1087271127
Short name T744
Test name
Test status
Simulation time 25443078 ps
CPU time 1.04 seconds
Started Aug 14 05:27:07 PM PDT 24
Finished Aug 14 05:27:08 PM PDT 24
Peak memory 217992 kb
Host smart-bf290d3d-4ed3-42b9-ab4d-0a3cfcae493d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087271127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1087271127
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3942978363
Short name T508
Test name
Test status
Simulation time 826858109 ps
CPU time 3.17 seconds
Started Aug 14 05:27:07 PM PDT 24
Finished Aug 14 05:27:10 PM PDT 24
Peak memory 232900 kb
Host smart-12539897-51c4-4442-afa0-a65e17e4ec60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942978363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3942978363
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2100018544
Short name T237
Test name
Test status
Simulation time 175980598 ps
CPU time 2.38 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:07 PM PDT 24
Peak memory 232920 kb
Host smart-dd5a4da7-8ce0-4076-b869-a14ca65fd76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100018544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2100018544
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.103818757
Short name T629
Test name
Test status
Simulation time 4723551159 ps
CPU time 11.27 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:16 PM PDT 24
Peak memory 222844 kb
Host smart-b261e30c-c770-49a1-9316-ce7fbb9cc6ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=103818757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.103818757
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2944614995
Short name T161
Test name
Test status
Simulation time 38239923132 ps
CPU time 148.94 seconds
Started Aug 14 05:27:07 PM PDT 24
Finished Aug 14 05:29:36 PM PDT 24
Peak memory 250852 kb
Host smart-b67492ad-b6d0-49b8-b1ca-5451d400e024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944614995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2944614995
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.624251219
Short name T87
Test name
Test status
Simulation time 3142901433 ps
CPU time 18.65 seconds
Started Aug 14 05:27:03 PM PDT 24
Finished Aug 14 05:27:22 PM PDT 24
Peak memory 216556 kb
Host smart-b498c315-7432-47b1-8af1-0d43078dbc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624251219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.624251219
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.474763606
Short name T1005
Test name
Test status
Simulation time 588643835 ps
CPU time 2.96 seconds
Started Aug 14 05:27:08 PM PDT 24
Finished Aug 14 05:27:12 PM PDT 24
Peak memory 216496 kb
Host smart-6acc7fab-a6bc-472b-9c3f-2626910212e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474763606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.474763606
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4267094751
Short name T713
Test name
Test status
Simulation time 553653685 ps
CPU time 1.98 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:07 PM PDT 24
Peak memory 216464 kb
Host smart-d0655013-0b60-49b5-86bc-c7a783b0daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267094751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4267094751
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2040624552
Short name T993
Test name
Test status
Simulation time 335845763 ps
CPU time 0.91 seconds
Started Aug 14 05:27:05 PM PDT 24
Finished Aug 14 05:27:06 PM PDT 24
Peak memory 207136 kb
Host smart-bafff7df-b9a2-4e0b-860f-6b91083b960d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040624552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2040624552
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.780096607
Short name T674
Test name
Test status
Simulation time 4790968553 ps
CPU time 18.62 seconds
Started Aug 14 05:27:04 PM PDT 24
Finished Aug 14 05:27:23 PM PDT 24
Peak memory 236520 kb
Host smart-db956ea4-460a-43e7-8c8d-60dbf7832d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780096607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.780096607
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4269901769
Short name T840
Test name
Test status
Simulation time 26212981 ps
CPU time 0.72 seconds
Started Aug 14 05:27:15 PM PDT 24
Finished Aug 14 05:27:16 PM PDT 24
Peak memory 205904 kb
Host smart-191cfb1a-f958-4b61-abc5-4e8aa77aa16c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269901769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4269901769
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3049417305
Short name T356
Test name
Test status
Simulation time 262746289 ps
CPU time 6.18 seconds
Started Aug 14 05:27:14 PM PDT 24
Finished Aug 14 05:27:21 PM PDT 24
Peak memory 232884 kb
Host smart-2adf2cac-9b2c-4098-bc25-e6504023b908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049417305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3049417305
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1312283823
Short name T738
Test name
Test status
Simulation time 19552165 ps
CPU time 0.8 seconds
Started Aug 14 05:27:15 PM PDT 24
Finished Aug 14 05:27:15 PM PDT 24
Peak memory 207004 kb
Host smart-aea8d3df-ece6-474d-b499-a70352e3fd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312283823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1312283823
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3353713532
Short name T720
Test name
Test status
Simulation time 20697480 ps
CPU time 0.71 seconds
Started Aug 14 05:27:13 PM PDT 24
Finished Aug 14 05:27:14 PM PDT 24
Peak memory 215904 kb
Host smart-7ce6bd33-52a7-4ae1-9299-3ab4d41e4cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353713532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3353713532
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2131281224
Short name T649
Test name
Test status
Simulation time 29384241968 ps
CPU time 244.81 seconds
Started Aug 14 05:27:16 PM PDT 24
Finished Aug 14 05:31:21 PM PDT 24
Peak memory 254956 kb
Host smart-e4b01175-4fe0-42ad-950e-7a786f256d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131281224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2131281224
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3854561535
Short name T288
Test name
Test status
Simulation time 46129822761 ps
CPU time 143.88 seconds
Started Aug 14 05:27:16 PM PDT 24
Finished Aug 14 05:29:40 PM PDT 24
Peak memory 256888 kb
Host smart-033d12b4-ab4e-4b7c-b71e-254c03b146c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854561535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3854561535
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1888126802
Short name T303
Test name
Test status
Simulation time 382111529 ps
CPU time 7.83 seconds
Started Aug 14 05:27:17 PM PDT 24
Finished Aug 14 05:27:24 PM PDT 24
Peak memory 249164 kb
Host smart-4761403c-c981-412d-9a92-9b1ff66efd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888126802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1888126802
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1957483107
Short name T200
Test name
Test status
Simulation time 10087088972 ps
CPU time 56.72 seconds
Started Aug 14 05:27:16 PM PDT 24
Finished Aug 14 05:28:12 PM PDT 24
Peak memory 249380 kb
Host smart-9e94689c-25b6-440b-8a65-5ff5cddcb09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957483107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1957483107
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3118347151
Short name T971
Test name
Test status
Simulation time 209059021 ps
CPU time 3.68 seconds
Started Aug 14 05:27:14 PM PDT 24
Finished Aug 14 05:27:18 PM PDT 24
Peak memory 232948 kb
Host smart-0b9fbb09-9168-4547-8297-399f09a51579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118347151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3118347151
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2590266199
Short name T523
Test name
Test status
Simulation time 136113137 ps
CPU time 2.61 seconds
Started Aug 14 05:27:15 PM PDT 24
Finished Aug 14 05:27:18 PM PDT 24
Peak memory 232904 kb
Host smart-c9ca9b0f-8ae8-41f8-b3b5-159611ad1c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590266199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2590266199
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2078949499
Short name T464
Test name
Test status
Simulation time 43357805 ps
CPU time 1.03 seconds
Started Aug 14 05:27:14 PM PDT 24
Finished Aug 14 05:27:15 PM PDT 24
Peak memory 216768 kb
Host smart-b40dd783-3622-493c-8622-9bb4445abde1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078949499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2078949499
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.451707600
Short name T13
Test name
Test status
Simulation time 58777079239 ps
CPU time 19.06 seconds
Started Aug 14 05:27:16 PM PDT 24
Finished Aug 14 05:27:35 PM PDT 24
Peak memory 241012 kb
Host smart-d2fe365d-842c-4008-ae67-e6d657cc747c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451707600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.451707600
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.523553781
Short name T784
Test name
Test status
Simulation time 1863056733 ps
CPU time 7.46 seconds
Started Aug 14 05:27:19 PM PDT 24
Finished Aug 14 05:27:27 PM PDT 24
Peak memory 232636 kb
Host smart-f9452a19-59eb-41bc-9f52-861d17dc0f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523553781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.523553781
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1638792677
Short name T150
Test name
Test status
Simulation time 915484396 ps
CPU time 6.38 seconds
Started Aug 14 05:27:15 PM PDT 24
Finished Aug 14 05:27:21 PM PDT 24
Peak memory 219384 kb
Host smart-6c857e81-add9-4f06-8c1b-d95ddbcaa2e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1638792677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1638792677
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2547245777
Short name T495
Test name
Test status
Simulation time 150372061 ps
CPU time 0.9 seconds
Started Aug 14 05:27:15 PM PDT 24
Finished Aug 14 05:27:16 PM PDT 24
Peak memory 207460 kb
Host smart-a1e65faa-a4bd-41c9-9c63-44af63c523e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547245777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2547245777
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3730219566
Short name T394
Test name
Test status
Simulation time 19845735 ps
CPU time 0.72 seconds
Started Aug 14 05:27:14 PM PDT 24
Finished Aug 14 05:27:14 PM PDT 24
Peak memory 205760 kb
Host smart-1102243d-5039-4c37-bce7-0717e30709af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730219566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3730219566
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.408714665
Short name T943
Test name
Test status
Simulation time 115006306 ps
CPU time 0.92 seconds
Started Aug 14 05:27:15 PM PDT 24
Finished Aug 14 05:27:16 PM PDT 24
Peak memory 207116 kb
Host smart-656a8194-acb2-446e-af1e-21474db5f5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408714665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.408714665
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2973510204
Short name T675
Test name
Test status
Simulation time 82921118 ps
CPU time 0.8 seconds
Started Aug 14 05:27:15 PM PDT 24
Finished Aug 14 05:27:16 PM PDT 24
Peak memory 206160 kb
Host smart-e5abba21-8414-48ca-89e8-bde9c112b8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973510204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2973510204
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.4009029163
Short name T961
Test name
Test status
Simulation time 30670975411 ps
CPU time 27.62 seconds
Started Aug 14 05:27:14 PM PDT 24
Finished Aug 14 05:27:42 PM PDT 24
Peak memory 240740 kb
Host smart-6b4e248a-2a47-4bc8-9cf6-cb31bacc065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009029163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4009029163
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1549071730
Short name T922
Test name
Test status
Simulation time 42352628 ps
CPU time 0.69 seconds
Started Aug 14 05:27:14 PM PDT 24
Finished Aug 14 05:27:15 PM PDT 24
Peak memory 205552 kb
Host smart-2c1fb463-07f7-493e-8926-9808d7d43836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549071730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1549071730
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.217511526
Short name T836
Test name
Test status
Simulation time 761206059 ps
CPU time 2.79 seconds
Started Aug 14 05:27:15 PM PDT 24
Finished Aug 14 05:27:18 PM PDT 24
Peak memory 224644 kb
Host smart-9e2a388d-497b-4f44-8f90-beb46a792170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217511526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.217511526
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2539364048
Short name T792
Test name
Test status
Simulation time 43800352 ps
CPU time 0.75 seconds
Started Aug 14 05:27:20 PM PDT 24
Finished Aug 14 05:27:21 PM PDT 24
Peak memory 205568 kb
Host smart-87be114f-8c47-417c-8e59-c6bf7823d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539364048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2539364048
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.394960600
Short name T736
Test name
Test status
Simulation time 11146915235 ps
CPU time 58.65 seconds
Started Aug 14 05:27:17 PM PDT 24
Finished Aug 14 05:28:16 PM PDT 24
Peak memory 253228 kb
Host smart-a16e38df-3701-436f-b7f1-e64020e24989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394960600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.394960600
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2671975852
Short name T624
Test name
Test status
Simulation time 138174144345 ps
CPU time 493.19 seconds
Started Aug 14 05:27:20 PM PDT 24
Finished Aug 14 05:35:33 PM PDT 24
Peak memory 255676 kb
Host smart-aeded1fe-1c9b-439a-838e-3a78d45c57a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671975852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2671975852
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1684276357
Short name T275
Test name
Test status
Simulation time 116935313533 ps
CPU time 169.05 seconds
Started Aug 14 05:27:17 PM PDT 24
Finished Aug 14 05:30:06 PM PDT 24
Peak memory 249680 kb
Host smart-bf91557a-4f3f-432d-80d5-79cf6c4e0159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684276357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1684276357
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.776677507
Short name T305
Test name
Test status
Simulation time 854383186 ps
CPU time 6.53 seconds
Started Aug 14 05:27:17 PM PDT 24
Finished Aug 14 05:27:24 PM PDT 24
Peak memory 232992 kb
Host smart-88d867aa-8e08-4f76-b1e8-2f3d6515846c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776677507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.776677507
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.253418453
Short name T586
Test name
Test status
Simulation time 49785262690 ps
CPU time 224.71 seconds
Started Aug 14 05:27:14 PM PDT 24
Finished Aug 14 05:30:59 PM PDT 24
Peak memory 249380 kb
Host smart-eead4372-1360-4840-97e7-92fd07c8d3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253418453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds
.253418453
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3367066625
Short name T441
Test name
Test status
Simulation time 2685440975 ps
CPU time 6.91 seconds
Started Aug 14 05:27:16 PM PDT 24
Finished Aug 14 05:27:23 PM PDT 24
Peak memory 224696 kb
Host smart-c8ff72da-6fdc-4410-87ab-0579467307d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367066625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3367066625
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1467896254
Short name T664
Test name
Test status
Simulation time 410766057 ps
CPU time 2.47 seconds
Started Aug 14 05:27:19 PM PDT 24
Finished Aug 14 05:27:22 PM PDT 24
Peak memory 223124 kb
Host smart-d84f85a6-0341-4a42-a865-d9658f6b82f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467896254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1467896254
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2193197413
Short name T361
Test name
Test status
Simulation time 36242079 ps
CPU time 1.08 seconds
Started Aug 14 05:27:17 PM PDT 24
Finished Aug 14 05:27:18 PM PDT 24
Peak memory 216940 kb
Host smart-6335d5e4-47fb-48c6-bb84-4c9c4b333069
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193197413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2193197413
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3283631101
Short name T835
Test name
Test status
Simulation time 37584086 ps
CPU time 2.46 seconds
Started Aug 14 05:27:17 PM PDT 24
Finished Aug 14 05:27:19 PM PDT 24
Peak memory 232452 kb
Host smart-99b963f8-1cf7-4731-87d9-d688f043bc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283631101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3283631101
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3971036708
Short name T977
Test name
Test status
Simulation time 13561147244 ps
CPU time 38.12 seconds
Started Aug 14 05:27:15 PM PDT 24
Finished Aug 14 05:27:53 PM PDT 24
Peak memory 232972 kb
Host smart-25e61401-5c41-4226-9111-fd6940eab881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971036708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3971036708
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2041385014
Short name T345
Test name
Test status
Simulation time 3751970347 ps
CPU time 9.83 seconds
Started Aug 14 05:27:16 PM PDT 24
Finished Aug 14 05:27:26 PM PDT 24
Peak memory 222476 kb
Host smart-e3e8f2e9-5a84-421e-beed-b44d7810b33f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2041385014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2041385014
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.60723041
Short name T795
Test name
Test status
Simulation time 65177349946 ps
CPU time 604.17 seconds
Started Aug 14 05:27:20 PM PDT 24
Finished Aug 14 05:37:24 PM PDT 24
Peak memory 270004 kb
Host smart-08bcfdf4-a8a8-4f67-ab02-19256f13140e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60723041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress
_all.60723041
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1749809286
Short name T803
Test name
Test status
Simulation time 1058680647 ps
CPU time 3.47 seconds
Started Aug 14 05:27:20 PM PDT 24
Finished Aug 14 05:27:24 PM PDT 24
Peak memory 216496 kb
Host smart-dd943e8e-ad2d-4b67-b327-12b72d73f008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749809286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1749809286
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1125444842
Short name T10
Test name
Test status
Simulation time 5068524105 ps
CPU time 14.14 seconds
Started Aug 14 05:27:16 PM PDT 24
Finished Aug 14 05:27:31 PM PDT 24
Peak memory 216596 kb
Host smart-4e7a1bcb-523c-41af-8eff-0d00575b7bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125444842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1125444842
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2795318762
Short name T168
Test name
Test status
Simulation time 332837369 ps
CPU time 2.27 seconds
Started Aug 14 05:27:14 PM PDT 24
Finished Aug 14 05:27:16 PM PDT 24
Peak memory 216392 kb
Host smart-f54627e3-f116-466a-bb0d-fc68d9f7d890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795318762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2795318762
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3839677695
Short name T936
Test name
Test status
Simulation time 136244480 ps
CPU time 1.02 seconds
Started Aug 14 05:27:17 PM PDT 24
Finished Aug 14 05:27:18 PM PDT 24
Peak memory 207140 kb
Host smart-2201afdd-f2c8-4cfd-8044-259cc312bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839677695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3839677695
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2008225505
Short name T974
Test name
Test status
Simulation time 519526145 ps
CPU time 2.39 seconds
Started Aug 14 05:27:17 PM PDT 24
Finished Aug 14 05:27:19 PM PDT 24
Peak memory 224608 kb
Host smart-a8f1f505-2de6-4d9d-8c64-83b26e6c604a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008225505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2008225505
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3215021083
Short name T373
Test name
Test status
Simulation time 14575824 ps
CPU time 0.73 seconds
Started Aug 14 05:25:49 PM PDT 24
Finished Aug 14 05:25:50 PM PDT 24
Peak memory 205836 kb
Host smart-768d0503-6936-4b9a-ad3c-9cfdd72a9b7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215021083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
215021083
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1286812427
Short name T443
Test name
Test status
Simulation time 502638671 ps
CPU time 2.36 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:25:52 PM PDT 24
Peak memory 232856 kb
Host smart-523f3d73-269d-4338-bf61-f29258280715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286812427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1286812427
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4211774940
Short name T994
Test name
Test status
Simulation time 17033985 ps
CPU time 0.8 seconds
Started Aug 14 05:25:40 PM PDT 24
Finished Aug 14 05:25:41 PM PDT 24
Peak memory 206972 kb
Host smart-0948dc83-89e5-46cb-84b5-7b641d5fc6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211774940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4211774940
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1361681926
Short name T605
Test name
Test status
Simulation time 16055300 ps
CPU time 0.77 seconds
Started Aug 14 05:25:46 PM PDT 24
Finished Aug 14 05:25:47 PM PDT 24
Peak memory 215908 kb
Host smart-edb2d4e6-751e-4ecd-9e5a-387e730db018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361681926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1361681926
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3798816064
Short name T909
Test name
Test status
Simulation time 3768203075 ps
CPU time 33.97 seconds
Started Aug 14 05:25:49 PM PDT 24
Finished Aug 14 05:26:23 PM PDT 24
Peak memory 224996 kb
Host smart-be7de9e2-6f69-482e-9586-ad3848fbf451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798816064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3798816064
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1839752172
Short name T483
Test name
Test status
Simulation time 286915703 ps
CPU time 8.23 seconds
Started Aug 14 05:25:48 PM PDT 24
Finished Aug 14 05:25:56 PM PDT 24
Peak memory 232828 kb
Host smart-b20ab773-0b58-4bd2-b777-010f9050d88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839752172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1839752172
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3078048522
Short name T698
Test name
Test status
Simulation time 695103016 ps
CPU time 2.97 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:25:53 PM PDT 24
Peak memory 224700 kb
Host smart-13c1b84e-dd16-49f8-973a-5407653619d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078048522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3078048522
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.628091324
Short name T192
Test name
Test status
Simulation time 942268316 ps
CPU time 21.12 seconds
Started Aug 14 05:25:48 PM PDT 24
Finished Aug 14 05:26:09 PM PDT 24
Peak memory 240376 kb
Host smart-27b66ed9-ad36-4b07-a246-1566b6beccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628091324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.628091324
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1120893882
Short name T35
Test name
Test status
Simulation time 17013689 ps
CPU time 1.03 seconds
Started Aug 14 05:25:40 PM PDT 24
Finished Aug 14 05:25:41 PM PDT 24
Peak memory 216940 kb
Host smart-471de791-f2fb-475a-9221-32a9c5adae30
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120893882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1120893882
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3201350379
Short name T268
Test name
Test status
Simulation time 8597793486 ps
CPU time 5.49 seconds
Started Aug 14 05:25:41 PM PDT 24
Finished Aug 14 05:25:47 PM PDT 24
Peak memory 232928 kb
Host smart-0769f5de-523d-4905-9326-ebf9b1e75b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201350379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3201350379
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2060255497
Short name T929
Test name
Test status
Simulation time 6456812136 ps
CPU time 9.62 seconds
Started Aug 14 05:25:43 PM PDT 24
Finished Aug 14 05:25:53 PM PDT 24
Peak memory 233076 kb
Host smart-1744371a-a27d-4899-adc1-c33ff642695c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060255497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2060255497
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2380297771
Short name T691
Test name
Test status
Simulation time 968541803 ps
CPU time 7.79 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:25:58 PM PDT 24
Peak memory 222780 kb
Host smart-9de81d26-26be-464e-8f02-057f12f0a636
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2380297771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2380297771
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3317205689
Short name T71
Test name
Test status
Simulation time 85358055 ps
CPU time 1.21 seconds
Started Aug 14 05:25:47 PM PDT 24
Finished Aug 14 05:25:49 PM PDT 24
Peak memory 236044 kb
Host smart-4f06f668-7c94-49b0-a97f-0630a178de4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317205689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3317205689
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3852926497
Short name T986
Test name
Test status
Simulation time 121511871375 ps
CPU time 259.99 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:30:10 PM PDT 24
Peak memory 252504 kb
Host smart-0b19b983-6a70-478e-82e8-e51e2d3ae317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852926497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3852926497
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3059266262
Short name T565
Test name
Test status
Simulation time 1879249254 ps
CPU time 13.35 seconds
Started Aug 14 05:25:38 PM PDT 24
Finished Aug 14 05:25:51 PM PDT 24
Peak memory 216492 kb
Host smart-9ab38ae3-0f42-42e8-b73f-dad09a2b9162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059266262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3059266262
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4008370360
Short name T566
Test name
Test status
Simulation time 3131777101 ps
CPU time 4.66 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:25:44 PM PDT 24
Peak memory 216572 kb
Host smart-1783ef86-f2b7-4697-81d8-a4c20f1892cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008370360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4008370360
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2687933013
Short name T732
Test name
Test status
Simulation time 60061121 ps
CPU time 1.08 seconds
Started Aug 14 05:25:40 PM PDT 24
Finished Aug 14 05:25:41 PM PDT 24
Peak memory 208076 kb
Host smart-7608c314-e151-4f5e-8d47-d9febe19718b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687933013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2687933013
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3719965358
Short name T670
Test name
Test status
Simulation time 91932932 ps
CPU time 0.72 seconds
Started Aug 14 05:25:39 PM PDT 24
Finished Aug 14 05:25:40 PM PDT 24
Peak memory 206136 kb
Host smart-c040447a-586e-4bd5-8f5e-ee2bd43d8ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719965358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3719965358
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.4124462462
Short name T239
Test name
Test status
Simulation time 1734120294 ps
CPU time 7.67 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:25:58 PM PDT 24
Peak memory 224664 kb
Host smart-95fc8462-cd7e-4636-a003-65f1e8e8ebe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124462462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.4124462462
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3318354220
Short name T322
Test name
Test status
Simulation time 32873426 ps
CPU time 0.76 seconds
Started Aug 14 05:27:26 PM PDT 24
Finished Aug 14 05:27:27 PM PDT 24
Peak memory 205600 kb
Host smart-f1a18b66-002d-42cd-bb88-73b100c96633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318354220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3318354220
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.105539934
Short name T846
Test name
Test status
Simulation time 290813743 ps
CPU time 4.26 seconds
Started Aug 14 05:27:14 PM PDT 24
Finished Aug 14 05:27:19 PM PDT 24
Peak memory 224668 kb
Host smart-f2d87080-e455-4ca6-9b43-4517f31adda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105539934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.105539934
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3663878375
Short name T512
Test name
Test status
Simulation time 62508483 ps
CPU time 0.74 seconds
Started Aug 14 05:27:21 PM PDT 24
Finished Aug 14 05:27:21 PM PDT 24
Peak memory 205544 kb
Host smart-189db396-f016-42fb-84ba-081e046e6a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663878375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3663878375
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.843806326
Short name T213
Test name
Test status
Simulation time 45771421002 ps
CPU time 109.86 seconds
Started Aug 14 05:27:23 PM PDT 24
Finished Aug 14 05:29:13 PM PDT 24
Peak memory 252472 kb
Host smart-cf0a787f-713c-4359-9463-4aa68121323b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843806326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.843806326
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2464727727
Short name T662
Test name
Test status
Simulation time 48693506598 ps
CPU time 105.44 seconds
Started Aug 14 05:27:23 PM PDT 24
Finished Aug 14 05:29:09 PM PDT 24
Peak memory 249424 kb
Host smart-a428dc3e-6186-407b-867e-ce11717f9a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464727727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2464727727
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1867434792
Short name T167
Test name
Test status
Simulation time 34360610313 ps
CPU time 160.13 seconds
Started Aug 14 05:27:25 PM PDT 24
Finished Aug 14 05:30:05 PM PDT 24
Peak memory 250480 kb
Host smart-88909d04-93f7-4f47-990f-e0a92a4b2018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867434792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1867434792
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.44169570
Short name T399
Test name
Test status
Simulation time 100957697 ps
CPU time 3.72 seconds
Started Aug 14 05:27:25 PM PDT 24
Finished Aug 14 05:27:29 PM PDT 24
Peak memory 224732 kb
Host smart-ca34a487-e22b-42e3-9205-181bb7f0bb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44169570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.44169570
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.958768988
Short name T92
Test name
Test status
Simulation time 7513085224 ps
CPU time 67.75 seconds
Started Aug 14 05:27:25 PM PDT 24
Finished Aug 14 05:28:33 PM PDT 24
Peak memory 257428 kb
Host smart-ee30f944-e58e-41f8-8ef3-6b9e0b8bc5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958768988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.958768988
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3944469071
Short name T501
Test name
Test status
Simulation time 2471884575 ps
CPU time 8.03 seconds
Started Aug 14 05:27:19 PM PDT 24
Finished Aug 14 05:27:27 PM PDT 24
Peak memory 224656 kb
Host smart-f5d94763-3667-483e-bdb7-86b0aa07dbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944469071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3944469071
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1549423023
Short name T618
Test name
Test status
Simulation time 1058178131 ps
CPU time 12.04 seconds
Started Aug 14 05:27:20 PM PDT 24
Finished Aug 14 05:27:32 PM PDT 24
Peak memory 232952 kb
Host smart-62c758ca-bc0a-4313-bedc-5ad89b57738d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549423023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1549423023
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1089824479
Short name T852
Test name
Test status
Simulation time 6921860471 ps
CPU time 6.16 seconds
Started Aug 14 05:27:16 PM PDT 24
Finished Aug 14 05:27:22 PM PDT 24
Peak memory 224708 kb
Host smart-c8b944e3-cb56-440a-a7de-65d07447a0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089824479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1089824479
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3408626466
Short name T81
Test name
Test status
Simulation time 1986652194 ps
CPU time 14.13 seconds
Started Aug 14 05:27:16 PM PDT 24
Finished Aug 14 05:27:31 PM PDT 24
Peak memory 240884 kb
Host smart-ac2b5e9b-31d9-4bae-856c-c3f55a449eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408626466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3408626466
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1849921924
Short name T1012
Test name
Test status
Simulation time 241634309 ps
CPU time 3.91 seconds
Started Aug 14 05:27:25 PM PDT 24
Finished Aug 14 05:27:29 PM PDT 24
Peak memory 220784 kb
Host smart-1041e80a-69be-4a6c-ac3e-a42a3b35f0b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1849921924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1849921924
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1090375835
Short name T682
Test name
Test status
Simulation time 28338457583 ps
CPU time 59.65 seconds
Started Aug 14 05:27:23 PM PDT 24
Finished Aug 14 05:28:23 PM PDT 24
Peak memory 250380 kb
Host smart-f561f76a-1b1e-4b21-8e79-b97588659676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090375835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1090375835
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4130786223
Short name T104
Test name
Test status
Simulation time 2988324913 ps
CPU time 20.08 seconds
Started Aug 14 05:27:19 PM PDT 24
Finished Aug 14 05:27:39 PM PDT 24
Peak memory 216532 kb
Host smart-a1eb37a9-46d2-4836-93bc-b8cb8146e1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130786223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4130786223
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.569816444
Short name T551
Test name
Test status
Simulation time 10989828328 ps
CPU time 8.4 seconds
Started Aug 14 05:27:15 PM PDT 24
Finished Aug 14 05:27:24 PM PDT 24
Peak memory 216608 kb
Host smart-9ffb2cf2-2d3e-43d1-84cb-83ac0133a521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569816444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.569816444
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.879669708
Short name T884
Test name
Test status
Simulation time 31974332 ps
CPU time 0.93 seconds
Started Aug 14 05:27:20 PM PDT 24
Finished Aug 14 05:27:21 PM PDT 24
Peak memory 207088 kb
Host smart-fb5c470e-a439-4c69-a0dc-e01dc66ceca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879669708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.879669708
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3611486125
Short name T805
Test name
Test status
Simulation time 50861284 ps
CPU time 0.77 seconds
Started Aug 14 05:27:14 PM PDT 24
Finished Aug 14 05:27:15 PM PDT 24
Peak memory 206148 kb
Host smart-2b857a56-4963-4a29-93be-4675fb19351e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611486125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3611486125
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4260524373
Short name T656
Test name
Test status
Simulation time 687538302 ps
CPU time 2.69 seconds
Started Aug 14 05:27:19 PM PDT 24
Finished Aug 14 05:27:22 PM PDT 24
Peak memory 232488 kb
Host smart-86fb36a7-1904-407e-8693-2f6ddd3359a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260524373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4260524373
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1162325878
Short name T386
Test name
Test status
Simulation time 11332874 ps
CPU time 0.69 seconds
Started Aug 14 05:27:25 PM PDT 24
Finished Aug 14 05:27:26 PM PDT 24
Peak memory 205612 kb
Host smart-dbd674a6-6037-4b83-9137-3e2c6c6b031a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162325878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1162325878
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3140759244
Short name T485
Test name
Test status
Simulation time 57740947 ps
CPU time 1.88 seconds
Started Aug 14 05:27:26 PM PDT 24
Finished Aug 14 05:27:28 PM PDT 24
Peak memory 223800 kb
Host smart-82054637-045a-4718-9970-7e51536eb617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140759244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3140759244
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2906903089
Short name T937
Test name
Test status
Simulation time 28617258 ps
CPU time 0.72 seconds
Started Aug 14 05:27:24 PM PDT 24
Finished Aug 14 05:27:25 PM PDT 24
Peak memory 205608 kb
Host smart-a92f36ca-5414-4a97-bb49-e8824cd7a51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906903089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2906903089
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1253033070
Short name T506
Test name
Test status
Simulation time 12430977914 ps
CPU time 97.84 seconds
Started Aug 14 05:27:26 PM PDT 24
Finished Aug 14 05:29:04 PM PDT 24
Peak memory 251160 kb
Host smart-d88a5a7e-51d2-4a30-897b-253574323473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253033070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1253033070
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1687865090
Short name T949
Test name
Test status
Simulation time 6461319598 ps
CPU time 30.35 seconds
Started Aug 14 05:27:26 PM PDT 24
Finished Aug 14 05:27:57 PM PDT 24
Peak memory 224872 kb
Host smart-52269fc2-953e-4c2e-b9b4-d12daa1790a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687865090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1687865090
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.32073257
Short name T910
Test name
Test status
Simulation time 203915403887 ps
CPU time 171.88 seconds
Started Aug 14 05:27:26 PM PDT 24
Finished Aug 14 05:30:18 PM PDT 24
Peak memory 253820 kb
Host smart-c40474a4-f481-403d-bea2-53f22d0430f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32073257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.32073257
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.838711532
Short name T480
Test name
Test status
Simulation time 38616924 ps
CPU time 2.71 seconds
Started Aug 14 05:27:27 PM PDT 24
Finished Aug 14 05:27:29 PM PDT 24
Peak memory 232928 kb
Host smart-10d2104e-0b01-4fa3-906f-209f3058fc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838711532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.838711532
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3373970615
Short name T862
Test name
Test status
Simulation time 5940192201 ps
CPU time 80.5 seconds
Started Aug 14 05:27:25 PM PDT 24
Finished Aug 14 05:28:45 PM PDT 24
Peak memory 266700 kb
Host smart-8581601d-5ac3-44eb-924a-f025727456ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373970615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3373970615
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.245245124
Short name T701
Test name
Test status
Simulation time 416071756 ps
CPU time 5.34 seconds
Started Aug 14 05:27:24 PM PDT 24
Finished Aug 14 05:27:29 PM PDT 24
Peak memory 224724 kb
Host smart-f3fdc6a2-2a59-4be6-b182-2658559ec025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245245124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.245245124
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.903465265
Short name T811
Test name
Test status
Simulation time 7784503527 ps
CPU time 74.51 seconds
Started Aug 14 05:27:27 PM PDT 24
Finished Aug 14 05:28:41 PM PDT 24
Peak memory 240608 kb
Host smart-2c0c3362-01a6-4789-946f-7f53e8257ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903465265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.903465265
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.176294593
Short name T970
Test name
Test status
Simulation time 5901430222 ps
CPU time 6.9 seconds
Started Aug 14 05:27:26 PM PDT 24
Finished Aug 14 05:27:33 PM PDT 24
Peak memory 224736 kb
Host smart-6d7c9dcf-44be-4126-84fc-6c66619b3e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176294593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.176294593
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.385240227
Short name T930
Test name
Test status
Simulation time 250883436 ps
CPU time 2.48 seconds
Started Aug 14 05:27:24 PM PDT 24
Finished Aug 14 05:27:26 PM PDT 24
Peak memory 224796 kb
Host smart-fa97772d-7318-4ac9-a9de-8cea15896a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385240227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.385240227
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1944169874
Short name T40
Test name
Test status
Simulation time 580283897 ps
CPU time 4.58 seconds
Started Aug 14 05:27:27 PM PDT 24
Finished Aug 14 05:27:32 PM PDT 24
Peak memory 219304 kb
Host smart-07540522-7511-48dc-b2d6-3ab099f50a95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1944169874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1944169874
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1902926489
Short name T509
Test name
Test status
Simulation time 560918097 ps
CPU time 9.86 seconds
Started Aug 14 05:27:24 PM PDT 24
Finished Aug 14 05:27:34 PM PDT 24
Peak memory 224768 kb
Host smart-87df3144-7367-4044-bc91-d9cdb9c8afc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902926489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1902926489
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1262395319
Short name T378
Test name
Test status
Simulation time 10869234829 ps
CPU time 19.9 seconds
Started Aug 14 05:27:23 PM PDT 24
Finished Aug 14 05:27:43 PM PDT 24
Peak memory 216640 kb
Host smart-4c1491aa-5096-452a-bb99-708cc2e9bbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262395319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1262395319
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.4280535965
Short name T341
Test name
Test status
Simulation time 1732422910 ps
CPU time 9.31 seconds
Started Aug 14 05:27:23 PM PDT 24
Finished Aug 14 05:27:33 PM PDT 24
Peak memory 216472 kb
Host smart-b23c685d-ba1a-4b8d-8102-303c7f8ecb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280535965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4280535965
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3656800994
Short name T843
Test name
Test status
Simulation time 128307248 ps
CPU time 5.99 seconds
Started Aug 14 05:27:25 PM PDT 24
Finished Aug 14 05:27:31 PM PDT 24
Peak memory 216492 kb
Host smart-d02376a3-d686-4c0d-a5c7-8b3f81f4e284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656800994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3656800994
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.356219032
Short name T786
Test name
Test status
Simulation time 13494271 ps
CPU time 0.76 seconds
Started Aug 14 05:27:28 PM PDT 24
Finished Aug 14 05:27:29 PM PDT 24
Peak memory 206144 kb
Host smart-5079f4dd-71f6-4db4-adfd-90e405aea0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356219032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.356219032
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3920639339
Short name T841
Test name
Test status
Simulation time 7551154512 ps
CPU time 23.26 seconds
Started Aug 14 05:27:29 PM PDT 24
Finished Aug 14 05:27:52 PM PDT 24
Peak memory 232988 kb
Host smart-34e31605-15ef-4c94-b43c-be1a6c0ce8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920639339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3920639339
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3381301086
Short name T5
Test name
Test status
Simulation time 35960568 ps
CPU time 0.7 seconds
Started Aug 14 05:27:23 PM PDT 24
Finished Aug 14 05:27:24 PM PDT 24
Peak memory 205584 kb
Host smart-3e5e376a-8f3e-4792-989c-129d01f1cb43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381301086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3381301086
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1694450727
Short name T393
Test name
Test status
Simulation time 56566231 ps
CPU time 2.61 seconds
Started Aug 14 05:27:25 PM PDT 24
Finished Aug 14 05:27:28 PM PDT 24
Peak memory 232852 kb
Host smart-d41e3e11-e067-4c0c-9113-0fe6fd3fb01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694450727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1694450727
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2128609588
Short name T969
Test name
Test status
Simulation time 16451911 ps
CPU time 0.75 seconds
Started Aug 14 05:27:26 PM PDT 24
Finished Aug 14 05:27:27 PM PDT 24
Peak memory 206932 kb
Host smart-f88aadac-51cc-44e8-974e-91e0142af508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128609588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2128609588
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2071567995
Short name T94
Test name
Test status
Simulation time 327601017 ps
CPU time 6.57 seconds
Started Aug 14 05:27:25 PM PDT 24
Finished Aug 14 05:27:32 PM PDT 24
Peak memory 224724 kb
Host smart-af4acacd-11d2-4fb2-9c67-1986c1c9827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071567995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2071567995
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1640986398
Short name T235
Test name
Test status
Simulation time 35645388621 ps
CPU time 62.36 seconds
Started Aug 14 05:27:29 PM PDT 24
Finished Aug 14 05:28:31 PM PDT 24
Peak memory 241228 kb
Host smart-dbad1bbd-06fc-4697-9b63-e8b0d483d547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640986398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1640986398
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3451773786
Short name T883
Test name
Test status
Simulation time 670429094 ps
CPU time 9.06 seconds
Started Aug 14 05:27:26 PM PDT 24
Finished Aug 14 05:27:36 PM PDT 24
Peak memory 241056 kb
Host smart-92ccbcad-71e0-4b12-b256-442740b6a422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451773786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3451773786
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2014231351
Short name T665
Test name
Test status
Simulation time 470560177 ps
CPU time 6.96 seconds
Started Aug 14 05:27:23 PM PDT 24
Finished Aug 14 05:27:30 PM PDT 24
Peak memory 232872 kb
Host smart-c154785c-3c0d-4e71-98ea-c62e0532b597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014231351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2014231351
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1083047603
Short name T522
Test name
Test status
Simulation time 15981394658 ps
CPU time 124.73 seconds
Started Aug 14 05:27:26 PM PDT 24
Finished Aug 14 05:29:31 PM PDT 24
Peak memory 240292 kb
Host smart-2522e3e1-54c8-4677-906d-978e0fdeafc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083047603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1083047603
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.908095839
Short name T839
Test name
Test status
Simulation time 396386210 ps
CPU time 2.31 seconds
Started Aug 14 05:27:24 PM PDT 24
Finished Aug 14 05:27:27 PM PDT 24
Peak memory 222824 kb
Host smart-7780fb89-3fcc-422c-b0eb-dd8a2a683098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908095839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.908095839
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1511024248
Short name T383
Test name
Test status
Simulation time 2164616720 ps
CPU time 6.86 seconds
Started Aug 14 05:27:27 PM PDT 24
Finished Aug 14 05:27:34 PM PDT 24
Peak memory 240912 kb
Host smart-b6964bdf-733a-4bef-aae0-4e713c8269b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511024248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1511024248
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3031642134
Short name T41
Test name
Test status
Simulation time 1135733471 ps
CPU time 7.38 seconds
Started Aug 14 05:27:25 PM PDT 24
Finished Aug 14 05:27:33 PM PDT 24
Peak memory 220324 kb
Host smart-1fb52b56-caf2-4854-8be3-89daff3e42ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3031642134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3031642134
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1511636728
Short name T21
Test name
Test status
Simulation time 43075825 ps
CPU time 0.89 seconds
Started Aug 14 05:27:23 PM PDT 24
Finished Aug 14 05:27:24 PM PDT 24
Peak memory 205744 kb
Host smart-daff80fb-f885-4d30-b93c-6cf19148e558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511636728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1511636728
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1190513226
Short name T382
Test name
Test status
Simulation time 27747390436 ps
CPU time 23.13 seconds
Started Aug 14 05:27:23 PM PDT 24
Finished Aug 14 05:27:46 PM PDT 24
Peak memory 216536 kb
Host smart-cf572dce-645b-4b75-b7ba-1a4cceb57659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190513226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1190513226
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2508133649
Short name T577
Test name
Test status
Simulation time 14140689349 ps
CPU time 9.85 seconds
Started Aug 14 05:27:27 PM PDT 24
Finished Aug 14 05:27:38 PM PDT 24
Peak memory 216572 kb
Host smart-19366587-5779-4eda-ae2a-ee3509ccd072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508133649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2508133649
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2592704886
Short name T1000
Test name
Test status
Simulation time 488501076 ps
CPU time 1.12 seconds
Started Aug 14 05:27:28 PM PDT 24
Finished Aug 14 05:27:29 PM PDT 24
Peak memory 208076 kb
Host smart-f75825dd-e3c3-48f6-bfb8-11b157469c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592704886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2592704886
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3972695659
Short name T957
Test name
Test status
Simulation time 17021268 ps
CPU time 0.76 seconds
Started Aug 14 05:27:28 PM PDT 24
Finished Aug 14 05:27:29 PM PDT 24
Peak memory 206088 kb
Host smart-770853e0-431b-47cc-9939-647564354362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972695659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3972695659
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1011245211
Short name T777
Test name
Test status
Simulation time 106835185 ps
CPU time 2.42 seconds
Started Aug 14 05:27:24 PM PDT 24
Finished Aug 14 05:27:27 PM PDT 24
Peak memory 224648 kb
Host smart-12cb115a-1ff2-426b-abf6-8e43d7ad3bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011245211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1011245211
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4213662816
Short name T469
Test name
Test status
Simulation time 10493826 ps
CPU time 0.68 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:35 PM PDT 24
Peak memory 205016 kb
Host smart-ecb72f99-0641-430e-a714-5f2588ba57d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213662816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4213662816
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2494419270
Short name T528
Test name
Test status
Simulation time 1091400791 ps
CPU time 9.27 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:43 PM PDT 24
Peak memory 232904 kb
Host smart-a7a722af-3cab-4b1a-ba18-d4661f3c23a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494419270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2494419270
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.625046229
Short name T358
Test name
Test status
Simulation time 31989443 ps
CPU time 0.77 seconds
Started Aug 14 05:27:33 PM PDT 24
Finished Aug 14 05:27:34 PM PDT 24
Peak memory 206972 kb
Host smart-fbee7765-7e83-4cf4-a9c6-1754100af038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625046229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.625046229
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3994027034
Short name T828
Test name
Test status
Simulation time 28709370853 ps
CPU time 60.32 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:28:35 PM PDT 24
Peak memory 241124 kb
Host smart-baa3b3bb-2bc9-4bfd-accd-24cdf1351124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994027034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3994027034
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1735241976
Short name T760
Test name
Test status
Simulation time 80971335212 ps
CPU time 213.45 seconds
Started Aug 14 05:27:35 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 256184 kb
Host smart-a8f0c1c0-f98f-4372-8f5c-d319f1301ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735241976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1735241976
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3965601418
Short name T851
Test name
Test status
Simulation time 124174481295 ps
CPU time 141.43 seconds
Started Aug 14 05:27:35 PM PDT 24
Finished Aug 14 05:29:56 PM PDT 24
Peak memory 255132 kb
Host smart-3620bceb-d919-4fea-890b-ae668567f0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965601418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3965601418
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1772453048
Short name T874
Test name
Test status
Simulation time 4754534093 ps
CPU time 9.81 seconds
Started Aug 14 05:27:35 PM PDT 24
Finished Aug 14 05:27:45 PM PDT 24
Peak memory 224784 kb
Host smart-4010793a-6021-4660-94b8-e6c259dc8a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772453048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1772453048
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2815562382
Short name T879
Test name
Test status
Simulation time 48580856741 ps
CPU time 183.91 seconds
Started Aug 14 05:27:32 PM PDT 24
Finished Aug 14 05:30:36 PM PDT 24
Peak memory 249400 kb
Host smart-fe7b2b87-c354-43b1-9967-930c2e40a5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815562382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2815562382
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2065168620
Short name T669
Test name
Test status
Simulation time 36116607 ps
CPU time 2.45 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:37 PM PDT 24
Peak memory 232536 kb
Host smart-7e3f0e05-df3a-47f1-90fe-b722c86df319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065168620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2065168620
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2065859385
Short name T733
Test name
Test status
Simulation time 2386659073 ps
CPU time 11.38 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:45 PM PDT 24
Peak memory 221576 kb
Host smart-78994bf2-a552-4a62-854a-ee1ce7ee08ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065859385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2065859385
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.519158130
Short name T106
Test name
Test status
Simulation time 662816279 ps
CPU time 4.12 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:39 PM PDT 24
Peak memory 224684 kb
Host smart-56e6d50f-58ea-4b07-a022-ebca329c1948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519158130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.519158130
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.508311192
Short name T63
Test name
Test status
Simulation time 5551277576 ps
CPU time 19.51 seconds
Started Aug 14 05:27:32 PM PDT 24
Finished Aug 14 05:27:52 PM PDT 24
Peak memory 256856 kb
Host smart-76fbd7d0-5e6d-4e71-ae89-2d77d3ba2784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508311192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.508311192
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2466321781
Short name T643
Test name
Test status
Simulation time 455587380 ps
CPU time 4.61 seconds
Started Aug 14 05:27:38 PM PDT 24
Finished Aug 14 05:27:43 PM PDT 24
Peak memory 222676 kb
Host smart-d6434271-11e8-4d07-b0fd-3d55912637e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2466321781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2466321781
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3568688879
Short name T598
Test name
Test status
Simulation time 551996807 ps
CPU time 6.31 seconds
Started Aug 14 05:27:32 PM PDT 24
Finished Aug 14 05:27:39 PM PDT 24
Peak memory 216672 kb
Host smart-33957999-db19-47e6-9125-268aefa10266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568688879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3568688879
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2636376598
Short name T904
Test name
Test status
Simulation time 1308136769 ps
CPU time 5.32 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:40 PM PDT 24
Peak memory 216520 kb
Host smart-c4278c79-e134-40de-8c13-1228b321eb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636376598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2636376598
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2931912196
Short name T391
Test name
Test status
Simulation time 44712666 ps
CPU time 1.4 seconds
Started Aug 14 05:27:38 PM PDT 24
Finished Aug 14 05:27:39 PM PDT 24
Peak memory 208320 kb
Host smart-0dc2796a-226a-420a-ba80-5588d966746d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931912196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2931912196
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2396354266
Short name T538
Test name
Test status
Simulation time 48173828 ps
CPU time 0.8 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:35 PM PDT 24
Peak memory 206312 kb
Host smart-b38dc4cb-4eac-4728-bf07-3ef0e62b6cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396354266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2396354266
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.289902443
Short name T684
Test name
Test status
Simulation time 25624667313 ps
CPU time 23.04 seconds
Started Aug 14 05:27:33 PM PDT 24
Finished Aug 14 05:27:57 PM PDT 24
Peak memory 241196 kb
Host smart-34fce8d8-e98e-4072-8695-714880dba576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289902443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.289902443
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.897506814
Short name T869
Test name
Test status
Simulation time 45004095 ps
CPU time 0.7 seconds
Started Aug 14 05:27:53 PM PDT 24
Finished Aug 14 05:27:54 PM PDT 24
Peak memory 204980 kb
Host smart-dfd30dee-ff8f-49e6-94ed-04dad993a36e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897506814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.897506814
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2399123949
Short name T886
Test name
Test status
Simulation time 124991777 ps
CPU time 2.17 seconds
Started Aug 14 05:27:33 PM PDT 24
Finished Aug 14 05:27:35 PM PDT 24
Peak memory 224724 kb
Host smart-51a4b734-6bb1-4066-9f7e-508e2e77b310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399123949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2399123949
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2524452269
Short name T806
Test name
Test status
Simulation time 14170860 ps
CPU time 0.78 seconds
Started Aug 14 05:27:33 PM PDT 24
Finished Aug 14 05:27:34 PM PDT 24
Peak memory 206888 kb
Host smart-df3273c8-842a-4666-9dde-1ac1e683049e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524452269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2524452269
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1324372756
Short name T289
Test name
Test status
Simulation time 202552192014 ps
CPU time 322.4 seconds
Started Aug 14 05:27:51 PM PDT 24
Finished Aug 14 05:33:14 PM PDT 24
Peak memory 267436 kb
Host smart-ff8edee6-b0d9-4148-8e5a-ab28d2c1332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324372756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1324372756
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3957797916
Short name T718
Test name
Test status
Simulation time 20341148684 ps
CPU time 83.31 seconds
Started Aug 14 05:27:45 PM PDT 24
Finished Aug 14 05:29:08 PM PDT 24
Peak memory 249420 kb
Host smart-9fb6bfa9-2a41-4588-a6ad-3a757ad9db58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957797916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3957797916
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.678879047
Short name T285
Test name
Test status
Simulation time 125782142687 ps
CPU time 323.09 seconds
Started Aug 14 05:27:45 PM PDT 24
Finished Aug 14 05:33:08 PM PDT 24
Peak memory 256672 kb
Host smart-8200b5f3-0798-43d5-bc9d-76dd4f1edf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678879047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.678879047
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2247249126
Short name T80
Test name
Test status
Simulation time 1696227736 ps
CPU time 17.4 seconds
Started Aug 14 05:27:35 PM PDT 24
Finished Aug 14 05:27:53 PM PDT 24
Peak memory 232928 kb
Host smart-bfa38025-0498-4f83-8764-71ec54d9a51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247249126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2247249126
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3904878568
Short name T440
Test name
Test status
Simulation time 809779958 ps
CPU time 6.15 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:40 PM PDT 24
Peak memory 239436 kb
Host smart-febc89d0-494a-4e71-aba9-a772a0a667b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904878568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3904878568
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3419384380
Short name T431
Test name
Test status
Simulation time 2634265880 ps
CPU time 12.94 seconds
Started Aug 14 05:27:38 PM PDT 24
Finished Aug 14 05:27:51 PM PDT 24
Peak memory 232932 kb
Host smart-2b5815cd-1ef2-478e-944c-557c0be219df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419384380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3419384380
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3972928104
Short name T403
Test name
Test status
Simulation time 3843446655 ps
CPU time 5.28 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:40 PM PDT 24
Peak memory 232968 kb
Host smart-d290ca1f-753e-46f7-9273-cc8538d07bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972928104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3972928104
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.955698045
Short name T76
Test name
Test status
Simulation time 1945768725 ps
CPU time 7.8 seconds
Started Aug 14 05:27:39 PM PDT 24
Finished Aug 14 05:27:47 PM PDT 24
Peak memory 223300 kb
Host smart-e3284adf-2f82-4c1f-811c-509b633bd23b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=955698045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.955698045
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3235480446
Short name T446
Test name
Test status
Simulation time 82531701 ps
CPU time 1.23 seconds
Started Aug 14 05:27:42 PM PDT 24
Finished Aug 14 05:27:44 PM PDT 24
Peak memory 206840 kb
Host smart-7faae9fd-2ab4-42b5-ad7d-a7f19dd04dd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235480446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3235480446
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.524924146
Short name T709
Test name
Test status
Simulation time 12496138 ps
CPU time 0.72 seconds
Started Aug 14 05:27:33 PM PDT 24
Finished Aug 14 05:27:34 PM PDT 24
Peak memory 205724 kb
Host smart-8dcb5df2-b4a6-4bc0-bd01-4ae4910767c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524924146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.524924146
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.140952366
Short name T595
Test name
Test status
Simulation time 9922043448 ps
CPU time 8.04 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:42 PM PDT 24
Peak memory 216620 kb
Host smart-e397a3ad-b739-4b70-a343-2b0bdff42659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140952366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.140952366
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4078225468
Short name T790
Test name
Test status
Simulation time 38096838 ps
CPU time 2.52 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:36 PM PDT 24
Peak memory 208260 kb
Host smart-db238989-b6d7-4895-9178-02439b2242e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078225468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4078225468
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2215376077
Short name T578
Test name
Test status
Simulation time 137543274 ps
CPU time 0.96 seconds
Started Aug 14 05:27:34 PM PDT 24
Finished Aug 14 05:27:36 PM PDT 24
Peak memory 206480 kb
Host smart-ef65f790-5662-4d4f-bf47-ec0c01659a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215376077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2215376077
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1510513583
Short name T726
Test name
Test status
Simulation time 2944695977 ps
CPU time 8.14 seconds
Started Aug 14 05:27:33 PM PDT 24
Finished Aug 14 05:27:41 PM PDT 24
Peak memory 232928 kb
Host smart-fa89db1b-d8e6-453f-8cb2-e5cdb8a35e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510513583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1510513583
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3983220637
Short name T493
Test name
Test status
Simulation time 40729133 ps
CPU time 0.7 seconds
Started Aug 14 05:27:47 PM PDT 24
Finished Aug 14 05:27:48 PM PDT 24
Peak memory 205452 kb
Host smart-3dd08f4e-41cd-422b-b589-342535823e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983220637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3983220637
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.64309868
Short name T557
Test name
Test status
Simulation time 181653835 ps
CPU time 3.89 seconds
Started Aug 14 05:27:48 PM PDT 24
Finished Aug 14 05:27:52 PM PDT 24
Peak memory 224648 kb
Host smart-2a4035fa-3673-47e0-a838-b4384e0c3e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64309868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.64309868
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2330862525
Short name T920
Test name
Test status
Simulation time 40502789 ps
CPU time 0.79 seconds
Started Aug 14 05:27:46 PM PDT 24
Finished Aug 14 05:27:47 PM PDT 24
Peak memory 205608 kb
Host smart-2867d362-2b75-4212-9095-3e7925d11d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330862525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2330862525
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.716513106
Short name T434
Test name
Test status
Simulation time 62233305 ps
CPU time 0.98 seconds
Started Aug 14 05:27:45 PM PDT 24
Finished Aug 14 05:27:46 PM PDT 24
Peak memory 216080 kb
Host smart-d490dad6-215b-475d-b727-879f4afae73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716513106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.716513106
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.143174561
Short name T856
Test name
Test status
Simulation time 96757436028 ps
CPU time 104.55 seconds
Started Aug 14 05:27:43 PM PDT 24
Finished Aug 14 05:29:28 PM PDT 24
Peak memory 266776 kb
Host smart-504e4863-12fb-4822-96a2-77227462722e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143174561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.143174561
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1127625862
Short name T287
Test name
Test status
Simulation time 7776767775 ps
CPU time 59.31 seconds
Started Aug 14 05:27:45 PM PDT 24
Finished Aug 14 05:28:45 PM PDT 24
Peak memory 260672 kb
Host smart-0f93db18-8b68-47a9-b8d0-a553e88beb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127625862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1127625862
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2063446850
Short name T660
Test name
Test status
Simulation time 433522623 ps
CPU time 9.99 seconds
Started Aug 14 05:27:51 PM PDT 24
Finished Aug 14 05:28:01 PM PDT 24
Peak memory 232928 kb
Host smart-d604cdd8-661e-4f58-883f-e0f007f73b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063446850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2063446850
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2995645586
Short name T844
Test name
Test status
Simulation time 71690276308 ps
CPU time 67.99 seconds
Started Aug 14 05:27:48 PM PDT 24
Finished Aug 14 05:28:56 PM PDT 24
Peak memory 241176 kb
Host smart-44ae5b91-b6a4-451a-ba2a-8d3fc2ac0939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995645586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2995645586
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2080924770
Short name T91
Test name
Test status
Simulation time 317866573 ps
CPU time 2.94 seconds
Started Aug 14 05:27:46 PM PDT 24
Finished Aug 14 05:27:49 PM PDT 24
Peak memory 232856 kb
Host smart-9b15240d-c492-4fa1-9060-e8667a81a7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080924770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2080924770
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3482809386
Short name T927
Test name
Test status
Simulation time 3614052339 ps
CPU time 9.53 seconds
Started Aug 14 05:27:45 PM PDT 24
Finished Aug 14 05:27:55 PM PDT 24
Peak memory 241096 kb
Host smart-89a3f355-435b-4883-baeb-3454c1ec57cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482809386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3482809386
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.233853576
Short name T254
Test name
Test status
Simulation time 23141123412 ps
CPU time 31.49 seconds
Started Aug 14 05:27:52 PM PDT 24
Finished Aug 14 05:28:23 PM PDT 24
Peak memory 253256 kb
Host smart-c51718b6-3eb2-460c-ae9e-d25fff564108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233853576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.233853576
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1590006596
Short name T776
Test name
Test status
Simulation time 138658256 ps
CPU time 2.71 seconds
Started Aug 14 05:27:43 PM PDT 24
Finished Aug 14 05:27:46 PM PDT 24
Peak memory 224664 kb
Host smart-e0e5d0d0-f863-4702-a767-03555104070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590006596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1590006596
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.658376755
Short name T39
Test name
Test status
Simulation time 3795362554 ps
CPU time 17.46 seconds
Started Aug 14 05:27:44 PM PDT 24
Finished Aug 14 05:28:01 PM PDT 24
Peak memory 219644 kb
Host smart-51ccab4c-b7bf-4bb7-959c-a5d5e97891fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=658376755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.658376755
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.129809026
Short name T707
Test name
Test status
Simulation time 92881628 ps
CPU time 0.96 seconds
Started Aug 14 05:27:45 PM PDT 24
Finished Aug 14 05:27:46 PM PDT 24
Peak memory 207524 kb
Host smart-609b64df-0679-4db2-a9df-72e93e3bdc00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129809026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.129809026
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1875687798
Short name T842
Test name
Test status
Simulation time 3027235490 ps
CPU time 4.57 seconds
Started Aug 14 05:27:44 PM PDT 24
Finished Aug 14 05:27:49 PM PDT 24
Peak memory 216536 kb
Host smart-2757d174-4a48-4c00-9c5b-ab71ae085989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875687798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1875687798
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.4185195922
Short name T323
Test name
Test status
Simulation time 233572882 ps
CPU time 1.95 seconds
Started Aug 14 05:27:47 PM PDT 24
Finished Aug 14 05:27:49 PM PDT 24
Peak memory 207832 kb
Host smart-950497e6-7d1d-4275-af73-376014bd82e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185195922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4185195922
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2293133373
Short name T314
Test name
Test status
Simulation time 304191649 ps
CPU time 1.1 seconds
Started Aug 14 05:27:52 PM PDT 24
Finished Aug 14 05:27:53 PM PDT 24
Peak memory 207352 kb
Host smart-9ed43adb-f605-4738-a686-9eceb7c3e56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293133373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2293133373
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2971328693
Short name T706
Test name
Test status
Simulation time 22250942 ps
CPU time 0.69 seconds
Started Aug 14 05:27:44 PM PDT 24
Finished Aug 14 05:27:45 PM PDT 24
Peak memory 205632 kb
Host smart-40da9519-4b87-44e1-add6-127c0bfb5cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971328693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2971328693
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3325370040
Short name T824
Test name
Test status
Simulation time 5865312485 ps
CPU time 5.97 seconds
Started Aug 14 05:27:47 PM PDT 24
Finished Aug 14 05:27:53 PM PDT 24
Peak memory 224768 kb
Host smart-25cc43b1-fa81-40ea-9e29-2d86ef3bebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325370040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3325370040
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2712550399
Short name T374
Test name
Test status
Simulation time 24468299 ps
CPU time 0.77 seconds
Started Aug 14 05:27:54 PM PDT 24
Finished Aug 14 05:27:55 PM PDT 24
Peak memory 205556 kb
Host smart-78605e95-ad15-4e99-a791-3e20eb4af2e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712550399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2712550399
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4198715247
Short name T559
Test name
Test status
Simulation time 242546507 ps
CPU time 5.61 seconds
Started Aug 14 05:27:44 PM PDT 24
Finished Aug 14 05:27:50 PM PDT 24
Peak memory 232932 kb
Host smart-b20e20e1-f5e4-4907-9fd7-2129bdc11097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198715247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4198715247
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2723274073
Short name T819
Test name
Test status
Simulation time 74971763 ps
CPU time 0.83 seconds
Started Aug 14 05:27:43 PM PDT 24
Finished Aug 14 05:27:44 PM PDT 24
Peak memory 206964 kb
Host smart-39334266-a613-4b17-a1a9-e04f92151dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723274073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2723274073
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3796902293
Short name T201
Test name
Test status
Simulation time 5688565562 ps
CPU time 57.49 seconds
Started Aug 14 05:27:44 PM PDT 24
Finished Aug 14 05:28:41 PM PDT 24
Peak memory 250900 kb
Host smart-0f0ff6c9-4091-4473-bd29-8a6329938d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796902293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3796902293
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1042229124
Short name T45
Test name
Test status
Simulation time 6864531118 ps
CPU time 30.69 seconds
Started Aug 14 05:27:50 PM PDT 24
Finished Aug 14 05:28:21 PM PDT 24
Peak memory 236452 kb
Host smart-6022f120-da42-4dfc-b1cc-7247670e7375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042229124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1042229124
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1834576933
Short name T1006
Test name
Test status
Simulation time 424911964383 ps
CPU time 446.29 seconds
Started Aug 14 05:27:44 PM PDT 24
Finished Aug 14 05:35:11 PM PDT 24
Peak memory 264892 kb
Host smart-d743f003-beb7-4cdc-8612-47d427b4630a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834576933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1834576933
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2053449771
Short name T604
Test name
Test status
Simulation time 142477613 ps
CPU time 4.27 seconds
Started Aug 14 05:27:44 PM PDT 24
Finished Aug 14 05:27:49 PM PDT 24
Peak memory 232944 kb
Host smart-3e259516-4071-467c-ad33-70d992a76c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053449771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2053449771
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4248807155
Short name T571
Test name
Test status
Simulation time 761616418 ps
CPU time 5.16 seconds
Started Aug 14 05:27:44 PM PDT 24
Finished Aug 14 05:27:49 PM PDT 24
Peak memory 224696 kb
Host smart-3b6af012-dbe3-4c27-b5e6-11e2fca143e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248807155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4248807155
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2425031061
Short name T59
Test name
Test status
Simulation time 43807791419 ps
CPU time 11.86 seconds
Started Aug 14 05:27:50 PM PDT 24
Finished Aug 14 05:28:03 PM PDT 24
Peak memory 224744 kb
Host smart-0bd2939b-c0f4-41a7-b263-1a9e88b196c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425031061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2425031061
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1024702223
Short name T468
Test name
Test status
Simulation time 11710545266 ps
CPU time 16.57 seconds
Started Aug 14 05:27:44 PM PDT 24
Finished Aug 14 05:28:00 PM PDT 24
Peak memory 232940 kb
Host smart-f6edbc5b-8716-4160-8e42-54a786b45a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024702223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1024702223
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3098534851
Short name T747
Test name
Test status
Simulation time 1275022673 ps
CPU time 16.18 seconds
Started Aug 14 05:27:44 PM PDT 24
Finished Aug 14 05:28:01 PM PDT 24
Peak memory 222124 kb
Host smart-2078b1ca-2163-4b73-bd9a-5d2011d6bdf5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3098534851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3098534851
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.137241752
Short name T244
Test name
Test status
Simulation time 140054231589 ps
CPU time 436.51 seconds
Started Aug 14 05:27:50 PM PDT 24
Finished Aug 14 05:35:07 PM PDT 24
Peak memory 290340 kb
Host smart-ddd3eb38-e262-40be-8fba-1e417b88a2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137241752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.137241752
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.145321314
Short name T960
Test name
Test status
Simulation time 5771336119 ps
CPU time 26.18 seconds
Started Aug 14 05:27:44 PM PDT 24
Finished Aug 14 05:28:11 PM PDT 24
Peak memory 216608 kb
Host smart-78d95af6-1213-4afe-a6f9-ed9a9b4a62a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145321314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.145321314
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1854230531
Short name T838
Test name
Test status
Simulation time 3822439645 ps
CPU time 5.44 seconds
Started Aug 14 05:27:42 PM PDT 24
Finished Aug 14 05:27:48 PM PDT 24
Peak memory 216532 kb
Host smart-1aacce61-247c-4251-8666-0f981180b014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854230531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1854230531
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.4091955430
Short name T774
Test name
Test status
Simulation time 288661317 ps
CPU time 2.74 seconds
Started Aug 14 05:27:47 PM PDT 24
Finished Aug 14 05:27:50 PM PDT 24
Peak memory 216212 kb
Host smart-e39fd983-8226-481b-8485-020662775cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091955430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4091955430
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4249542840
Short name T678
Test name
Test status
Simulation time 63345080 ps
CPU time 0.77 seconds
Started Aug 14 05:27:47 PM PDT 24
Finished Aug 14 05:27:48 PM PDT 24
Peak memory 206164 kb
Host smart-0d0c7b25-2674-4e45-a9ff-20a0d219d0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249542840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4249542840
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1698576313
Short name T683
Test name
Test status
Simulation time 389686159 ps
CPU time 2.88 seconds
Started Aug 14 05:27:48 PM PDT 24
Finished Aug 14 05:27:51 PM PDT 24
Peak memory 224740 kb
Host smart-799aceb1-da70-4015-b6c2-c481badad4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698576313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1698576313
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1607506614
Short name T801
Test name
Test status
Simulation time 14891950 ps
CPU time 0.72 seconds
Started Aug 14 05:28:01 PM PDT 24
Finished Aug 14 05:28:02 PM PDT 24
Peak memory 205892 kb
Host smart-f4917ba8-6088-4f94-be59-f5438f736923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607506614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1607506614
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.192710023
Short name T653
Test name
Test status
Simulation time 289743163 ps
CPU time 3.13 seconds
Started Aug 14 05:27:58 PM PDT 24
Finished Aug 14 05:28:01 PM PDT 24
Peak memory 232932 kb
Host smart-93ce7ded-947e-4f30-aafe-14f3269122e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192710023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.192710023
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.4253077347
Short name T870
Test name
Test status
Simulation time 19502064 ps
CPU time 0.76 seconds
Started Aug 14 05:27:52 PM PDT 24
Finished Aug 14 05:27:53 PM PDT 24
Peak memory 206976 kb
Host smart-ffb5fcf8-0e0e-499e-9355-6f32bfc1095e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253077347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.4253077347
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.803199454
Short name T252
Test name
Test status
Simulation time 47746836348 ps
CPU time 127.26 seconds
Started Aug 14 05:28:00 PM PDT 24
Finished Aug 14 05:30:07 PM PDT 24
Peak memory 262644 kb
Host smart-9011cfc9-bdc0-4282-bbe5-003c242f6ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803199454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.803199454
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1823643244
Short name T822
Test name
Test status
Simulation time 4441341808 ps
CPU time 88.46 seconds
Started Aug 14 05:27:53 PM PDT 24
Finished Aug 14 05:29:21 PM PDT 24
Peak memory 264296 kb
Host smart-9a92bacb-1eda-4486-ac82-ea29fad24f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823643244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1823643244
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1378087346
Short name T448
Test name
Test status
Simulation time 3282776794 ps
CPU time 15.5 seconds
Started Aug 14 05:27:53 PM PDT 24
Finished Aug 14 05:28:09 PM PDT 24
Peak memory 236732 kb
Host smart-2810444c-38f5-4641-bb05-33b480a388ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378087346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1378087346
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3283300133
Short name T938
Test name
Test status
Simulation time 17805546286 ps
CPU time 55.52 seconds
Started Aug 14 05:27:54 PM PDT 24
Finished Aug 14 05:28:50 PM PDT 24
Peak memory 251116 kb
Host smart-b16d69c1-e073-4095-9fb5-84a75da0c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283300133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3283300133
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1993983238
Short name T749
Test name
Test status
Simulation time 700646118 ps
CPU time 5.09 seconds
Started Aug 14 05:28:01 PM PDT 24
Finished Aug 14 05:28:06 PM PDT 24
Peak memory 232912 kb
Host smart-bcf02ce0-a736-4856-a54c-f4e78649805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993983238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1993983238
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1841558693
Short name T719
Test name
Test status
Simulation time 458701880 ps
CPU time 14.17 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:28:16 PM PDT 24
Peak memory 249316 kb
Host smart-1f81aade-ec2c-4efa-9f2e-4715ea2acb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841558693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1841558693
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2615868705
Short name T44
Test name
Test status
Simulation time 15242559848 ps
CPU time 10.74 seconds
Started Aug 14 05:27:58 PM PDT 24
Finished Aug 14 05:28:09 PM PDT 24
Peak memory 233076 kb
Host smart-4acc4bae-d722-46f1-aeda-367992563f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615868705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2615868705
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.686101032
Short name T768
Test name
Test status
Simulation time 68399122 ps
CPU time 2.53 seconds
Started Aug 14 05:28:05 PM PDT 24
Finished Aug 14 05:28:07 PM PDT 24
Peak memory 232868 kb
Host smart-4e350c62-0372-425b-a900-3aed1378bead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686101032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.686101032
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2490011107
Short name T511
Test name
Test status
Simulation time 2819709017 ps
CPU time 5.15 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:28:07 PM PDT 24
Peak memory 223172 kb
Host smart-6b3f8e4b-ee95-4a60-a40f-f8690cc1054c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2490011107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2490011107
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1229909640
Short name T8
Test name
Test status
Simulation time 135316922 ps
CPU time 1.01 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:28:04 PM PDT 24
Peak memory 206616 kb
Host smart-0bc222e2-8ed4-44dc-aaca-f410150e9c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229909640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1229909640
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.345953463
Short name T28
Test name
Test status
Simulation time 2338581809 ps
CPU time 25.26 seconds
Started Aug 14 05:28:01 PM PDT 24
Finished Aug 14 05:28:27 PM PDT 24
Peak memory 216608 kb
Host smart-03cd55b5-4d3a-4b90-beac-9e17b1c12300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345953463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.345953463
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3482061621
Short name T963
Test name
Test status
Simulation time 12056605646 ps
CPU time 5.51 seconds
Started Aug 14 05:28:05 PM PDT 24
Finished Aug 14 05:28:10 PM PDT 24
Peak memory 216572 kb
Host smart-2f23fa17-b8a1-4ca5-8645-2a71c90d1ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482061621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3482061621
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1991812041
Short name T693
Test name
Test status
Simulation time 74298752 ps
CPU time 2.28 seconds
Started Aug 14 05:27:54 PM PDT 24
Finished Aug 14 05:27:57 PM PDT 24
Peak memory 216512 kb
Host smart-21f3967f-e55a-4fb9-a01f-d84a7b803451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991812041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1991812041
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3931039904
Short name T619
Test name
Test status
Simulation time 119258993 ps
CPU time 0.79 seconds
Started Aug 14 05:27:55 PM PDT 24
Finished Aug 14 05:27:56 PM PDT 24
Peak memory 206152 kb
Host smart-1b408a43-4e70-4ba4-9387-ad7114e07d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931039904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3931039904
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3752902905
Short name T460
Test name
Test status
Simulation time 289285503 ps
CPU time 3.04 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:28:07 PM PDT 24
Peak memory 224644 kb
Host smart-7da71786-37f7-468e-af5e-860537671033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752902905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3752902905
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3851340768
Short name T454
Test name
Test status
Simulation time 16005319 ps
CPU time 0.78 seconds
Started Aug 14 05:28:03 PM PDT 24
Finished Aug 14 05:28:04 PM PDT 24
Peak memory 204976 kb
Host smart-f15c7c2f-3f7b-4065-9218-93632257554f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851340768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3851340768
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1768706930
Short name T14
Test name
Test status
Simulation time 93204105 ps
CPU time 2.81 seconds
Started Aug 14 05:28:00 PM PDT 24
Finished Aug 14 05:28:03 PM PDT 24
Peak memory 232860 kb
Host smart-88037cfc-3b9c-456c-989c-4a5095b7cb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768706930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1768706930
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1297466274
Short name T642
Test name
Test status
Simulation time 55376617 ps
CPU time 0.79 seconds
Started Aug 14 05:27:55 PM PDT 24
Finished Aug 14 05:27:56 PM PDT 24
Peak memory 206708 kb
Host smart-8571c485-5384-48e5-a04a-731a35f472c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297466274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1297466274
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3949086945
Short name T758
Test name
Test status
Simulation time 3429414405 ps
CPU time 55.53 seconds
Started Aug 14 05:28:03 PM PDT 24
Finished Aug 14 05:28:58 PM PDT 24
Peak memory 251348 kb
Host smart-108fe223-ea75-4471-9055-33c4019763f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949086945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3949086945
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4029700576
Short name T666
Test name
Test status
Simulation time 5372888955 ps
CPU time 69.95 seconds
Started Aug 14 05:28:03 PM PDT 24
Finished Aug 14 05:29:13 PM PDT 24
Peak memory 249444 kb
Host smart-eac2d627-a9ce-42c8-920b-752f7d6de985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029700576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4029700576
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1086197142
Short name T194
Test name
Test status
Simulation time 213014195667 ps
CPU time 487.73 seconds
Started Aug 14 05:28:10 PM PDT 24
Finished Aug 14 05:36:18 PM PDT 24
Peak memory 255928 kb
Host smart-36486ac5-0646-4035-872e-9eac3b650dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086197142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1086197142
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.784226447
Short name T600
Test name
Test status
Simulation time 2532175278 ps
CPU time 8.18 seconds
Started Aug 14 05:27:54 PM PDT 24
Finished Aug 14 05:28:02 PM PDT 24
Peak memory 224776 kb
Host smart-8ecd3b10-53e3-4fbe-a032-487d5a3f6514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784226447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.784226447
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1816438113
Short name T739
Test name
Test status
Simulation time 23984454093 ps
CPU time 60.35 seconds
Started Aug 14 05:27:54 PM PDT 24
Finished Aug 14 05:28:54 PM PDT 24
Peak memory 249348 kb
Host smart-b8c5c835-1a63-4d33-bb83-502bf83717f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816438113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1816438113
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1520208228
Short name T810
Test name
Test status
Simulation time 85015994 ps
CPU time 2.83 seconds
Started Aug 14 05:27:51 PM PDT 24
Finished Aug 14 05:27:54 PM PDT 24
Peak memory 232804 kb
Host smart-e6132fde-0bf7-4e77-9c8a-21620b445442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520208228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1520208228
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.650182678
Short name T264
Test name
Test status
Simulation time 807614265 ps
CPU time 8.62 seconds
Started Aug 14 05:27:54 PM PDT 24
Finished Aug 14 05:28:02 PM PDT 24
Peak memory 239344 kb
Host smart-6ab17e9e-911f-4b9d-9193-a53d13eb0b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650182678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.650182678
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4078131740
Short name T931
Test name
Test status
Simulation time 582541880 ps
CPU time 4.64 seconds
Started Aug 14 05:27:54 PM PDT 24
Finished Aug 14 05:27:59 PM PDT 24
Peak memory 224688 kb
Host smart-eca27e4c-ae8e-4112-aac9-c36dc887be21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078131740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4078131740
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1686053403
Short name T789
Test name
Test status
Simulation time 635995798 ps
CPU time 5.9 seconds
Started Aug 14 05:27:54 PM PDT 24
Finished Aug 14 05:28:00 PM PDT 24
Peak memory 224648 kb
Host smart-9e669332-a061-4036-8f63-8e9087fa4483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686053403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1686053403
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3419165669
Short name T515
Test name
Test status
Simulation time 550180582 ps
CPU time 3.28 seconds
Started Aug 14 05:28:05 PM PDT 24
Finished Aug 14 05:28:09 PM PDT 24
Peak memory 219768 kb
Host smart-687a0b1d-2406-4ccb-9ad0-20dc1b2eaf58
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3419165669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3419165669
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3581550623
Short name T708
Test name
Test status
Simulation time 3620084540 ps
CPU time 21.14 seconds
Started Aug 14 05:28:01 PM PDT 24
Finished Aug 14 05:28:23 PM PDT 24
Peak memory 216580 kb
Host smart-f63bff0e-c692-4d6b-a787-7a41d3eaf1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581550623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3581550623
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3606554118
Short name T136
Test name
Test status
Simulation time 1405062466 ps
CPU time 7.82 seconds
Started Aug 14 05:28:00 PM PDT 24
Finished Aug 14 05:28:08 PM PDT 24
Peak memory 216532 kb
Host smart-e090d212-e7b5-4d15-bc9a-f2fdc9c38582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606554118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3606554118
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1407167935
Short name T576
Test name
Test status
Simulation time 273410111 ps
CPU time 1.77 seconds
Started Aug 14 05:28:03 PM PDT 24
Finished Aug 14 05:28:05 PM PDT 24
Peak memory 208344 kb
Host smart-5e9d08ca-db5a-40df-b3f3-8b88dec9b065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407167935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1407167935
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1724482600
Short name T349
Test name
Test status
Simulation time 13455986 ps
CPU time 0.71 seconds
Started Aug 14 05:27:56 PM PDT 24
Finished Aug 14 05:27:57 PM PDT 24
Peak memory 205740 kb
Host smart-7790c9a1-6e3a-45c4-8d1f-83d03777f8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724482600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1724482600
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3440155030
Short name T524
Test name
Test status
Simulation time 4863228672 ps
CPU time 9.17 seconds
Started Aug 14 05:27:54 PM PDT 24
Finished Aug 14 05:28:03 PM PDT 24
Peak memory 232988 kb
Host smart-c619ce8e-a085-4454-a673-d13da2ce2355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440155030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3440155030
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2063076201
Short name T336
Test name
Test status
Simulation time 39026745 ps
CPU time 0.7 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:28:10 PM PDT 24
Peak memory 205024 kb
Host smart-96c51c29-c0ce-4f74-a358-7fc2c80ce9b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063076201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2063076201
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1730305122
Short name T820
Test name
Test status
Simulation time 26121392357 ps
CPU time 16.78 seconds
Started Aug 14 05:28:05 PM PDT 24
Finished Aug 14 05:28:22 PM PDT 24
Peak memory 232984 kb
Host smart-150befce-9f87-4ea5-b976-6272fd6f21ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730305122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1730305122
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1039307503
Short name T716
Test name
Test status
Simulation time 64877496 ps
CPU time 0.75 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:28:10 PM PDT 24
Peak memory 205632 kb
Host smart-21ffefc0-c50b-4172-bf06-efe42bc211ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039307503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1039307503
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.4277950034
Short name T170
Test name
Test status
Simulation time 405473510951 ps
CPU time 327.99 seconds
Started Aug 14 05:28:10 PM PDT 24
Finished Aug 14 05:33:38 PM PDT 24
Peak memory 265712 kb
Host smart-c612cd96-c26f-4e07-b8c0-aaed8c868041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277950034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.4277950034
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2615440663
Short name T217
Test name
Test status
Simulation time 849351664 ps
CPU time 20.23 seconds
Started Aug 14 05:28:07 PM PDT 24
Finished Aug 14 05:28:27 PM PDT 24
Peak memory 224792 kb
Host smart-12a7f861-b45a-46c0-8812-f66103ba2112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615440663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2615440663
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1684868962
Short name T75
Test name
Test status
Simulation time 4804985881 ps
CPU time 31.87 seconds
Started Aug 14 05:28:03 PM PDT 24
Finished Aug 14 05:28:35 PM PDT 24
Peak memory 251544 kb
Host smart-bdb9c22a-a2f0-49f7-9a4c-dc9adcfc88aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684868962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1684868962
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1453480673
Short name T304
Test name
Test status
Simulation time 2455389637 ps
CPU time 8.02 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:28:11 PM PDT 24
Peak memory 224744 kb
Host smart-653b2128-d42e-480a-ad4d-c415d27308f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453480673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1453480673
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.402302726
Short name T271
Test name
Test status
Simulation time 131262533271 ps
CPU time 382.97 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:34:27 PM PDT 24
Peak memory 261280 kb
Host smart-dd51bb4b-e300-4c57-9276-e038a9555b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402302726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.402302726
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4189657254
Short name T973
Test name
Test status
Simulation time 393206842 ps
CPU time 5.22 seconds
Started Aug 14 05:28:01 PM PDT 24
Finished Aug 14 05:28:07 PM PDT 24
Peak memory 232824 kb
Host smart-8949cc42-2aaa-4247-8401-2003a740f4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189657254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4189657254
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2822412092
Short name T236
Test name
Test status
Simulation time 448608416 ps
CPU time 9.46 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:28:11 PM PDT 24
Peak memory 232892 kb
Host smart-73ee747a-6877-4dc3-be08-04c847fc1f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822412092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2822412092
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3126620139
Short name T215
Test name
Test status
Simulation time 12136763923 ps
CPU time 14.99 seconds
Started Aug 14 05:28:03 PM PDT 24
Finished Aug 14 05:28:18 PM PDT 24
Peak memory 233948 kb
Host smart-6c2c6fde-9208-47d6-abd4-f65346ce56a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126620139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3126620139
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1814683882
Short name T685
Test name
Test status
Simulation time 68044811 ps
CPU time 2.25 seconds
Started Aug 14 05:28:03 PM PDT 24
Finished Aug 14 05:28:05 PM PDT 24
Peak memory 224260 kb
Host smart-dd0734a4-93a4-4d4d-a6f9-e0cc1b085008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814683882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1814683882
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2663725556
Short name T1021
Test name
Test status
Simulation time 2242141364 ps
CPU time 11.85 seconds
Started Aug 14 05:28:06 PM PDT 24
Finished Aug 14 05:28:18 PM PDT 24
Peak memory 222516 kb
Host smart-1929fa5c-c756-470e-a0cf-c7d4f9b8cbc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2663725556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2663725556
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.636490640
Short name T467
Test name
Test status
Simulation time 82458909 ps
CPU time 0.97 seconds
Started Aug 14 05:28:05 PM PDT 24
Finished Aug 14 05:28:07 PM PDT 24
Peak memory 207584 kb
Host smart-b480dd07-0943-4210-8fba-3ed76ea83bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636490640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.636490640
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1921605079
Short name T804
Test name
Test status
Simulation time 32437421 ps
CPU time 0.76 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:28:03 PM PDT 24
Peak memory 205736 kb
Host smart-67388828-7a6d-478a-b4e9-20404b8ec1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921605079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1921605079
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1286404258
Short name T444
Test name
Test status
Simulation time 217383621 ps
CPU time 1.59 seconds
Started Aug 14 05:28:05 PM PDT 24
Finished Aug 14 05:28:07 PM PDT 24
Peak memory 208096 kb
Host smart-7e438c00-662c-4a61-ba28-a6d80f408434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286404258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1286404258
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3990761875
Short name T525
Test name
Test status
Simulation time 21059961 ps
CPU time 0.86 seconds
Started Aug 14 05:28:05 PM PDT 24
Finished Aug 14 05:28:06 PM PDT 24
Peak memory 207152 kb
Host smart-dcdd2198-2c5b-4626-8c28-49b6dce5188c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990761875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3990761875
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1129762422
Short name T516
Test name
Test status
Simulation time 32235030 ps
CPU time 0.84 seconds
Started Aug 14 05:28:06 PM PDT 24
Finished Aug 14 05:28:07 PM PDT 24
Peak memory 206140 kb
Host smart-fbd8d3f8-f413-49c0-a25f-7fbe7f5d3e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129762422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1129762422
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1934623183
Short name T782
Test name
Test status
Simulation time 375523335 ps
CPU time 2.93 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:28:05 PM PDT 24
Peak memory 232888 kb
Host smart-8ad4f1f1-a2f2-4847-ac5e-63cdc9fd8759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934623183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1934623183
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4052379441
Short name T944
Test name
Test status
Simulation time 11932076 ps
CPU time 0.71 seconds
Started Aug 14 05:25:49 PM PDT 24
Finished Aug 14 05:25:50 PM PDT 24
Peak memory 205560 kb
Host smart-7bf9d312-beca-4651-86ba-f689222dd7cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052379441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
052379441
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2113353084
Short name T507
Test name
Test status
Simulation time 269176319 ps
CPU time 2.52 seconds
Started Aug 14 05:25:47 PM PDT 24
Finished Aug 14 05:25:49 PM PDT 24
Peak memory 232876 kb
Host smart-3f1670e9-fab4-44d4-8754-522f25e2a0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113353084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2113353084
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2298328233
Short name T68
Test name
Test status
Simulation time 92854721 ps
CPU time 0.77 seconds
Started Aug 14 05:25:48 PM PDT 24
Finished Aug 14 05:25:48 PM PDT 24
Peak memory 206964 kb
Host smart-22e767c9-928c-4730-81f9-90023b0250fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298328233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2298328233
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.4047839721
Short name T875
Test name
Test status
Simulation time 37217984332 ps
CPU time 52.77 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:26:42 PM PDT 24
Peak memory 224796 kb
Host smart-88f1c08c-b739-4720-bdf2-8a0c07aa6ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047839721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4047839721
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3262127532
Short name T195
Test name
Test status
Simulation time 8874011948 ps
CPU time 85.05 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:27:15 PM PDT 24
Peak memory 257576 kb
Host smart-df6099c9-5e5c-4e65-8a11-02f420dc4d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262127532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3262127532
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2168442597
Short name T205
Test name
Test status
Simulation time 126671852811 ps
CPU time 538.24 seconds
Started Aug 14 05:25:48 PM PDT 24
Finished Aug 14 05:34:47 PM PDT 24
Peak memory 270004 kb
Host smart-7b20965f-fdbf-49c6-8878-8bb3415988eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168442597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2168442597
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4115743514
Short name T654
Test name
Test status
Simulation time 1475001437 ps
CPU time 7.22 seconds
Started Aug 14 05:25:48 PM PDT 24
Finished Aug 14 05:25:55 PM PDT 24
Peak memory 224720 kb
Host smart-32f6b864-9093-4da6-a59d-1c6936dd5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115743514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4115743514
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.967765399
Short name T731
Test name
Test status
Simulation time 21281903 ps
CPU time 0.79 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:25:51 PM PDT 24
Peak memory 215792 kb
Host smart-52f7d809-0622-499f-824a-a9a0bbff0fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967765399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
967765399
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2822582749
Short name T406
Test name
Test status
Simulation time 307731781 ps
CPU time 2.32 seconds
Started Aug 14 05:25:48 PM PDT 24
Finished Aug 14 05:25:51 PM PDT 24
Peak memory 223272 kb
Host smart-3b920041-7ef1-401f-b77b-72709d2f1064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822582749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2822582749
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3381721968
Short name T256
Test name
Test status
Simulation time 2791984396 ps
CPU time 43.69 seconds
Started Aug 14 05:25:48 PM PDT 24
Finished Aug 14 05:26:31 PM PDT 24
Peak memory 224796 kb
Host smart-80888945-9525-40dd-af7a-c273b2c1d0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381721968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3381721968
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2920152226
Short name T364
Test name
Test status
Simulation time 14616256 ps
CPU time 1.03 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:25:51 PM PDT 24
Peak memory 216752 kb
Host smart-050b0d3d-f229-4751-a891-50a0ff3e040a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920152226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2920152226
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.837702096
Short name T476
Test name
Test status
Simulation time 634151564 ps
CPU time 6.51 seconds
Started Aug 14 05:25:48 PM PDT 24
Finished Aug 14 05:25:55 PM PDT 24
Peak memory 232908 kb
Host smart-7552e63f-654f-4dcc-81b5-5725f20330e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837702096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
837702096
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3093888455
Short name T120
Test name
Test status
Simulation time 2918200213 ps
CPU time 6.51 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:25:56 PM PDT 24
Peak memory 232944 kb
Host smart-a3194aa7-4f18-44db-b53f-a7cfb4f87a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093888455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3093888455
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3826679083
Short name T503
Test name
Test status
Simulation time 205430995 ps
CPU time 4.36 seconds
Started Aug 14 05:25:49 PM PDT 24
Finished Aug 14 05:25:54 PM PDT 24
Peak memory 220096 kb
Host smart-fd525dfa-3355-49aa-95da-b66c8c929d06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3826679083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3826679083
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1854048558
Short name T74
Test name
Test status
Simulation time 167537203 ps
CPU time 1.19 seconds
Started Aug 14 05:25:47 PM PDT 24
Finished Aug 14 05:25:49 PM PDT 24
Peak memory 236132 kb
Host smart-bb7f708a-f211-4fab-8490-8f7c7d98b336
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854048558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1854048558
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2869620479
Short name T979
Test name
Test status
Simulation time 60650534 ps
CPU time 1.11 seconds
Started Aug 14 05:25:49 PM PDT 24
Finished Aug 14 05:25:50 PM PDT 24
Peak memory 207084 kb
Host smart-7b6256ff-9e4c-46ef-a1ca-254dd1a44980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869620479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2869620479
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4081911258
Short name T676
Test name
Test status
Simulation time 1395717367 ps
CPU time 3.85 seconds
Started Aug 14 05:25:47 PM PDT 24
Finished Aug 14 05:25:51 PM PDT 24
Peak memory 217724 kb
Host smart-deb2e72e-7de4-432d-8ad7-121ac552c59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081911258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4081911258
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.457794389
Short name T319
Test name
Test status
Simulation time 14532858 ps
CPU time 0.73 seconds
Started Aug 14 05:25:49 PM PDT 24
Finished Aug 14 05:25:50 PM PDT 24
Peak memory 205684 kb
Host smart-7f9526b1-6fa7-4303-8b46-38f900133c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457794389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.457794389
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2285626105
Short name T607
Test name
Test status
Simulation time 475976377 ps
CPU time 1.99 seconds
Started Aug 14 05:25:48 PM PDT 24
Finished Aug 14 05:25:50 PM PDT 24
Peak memory 216460 kb
Host smart-b5399a38-287c-4962-8688-6de5fc4d9d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285626105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2285626105
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2874279283
Short name T903
Test name
Test status
Simulation time 88054213 ps
CPU time 0.83 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:25:51 PM PDT 24
Peak memory 206144 kb
Host smart-1cb8297b-3357-4508-be1f-aa4b77a38749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874279283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2874279283
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3966146072
Short name T233
Test name
Test status
Simulation time 6216606201 ps
CPU time 12.13 seconds
Started Aug 14 05:25:50 PM PDT 24
Finished Aug 14 05:26:02 PM PDT 24
Peak memory 224664 kb
Host smart-fd6a4fb0-4532-41b9-8979-b0a6394ebbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966146072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3966146072
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1156370903
Short name T541
Test name
Test status
Simulation time 33747008 ps
CPU time 0.73 seconds
Started Aug 14 05:28:06 PM PDT 24
Finished Aug 14 05:28:07 PM PDT 24
Peak memory 205576 kb
Host smart-084b1b1c-731b-45a5-810c-79d65400ad13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156370903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1156370903
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2402215330
Short name T333
Test name
Test status
Simulation time 1693490657 ps
CPU time 14.56 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:28:24 PM PDT 24
Peak memory 224728 kb
Host smart-b43dcc01-0dc2-49e0-833b-e2c3bd4a9dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402215330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2402215330
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4287075543
Short name T69
Test name
Test status
Simulation time 26665739 ps
CPU time 0.81 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:28:05 PM PDT 24
Peak memory 206552 kb
Host smart-f0061a60-1695-4a7a-99d0-cbcb6c4e9cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287075543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4287075543
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.733396053
Short name T392
Test name
Test status
Simulation time 1994405252 ps
CPU time 8.48 seconds
Started Aug 14 05:28:03 PM PDT 24
Finished Aug 14 05:28:11 PM PDT 24
Peak memory 235412 kb
Host smart-613e5277-c942-452e-80dc-17fb4c8bec8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733396053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.733396053
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3649804475
Short name T82
Test name
Test status
Simulation time 3262799309 ps
CPU time 38.39 seconds
Started Aug 14 05:28:03 PM PDT 24
Finished Aug 14 05:28:42 PM PDT 24
Peak memory 249376 kb
Host smart-be0d1428-a3a6-43c2-b706-167b744082d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649804475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3649804475
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3835423696
Short name T723
Test name
Test status
Simulation time 28847684440 ps
CPU time 65.29 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:29:08 PM PDT 24
Peak memory 239468 kb
Host smart-d1e323af-2d74-4a46-9516-2a982f4983f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835423696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3835423696
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.266863178
Short name T765
Test name
Test status
Simulation time 1539481636 ps
CPU time 5.21 seconds
Started Aug 14 05:28:08 PM PDT 24
Finished Aug 14 05:28:13 PM PDT 24
Peak memory 234564 kb
Host smart-a123a470-97b1-44f1-aef2-754f0240c331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266863178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.266863178
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.928702023
Short name T951
Test name
Test status
Simulation time 48570997942 ps
CPU time 313.01 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:33:22 PM PDT 24
Peak memory 268384 kb
Host smart-79d957c0-df88-4b54-bf9e-bd513ff9edf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928702023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.928702023
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.579863311
Short name T748
Test name
Test status
Simulation time 351889106 ps
CPU time 5.31 seconds
Started Aug 14 05:28:08 PM PDT 24
Finished Aug 14 05:28:13 PM PDT 24
Peak memory 224668 kb
Host smart-85b1350f-40e5-4de9-a7a0-6535e70bf7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579863311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.579863311
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3132647269
Short name T826
Test name
Test status
Simulation time 499484002 ps
CPU time 2.5 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:28:06 PM PDT 24
Peak memory 232556 kb
Host smart-3cb95371-b063-4d39-9447-14503a4eae31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132647269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3132647269
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.398039258
Short name T190
Test name
Test status
Simulation time 1937075923 ps
CPU time 6.82 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:28:11 PM PDT 24
Peak memory 237572 kb
Host smart-811c06a8-e786-41dd-a214-b3f0d36344e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398039258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.398039258
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2733450126
Short name T533
Test name
Test status
Simulation time 7325668385 ps
CPU time 8.49 seconds
Started Aug 14 05:28:03 PM PDT 24
Finished Aug 14 05:28:11 PM PDT 24
Peak memory 232988 kb
Host smart-0747f35c-0cf6-4cff-ab2b-17f4d7cae4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733450126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2733450126
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3130748968
Short name T540
Test name
Test status
Simulation time 1003761581 ps
CPU time 4.85 seconds
Started Aug 14 05:28:06 PM PDT 24
Finished Aug 14 05:28:11 PM PDT 24
Peak memory 222492 kb
Host smart-2b06092a-ee88-4aa7-9612-7b7c5d009ca7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3130748968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3130748968
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3243809904
Short name T762
Test name
Test status
Simulation time 39781105 ps
CPU time 0.94 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:28:10 PM PDT 24
Peak memory 206648 kb
Host smart-9ea0d583-e86b-4043-97d3-01994b67d88c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243809904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3243809904
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2633617102
Short name T29
Test name
Test status
Simulation time 6116427375 ps
CPU time 21.54 seconds
Started Aug 14 05:28:10 PM PDT 24
Finished Aug 14 05:28:32 PM PDT 24
Peak memory 216924 kb
Host smart-f078299a-aac6-4554-b038-0ca91a958fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633617102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2633617102
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1795924365
Short name T328
Test name
Test status
Simulation time 1875821070 ps
CPU time 7.89 seconds
Started Aug 14 05:28:07 PM PDT 24
Finished Aug 14 05:28:15 PM PDT 24
Peak memory 216492 kb
Host smart-3c742d67-f07f-4f04-b8df-133ef3614279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795924365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1795924365
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.446630825
Short name T962
Test name
Test status
Simulation time 80760444 ps
CPU time 0.83 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:28:03 PM PDT 24
Peak memory 206136 kb
Host smart-a0a4fd58-8dc6-4d01-b1d6-b459ed38e11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446630825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.446630825
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4095993489
Short name T141
Test name
Test status
Simulation time 94402231 ps
CPU time 1.01 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:28:05 PM PDT 24
Peak memory 207084 kb
Host smart-680f7d8b-240a-4d2d-960b-35ef47af105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095993489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4095993489
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.493805239
Short name T560
Test name
Test status
Simulation time 4521491720 ps
CPU time 14.94 seconds
Started Aug 14 05:28:08 PM PDT 24
Finished Aug 14 05:28:23 PM PDT 24
Peak memory 232976 kb
Host smart-0783ab44-71bf-4ba3-a2a7-ed73f1880f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493805239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.493805239
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2737453987
Short name T388
Test name
Test status
Simulation time 12273977 ps
CPU time 0.72 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:28:12 PM PDT 24
Peak memory 205932 kb
Host smart-6f4703e6-d158-4b37-8069-dc3e6c062ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737453987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2737453987
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3341016534
Short name T800
Test name
Test status
Simulation time 5036323476 ps
CPU time 12.49 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:28:24 PM PDT 24
Peak memory 232988 kb
Host smart-f087fb4b-b159-4d8c-9d2d-9513d69d9302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341016534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3341016534
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1479185670
Short name T325
Test name
Test status
Simulation time 82157463 ps
CPU time 0.79 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:28:05 PM PDT 24
Peak memory 206552 kb
Host smart-fc16465a-762a-4623-bf1f-a88e2ee6ea5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479185670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1479185670
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.936121305
Short name T260
Test name
Test status
Simulation time 16056061837 ps
CPU time 27.49 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:28:36 PM PDT 24
Peak memory 224768 kb
Host smart-36f89aa8-6fd6-458f-8b78-ef1dcc76bcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936121305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.936121305
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1578291872
Short name T266
Test name
Test status
Simulation time 23615584282 ps
CPU time 135.33 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:30:25 PM PDT 24
Peak memory 254064 kb
Host smart-2755747a-4dbd-47c3-8b40-3ffa8906d555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578291872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1578291872
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1129581727
Short name T655
Test name
Test status
Simulation time 43118405135 ps
CPU time 28 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:28:37 PM PDT 24
Peak memory 217780 kb
Host smart-60a60470-c85d-4fe4-a505-d3734d38ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129581727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1129581727
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1233004615
Short name T377
Test name
Test status
Simulation time 564344580 ps
CPU time 8.36 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:28:12 PM PDT 24
Peak memory 241116 kb
Host smart-f60b9008-faaf-445a-881b-2d7200307afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233004615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1233004615
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.78645357
Short name T258
Test name
Test status
Simulation time 50047442980 ps
CPU time 168.61 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:30:53 PM PDT 24
Peak memory 252332 kb
Host smart-4fbb91d6-aa50-4ca0-9fd9-701a6505b76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78645357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.78645357
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1115928605
Short name T43
Test name
Test status
Simulation time 3238601067 ps
CPU time 38.01 seconds
Started Aug 14 05:28:07 PM PDT 24
Finished Aug 14 05:28:45 PM PDT 24
Peak memory 224812 kb
Host smart-7099073c-602a-428d-a7ec-a2ca5f28757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115928605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1115928605
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3691520298
Short name T425
Test name
Test status
Simulation time 92753559 ps
CPU time 2.96 seconds
Started Aug 14 05:28:06 PM PDT 24
Finished Aug 14 05:28:10 PM PDT 24
Peak memory 232888 kb
Host smart-8eb1d015-56f8-42b4-8f90-2e2964e6b915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691520298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3691520298
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3313956939
Short name T291
Test name
Test status
Simulation time 1228170643 ps
CPU time 2.91 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:28:05 PM PDT 24
Peak memory 224632 kb
Host smart-24b20b06-34b9-4c5d-aaef-a10d8bb35755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313956939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3313956939
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1818754841
Short name T967
Test name
Test status
Simulation time 6703784972 ps
CPU time 10.14 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:28:14 PM PDT 24
Peak memory 232920 kb
Host smart-80b951aa-6c53-4b3f-a560-bd540f62fc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818754841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1818754841
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3102712652
Short name T933
Test name
Test status
Simulation time 685264015 ps
CPU time 3.6 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:28:08 PM PDT 24
Peak memory 219000 kb
Host smart-8f088231-67a8-4dec-8754-45d29c6bf449
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3102712652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3102712652
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.882045678
Short name T570
Test name
Test status
Simulation time 28757392551 ps
CPU time 178.75 seconds
Started Aug 14 05:28:10 PM PDT 24
Finished Aug 14 05:31:09 PM PDT 24
Peak memory 254636 kb
Host smart-7e74db34-f685-41d1-89e2-4a8e029e35b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882045678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.882045678
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1883887681
Short name T315
Test name
Test status
Simulation time 8829126092 ps
CPU time 23.56 seconds
Started Aug 14 05:28:04 PM PDT 24
Finished Aug 14 05:28:28 PM PDT 24
Peak memory 216544 kb
Host smart-568181e3-f68b-4c05-86b3-a135155eeef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883887681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1883887681
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3522029968
Short name T923
Test name
Test status
Simulation time 2365137400 ps
CPU time 5.62 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:28:08 PM PDT 24
Peak memory 216624 kb
Host smart-8d2bb500-a74d-4c4e-8c33-dd183b6b8cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522029968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3522029968
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3637110017
Short name T510
Test name
Test status
Simulation time 25067880 ps
CPU time 0.77 seconds
Started Aug 14 05:28:06 PM PDT 24
Finished Aug 14 05:28:07 PM PDT 24
Peak memory 206264 kb
Host smart-305d97f8-a31b-4ede-93b2-0ec6394b8a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637110017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3637110017
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1482409682
Short name T537
Test name
Test status
Simulation time 88191110 ps
CPU time 1.01 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:28:10 PM PDT 24
Peak memory 206084 kb
Host smart-4b72a0d9-0156-440a-b395-5dd4a6adfcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482409682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1482409682
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1534007800
Short name T704
Test name
Test status
Simulation time 5414854243 ps
CPU time 7.56 seconds
Started Aug 14 05:28:02 PM PDT 24
Finished Aug 14 05:28:10 PM PDT 24
Peak memory 232956 kb
Host smart-f6e3b0dd-9ffc-439a-9743-e7347550b41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534007800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1534007800
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3383327313
Short name T687
Test name
Test status
Simulation time 22519403 ps
CPU time 0.71 seconds
Started Aug 14 05:28:18 PM PDT 24
Finished Aug 14 05:28:19 PM PDT 24
Peak memory 204964 kb
Host smart-ee9afaef-a67b-4234-9623-1b0e1c147336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383327313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3383327313
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2556886775
Short name T849
Test name
Test status
Simulation time 340476856 ps
CPU time 2.88 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:28:12 PM PDT 24
Peak memory 232872 kb
Host smart-3dd39295-fd96-46e8-8562-8231c62a64de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556886775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2556886775
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1590294011
Short name T613
Test name
Test status
Simulation time 17562580 ps
CPU time 0.81 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:28:12 PM PDT 24
Peak memory 206548 kb
Host smart-7ca38105-c1df-4880-a207-d7033aa31c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590294011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1590294011
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3412632052
Short name T863
Test name
Test status
Simulation time 5158415600 ps
CPU time 95.83 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:29:47 PM PDT 24
Peak memory 255908 kb
Host smart-46a3c391-122c-4be0-b69e-5f39910b39f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412632052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3412632052
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2051804971
Short name T209
Test name
Test status
Simulation time 72609291270 ps
CPU time 722.21 seconds
Started Aug 14 05:28:18 PM PDT 24
Finished Aug 14 05:40:20 PM PDT 24
Peak memory 255804 kb
Host smart-6ae4c343-21a9-4e54-85bc-f1b2f54f1804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051804971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2051804971
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4136187261
Short name T296
Test name
Test status
Simulation time 24165821450 ps
CPU time 235.52 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:32:05 PM PDT 24
Peak memory 256964 kb
Host smart-9f12bd1f-4aaa-4a88-8cc0-0c1e14a151a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136187261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4136187261
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3357660827
Short name T299
Test name
Test status
Simulation time 3373734806 ps
CPU time 16.11 seconds
Started Aug 14 05:28:10 PM PDT 24
Finished Aug 14 05:28:27 PM PDT 24
Peak memory 234032 kb
Host smart-27d91c5f-b610-4de1-8379-099051ad6de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357660827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3357660827
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1016452436
Short name T650
Test name
Test status
Simulation time 1693575717 ps
CPU time 35.94 seconds
Started Aug 14 05:28:18 PM PDT 24
Finished Aug 14 05:28:54 PM PDT 24
Peak memory 254616 kb
Host smart-a2f5ba62-723d-48a0-9dc3-487170db06e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016452436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1016452436
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2505154746
Short name T991
Test name
Test status
Simulation time 1375038434 ps
CPU time 3.81 seconds
Started Aug 14 05:28:10 PM PDT 24
Finished Aug 14 05:28:14 PM PDT 24
Peak memory 224680 kb
Host smart-e134e9ad-e658-4a9a-b449-985f8cc1c3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505154746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2505154746
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.124859346
Short name T833
Test name
Test status
Simulation time 16651204230 ps
CPU time 38.95 seconds
Started Aug 14 05:28:18 PM PDT 24
Finished Aug 14 05:28:57 PM PDT 24
Peak memory 232964 kb
Host smart-e1df33e6-62a4-4c45-994b-799be365acd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124859346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.124859346
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.56235586
Short name T817
Test name
Test status
Simulation time 82544607 ps
CPU time 2.19 seconds
Started Aug 14 05:28:13 PM PDT 24
Finished Aug 14 05:28:15 PM PDT 24
Peak memory 224576 kb
Host smart-92e054b7-aad3-490d-8076-2ebdeeb95142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56235586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.56235586
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4214355884
Short name T543
Test name
Test status
Simulation time 3399085161 ps
CPU time 11.21 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:28:23 PM PDT 24
Peak memory 241128 kb
Host smart-0114c2c0-7c1c-426a-bce2-d755ad5066f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214355884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4214355884
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2304781216
Short name T438
Test name
Test status
Simulation time 1063268841 ps
CPU time 11.45 seconds
Started Aug 14 05:28:10 PM PDT 24
Finished Aug 14 05:28:21 PM PDT 24
Peak memory 220672 kb
Host smart-d316b400-a2fb-4d19-bd59-14e86c4f1a59
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2304781216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2304781216
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1959488935
Short name T987
Test name
Test status
Simulation time 11603764236 ps
CPU time 22.23 seconds
Started Aug 14 05:28:13 PM PDT 24
Finished Aug 14 05:28:35 PM PDT 24
Peak memory 224700 kb
Host smart-9fb46ab8-f36f-4b06-bcc1-3d5a1a57d140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959488935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1959488935
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3780558226
Short name T427
Test name
Test status
Simulation time 59978176774 ps
CPU time 35.63 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:28:47 PM PDT 24
Peak memory 216528 kb
Host smart-d74bc4d1-3649-4ac4-95fd-93279d968a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780558226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3780558226
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1571966134
Short name T807
Test name
Test status
Simulation time 1240409517 ps
CPU time 3.88 seconds
Started Aug 14 05:28:20 PM PDT 24
Finished Aug 14 05:28:24 PM PDT 24
Peak memory 216480 kb
Host smart-fda6c654-b848-499d-820a-535ff0db629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571966134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1571966134
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3748598716
Short name T1019
Test name
Test status
Simulation time 687379162 ps
CPU time 1.73 seconds
Started Aug 14 05:28:21 PM PDT 24
Finished Aug 14 05:28:23 PM PDT 24
Peak memory 216452 kb
Host smart-a808508e-bda0-4e11-8ad6-40a19001d584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748598716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3748598716
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.593092082
Short name T845
Test name
Test status
Simulation time 26749889 ps
CPU time 0.7 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:28:12 PM PDT 24
Peak memory 205684 kb
Host smart-40eb8bff-e6e4-4e8e-9525-f2ad7e7f4945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593092082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.593092082
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3928165082
Short name T353
Test name
Test status
Simulation time 10115347766 ps
CPU time 10.26 seconds
Started Aug 14 05:28:10 PM PDT 24
Finished Aug 14 05:28:20 PM PDT 24
Peak memory 232960 kb
Host smart-51442085-f213-4406-82b7-c3f42f1a8038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928165082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3928165082
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1040109793
Short name T321
Test name
Test status
Simulation time 42529629 ps
CPU time 0.76 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:28:12 PM PDT 24
Peak memory 204976 kb
Host smart-6bb77857-71b8-4733-9ae4-636d7a6ff14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040109793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1040109793
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.955761777
Short name T375
Test name
Test status
Simulation time 3005350379 ps
CPU time 8.94 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:28:20 PM PDT 24
Peak memory 232972 kb
Host smart-7dc99e97-4e28-4edf-ad7e-8ebc33557d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955761777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.955761777
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3671700688
Short name T627
Test name
Test status
Simulation time 45581079 ps
CPU time 0.83 seconds
Started Aug 14 05:28:12 PM PDT 24
Finished Aug 14 05:28:13 PM PDT 24
Peak memory 207004 kb
Host smart-621108ab-263a-4bbd-b9e2-a0df50abe55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671700688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3671700688
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1563474264
Short name T558
Test name
Test status
Simulation time 1286840205 ps
CPU time 14.41 seconds
Started Aug 14 05:28:12 PM PDT 24
Finished Aug 14 05:28:26 PM PDT 24
Peak memory 224720 kb
Host smart-6c92ad28-32fa-4b3d-a5f0-3a6cd10c0082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563474264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1563474264
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1112077302
Short name T413
Test name
Test status
Simulation time 16447508850 ps
CPU time 20.18 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:28:30 PM PDT 24
Peak memory 217716 kb
Host smart-723b0c97-8035-4787-a5df-ebed2b96235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112077302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1112077302
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1070044136
Short name T175
Test name
Test status
Simulation time 13072688178 ps
CPU time 120.4 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 261912 kb
Host smart-0ce86910-c453-410a-94cd-131fbe0d9eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070044136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1070044136
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1217921391
Short name T302
Test name
Test status
Simulation time 11706939631 ps
CPU time 37.01 seconds
Started Aug 14 05:28:20 PM PDT 24
Finished Aug 14 05:28:58 PM PDT 24
Peak memory 234176 kb
Host smart-1aadb6b0-7051-4eb7-b052-aba114dc62c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217921391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1217921391
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3009212729
Short name T663
Test name
Test status
Simulation time 28022649208 ps
CPU time 111.92 seconds
Started Aug 14 05:28:20 PM PDT 24
Finished Aug 14 05:30:12 PM PDT 24
Peak memory 251068 kb
Host smart-fc8181ef-876c-44f3-a225-9c3cd3a19856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009212729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3009212729
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1312413411
Short name T756
Test name
Test status
Simulation time 290143359 ps
CPU time 5.31 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:28:16 PM PDT 24
Peak memory 224676 kb
Host smart-6eedf9a1-7f40-4be4-bd18-3f6249f2bb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312413411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1312413411
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2625421447
Short name T477
Test name
Test status
Simulation time 27369088017 ps
CPU time 48.22 seconds
Started Aug 14 05:28:12 PM PDT 24
Finished Aug 14 05:29:00 PM PDT 24
Peak memory 233952 kb
Host smart-0d2d38dc-9d43-4fa2-bcc1-1cc6c9a3f154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625421447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2625421447
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3085992461
Short name T465
Test name
Test status
Simulation time 3667309928 ps
CPU time 4.78 seconds
Started Aug 14 05:28:08 PM PDT 24
Finished Aug 14 05:28:13 PM PDT 24
Peak memory 224732 kb
Host smart-d22b8da0-6bb7-43e7-8156-e6ff67fc291a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085992461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3085992461
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.692238561
Short name T338
Test name
Test status
Simulation time 106145677 ps
CPU time 2.12 seconds
Started Aug 14 05:28:12 PM PDT 24
Finished Aug 14 05:28:14 PM PDT 24
Peak memory 223980 kb
Host smart-e76e320a-f70a-401b-85e2-4fc82e99b0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692238561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.692238561
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.502345677
Short name T592
Test name
Test status
Simulation time 231714369 ps
CPU time 5.38 seconds
Started Aug 14 05:28:10 PM PDT 24
Finished Aug 14 05:28:15 PM PDT 24
Peak memory 220376 kb
Host smart-9da5e6d0-5386-4522-8c30-bedb9065a3d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=502345677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.502345677
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.4017214958
Short name T995
Test name
Test status
Simulation time 38792595 ps
CPU time 0.92 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:28:10 PM PDT 24
Peak memory 206612 kb
Host smart-35cc67fa-1ee9-43da-89ae-72b614ecbd80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017214958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.4017214958
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4149956904
Short name T470
Test name
Test status
Simulation time 27252558684 ps
CPU time 28.13 seconds
Started Aug 14 05:28:10 PM PDT 24
Finished Aug 14 05:28:39 PM PDT 24
Peak memory 217604 kb
Host smart-7a101e79-d6e8-46e3-91b3-da370c9d13c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149956904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4149956904
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3457040439
Short name T631
Test name
Test status
Simulation time 755295189 ps
CPU time 2.26 seconds
Started Aug 14 05:28:12 PM PDT 24
Finished Aug 14 05:28:14 PM PDT 24
Peak memory 216416 kb
Host smart-da190e10-6f2e-43d0-aeb6-9af6ef38f026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457040439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3457040439
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2316683217
Short name T791
Test name
Test status
Simulation time 55908841 ps
CPU time 0.86 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:28:12 PM PDT 24
Peak memory 206148 kb
Host smart-642d1595-84cb-4b26-97c1-07181019f05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316683217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2316683217
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3667970054
Short name T700
Test name
Test status
Simulation time 123559361 ps
CPU time 0.77 seconds
Started Aug 14 05:28:21 PM PDT 24
Finished Aug 14 05:28:22 PM PDT 24
Peak memory 206168 kb
Host smart-8e8dd075-3a04-4f3b-a96d-3c705171428e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667970054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3667970054
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2160373681
Short name T814
Test name
Test status
Simulation time 9535577129 ps
CPU time 9.46 seconds
Started Aug 14 05:28:08 PM PDT 24
Finished Aug 14 05:28:18 PM PDT 24
Peak memory 232956 kb
Host smart-196907f3-44e5-4556-8f61-76786100eb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160373681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2160373681
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1658651233
Short name T714
Test name
Test status
Simulation time 24535266 ps
CPU time 0.73 seconds
Started Aug 14 05:28:17 PM PDT 24
Finished Aug 14 05:28:18 PM PDT 24
Peak memory 204956 kb
Host smart-3e293ffa-7231-4886-a418-c4ed369c8ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658651233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1658651233
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3794882865
Short name T232
Test name
Test status
Simulation time 334924280 ps
CPU time 4.79 seconds
Started Aug 14 05:28:21 PM PDT 24
Finished Aug 14 05:28:26 PM PDT 24
Peak memory 224728 kb
Host smart-2cc9666b-f5b3-4940-b7b3-7b9ebd490e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794882865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3794882865
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3435942345
Short name T799
Test name
Test status
Simulation time 21991047 ps
CPU time 0.81 seconds
Started Aug 14 05:28:18 PM PDT 24
Finished Aug 14 05:28:19 PM PDT 24
Peak memory 206560 kb
Host smart-be99b3ea-e38e-48d4-80b2-eb8a2d18c18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435942345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3435942345
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3327195837
Short name T948
Test name
Test status
Simulation time 346365928 ps
CPU time 5.91 seconds
Started Aug 14 05:28:25 PM PDT 24
Finished Aug 14 05:28:31 PM PDT 24
Peak memory 224660 kb
Host smart-8bda183d-8648-4d21-b3f3-56522949765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327195837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3327195837
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1845298366
Short name T12
Test name
Test status
Simulation time 4185485462 ps
CPU time 35.46 seconds
Started Aug 14 05:28:17 PM PDT 24
Finished Aug 14 05:28:53 PM PDT 24
Peak memory 223872 kb
Host smart-385aaf73-88c1-4e04-8b69-7947f58fc0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845298366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1845298366
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.862170500
Short name T834
Test name
Test status
Simulation time 5830189311 ps
CPU time 58.39 seconds
Started Aug 14 05:28:21 PM PDT 24
Finished Aug 14 05:29:20 PM PDT 24
Peak memory 241256 kb
Host smart-aac54b31-35ab-40c7-af5f-216574830ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862170500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.862170500
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3642517635
Short name T426
Test name
Test status
Simulation time 2857594801 ps
CPU time 16.27 seconds
Started Aug 14 05:28:20 PM PDT 24
Finished Aug 14 05:28:36 PM PDT 24
Peak memory 232992 kb
Host smart-d021cdf0-bfee-4991-a172-10af9512e404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642517635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3642517635
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.833958128
Short name T673
Test name
Test status
Simulation time 20450247331 ps
CPU time 48.91 seconds
Started Aug 14 05:28:19 PM PDT 24
Finished Aug 14 05:29:08 PM PDT 24
Peak memory 249376 kb
Host smart-5cd964cf-afde-4223-b458-7a8046830677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833958128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.833958128
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.15883159
Short name T680
Test name
Test status
Simulation time 3053815836 ps
CPU time 29.38 seconds
Started Aug 14 05:28:25 PM PDT 24
Finished Aug 14 05:28:55 PM PDT 24
Peak memory 232924 kb
Host smart-a5e187d9-7d3f-4f5f-945e-a6ac6d67d8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15883159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.15883159
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4186882582
Short name T240
Test name
Test status
Simulation time 4706894878 ps
CPU time 41.42 seconds
Started Aug 14 05:28:18 PM PDT 24
Finished Aug 14 05:29:00 PM PDT 24
Peak memory 249340 kb
Host smart-dc04b639-bfff-4286-bbb9-4b2f9b0d78e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186882582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4186882582
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.896165130
Short name T221
Test name
Test status
Simulation time 993428430 ps
CPU time 7.35 seconds
Started Aug 14 05:28:18 PM PDT 24
Finished Aug 14 05:28:25 PM PDT 24
Peak memory 224624 kb
Host smart-eb0c124d-2bd5-4f81-b08a-0c4f51a3d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896165130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.896165130
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1694687402
Short name T351
Test name
Test status
Simulation time 6952851642 ps
CPU time 19.7 seconds
Started Aug 14 05:28:10 PM PDT 24
Finished Aug 14 05:28:30 PM PDT 24
Peak memory 233056 kb
Host smart-0203a83e-2588-49bd-adde-f322f5eb9b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694687402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1694687402
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1175947360
Short name T622
Test name
Test status
Simulation time 57123998 ps
CPU time 3.14 seconds
Started Aug 14 05:28:18 PM PDT 24
Finished Aug 14 05:28:21 PM PDT 24
Peak memory 222732 kb
Host smart-c2850f15-888d-4af4-b427-efcdda6f899d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1175947360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1175947360
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1284005583
Short name T162
Test name
Test status
Simulation time 3397558379 ps
CPU time 39.24 seconds
Started Aug 14 05:28:31 PM PDT 24
Finished Aug 14 05:29:11 PM PDT 24
Peak memory 237980 kb
Host smart-3e6645ad-71d1-4a5b-9793-753a72e44eaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284005583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1284005583
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2300435602
Short name T552
Test name
Test status
Simulation time 63117159467 ps
CPU time 24.58 seconds
Started Aug 14 05:28:11 PM PDT 24
Finished Aug 14 05:28:35 PM PDT 24
Peak memory 216564 kb
Host smart-a6c951bf-bd65-42d3-94b3-61055c5e19c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300435602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2300435602
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1623132404
Short name T882
Test name
Test status
Simulation time 4087767012 ps
CPU time 9 seconds
Started Aug 14 05:28:09 PM PDT 24
Finished Aug 14 05:28:19 PM PDT 24
Peak memory 216604 kb
Host smart-719f9661-3e7d-4fe2-8fe2-afc9aa593d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623132404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1623132404
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1108054721
Short name T769
Test name
Test status
Simulation time 415116949 ps
CPU time 2.7 seconds
Started Aug 14 05:28:13 PM PDT 24
Finished Aug 14 05:28:16 PM PDT 24
Peak memory 216468 kb
Host smart-d783fb42-1060-4205-bd46-981553aba467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108054721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1108054721
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.64517590
Short name T539
Test name
Test status
Simulation time 25514095 ps
CPU time 0.76 seconds
Started Aug 14 05:28:20 PM PDT 24
Finished Aug 14 05:28:21 PM PDT 24
Peak memory 206024 kb
Host smart-76035e4c-5251-45f5-a8e6-42112e8dc592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64517590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.64517590
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4061603493
Short name T262
Test name
Test status
Simulation time 12655705703 ps
CPU time 14.41 seconds
Started Aug 14 05:28:28 PM PDT 24
Finished Aug 14 05:28:43 PM PDT 24
Peak memory 238844 kb
Host smart-76bce56e-90df-4f28-a0d5-b2f99c5a4166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061603493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4061603493
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.80286877
Short name T625
Test name
Test status
Simulation time 42572242 ps
CPU time 0.74 seconds
Started Aug 14 05:28:19 PM PDT 24
Finished Aug 14 05:28:20 PM PDT 24
Peak memory 205556 kb
Host smart-d766da19-fde9-48e6-9a35-fb419d250c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80286877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.80286877
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3249227267
Short name T79
Test name
Test status
Simulation time 185917538 ps
CPU time 3.09 seconds
Started Aug 14 05:28:19 PM PDT 24
Finished Aug 14 05:28:23 PM PDT 24
Peak memory 232820 kb
Host smart-c2ad7fa9-3a05-4b25-a91d-03798d375e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249227267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3249227267
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.689845542
Short name T647
Test name
Test status
Simulation time 41048607 ps
CPU time 0.78 seconds
Started Aug 14 05:28:18 PM PDT 24
Finished Aug 14 05:28:19 PM PDT 24
Peak memory 206972 kb
Host smart-3d838be9-10a5-46c8-bb80-e09e0fec53c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689845542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.689845542
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1268539245
Short name T225
Test name
Test status
Simulation time 103515980100 ps
CPU time 608.04 seconds
Started Aug 14 05:28:20 PM PDT 24
Finished Aug 14 05:38:28 PM PDT 24
Peak memory 268408 kb
Host smart-5bba59d7-0867-4289-afa0-333ff10639b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268539245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1268539245
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1553153092
Short name T457
Test name
Test status
Simulation time 2816871019 ps
CPU time 15.67 seconds
Started Aug 14 05:28:19 PM PDT 24
Finished Aug 14 05:28:35 PM PDT 24
Peak memory 233000 kb
Host smart-0e188f51-cac9-48ca-92e9-d889b79049f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553153092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1553153092
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2127049325
Short name T329
Test name
Test status
Simulation time 283691802 ps
CPU time 0.91 seconds
Started Aug 14 05:28:21 PM PDT 24
Finished Aug 14 05:28:22 PM PDT 24
Peak memory 217532 kb
Host smart-e01d758e-c713-44e9-aafc-fc89ceb193e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127049325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2127049325
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2283943265
Short name T697
Test name
Test status
Simulation time 18744336284 ps
CPU time 56.22 seconds
Started Aug 14 05:28:19 PM PDT 24
Finished Aug 14 05:29:15 PM PDT 24
Peak memory 232900 kb
Host smart-93840227-fe85-4790-bfb1-1adbaabd841f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283943265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2283943265
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1438162991
Short name T958
Test name
Test status
Simulation time 76841919 ps
CPU time 0.86 seconds
Started Aug 14 05:28:24 PM PDT 24
Finished Aug 14 05:28:25 PM PDT 24
Peak memory 216028 kb
Host smart-bce586fa-bf4b-49f8-887f-735db3cbaeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438162991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1438162991
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1911872556
Short name T905
Test name
Test status
Simulation time 24857784562 ps
CPU time 31.11 seconds
Started Aug 14 05:28:19 PM PDT 24
Finished Aug 14 05:28:51 PM PDT 24
Peak memory 224720 kb
Host smart-a2ae5355-479e-46f1-b2bf-3fee865f3538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911872556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1911872556
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2453549544
Short name T459
Test name
Test status
Simulation time 1859029803 ps
CPU time 9.4 seconds
Started Aug 14 05:28:19 PM PDT 24
Finished Aug 14 05:28:29 PM PDT 24
Peak memory 236460 kb
Host smart-5a091f34-e0fc-4fcf-bd4e-86d425d20719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453549544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2453549544
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2979616206
Short name T988
Test name
Test status
Simulation time 1313374421 ps
CPU time 5.16 seconds
Started Aug 14 05:28:19 PM PDT 24
Finished Aug 14 05:28:24 PM PDT 24
Peak memory 224584 kb
Host smart-d6de83b3-faa7-42e3-8afe-a09b66f8fb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979616206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2979616206
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1340922152
Short name T593
Test name
Test status
Simulation time 10713550494 ps
CPU time 8.29 seconds
Started Aug 14 05:28:19 PM PDT 24
Finished Aug 14 05:28:27 PM PDT 24
Peak memory 232996 kb
Host smart-cb1c33aa-5c4b-4fa2-bd47-b5e2f8ceef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340922152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1340922152
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.751615920
Short name T688
Test name
Test status
Simulation time 1391094747 ps
CPU time 7.21 seconds
Started Aug 14 05:28:20 PM PDT 24
Finished Aug 14 05:28:27 PM PDT 24
Peak memory 222084 kb
Host smart-8ab16e79-1914-4463-97eb-13e1d5f67129
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=751615920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.751615920
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1089358575
Short name T276
Test name
Test status
Simulation time 217103071315 ps
CPU time 267.07 seconds
Started Aug 14 05:28:20 PM PDT 24
Finished Aug 14 05:32:47 PM PDT 24
Peak memory 256072 kb
Host smart-cbbf6f5a-f257-44fd-9ab8-904be4c7bffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089358575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1089358575
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.616063987
Short name T346
Test name
Test status
Simulation time 7416860059 ps
CPU time 41.48 seconds
Started Aug 14 05:28:28 PM PDT 24
Finished Aug 14 05:29:09 PM PDT 24
Peak memory 216580 kb
Host smart-809c5518-8519-4a78-8bd0-140ae8db967b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616063987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.616063987
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2213427885
Short name T858
Test name
Test status
Simulation time 399054573 ps
CPU time 1.67 seconds
Started Aug 14 05:28:19 PM PDT 24
Finished Aug 14 05:28:20 PM PDT 24
Peak memory 207336 kb
Host smart-620b0038-fe70-4cad-a243-b34c3f59f397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213427885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2213427885
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1835086275
Short name T1025
Test name
Test status
Simulation time 169009572 ps
CPU time 1.5 seconds
Started Aug 14 05:28:18 PM PDT 24
Finished Aug 14 05:28:20 PM PDT 24
Peak memory 216480 kb
Host smart-3175ea17-064a-49fb-b32d-821e9b24cc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835086275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1835086275
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1322302699
Short name T772
Test name
Test status
Simulation time 73703067 ps
CPU time 0.76 seconds
Started Aug 14 05:28:19 PM PDT 24
Finished Aug 14 05:28:20 PM PDT 24
Peak memory 206152 kb
Host smart-73087d67-60ca-4df5-83c5-47148fbbd51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322302699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1322302699
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.243046254
Short name T754
Test name
Test status
Simulation time 404313250 ps
CPU time 2.59 seconds
Started Aug 14 05:28:17 PM PDT 24
Finished Aug 14 05:28:19 PM PDT 24
Peak memory 224308 kb
Host smart-747fcc0f-b9e9-435e-8ad4-fe888f65667b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243046254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.243046254
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3109690526
Short name T897
Test name
Test status
Simulation time 20093319 ps
CPU time 0.72 seconds
Started Aug 14 05:28:34 PM PDT 24
Finished Aug 14 05:28:35 PM PDT 24
Peak memory 205552 kb
Host smart-e59ccc54-69fe-493e-a6f4-6d41d80b8b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109690526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3109690526
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2136925141
Short name T975
Test name
Test status
Simulation time 23309444497 ps
CPU time 22.35 seconds
Started Aug 14 05:28:30 PM PDT 24
Finished Aug 14 05:28:53 PM PDT 24
Peak memory 232996 kb
Host smart-de3fe9b9-061b-4d09-9753-08170617d564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136925141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2136925141
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1017820871
Short name T350
Test name
Test status
Simulation time 83648065 ps
CPU time 0.78 seconds
Started Aug 14 05:28:28 PM PDT 24
Finished Aug 14 05:28:29 PM PDT 24
Peak memory 206640 kb
Host smart-ee7a2b41-5ef1-44bb-971c-9ed632cb6d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017820871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1017820871
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2211249005
Short name T204
Test name
Test status
Simulation time 295284235151 ps
CPU time 140.11 seconds
Started Aug 14 05:28:26 PM PDT 24
Finished Aug 14 05:30:46 PM PDT 24
Peak memory 249356 kb
Host smart-420480b6-846e-4153-912e-8916354d209c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211249005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2211249005
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3073650919
Short name T983
Test name
Test status
Simulation time 2082635467 ps
CPU time 23.96 seconds
Started Aug 14 05:28:29 PM PDT 24
Finished Aug 14 05:28:53 PM PDT 24
Peak memory 217880 kb
Host smart-4548a003-c99f-47a1-b2b4-961a23773d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073650919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3073650919
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.4252674771
Short name T347
Test name
Test status
Simulation time 2446810837 ps
CPU time 7.49 seconds
Started Aug 14 05:28:27 PM PDT 24
Finished Aug 14 05:28:35 PM PDT 24
Peak memory 224784 kb
Host smart-3d4b1000-1a83-48b8-a391-9a277093cb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252674771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.4252674771
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3674881571
Short name T49
Test name
Test status
Simulation time 48565739432 ps
CPU time 101.72 seconds
Started Aug 14 05:28:26 PM PDT 24
Finished Aug 14 05:30:08 PM PDT 24
Peak memory 255416 kb
Host smart-18fbe7e6-5e90-48c6-b4a7-4a462d2053ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674881571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3674881571
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.959087048
Short name T672
Test name
Test status
Simulation time 567410676 ps
CPU time 7.96 seconds
Started Aug 14 05:28:27 PM PDT 24
Finished Aug 14 05:28:35 PM PDT 24
Peak memory 224728 kb
Host smart-7918160f-e7de-4dfc-9e8b-4a702396c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959087048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.959087048
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3512598121
Short name T140
Test name
Test status
Simulation time 18074078529 ps
CPU time 38.47 seconds
Started Aug 14 05:28:29 PM PDT 24
Finished Aug 14 05:29:07 PM PDT 24
Peak memory 224740 kb
Host smart-ec237788-2fb2-4d88-8fa3-b6de4b9f4435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512598121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3512598121
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2716404201
Short name T253
Test name
Test status
Simulation time 259145796 ps
CPU time 3.42 seconds
Started Aug 14 05:28:28 PM PDT 24
Finished Aug 14 05:28:31 PM PDT 24
Peak memory 232936 kb
Host smart-e0e11437-7e8f-4f3b-a5e8-5be75bc00892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716404201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2716404201
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2387001110
Short name T989
Test name
Test status
Simulation time 1484637187 ps
CPU time 4.04 seconds
Started Aug 14 05:28:27 PM PDT 24
Finished Aug 14 05:28:31 PM PDT 24
Peak memory 232912 kb
Host smart-995b88eb-9e11-40a3-8885-a5001d339001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387001110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2387001110
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.486687245
Short name T154
Test name
Test status
Simulation time 506783141 ps
CPU time 5.73 seconds
Started Aug 14 05:28:29 PM PDT 24
Finished Aug 14 05:28:34 PM PDT 24
Peak memory 220444 kb
Host smart-595cb9cb-03f8-4143-9d5a-32f95c16009c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=486687245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.486687245
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1270237215
Short name T609
Test name
Test status
Simulation time 4654794288 ps
CPU time 27.22 seconds
Started Aug 14 05:28:17 PM PDT 24
Finished Aug 14 05:28:44 PM PDT 24
Peak memory 216780 kb
Host smart-f56c5f2e-8a6b-429d-b5d9-9d617f228b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270237215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1270237215
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1971469043
Short name T645
Test name
Test status
Simulation time 5566130752 ps
CPU time 9 seconds
Started Aug 14 05:28:18 PM PDT 24
Finished Aug 14 05:28:27 PM PDT 24
Peak memory 216612 kb
Host smart-52adb832-31b3-40cc-bec4-e875b1c07fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971469043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1971469043
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1499914349
Short name T638
Test name
Test status
Simulation time 184445923 ps
CPU time 1.39 seconds
Started Aug 14 05:28:25 PM PDT 24
Finished Aug 14 05:28:26 PM PDT 24
Peak memory 216476 kb
Host smart-89d1d662-dbf6-4a27-bda6-6a77fa7d8a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499914349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1499914349
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.383458724
Short name T745
Test name
Test status
Simulation time 120626399 ps
CPU time 1.01 seconds
Started Aug 14 05:28:23 PM PDT 24
Finished Aug 14 05:28:25 PM PDT 24
Peak memory 206080 kb
Host smart-5fe6bcc3-854a-462d-a0ae-ed7b7a320718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383458724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.383458724
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1444623221
Short name T893
Test name
Test status
Simulation time 38154620 ps
CPU time 2.42 seconds
Started Aug 14 05:28:28 PM PDT 24
Finished Aug 14 05:28:30 PM PDT 24
Peak memory 232480 kb
Host smart-1f698f57-8091-4210-b434-b517230ee7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444623221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1444623221
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1359510272
Short name T24
Test name
Test status
Simulation time 23025981 ps
CPU time 0.76 seconds
Started Aug 14 05:28:39 PM PDT 24
Finished Aug 14 05:28:40 PM PDT 24
Peak memory 205020 kb
Host smart-599d1629-f03a-472d-bf46-61075091ec0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359510272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1359510272
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.542182039
Short name T372
Test name
Test status
Simulation time 2620414650 ps
CPU time 29.91 seconds
Started Aug 14 05:28:30 PM PDT 24
Finished Aug 14 05:29:00 PM PDT 24
Peak memory 232988 kb
Host smart-6eeac716-330b-433a-b8de-e7c4e70cced9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542182039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.542182039
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2721811254
Short name T544
Test name
Test status
Simulation time 54342510 ps
CPU time 0.77 seconds
Started Aug 14 05:28:27 PM PDT 24
Finished Aug 14 05:28:28 PM PDT 24
Peak memory 206980 kb
Host smart-51b653cc-f66a-4737-a9c6-17f4235c2ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721811254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2721811254
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.376017303
Short name T812
Test name
Test status
Simulation time 2037083915 ps
CPU time 5.96 seconds
Started Aug 14 05:28:37 PM PDT 24
Finished Aug 14 05:28:43 PM PDT 24
Peak memory 224732 kb
Host smart-824ae6bd-262d-42ac-ba2c-d6b3e7607dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376017303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.376017303
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3086069537
Short name T134
Test name
Test status
Simulation time 158167281952 ps
CPU time 316.17 seconds
Started Aug 14 05:28:37 PM PDT 24
Finished Aug 14 05:33:53 PM PDT 24
Peak memory 252492 kb
Host smart-6f7417f5-4fac-43a4-a2c6-7a676d3a5898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086069537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3086069537
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3706212087
Short name T249
Test name
Test status
Simulation time 91649483558 ps
CPU time 222.43 seconds
Started Aug 14 05:28:36 PM PDT 24
Finished Aug 14 05:32:18 PM PDT 24
Peak memory 237308 kb
Host smart-6c75b8a4-5bb7-4732-8c82-ea37be972517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706212087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3706212087
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1398563441
Short name T561
Test name
Test status
Simulation time 1467340243 ps
CPU time 4.54 seconds
Started Aug 14 05:28:26 PM PDT 24
Finished Aug 14 05:28:31 PM PDT 24
Peak memory 224704 kb
Host smart-beaf0103-1957-4595-b1ee-417cbbce68f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398563441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1398563441
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3857372135
Short name T290
Test name
Test status
Simulation time 55022104024 ps
CPU time 390.31 seconds
Started Aug 14 05:28:30 PM PDT 24
Finished Aug 14 05:35:00 PM PDT 24
Peak memory 263224 kb
Host smart-85dbc5ea-353f-46ef-82ab-658801f91be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857372135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3857372135
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.163400702
Short name T692
Test name
Test status
Simulation time 32534619 ps
CPU time 2.4 seconds
Started Aug 14 05:28:34 PM PDT 24
Finished Aug 14 05:28:37 PM PDT 24
Peak memory 232548 kb
Host smart-2f05d559-998f-4719-85cc-7c60939db5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163400702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.163400702
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4134685531
Short name T78
Test name
Test status
Simulation time 150088746339 ps
CPU time 63.78 seconds
Started Aug 14 05:28:28 PM PDT 24
Finished Aug 14 05:29:31 PM PDT 24
Peak memory 232988 kb
Host smart-a5122ecc-42b1-496f-a3db-10082a4481fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134685531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4134685531
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1106935539
Short name T898
Test name
Test status
Simulation time 20533130006 ps
CPU time 15.31 seconds
Started Aug 14 05:28:27 PM PDT 24
Finished Aug 14 05:28:42 PM PDT 24
Peak memory 234264 kb
Host smart-b642ea21-986b-4e18-9e63-7668c58c5d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106935539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1106935539
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2609509315
Short name T246
Test name
Test status
Simulation time 4110605298 ps
CPU time 9.86 seconds
Started Aug 14 05:28:28 PM PDT 24
Finished Aug 14 05:28:38 PM PDT 24
Peak memory 232944 kb
Host smart-de2d756e-070f-430a-95aa-aa648614a24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609509315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2609509315
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1808503201
Short name T761
Test name
Test status
Simulation time 592225868 ps
CPU time 5.42 seconds
Started Aug 14 05:28:28 PM PDT 24
Finished Aug 14 05:28:34 PM PDT 24
Peak memory 218764 kb
Host smart-6715044a-5926-423e-9a6f-2b99e9ff8391
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1808503201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1808503201
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1436859222
Short name T639
Test name
Test status
Simulation time 9056069807 ps
CPU time 95.82 seconds
Started Aug 14 05:28:39 PM PDT 24
Finished Aug 14 05:30:15 PM PDT 24
Peak memory 253684 kb
Host smart-911f2b69-e88b-4ca3-8607-5cecad483c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436859222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1436859222
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2042658008
Short name T878
Test name
Test status
Simulation time 3527119796 ps
CPU time 15.37 seconds
Started Aug 14 05:28:27 PM PDT 24
Finished Aug 14 05:28:43 PM PDT 24
Peak memory 220316 kb
Host smart-af8277ce-af27-4e0d-b11b-3b13669a17be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042658008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2042658008
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1429582239
Short name T562
Test name
Test status
Simulation time 340554129 ps
CPU time 2.28 seconds
Started Aug 14 05:28:26 PM PDT 24
Finished Aug 14 05:28:28 PM PDT 24
Peak memory 216480 kb
Host smart-3eb64c49-895a-45e6-afc2-27615fd7027a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429582239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1429582239
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1449926700
Short name T917
Test name
Test status
Simulation time 239847495 ps
CPU time 3.19 seconds
Started Aug 14 05:28:34 PM PDT 24
Finished Aug 14 05:28:38 PM PDT 24
Peak memory 216360 kb
Host smart-8fbd1a68-8418-456d-b1aa-87df80cd5026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449926700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1449926700
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.317765391
Short name T599
Test name
Test status
Simulation time 158728070 ps
CPU time 0.89 seconds
Started Aug 14 05:28:28 PM PDT 24
Finished Aug 14 05:28:30 PM PDT 24
Peak memory 206052 kb
Host smart-ee634939-9bd4-49c8-a773-7ce261357b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317765391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.317765391
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1865409014
Short name T572
Test name
Test status
Simulation time 4159130378 ps
CPU time 6.21 seconds
Started Aug 14 05:28:29 PM PDT 24
Finished Aug 14 05:28:35 PM PDT 24
Peak memory 218308 kb
Host smart-c9acc462-5b21-471f-a418-3fd4092d54ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865409014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1865409014
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3320060492
Short name T865
Test name
Test status
Simulation time 28558535 ps
CPU time 0.75 seconds
Started Aug 14 05:28:36 PM PDT 24
Finished Aug 14 05:28:37 PM PDT 24
Peak memory 205548 kb
Host smart-6a110c34-6c40-4e87-95f4-498bba948d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320060492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3320060492
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3655783150
Short name T527
Test name
Test status
Simulation time 214349143 ps
CPU time 2.78 seconds
Started Aug 14 05:28:39 PM PDT 24
Finished Aug 14 05:28:41 PM PDT 24
Peak memory 232908 kb
Host smart-ce12c27b-8070-4de4-b5fe-c511823ba113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655783150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3655783150
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.338785122
Short name T545
Test name
Test status
Simulation time 16982100 ps
CPU time 0.79 seconds
Started Aug 14 05:28:39 PM PDT 24
Finished Aug 14 05:28:40 PM PDT 24
Peak memory 206628 kb
Host smart-d9b985e9-90e2-422f-a65e-0bcdb96c134d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338785122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.338785122
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1697421765
Short name T880
Test name
Test status
Simulation time 74980439 ps
CPU time 0.76 seconds
Started Aug 14 05:28:39 PM PDT 24
Finished Aug 14 05:28:40 PM PDT 24
Peak memory 215892 kb
Host smart-afc340d8-998f-4f0d-a5ab-84e9309e3554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697421765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1697421765
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.4074884347
Short name T58
Test name
Test status
Simulation time 189882900707 ps
CPU time 444 seconds
Started Aug 14 05:28:37 PM PDT 24
Finished Aug 14 05:36:01 PM PDT 24
Peak memory 270528 kb
Host smart-d9c70b00-be32-462a-b5ff-edfc8a49519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074884347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.4074884347
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3452593024
Short name T775
Test name
Test status
Simulation time 5788899279 ps
CPU time 92.99 seconds
Started Aug 14 05:28:38 PM PDT 24
Finished Aug 14 05:30:11 PM PDT 24
Peak memory 255556 kb
Host smart-b90b32a9-ff3e-4bb2-a361-13249ea1ccaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452593024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3452593024
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2196048392
Short name T750
Test name
Test status
Simulation time 5791363526 ps
CPU time 13.12 seconds
Started Aug 14 05:28:35 PM PDT 24
Finished Aug 14 05:28:49 PM PDT 24
Peak memory 234000 kb
Host smart-b6961d0d-629c-448f-88bc-d4029057f8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196048392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2196048392
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.493198865
Short name T632
Test name
Test status
Simulation time 218311908 ps
CPU time 0.86 seconds
Started Aug 14 05:28:36 PM PDT 24
Finished Aug 14 05:28:37 PM PDT 24
Peak memory 216000 kb
Host smart-df4f4100-138c-447a-9d95-e2410b3bb6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493198865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.493198865
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1098099632
Short name T3
Test name
Test status
Simulation time 633388194 ps
CPU time 10.58 seconds
Started Aug 14 05:28:40 PM PDT 24
Finished Aug 14 05:28:51 PM PDT 24
Peak memory 224784 kb
Host smart-6d2d0f63-6543-4702-acdf-4005fa01d6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098099632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1098099632
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1464032863
Short name T1024
Test name
Test status
Simulation time 628928106 ps
CPU time 6.44 seconds
Started Aug 14 05:28:37 PM PDT 24
Finished Aug 14 05:28:44 PM PDT 24
Peak memory 224712 kb
Host smart-a172d6ac-fb29-4b96-86be-7908dfa67218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464032863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1464032863
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1394582520
Short name T135
Test name
Test status
Simulation time 103461473 ps
CPU time 2.73 seconds
Started Aug 14 05:28:37 PM PDT 24
Finished Aug 14 05:28:40 PM PDT 24
Peak memory 232460 kb
Host smart-01f5fd30-f24a-4b41-96e3-e62d6b561e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394582520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1394582520
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3111305302
Short name T689
Test name
Test status
Simulation time 6461393572 ps
CPU time 8.44 seconds
Started Aug 14 05:28:38 PM PDT 24
Finished Aug 14 05:28:47 PM PDT 24
Peak memory 237276 kb
Host smart-357366f6-4cf1-4bfb-84e1-dd0c6bcca62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111305302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3111305302
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.638410863
Short name T343
Test name
Test status
Simulation time 112930528 ps
CPU time 4.25 seconds
Started Aug 14 05:28:36 PM PDT 24
Finished Aug 14 05:28:41 PM PDT 24
Peak memory 223228 kb
Host smart-7d622e76-85d1-4b93-ab1c-51334b46c28d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=638410863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.638410863
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2310349741
Short name T20
Test name
Test status
Simulation time 72327355 ps
CPU time 1.18 seconds
Started Aug 14 05:28:38 PM PDT 24
Finished Aug 14 05:28:40 PM PDT 24
Peak memory 206924 kb
Host smart-0f6eabd8-a38d-418b-9385-0912fdbe7fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310349741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2310349741
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3276484799
Short name T30
Test name
Test status
Simulation time 6505292038 ps
CPU time 12.48 seconds
Started Aug 14 05:28:37 PM PDT 24
Finished Aug 14 05:28:49 PM PDT 24
Peak memory 216608 kb
Host smart-99542955-5e03-4210-a81e-3787992e83b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276484799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3276484799
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1334680896
Short name T848
Test name
Test status
Simulation time 365955985 ps
CPU time 2.57 seconds
Started Aug 14 05:28:38 PM PDT 24
Finished Aug 14 05:28:41 PM PDT 24
Peak memory 216544 kb
Host smart-04f9704e-db8a-4c26-bc97-b259f07e89c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334680896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1334680896
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3596654414
Short name T950
Test name
Test status
Simulation time 252659300 ps
CPU time 11.52 seconds
Started Aug 14 05:28:39 PM PDT 24
Finished Aug 14 05:28:50 PM PDT 24
Peak memory 216516 kb
Host smart-8394e885-f2e3-4aa5-8c94-d6ec757cff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596654414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3596654414
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3235002675
Short name T357
Test name
Test status
Simulation time 106077773 ps
CPU time 0.96 seconds
Started Aug 14 05:28:38 PM PDT 24
Finished Aug 14 05:28:39 PM PDT 24
Peak memory 206160 kb
Host smart-c8a871ac-8433-4a49-a2a9-02298764716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235002675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3235002675
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.919438903
Short name T532
Test name
Test status
Simulation time 2564566166 ps
CPU time 6.25 seconds
Started Aug 14 05:28:35 PM PDT 24
Finished Aug 14 05:28:41 PM PDT 24
Peak memory 224768 kb
Host smart-2badd253-3f33-4616-80b8-b2d1d74d0aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919438903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.919438903
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1759376131
Short name T939
Test name
Test status
Simulation time 13193485 ps
CPU time 0.69 seconds
Started Aug 14 05:28:46 PM PDT 24
Finished Aug 14 05:28:47 PM PDT 24
Peak memory 205904 kb
Host smart-dbfe86e5-f22f-49d9-9fe0-520667d2fe97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759376131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1759376131
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4054783772
Short name T475
Test name
Test status
Simulation time 3226578083 ps
CPU time 10.47 seconds
Started Aug 14 05:28:37 PM PDT 24
Finished Aug 14 05:28:48 PM PDT 24
Peak memory 232920 kb
Host smart-93c2a688-4cc4-4967-a420-e5104ada2347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054783772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4054783772
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2113781004
Short name T959
Test name
Test status
Simulation time 31558485 ps
CPU time 0.76 seconds
Started Aug 14 05:28:40 PM PDT 24
Finished Aug 14 05:28:40 PM PDT 24
Peak memory 206632 kb
Host smart-e1cfbf35-1e47-4fe1-bd6d-7324177d69c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113781004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2113781004
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3626465293
Short name T227
Test name
Test status
Simulation time 97642367327 ps
CPU time 179.94 seconds
Started Aug 14 05:28:48 PM PDT 24
Finished Aug 14 05:31:48 PM PDT 24
Peak memory 251732 kb
Host smart-b02712f0-130a-4448-93c7-b776a418527a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626465293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3626465293
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.837442537
Short name T766
Test name
Test status
Simulation time 143624426355 ps
CPU time 327.16 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:34:12 PM PDT 24
Peak memory 265240 kb
Host smart-20f6a3a0-122c-4e6c-a0f4-3d9cc71d5819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837442537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.837442537
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1215586138
Short name T567
Test name
Test status
Simulation time 3334115056 ps
CPU time 53.46 seconds
Started Aug 14 05:28:48 PM PDT 24
Finished Aug 14 05:29:41 PM PDT 24
Peak memory 256936 kb
Host smart-aacd4ddb-991a-4c4b-8078-76760012bb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215586138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1215586138
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1729166721
Short name T339
Test name
Test status
Simulation time 161629355 ps
CPU time 3.26 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:28:48 PM PDT 24
Peak memory 232940 kb
Host smart-b141427c-12b1-4fee-bae0-646082e62583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729166721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1729166721
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3252655602
Short name T488
Test name
Test status
Simulation time 5235920645 ps
CPU time 36.79 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:29:22 PM PDT 24
Peak memory 224788 kb
Host smart-5deb9aa4-cb65-4572-b8a7-2faf2899d743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252655602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3252655602
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3416925895
Short name T496
Test name
Test status
Simulation time 14966060344 ps
CPU time 6.92 seconds
Started Aug 14 05:28:37 PM PDT 24
Finished Aug 14 05:28:44 PM PDT 24
Peak memory 224696 kb
Host smart-a7231696-88b0-41b6-97aa-87f3eb3e3826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416925895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3416925895
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2787301046
Short name T872
Test name
Test status
Simulation time 1651482043 ps
CPU time 18.83 seconds
Started Aug 14 05:28:37 PM PDT 24
Finished Aug 14 05:28:56 PM PDT 24
Peak memory 232892 kb
Host smart-b29b0cff-0a15-4fc1-ad31-a6c7d7ea9aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787301046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2787301046
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2052197421
Short name T574
Test name
Test status
Simulation time 2350862681 ps
CPU time 3.97 seconds
Started Aug 14 05:28:34 PM PDT 24
Finished Aug 14 05:28:39 PM PDT 24
Peak memory 232988 kb
Host smart-a5dc3cca-9c7f-4b37-931f-5b3a2e799a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052197421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2052197421
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1989691933
Short name T397
Test name
Test status
Simulation time 9439224709 ps
CPU time 27.42 seconds
Started Aug 14 05:28:36 PM PDT 24
Finished Aug 14 05:29:03 PM PDT 24
Peak memory 240824 kb
Host smart-136ef91e-f204-4eb6-91ea-58ef5bd9f291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989691933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1989691933
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2979717643
Short name T405
Test name
Test status
Simulation time 2035011472 ps
CPU time 5.86 seconds
Started Aug 14 05:28:48 PM PDT 24
Finished Aug 14 05:28:54 PM PDT 24
Peak memory 220668 kb
Host smart-729e3fad-ff23-476f-ae7f-e268f844d319
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2979717643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2979717643
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.124534919
Short name T32
Test name
Test status
Simulation time 36279195368 ps
CPU time 123.01 seconds
Started Aug 14 05:28:43 PM PDT 24
Finished Aug 14 05:30:46 PM PDT 24
Peak memory 251772 kb
Host smart-94721bdc-1264-4e14-9b0b-1398d5e46134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124534919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.124534919
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3971623783
Short name T694
Test name
Test status
Simulation time 5047265554 ps
CPU time 29.73 seconds
Started Aug 14 05:28:39 PM PDT 24
Finished Aug 14 05:29:09 PM PDT 24
Peak memory 216664 kb
Host smart-de8e797a-b14b-4d7e-a79d-c5ae11ce4be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971623783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3971623783
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.738349160
Short name T331
Test name
Test status
Simulation time 11779074924 ps
CPU time 8.33 seconds
Started Aug 14 05:28:39 PM PDT 24
Finished Aug 14 05:28:47 PM PDT 24
Peak memory 216648 kb
Host smart-7bbe6e80-8d32-446b-a98d-9b659059c470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738349160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.738349160
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3774472554
Short name T311
Test name
Test status
Simulation time 183851737 ps
CPU time 1.73 seconds
Started Aug 14 05:28:39 PM PDT 24
Finished Aug 14 05:28:41 PM PDT 24
Peak memory 216528 kb
Host smart-e36f0ecc-a65a-4e0e-bf13-992d54a2509f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774472554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3774472554
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2737615339
Short name T462
Test name
Test status
Simulation time 137724491 ps
CPU time 0.8 seconds
Started Aug 14 05:28:37 PM PDT 24
Finished Aug 14 05:28:38 PM PDT 24
Peak memory 206124 kb
Host smart-fe93f323-fe56-47af-9608-dfcb6587ec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737615339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2737615339
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.697021176
Short name T11
Test name
Test status
Simulation time 120970491 ps
CPU time 3.59 seconds
Started Aug 14 05:28:39 PM PDT 24
Finished Aug 14 05:28:42 PM PDT 24
Peak memory 224756 kb
Host smart-c93db259-767a-4f06-96a6-6e3f2e4fce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697021176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.697021176
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2366051736
Short name T362
Test name
Test status
Simulation time 12466276 ps
CPU time 0.71 seconds
Started Aug 14 05:25:57 PM PDT 24
Finished Aug 14 05:25:58 PM PDT 24
Peak memory 204980 kb
Host smart-2dd4b1b6-891d-452c-833a-6641660f9b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366051736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
366051736
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1185753602
Short name T261
Test name
Test status
Simulation time 270309918 ps
CPU time 2.83 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:26:00 PM PDT 24
Peak memory 224708 kb
Host smart-c4f30d03-69cd-4032-a293-99de94d84b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185753602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1185753602
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1953871612
Short name T590
Test name
Test status
Simulation time 157285229 ps
CPU time 0.76 seconds
Started Aug 14 05:25:48 PM PDT 24
Finished Aug 14 05:25:49 PM PDT 24
Peak memory 206624 kb
Host smart-057db6c5-97a8-45b3-a791-aaed6a96174b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953871612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1953871612
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.275974442
Short name T793
Test name
Test status
Simulation time 79400703165 ps
CPU time 141.97 seconds
Started Aug 14 05:26:00 PM PDT 24
Finished Aug 14 05:28:23 PM PDT 24
Peak memory 253540 kb
Host smart-bfe239eb-99d8-4b70-8a25-d0876701e034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275974442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.275974442
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2398913358
Short name T1007
Test name
Test status
Simulation time 141076118157 ps
CPU time 281.93 seconds
Started Aug 14 05:25:57 PM PDT 24
Finished Aug 14 05:30:39 PM PDT 24
Peak memory 255196 kb
Host smart-bfb77101-90a0-47b2-9bde-6126e177594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398913358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2398913358
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1144049984
Short name T1009
Test name
Test status
Simulation time 2224553973 ps
CPU time 20.04 seconds
Started Aug 14 05:25:59 PM PDT 24
Finished Aug 14 05:26:19 PM PDT 24
Peak memory 236380 kb
Host smart-a59bd839-496d-4c30-8d44-8c844a4539a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144049984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1144049984
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3541186475
Short name T282
Test name
Test status
Simulation time 104454910389 ps
CPU time 374.05 seconds
Started Aug 14 05:26:00 PM PDT 24
Finished Aug 14 05:32:15 PM PDT 24
Peak memory 256928 kb
Host smart-21da9767-0915-46d5-8618-972f4a89e40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541186475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3541186475
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2844608009
Short name T518
Test name
Test status
Simulation time 12189041276 ps
CPU time 23.39 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:26:22 PM PDT 24
Peak memory 224716 kb
Host smart-8ee7f0bf-6f40-4a42-af56-2f9dce540d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844608009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2844608009
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3503963967
Short name T563
Test name
Test status
Simulation time 34754874130 ps
CPU time 80.19 seconds
Started Aug 14 05:25:57 PM PDT 24
Finished Aug 14 05:27:17 PM PDT 24
Peak memory 224744 kb
Host smart-001abe29-8c5c-4b9c-a7c2-0c3a86ccfc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503963967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3503963967
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1089770383
Short name T348
Test name
Test status
Simulation time 126848744 ps
CPU time 1.07 seconds
Started Aug 14 05:26:00 PM PDT 24
Finished Aug 14 05:26:01 PM PDT 24
Peak memory 216720 kb
Host smart-7323c177-4dcc-428a-a3d7-ff78082e3756
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089770383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1089770383
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1732023879
Short name T591
Test name
Test status
Simulation time 8086526929 ps
CPU time 25.07 seconds
Started Aug 14 05:26:04 PM PDT 24
Finished Aug 14 05:26:29 PM PDT 24
Peak memory 232928 kb
Host smart-a0e1c499-8e81-4875-bee0-73863f8d478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732023879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1732023879
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3377052489
Short name T759
Test name
Test status
Simulation time 92656579 ps
CPU time 2.24 seconds
Started Aug 14 05:26:00 PM PDT 24
Finished Aug 14 05:26:02 PM PDT 24
Peak memory 223924 kb
Host smart-d11f5c0c-6671-4ac2-ab2a-273489f9f924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377052489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3377052489
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3937008816
Short name T912
Test name
Test status
Simulation time 421741266 ps
CPU time 4.27 seconds
Started Aug 14 05:26:04 PM PDT 24
Finished Aug 14 05:26:08 PM PDT 24
Peak memory 223312 kb
Host smart-16a0aed4-8cc2-457e-9100-df8756b67ed0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3937008816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3937008816
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3554587278
Short name T72
Test name
Test status
Simulation time 37668461 ps
CPU time 0.96 seconds
Started Aug 14 05:26:00 PM PDT 24
Finished Aug 14 05:26:01 PM PDT 24
Peak memory 235564 kb
Host smart-d10fe429-e557-4c76-94c5-eb855b2fac24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554587278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3554587278
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2423441698
Short name T850
Test name
Test status
Simulation time 27198560822 ps
CPU time 280.58 seconds
Started Aug 14 05:25:59 PM PDT 24
Finished Aug 14 05:30:40 PM PDT 24
Peak memory 260808 kb
Host smart-dd8bcd4d-72b6-46e6-8928-a979cc88180f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423441698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2423441698
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3541437076
Short name T1016
Test name
Test status
Simulation time 12254517832 ps
CPU time 32.01 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:26:30 PM PDT 24
Peak memory 216856 kb
Host smart-3694f765-67ae-465d-9849-eb85b89e1656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541437076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3541437076
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.276167749
Short name T420
Test name
Test status
Simulation time 1448200839 ps
CPU time 9.66 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:26:08 PM PDT 24
Peak memory 216516 kb
Host smart-916aa604-82c8-4576-8415-60a24dc5a93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276167749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.276167749
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2304361347
Short name T556
Test name
Test status
Simulation time 19038439 ps
CPU time 1.09 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:25:59 PM PDT 24
Peak memory 208092 kb
Host smart-92812159-cbed-4288-b6be-0b4232a83b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304361347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2304361347
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1544390720
Short name T829
Test name
Test status
Simulation time 38658872 ps
CPU time 0.82 seconds
Started Aug 14 05:25:57 PM PDT 24
Finished Aug 14 05:25:58 PM PDT 24
Peak memory 206104 kb
Host smart-75e4ffdb-85d5-4451-b9cf-8ea2085983e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544390720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1544390720
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4104092373
Short name T231
Test name
Test status
Simulation time 103934349720 ps
CPU time 44.81 seconds
Started Aug 14 05:25:59 PM PDT 24
Finished Aug 14 05:26:44 PM PDT 24
Peak memory 249388 kb
Host smart-2efd176a-5c69-4cc6-aa91-6a7eac3d704b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104092373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4104092373
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.642729058
Short name T424
Test name
Test status
Simulation time 21320648 ps
CPU time 0.69 seconds
Started Aug 14 05:28:44 PM PDT 24
Finished Aug 14 05:28:45 PM PDT 24
Peak memory 205560 kb
Host smart-966ef585-2c06-41c4-98a5-d94fdbab35ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642729058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.642729058
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.524561486
Short name T934
Test name
Test status
Simulation time 67456248 ps
CPU time 2.52 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:28:48 PM PDT 24
Peak memory 232500 kb
Host smart-68ef6cc8-b7ac-4ea9-b306-c918036c92e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524561486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.524561486
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2107869966
Short name T980
Test name
Test status
Simulation time 16823384 ps
CPU time 0.77 seconds
Started Aug 14 05:28:46 PM PDT 24
Finished Aug 14 05:28:47 PM PDT 24
Peak memory 205612 kb
Host smart-70b4e7e2-4c67-49da-92bb-e71a70e13367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107869966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2107869966
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1194749403
Short name T966
Test name
Test status
Simulation time 1466860007 ps
CPU time 33.53 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:29:19 PM PDT 24
Peak memory 255040 kb
Host smart-8d5d7e9d-4282-4df9-8f78-21e2abf50ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194749403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1194749403
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3455007981
Short name T146
Test name
Test status
Simulation time 10783981030 ps
CPU time 168.01 seconds
Started Aug 14 05:28:49 PM PDT 24
Finished Aug 14 05:31:37 PM PDT 24
Peak memory 249628 kb
Host smart-7c853438-e177-4e50-b9d2-91ae7e88f255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455007981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3455007981
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2474199006
Short name T925
Test name
Test status
Simulation time 17311746517 ps
CPU time 93.9 seconds
Started Aug 14 05:28:47 PM PDT 24
Finished Aug 14 05:30:21 PM PDT 24
Peak memory 251852 kb
Host smart-d0a4315e-8c2a-46b0-8848-9e557ea9d437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474199006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2474199006
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1330034434
Short name T955
Test name
Test status
Simulation time 154442270 ps
CPU time 5.53 seconds
Started Aug 14 05:28:47 PM PDT 24
Finished Aug 14 05:28:53 PM PDT 24
Peak memory 224708 kb
Host smart-ca7ecd33-4d9f-4a5a-9c62-b20a5bd95c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330034434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1330034434
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1007490066
Short name T832
Test name
Test status
Simulation time 15025426834 ps
CPU time 19.37 seconds
Started Aug 14 05:28:46 PM PDT 24
Finished Aug 14 05:29:06 PM PDT 24
Peak memory 235188 kb
Host smart-a1fe001f-28bb-4d50-927e-02f091b79d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007490066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1007490066
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.33128668
Short name T228
Test name
Test status
Simulation time 93826747 ps
CPU time 2.8 seconds
Started Aug 14 05:28:47 PM PDT 24
Finished Aug 14 05:28:50 PM PDT 24
Peak memory 224672 kb
Host smart-9a26d32a-0cee-41e5-b7f1-f125a1727cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33128668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.33128668
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1045068515
Short name T773
Test name
Test status
Simulation time 8794923082 ps
CPU time 44.9 seconds
Started Aug 14 05:28:47 PM PDT 24
Finished Aug 14 05:29:32 PM PDT 24
Peak memory 240680 kb
Host smart-049df90e-0656-4dba-bc64-a99a815b216e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045068515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1045068515
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1721849746
Short name T725
Test name
Test status
Simulation time 942325429 ps
CPU time 6.78 seconds
Started Aug 14 05:28:44 PM PDT 24
Finished Aug 14 05:28:51 PM PDT 24
Peak memory 224684 kb
Host smart-c5abed80-8eb3-4141-ba8a-a6c9c542ce42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721849746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1721849746
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.562068804
Short name T587
Test name
Test status
Simulation time 4965520298 ps
CPU time 7.41 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:28:53 PM PDT 24
Peak memory 224708 kb
Host smart-d9164208-0450-4dc8-aff9-3dbc1db6f038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562068804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.562068804
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.472275277
Short name T999
Test name
Test status
Simulation time 798257001 ps
CPU time 4.53 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:28:50 PM PDT 24
Peak memory 222832 kb
Host smart-66a8fc29-c456-473e-97f5-a0adfe3cc305
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=472275277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.472275277
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2080383987
Short name T19
Test name
Test status
Simulation time 6168036002 ps
CPU time 41.78 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:29:27 PM PDT 24
Peak memory 249416 kb
Host smart-64f4f545-3af9-4134-b27e-67b868e466d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080383987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2080383987
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1933785223
Short name T628
Test name
Test status
Simulation time 2897209287 ps
CPU time 28.41 seconds
Started Aug 14 05:28:47 PM PDT 24
Finished Aug 14 05:29:16 PM PDT 24
Peak memory 216884 kb
Host smart-bd44cae7-3e3c-4e60-af21-bdf3cdac76ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933785223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1933785223
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4089935938
Short name T686
Test name
Test status
Simulation time 240349538 ps
CPU time 1.42 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:28:46 PM PDT 24
Peak memory 207204 kb
Host smart-5924c34f-3f66-4c41-8ed3-e2f4ec879ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089935938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4089935938
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1243108424
Short name T411
Test name
Test status
Simulation time 15327022 ps
CPU time 0.83 seconds
Started Aug 14 05:28:46 PM PDT 24
Finished Aug 14 05:28:47 PM PDT 24
Peak memory 206112 kb
Host smart-96b5223b-9bd4-40f8-a0a9-e6b39dcc003c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243108424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1243108424
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.116249881
Short name T330
Test name
Test status
Simulation time 361634020 ps
CPU time 0.97 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:28:46 PM PDT 24
Peak memory 206500 kb
Host smart-82d6d539-0a3a-47f7-8511-aab12a7da2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116249881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.116249881
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1366304384
Short name T241
Test name
Test status
Simulation time 744491423 ps
CPU time 6.41 seconds
Started Aug 14 05:28:46 PM PDT 24
Finished Aug 14 05:28:53 PM PDT 24
Peak memory 224664 kb
Host smart-e1a7f65d-11be-4729-9af2-d2987cfe4da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366304384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1366304384
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1930095887
Short name T550
Test name
Test status
Simulation time 30952540 ps
CPU time 0.68 seconds
Started Aug 14 05:28:57 PM PDT 24
Finished Aug 14 05:28:58 PM PDT 24
Peak memory 205504 kb
Host smart-bfb48377-dc60-4ea8-a412-1dc3e4c1b9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930095887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1930095887
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3762827633
Short name T535
Test name
Test status
Simulation time 1984086795 ps
CPU time 16.59 seconds
Started Aug 14 05:28:49 PM PDT 24
Finished Aug 14 05:29:06 PM PDT 24
Peak memory 224820 kb
Host smart-41bdcf6c-7f0c-4b18-9543-a07f9bce0c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762827633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3762827633
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3180203875
Short name T1017
Test name
Test status
Simulation time 41232617 ps
CPU time 0.78 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:28:46 PM PDT 24
Peak memory 206600 kb
Host smart-c7b4fe18-3100-41fe-bc4f-840a28aa6365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180203875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3180203875
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2857962140
Short name T67
Test name
Test status
Simulation time 10191333805 ps
CPU time 137.96 seconds
Started Aug 14 05:28:48 PM PDT 24
Finished Aug 14 05:31:06 PM PDT 24
Peak memory 254876 kb
Host smart-1db8eb31-a71a-4035-bd20-3d2674435e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857962140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2857962140
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.325443347
Short name T911
Test name
Test status
Simulation time 5068566009 ps
CPU time 27.23 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:29:23 PM PDT 24
Peak memory 241252 kb
Host smart-4b8565cf-764b-45cf-a5b0-8b5339484c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325443347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.325443347
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3008350035
Short name T497
Test name
Test status
Simulation time 232430349 ps
CPU time 4.75 seconds
Started Aug 14 05:28:44 PM PDT 24
Finished Aug 14 05:28:49 PM PDT 24
Peak memory 241108 kb
Host smart-f60c3707-86eb-428e-821a-367a21d327fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008350035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3008350035
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1375293550
Short name T62
Test name
Test status
Simulation time 1898860470 ps
CPU time 29.7 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:29:14 PM PDT 24
Peak memory 249288 kb
Host smart-22c1f478-e7d5-4f3c-b3f8-dcc96de28260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375293550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1375293550
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2934809666
Short name T783
Test name
Test status
Simulation time 5510237791 ps
CPU time 20.16 seconds
Started Aug 14 05:28:46 PM PDT 24
Finished Aug 14 05:29:06 PM PDT 24
Peak memory 232948 kb
Host smart-7b5f7738-6ea1-4544-be2c-f9da741e86e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934809666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2934809666
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2753441322
Short name T456
Test name
Test status
Simulation time 24936243821 ps
CPU time 40.59 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:29:26 PM PDT 24
Peak memory 240492 kb
Host smart-eccd0947-9450-4033-ba18-ba660dd3c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753441322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2753441322
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2439250478
Short name T780
Test name
Test status
Simulation time 7470680084 ps
CPU time 25.15 seconds
Started Aug 14 05:28:47 PM PDT 24
Finished Aug 14 05:29:12 PM PDT 24
Peak memory 232924 kb
Host smart-94fe61f3-4024-4159-a082-dd76606679dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439250478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2439250478
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2188781208
Short name T681
Test name
Test status
Simulation time 28081686 ps
CPU time 2.06 seconds
Started Aug 14 05:28:46 PM PDT 24
Finished Aug 14 05:28:48 PM PDT 24
Peak memory 223072 kb
Host smart-08c04d63-33c7-4325-9d68-a1b8d49c4330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188781208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2188781208
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2841128194
Short name T400
Test name
Test status
Simulation time 1498765959 ps
CPU time 9.33 seconds
Started Aug 14 05:28:45 PM PDT 24
Finished Aug 14 05:28:55 PM PDT 24
Peak memory 221096 kb
Host smart-f8b983b8-29e9-4049-8dc3-812c671dbfe1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2841128194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2841128194
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2776392905
Short name T166
Test name
Test status
Simulation time 1095557298 ps
CPU time 30.52 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:29:25 PM PDT 24
Peak memory 249644 kb
Host smart-4edd0021-e85a-4602-9322-aa8c3adf8c54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776392905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2776392905
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.315642644
Short name T945
Test name
Test status
Simulation time 5427201512 ps
CPU time 14.59 seconds
Started Aug 14 05:28:49 PM PDT 24
Finished Aug 14 05:29:04 PM PDT 24
Peak memory 220284 kb
Host smart-06189296-2df3-4864-9a13-58bcfb8b3c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315642644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.315642644
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.762529953
Short name T355
Test name
Test status
Simulation time 1392087670 ps
CPU time 5.6 seconds
Started Aug 14 05:28:46 PM PDT 24
Finished Aug 14 05:28:52 PM PDT 24
Peak memory 216508 kb
Host smart-ed8796a7-a473-420e-9286-eece5dfd66ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762529953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.762529953
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3990075309
Short name T409
Test name
Test status
Simulation time 106165975 ps
CPU time 1.51 seconds
Started Aug 14 05:28:47 PM PDT 24
Finished Aug 14 05:28:49 PM PDT 24
Peak memory 216512 kb
Host smart-c1fef604-091a-4265-9df6-620d1d9b6972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990075309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3990075309
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2900274870
Short name T742
Test name
Test status
Simulation time 63732857 ps
CPU time 0.82 seconds
Started Aug 14 05:28:44 PM PDT 24
Finished Aug 14 05:28:45 PM PDT 24
Peak memory 206136 kb
Host smart-737ca29c-d3f5-4b69-8a6c-58fbde783974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900274870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2900274870
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2948644022
Short name T385
Test name
Test status
Simulation time 1114512399 ps
CPU time 2.21 seconds
Started Aug 14 05:28:46 PM PDT 24
Finished Aug 14 05:28:49 PM PDT 24
Peak memory 223904 kb
Host smart-3271aa64-c500-4d37-85be-b6691aa250ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948644022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2948644022
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3695184513
Short name T327
Test name
Test status
Simulation time 13468147 ps
CPU time 0.7 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:28:54 PM PDT 24
Peak memory 205900 kb
Host smart-c984cbc4-7146-475d-8867-4cf242d4599a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695184513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3695184513
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3892014537
Short name T245
Test name
Test status
Simulation time 237681074 ps
CPU time 5.07 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:28:59 PM PDT 24
Peak memory 232860 kb
Host smart-9e960ca4-fa7e-4ae2-8e82-a790d1235af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892014537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3892014537
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.708581437
Short name T596
Test name
Test status
Simulation time 61863637 ps
CPU time 0.79 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:28:56 PM PDT 24
Peak memory 206632 kb
Host smart-6baed373-9e84-4ca3-88c2-edab8dc7515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708581437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.708581437
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3797927772
Short name T721
Test name
Test status
Simulation time 17509311025 ps
CPU time 30 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:29:25 PM PDT 24
Peak memory 224720 kb
Host smart-de3d5044-9864-47c6-ae7f-d0959e5ff296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797927772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3797927772
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3732129207
Short name T57
Test name
Test status
Simulation time 318075129974 ps
CPU time 341.74 seconds
Started Aug 14 05:28:58 PM PDT 24
Finished Aug 14 05:34:40 PM PDT 24
Peak memory 260444 kb
Host smart-acacc187-6523-49ba-b624-497ed0fa02ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732129207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3732129207
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1942330329
Short name T735
Test name
Test status
Simulation time 288815984 ps
CPU time 4.62 seconds
Started Aug 14 05:28:56 PM PDT 24
Finished Aug 14 05:29:00 PM PDT 24
Peak memory 232840 kb
Host smart-4a6f27a6-acc0-480b-8230-cf8227ca0983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942330329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1942330329
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3080099445
Short name T737
Test name
Test status
Simulation time 933275325 ps
CPU time 9.13 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:29:05 PM PDT 24
Peak memory 224728 kb
Host smart-82d258e9-a710-4394-bd4c-33be3af9adb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080099445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3080099445
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3447963005
Short name T798
Test name
Test status
Simulation time 75585916 ps
CPU time 2.31 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:28:56 PM PDT 24
Peak memory 224692 kb
Host smart-9d00bae6-06b6-4bb3-b5a1-3ec5a7798957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447963005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3447963005
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2277642633
Short name T677
Test name
Test status
Simulation time 48960128037 ps
CPU time 24.7 seconds
Started Aug 14 05:28:58 PM PDT 24
Finished Aug 14 05:29:22 PM PDT 24
Peak memory 232924 kb
Host smart-a1246244-f9d2-49c8-bb02-cdebc0e294fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277642633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2277642633
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1775365724
Short name T390
Test name
Test status
Simulation time 3978537575 ps
CPU time 13.68 seconds
Started Aug 14 05:28:58 PM PDT 24
Finished Aug 14 05:29:12 PM PDT 24
Peak memory 233060 kb
Host smart-1ecae552-d14c-4c55-9058-e849caaec714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775365724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1775365724
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.862026897
Short name T785
Test name
Test status
Simulation time 285267932 ps
CPU time 3.89 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:28:59 PM PDT 24
Peak memory 222624 kb
Host smart-4a78a9f4-3695-4857-a2d0-496e7eb7bf55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=862026897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.862026897
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4046767370
Short name T199
Test name
Test status
Simulation time 19342830829 ps
CPU time 70.56 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:30:05 PM PDT 24
Peak memory 254920 kb
Host smart-348b9fe5-d31e-41fa-bb2c-2bf1633aea04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046767370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4046767370
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1211833361
Short name T581
Test name
Test status
Simulation time 3256838232 ps
CPU time 36.39 seconds
Started Aug 14 05:28:58 PM PDT 24
Finished Aug 14 05:29:35 PM PDT 24
Peak memory 218712 kb
Host smart-8cdbd94b-340e-4d35-8858-af26f9d3f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211833361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1211833361
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1308519305
Short name T542
Test name
Test status
Simulation time 16795853132 ps
CPU time 13.7 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:29:09 PM PDT 24
Peak memory 216608 kb
Host smart-5b04b425-2c81-4b7e-9498-970143f0b402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308519305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1308519305
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1810452540
Short name T1013
Test name
Test status
Simulation time 27980030 ps
CPU time 0.86 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:28:55 PM PDT 24
Peak memory 206904 kb
Host smart-72dd72de-39cd-41e5-9a4f-60355e43f910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810452540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1810452540
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3783745941
Short name T588
Test name
Test status
Simulation time 21105594 ps
CPU time 0.81 seconds
Started Aug 14 05:28:58 PM PDT 24
Finished Aug 14 05:28:59 PM PDT 24
Peak memory 206228 kb
Host smart-b895dbc8-14c8-43a4-a4c4-b2a0cf74d02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783745941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3783745941
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.481046487
Short name T997
Test name
Test status
Simulation time 2490015842 ps
CPU time 4.96 seconds
Started Aug 14 05:28:56 PM PDT 24
Finished Aug 14 05:29:01 PM PDT 24
Peak memory 233016 kb
Host smart-6653da42-4466-4bac-91ce-928f5cf36ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481046487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.481046487
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3047479478
Short name T1001
Test name
Test status
Simulation time 46949166 ps
CPU time 0.75 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:28:55 PM PDT 24
Peak memory 205612 kb
Host smart-4b76c53a-15c8-465e-9457-80e35f619924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047479478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3047479478
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2566890561
Short name T461
Test name
Test status
Simulation time 885547331 ps
CPU time 10.2 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:29:04 PM PDT 24
Peak memory 224688 kb
Host smart-6b6d5127-9fd0-4930-8dfc-6ed9a23b3b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566890561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2566890561
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.163256263
Short name T767
Test name
Test status
Simulation time 79323876 ps
CPU time 0.83 seconds
Started Aug 14 05:28:52 PM PDT 24
Finished Aug 14 05:28:53 PM PDT 24
Peak memory 206636 kb
Host smart-beb767ac-0ce5-4628-952d-924f1c7b9f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163256263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.163256263
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.574837641
Short name T42
Test name
Test status
Simulation time 29754929745 ps
CPU time 79.04 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:30:14 PM PDT 24
Peak memory 251684 kb
Host smart-b77c8fbf-744b-4058-b40c-dfd81954a28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574837641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.574837641
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4239636690
Short name T412
Test name
Test status
Simulation time 1808210493 ps
CPU time 50.19 seconds
Started Aug 14 05:28:58 PM PDT 24
Finished Aug 14 05:29:49 PM PDT 24
Peak memory 254128 kb
Host smart-3835c9b5-3417-4cff-887a-132a1e18f176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239636690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4239636690
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1658603060
Short name T234
Test name
Test status
Simulation time 11165917743 ps
CPU time 160.87 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:31:35 PM PDT 24
Peak memory 262704 kb
Host smart-41b426aa-9f98-45d2-990f-0a8c0a25add6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658603060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1658603060
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.189750175
Short name T307
Test name
Test status
Simulation time 256782941 ps
CPU time 9.58 seconds
Started Aug 14 05:28:53 PM PDT 24
Finished Aug 14 05:29:03 PM PDT 24
Peak memory 232848 kb
Host smart-145c33c5-68cf-4e4d-8ce7-ff64606ff77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189750175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.189750175
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1722595146
Short name T93
Test name
Test status
Simulation time 4971254962 ps
CPU time 69.96 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:30:04 PM PDT 24
Peak memory 253276 kb
Host smart-72b7ea33-fb5f-40e8-ba57-a8d03116793e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722595146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1722595146
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3851705582
Short name T972
Test name
Test status
Simulation time 384620515 ps
CPU time 5.43 seconds
Started Aug 14 05:28:57 PM PDT 24
Finished Aug 14 05:29:02 PM PDT 24
Peak memory 224668 kb
Host smart-783c7423-4331-475f-86da-f47ec4160fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851705582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3851705582
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1533433638
Short name T941
Test name
Test status
Simulation time 3332830107 ps
CPU time 12.99 seconds
Started Aug 14 05:28:53 PM PDT 24
Finished Aug 14 05:29:06 PM PDT 24
Peak memory 233016 kb
Host smart-fe4a1072-d294-465a-a501-2f0ad60b75f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533433638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1533433638
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1247583379
Short name T342
Test name
Test status
Simulation time 6049467248 ps
CPU time 12.4 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:29:07 PM PDT 24
Peak memory 232952 kb
Host smart-7fc0a426-f935-411e-83e3-30663935c47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247583379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1247583379
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1737506921
Short name T585
Test name
Test status
Simulation time 887717928 ps
CPU time 3.78 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:28:59 PM PDT 24
Peak memory 232852 kb
Host smart-c5bc42e5-4c6c-4785-962a-7bfe490caafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737506921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1737506921
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2022922755
Short name T149
Test name
Test status
Simulation time 1655495159 ps
CPU time 5.91 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:29:01 PM PDT 24
Peak memory 222068 kb
Host smart-c7419e56-ca12-4f8c-9a30-e64d19a405a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2022922755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2022922755
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.249306538
Short name T818
Test name
Test status
Simulation time 682936307 ps
CPU time 9.48 seconds
Started Aug 14 05:28:57 PM PDT 24
Finished Aug 14 05:29:06 PM PDT 24
Peak memory 216132 kb
Host smart-a7b6f22d-2269-4360-ae76-ea208a2ad2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249306538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.249306538
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3609532122
Short name T547
Test name
Test status
Simulation time 1505781906 ps
CPU time 3.37 seconds
Started Aug 14 05:28:57 PM PDT 24
Finished Aug 14 05:29:00 PM PDT 24
Peak memory 216088 kb
Host smart-7238c398-74ac-463b-8e73-11c329de4a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609532122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3609532122
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3355261570
Short name T376
Test name
Test status
Simulation time 321814022 ps
CPU time 2.17 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:28:58 PM PDT 24
Peak memory 216336 kb
Host smart-56e093f7-a84a-47dd-aeeb-d8494c821208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355261570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3355261570
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3050517260
Short name T710
Test name
Test status
Simulation time 174655581 ps
CPU time 0.86 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:28:56 PM PDT 24
Peak memory 206104 kb
Host smart-4ea995bd-4cbf-4ede-a4ca-2f5601ee6672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050517260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3050517260
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.507443007
Short name T107
Test name
Test status
Simulation time 43194121 ps
CPU time 2.43 seconds
Started Aug 14 05:28:58 PM PDT 24
Finished Aug 14 05:29:01 PM PDT 24
Peak memory 232488 kb
Host smart-f88c9355-d9e5-4e5f-a383-b79a1fa29782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507443007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.507443007
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3322468417
Short name T553
Test name
Test status
Simulation time 21156088 ps
CPU time 0.71 seconds
Started Aug 14 05:29:06 PM PDT 24
Finished Aug 14 05:29:07 PM PDT 24
Peak memory 205580 kb
Host smart-da658a4b-782a-4461-9971-a2e6efb199a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322468417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3322468417
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.710353934
Short name T436
Test name
Test status
Simulation time 112196383 ps
CPU time 2.46 seconds
Started Aug 14 05:28:58 PM PDT 24
Finished Aug 14 05:29:01 PM PDT 24
Peak memory 232864 kb
Host smart-2d8fea6b-7d61-4633-be67-dcd3b333dd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710353934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.710353934
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2378831221
Short name T398
Test name
Test status
Simulation time 103137655 ps
CPU time 0.72 seconds
Started Aug 14 05:28:57 PM PDT 24
Finished Aug 14 05:28:58 PM PDT 24
Peak memory 206968 kb
Host smart-7ff1dfec-acbb-4541-a878-f35eaf4d204f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378831221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2378831221
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2204470666
Short name T743
Test name
Test status
Simulation time 2641041352 ps
CPU time 10.58 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:29:18 PM PDT 24
Peak memory 233952 kb
Host smart-ae2d2f2a-9fc9-45e9-a6a9-0c4b6b861e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204470666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2204470666
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2768873735
Short name T219
Test name
Test status
Simulation time 7608145648 ps
CPU time 74.92 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:30:19 PM PDT 24
Peak memory 238284 kb
Host smart-e327ba84-e3a6-4b7f-9596-1b3763c50f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768873735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2768873735
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3742741933
Short name T188
Test name
Test status
Simulation time 8984550074 ps
CPU time 95.14 seconds
Started Aug 14 05:29:02 PM PDT 24
Finished Aug 14 05:30:37 PM PDT 24
Peak memory 252272 kb
Host smart-53720d7c-6d53-4cc9-a846-b011350c3582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742741933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3742741933
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.997606612
Short name T809
Test name
Test status
Simulation time 3607913600 ps
CPU time 48.9 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:29:53 PM PDT 24
Peak memory 239736 kb
Host smart-07450e96-a3c9-4ba7-8993-b469463a14cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997606612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.997606612
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3041265285
Short name T919
Test name
Test status
Simulation time 676750599 ps
CPU time 4.45 seconds
Started Aug 14 05:28:54 PM PDT 24
Finished Aug 14 05:28:59 PM PDT 24
Peak memory 224652 kb
Host smart-d2b97472-8acc-46f1-9af3-511eef4c56e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041265285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3041265285
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1837310206
Short name T529
Test name
Test status
Simulation time 1486332197 ps
CPU time 11.52 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:29:07 PM PDT 24
Peak memory 232840 kb
Host smart-2b483799-75d2-497e-b6e5-bb02023a2daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837310206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1837310206
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.51693401
Short name T861
Test name
Test status
Simulation time 10811999733 ps
CPU time 16.79 seconds
Started Aug 14 05:28:56 PM PDT 24
Finished Aug 14 05:29:13 PM PDT 24
Peak memory 237332 kb
Host smart-c4198446-78d9-41ec-a432-eebd6e433b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51693401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.51693401
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2102588298
Short name T568
Test name
Test status
Simulation time 12136411883 ps
CPU time 25.11 seconds
Started Aug 14 05:28:57 PM PDT 24
Finished Aug 14 05:29:22 PM PDT 24
Peak memory 224668 kb
Host smart-ca97684b-c3a8-4462-9d2d-ad720621907f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102588298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2102588298
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2674212440
Short name T520
Test name
Test status
Simulation time 1704347748 ps
CPU time 20.62 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:29:28 PM PDT 24
Peak memory 223500 kb
Host smart-173671cc-d8dc-419f-953c-78db8c2ef32f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674212440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2674212440
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3026148813
Short name T1026
Test name
Test status
Simulation time 842918115 ps
CPU time 11.8 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:29:07 PM PDT 24
Peak memory 216532 kb
Host smart-5349dc47-5a6c-4cd6-8d5c-801745077dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026148813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3026148813
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3539122216
Short name T369
Test name
Test status
Simulation time 13519092732 ps
CPU time 11.74 seconds
Started Aug 14 05:28:53 PM PDT 24
Finished Aug 14 05:29:05 PM PDT 24
Peak memory 216524 kb
Host smart-567d09f3-8026-4fd2-bfff-8ce4fe661410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539122216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3539122216
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1635663265
Short name T584
Test name
Test status
Simulation time 1003820849 ps
CPU time 2.65 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:28:58 PM PDT 24
Peak memory 216528 kb
Host smart-46d3512f-3797-4c4d-96d3-2dd4a3ffde95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635663265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1635663265
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2571177848
Short name T668
Test name
Test status
Simulation time 129366613 ps
CPU time 1.05 seconds
Started Aug 14 05:28:53 PM PDT 24
Finished Aug 14 05:28:54 PM PDT 24
Peak memory 206572 kb
Host smart-fa7f7539-41d6-4893-8259-4e8fcd198b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571177848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2571177848
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2964365631
Short name T746
Test name
Test status
Simulation time 637276688 ps
CPU time 10.74 seconds
Started Aug 14 05:28:55 PM PDT 24
Finished Aug 14 05:29:06 PM PDT 24
Peak memory 250400 kb
Host smart-71bb34e5-26cc-4676-b438-a17e60f5df28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964365631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2964365631
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1757320693
Short name T794
Test name
Test status
Simulation time 36921942 ps
CPU time 0.73 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:29:08 PM PDT 24
Peak memory 205008 kb
Host smart-2a8ff439-49af-4a61-bf3c-dee95417ef96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757320693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1757320693
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1651374950
Short name T238
Test name
Test status
Simulation time 100888903 ps
CPU time 3.28 seconds
Started Aug 14 05:29:08 PM PDT 24
Finished Aug 14 05:29:11 PM PDT 24
Peak memory 224672 kb
Host smart-407c6e8a-b8e8-4adf-828e-0d95715858dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651374950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1651374950
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3841037027
Short name T729
Test name
Test status
Simulation time 13921334 ps
CPU time 0.75 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:29:08 PM PDT 24
Peak memory 206972 kb
Host smart-6283ad92-0fd5-422c-9499-1035c5d9d838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841037027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3841037027
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3738473486
Short name T218
Test name
Test status
Simulation time 171459209783 ps
CPU time 383.21 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:35:30 PM PDT 24
Peak memory 264640 kb
Host smart-2bc61ca1-d5a1-4781-87e0-b6c2f74e7ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738473486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3738473486
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1102494188
Short name T992
Test name
Test status
Simulation time 54339399301 ps
CPU time 166.12 seconds
Started Aug 14 05:29:06 PM PDT 24
Finished Aug 14 05:31:52 PM PDT 24
Peak memory 265820 kb
Host smart-b70128cf-2b26-4cfa-b796-deb7511012e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102494188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1102494188
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3308584653
Short name T223
Test name
Test status
Simulation time 20802998265 ps
CPU time 83.87 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:30:31 PM PDT 24
Peak memory 233032 kb
Host smart-8bfe435e-199c-4f49-ab46-4491cd8a5453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308584653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3308584653
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.989975703
Short name T224
Test name
Test status
Simulation time 4082539846 ps
CPU time 11.04 seconds
Started Aug 14 05:29:05 PM PDT 24
Finished Aug 14 05:29:16 PM PDT 24
Peak memory 224684 kb
Host smart-42051134-6d65-4ddd-84e6-b5fff6951a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989975703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.989975703
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2500314650
Short name T740
Test name
Test status
Simulation time 8589567447 ps
CPU time 96.8 seconds
Started Aug 14 05:29:05 PM PDT 24
Finished Aug 14 05:30:42 PM PDT 24
Peak memory 257508 kb
Host smart-0d3135fc-3da7-4e3b-aca9-64fcdf840c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500314650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2500314650
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3169917621
Short name T965
Test name
Test status
Simulation time 71864561 ps
CPU time 2.48 seconds
Started Aug 14 05:29:06 PM PDT 24
Finished Aug 14 05:29:09 PM PDT 24
Peak memory 224740 kb
Host smart-e41c3a5e-0919-4183-a0ed-b6914fba2c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169917621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3169917621
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2609630227
Short name T854
Test name
Test status
Simulation time 7159447655 ps
CPU time 50.92 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:29:55 PM PDT 24
Peak memory 248924 kb
Host smart-99749ad2-1272-419d-92ad-d9d66a030f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609630227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2609630227
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2721535453
Short name T942
Test name
Test status
Simulation time 1672132589 ps
CPU time 6.04 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:29:10 PM PDT 24
Peak memory 232820 kb
Host smart-f5f6d518-a9bc-4f27-82c4-b7ebd3c2763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721535453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2721535453
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2535116177
Short name T827
Test name
Test status
Simulation time 2882252122 ps
CPU time 7.44 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:29:11 PM PDT 24
Peak memory 232976 kb
Host smart-01fc4acb-14e3-4425-b459-e87d27be6844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535116177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2535116177
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2876478011
Short name T152
Test name
Test status
Simulation time 2846913419 ps
CPU time 6.18 seconds
Started Aug 14 05:29:03 PM PDT 24
Finished Aug 14 05:29:10 PM PDT 24
Peak memory 220816 kb
Host smart-d1c890a0-2fdd-4555-b36e-1f1cbd3ccaf5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2876478011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2876478011
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1511312144
Short name T867
Test name
Test status
Simulation time 14712206430 ps
CPU time 176.61 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:32:01 PM PDT 24
Peak memory 264776 kb
Host smart-922ff61e-259d-4d21-9d9b-45fe250cfdb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511312144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1511312144
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2311383782
Short name T352
Test name
Test status
Simulation time 1530371179 ps
CPU time 10.91 seconds
Started Aug 14 05:29:08 PM PDT 24
Finished Aug 14 05:29:19 PM PDT 24
Peak memory 219360 kb
Host smart-70ba77f5-44df-4b28-b9ec-2453ecf1c96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311383782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2311383782
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2879531230
Short name T667
Test name
Test status
Simulation time 247035305 ps
CPU time 1.03 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:29:05 PM PDT 24
Peak memory 207276 kb
Host smart-60ae30fa-be85-4928-beed-a23dc65b5abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879531230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2879531230
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2044204594
Short name T916
Test name
Test status
Simulation time 442293205 ps
CPU time 1.68 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:29:09 PM PDT 24
Peak memory 216492 kb
Host smart-099dd270-adc3-454a-a424-e142137bf2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044204594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2044204594
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2437902808
Short name T830
Test name
Test status
Simulation time 62851413 ps
CPU time 0.81 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:29:05 PM PDT 24
Peak memory 206168 kb
Host smart-d89a6a6b-8df9-4f7c-81dd-dc4c01cc4b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437902808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2437902808
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.550566716
Short name T206
Test name
Test status
Simulation time 398469869 ps
CPU time 3.1 seconds
Started Aug 14 05:29:06 PM PDT 24
Finished Aug 14 05:29:09 PM PDT 24
Peak memory 224700 kb
Host smart-93a8d787-d42e-4eb7-92f6-343f31360bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550566716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.550566716
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3097940756
Short name T831
Test name
Test status
Simulation time 16395302 ps
CPU time 0.72 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:29:05 PM PDT 24
Peak memory 205544 kb
Host smart-5ed687c5-d781-497a-8e14-7ca99c8e0b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097940756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3097940756
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.616309767
Short name T61
Test name
Test status
Simulation time 407590566 ps
CPU time 6.33 seconds
Started Aug 14 05:29:05 PM PDT 24
Finished Aug 14 05:29:12 PM PDT 24
Peak memory 232928 kb
Host smart-770338fa-458f-4b74-b8ea-8119c3afe92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616309767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.616309767
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1295076570
Short name T367
Test name
Test status
Simulation time 202266910 ps
CPU time 0.83 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:29:04 PM PDT 24
Peak memory 207004 kb
Host smart-870b0d3f-7d3c-43c7-9d74-49ed72df26c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295076570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1295076570
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.540636696
Short name T504
Test name
Test status
Simulation time 2987148796 ps
CPU time 39.13 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:29:46 PM PDT 24
Peak memory 250416 kb
Host smart-ac5436be-d2e0-42f2-b2ef-87652ac59394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540636696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.540636696
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2821004852
Short name T174
Test name
Test status
Simulation time 27462057743 ps
CPU time 104.14 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:30:48 PM PDT 24
Peak memory 249348 kb
Host smart-30f27130-6d35-4100-b35a-c31e2c51ad51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821004852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2821004852
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.499638880
Short name T60
Test name
Test status
Simulation time 152762633 ps
CPU time 5.86 seconds
Started Aug 14 05:29:08 PM PDT 24
Finished Aug 14 05:29:14 PM PDT 24
Peak memory 233960 kb
Host smart-f576bb05-993e-4c39-944e-d0db1afc6f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499638880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.499638880
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1093938551
Short name T634
Test name
Test status
Simulation time 8118509230 ps
CPU time 24.92 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:29:32 PM PDT 24
Peak memory 236564 kb
Host smart-15223549-c545-45a2-b5ce-ca72251cc339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093938551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1093938551
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.746776234
Short name T763
Test name
Test status
Simulation time 69894316 ps
CPU time 2.11 seconds
Started Aug 14 05:29:03 PM PDT 24
Finished Aug 14 05:29:05 PM PDT 24
Peak memory 224644 kb
Host smart-32fe4a68-fd14-452f-95f5-72a009caa4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746776234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.746776234
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2376187995
Short name T978
Test name
Test status
Simulation time 2302869844 ps
CPU time 24.21 seconds
Started Aug 14 05:29:03 PM PDT 24
Finished Aug 14 05:29:27 PM PDT 24
Peak memory 241176 kb
Host smart-236adc67-00ed-40e1-97a5-4077d0a10f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376187995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2376187995
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2359108367
Short name T517
Test name
Test status
Simulation time 186911849 ps
CPU time 2.4 seconds
Started Aug 14 05:29:05 PM PDT 24
Finished Aug 14 05:29:07 PM PDT 24
Peak memory 224592 kb
Host smart-665fd348-3d97-459c-9064-3e4fe925add9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359108367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2359108367
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1931671920
Short name T813
Test name
Test status
Simulation time 143883363145 ps
CPU time 37.08 seconds
Started Aug 14 05:29:06 PM PDT 24
Finished Aug 14 05:29:43 PM PDT 24
Peak memory 249336 kb
Host smart-7b2044c0-8053-40ac-bee1-38ece3b2c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931671920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1931671920
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2854173101
Short name T579
Test name
Test status
Simulation time 235357483 ps
CPU time 3.77 seconds
Started Aug 14 05:29:05 PM PDT 24
Finished Aug 14 05:29:09 PM PDT 24
Peak memory 223240 kb
Host smart-d47fc7d1-3885-4a41-8beb-a93f66a10e72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2854173101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2854173101
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.472044309
Short name T211
Test name
Test status
Simulation time 18185699910 ps
CPU time 91.58 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:30:39 PM PDT 24
Peak memory 265636 kb
Host smart-05ea82ef-afe0-45e9-a80f-839abf273918
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472044309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.472044309
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1413972191
Short name T926
Test name
Test status
Simulation time 1849436441 ps
CPU time 21.23 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:29:28 PM PDT 24
Peak memory 216768 kb
Host smart-d0c68def-f898-48eb-80c9-390ddcbf3d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413972191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1413972191
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3763449251
Short name T451
Test name
Test status
Simulation time 9761311019 ps
CPU time 3.97 seconds
Started Aug 14 05:29:08 PM PDT 24
Finished Aug 14 05:29:12 PM PDT 24
Peak memory 216612 kb
Host smart-2e328708-ce20-4624-b8c6-307f87927b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763449251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3763449251
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2321933045
Short name T536
Test name
Test status
Simulation time 117013884 ps
CPU time 2.53 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:29:07 PM PDT 24
Peak memory 216524 kb
Host smart-06316c98-4da3-4f3c-be79-7c078b1af2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321933045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2321933045
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1640581704
Short name T712
Test name
Test status
Simulation time 162091130 ps
CPU time 0.92 seconds
Started Aug 14 05:29:07 PM PDT 24
Finished Aug 14 05:29:08 PM PDT 24
Peak memory 206140 kb
Host smart-65fa9a9a-f1ab-48ed-a0b6-336145138fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640581704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1640581704
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3514195795
Short name T728
Test name
Test status
Simulation time 200183146 ps
CPU time 3.42 seconds
Started Aug 14 05:29:05 PM PDT 24
Finished Aug 14 05:29:09 PM PDT 24
Peak memory 230688 kb
Host smart-2f785e5f-0706-4c00-a9c4-8528e1baed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514195795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3514195795
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2764862189
Short name T435
Test name
Test status
Simulation time 27482838 ps
CPU time 0.7 seconds
Started Aug 14 05:29:14 PM PDT 24
Finished Aug 14 05:29:15 PM PDT 24
Peak memory 205564 kb
Host smart-a46dd79d-8d8d-4d26-9943-1a044fb3600c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764862189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2764862189
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2439010044
Short name T868
Test name
Test status
Simulation time 12051371328 ps
CPU time 12.71 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:29:26 PM PDT 24
Peak memory 232988 kb
Host smart-225436c1-e4d8-47fb-b297-e26f7cf415ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439010044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2439010044
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3943084153
Short name T724
Test name
Test status
Simulation time 94360384 ps
CPU time 0.78 seconds
Started Aug 14 05:29:08 PM PDT 24
Finished Aug 14 05:29:09 PM PDT 24
Peak memory 206632 kb
Host smart-4febfd7d-2d0b-4b52-af7b-3c8d70950b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943084153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3943084153
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.220369270
Short name T173
Test name
Test status
Simulation time 462236240 ps
CPU time 5.51 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:29:19 PM PDT 24
Peak memory 241112 kb
Host smart-09ae05f6-7ea4-4514-b72a-06e78436e6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220369270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.220369270
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2492294797
Short name T857
Test name
Test status
Simulation time 19229426073 ps
CPU time 204.08 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:32:38 PM PDT 24
Peak memory 256456 kb
Host smart-701638b5-a522-4020-9cb9-5f9892d66231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492294797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2492294797
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3986027435
Short name T866
Test name
Test status
Simulation time 4869160131 ps
CPU time 61.78 seconds
Started Aug 14 05:29:14 PM PDT 24
Finished Aug 14 05:30:16 PM PDT 24
Peak memory 249388 kb
Host smart-dcdd1fb2-3925-407c-aefc-f520f57be0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986027435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3986027435
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2267351390
Short name T996
Test name
Test status
Simulation time 2654191460 ps
CPU time 34.77 seconds
Started Aug 14 05:29:24 PM PDT 24
Finished Aug 14 05:29:59 PM PDT 24
Peak memory 238380 kb
Host smart-0a2c724f-2ad8-44e1-bfdf-fb413e1250e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267351390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2267351390
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2630071525
Short name T940
Test name
Test status
Simulation time 30344714598 ps
CPU time 205.67 seconds
Started Aug 14 05:29:24 PM PDT 24
Finished Aug 14 05:32:49 PM PDT 24
Peak memory 254424 kb
Host smart-b14ce0dd-d9b4-414a-bfd3-ee1f35e28108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630071525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2630071525
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1816730796
Short name T389
Test name
Test status
Simulation time 115629816 ps
CPU time 3.33 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:29:16 PM PDT 24
Peak memory 224676 kb
Host smart-194da85a-48ac-426d-b719-9d17af91678b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816730796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1816730796
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2542958023
Short name T265
Test name
Test status
Simulation time 9305869849 ps
CPU time 29.26 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:29:42 PM PDT 24
Peak memory 232848 kb
Host smart-dd0aebfb-b543-4fef-b862-abd9a862dac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542958023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2542958023
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1171046179
Short name T437
Test name
Test status
Simulation time 15171854117 ps
CPU time 11.03 seconds
Started Aug 14 05:29:12 PM PDT 24
Finished Aug 14 05:29:23 PM PDT 24
Peak memory 219076 kb
Host smart-780b5909-dd0f-4399-9cab-d4477a84e273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171046179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1171046179
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2961992747
Short name T602
Test name
Test status
Simulation time 841117141 ps
CPU time 11.94 seconds
Started Aug 14 05:29:14 PM PDT 24
Finished Aug 14 05:29:26 PM PDT 24
Peak memory 249268 kb
Host smart-7620d1d0-2000-4ffc-b442-20ac726d8f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961992747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2961992747
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3032818102
Short name T611
Test name
Test status
Simulation time 2622256442 ps
CPU time 11.99 seconds
Started Aug 14 05:29:12 PM PDT 24
Finished Aug 14 05:29:24 PM PDT 24
Peak memory 220428 kb
Host smart-8642a6b1-9ba5-4e4f-b210-c489884e7e42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3032818102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3032818102
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1393803471
Short name T1004
Test name
Test status
Simulation time 9237951798 ps
CPU time 108.82 seconds
Started Aug 14 05:29:15 PM PDT 24
Finished Aug 14 05:31:04 PM PDT 24
Peak memory 257396 kb
Host smart-5087805f-4090-4a61-9e9b-30de3ce80fd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393803471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1393803471
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4278437092
Short name T796
Test name
Test status
Simulation time 5793569021 ps
CPU time 35.64 seconds
Started Aug 14 05:29:05 PM PDT 24
Finished Aug 14 05:29:41 PM PDT 24
Peak memory 216580 kb
Host smart-6efaed47-c5ab-48c4-ac36-fd1382b48141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278437092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4278437092
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3867834641
Short name T77
Test name
Test status
Simulation time 927878827 ps
CPU time 5.54 seconds
Started Aug 14 05:29:03 PM PDT 24
Finished Aug 14 05:29:09 PM PDT 24
Peak memory 216448 kb
Host smart-5f867069-2f33-4b6b-9491-658cffa31265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867834641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3867834641
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2876090814
Short name T610
Test name
Test status
Simulation time 99258169 ps
CPU time 0.96 seconds
Started Aug 14 05:29:03 PM PDT 24
Finished Aug 14 05:29:04 PM PDT 24
Peak memory 206972 kb
Host smart-471d0854-f18e-4b74-a581-381b4dd13822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876090814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2876090814
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3698164311
Short name T489
Test name
Test status
Simulation time 106313050 ps
CPU time 0.82 seconds
Started Aug 14 05:29:04 PM PDT 24
Finished Aug 14 05:29:05 PM PDT 24
Peak memory 206156 kb
Host smart-4ce35ed3-1604-42b9-a0a6-623ebf879c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698164311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3698164311
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1889773778
Short name T404
Test name
Test status
Simulation time 177412408 ps
CPU time 2.43 seconds
Started Aug 14 05:29:12 PM PDT 24
Finished Aug 14 05:29:15 PM PDT 24
Peak memory 224312 kb
Host smart-073e806e-4d87-473f-82d9-160b1c1c2044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889773778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1889773778
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1714096180
Short name T370
Test name
Test status
Simulation time 10994606 ps
CPU time 0.72 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:29:14 PM PDT 24
Peak memory 205592 kb
Host smart-4871b531-4889-4ba8-bea7-f679e6cb7972
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714096180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1714096180
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1828479066
Short name T617
Test name
Test status
Simulation time 88228336 ps
CPU time 2.39 seconds
Started Aug 14 05:29:15 PM PDT 24
Finished Aug 14 05:29:17 PM PDT 24
Peak memory 224724 kb
Host smart-9b0509a6-9181-441c-bd50-1e05b70d4490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828479066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1828479066
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.103099040
Short name T575
Test name
Test status
Simulation time 17359487 ps
CPU time 0.78 seconds
Started Aug 14 05:29:25 PM PDT 24
Finished Aug 14 05:29:26 PM PDT 24
Peak memory 205640 kb
Host smart-bd358f40-21ef-4332-bca0-4788e9e21877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103099040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.103099040
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1607103508
Short name T651
Test name
Test status
Simulation time 21453591462 ps
CPU time 63.47 seconds
Started Aug 14 05:29:24 PM PDT 24
Finished Aug 14 05:30:28 PM PDT 24
Peak memory 250432 kb
Host smart-d862ec85-1475-4e89-b6c4-b7410012b1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607103508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1607103508
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3279583761
Short name T589
Test name
Test status
Simulation time 48929231996 ps
CPU time 47.02 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:30:00 PM PDT 24
Peak memory 251340 kb
Host smart-577bed04-af9d-49ea-bdf2-71fbffece6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279583761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3279583761
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1956456130
Short name T976
Test name
Test status
Simulation time 4570933105 ps
CPU time 7.27 seconds
Started Aug 14 05:29:12 PM PDT 24
Finished Aug 14 05:29:19 PM PDT 24
Peak memory 233016 kb
Host smart-f0e85b2b-be22-4ffc-8a43-a2f88ff6d7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956456130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1956456130
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3820890841
Short name T471
Test name
Test status
Simulation time 28647857898 ps
CPU time 54.17 seconds
Started Aug 14 05:29:14 PM PDT 24
Finished Aug 14 05:30:09 PM PDT 24
Peak memory 241208 kb
Host smart-da8d368d-c8e4-4783-8455-92b49dc73552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820890841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3820890841
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.478730079
Short name T137
Test name
Test status
Simulation time 3649922888 ps
CPU time 11.36 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:29:25 PM PDT 24
Peak memory 224728 kb
Host smart-709acace-4df9-49c7-9fdf-fc9b1b6ed698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478730079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.478730079
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1742643839
Short name T505
Test name
Test status
Simulation time 99202973 ps
CPU time 2.8 seconds
Started Aug 14 05:29:12 PM PDT 24
Finished Aug 14 05:29:15 PM PDT 24
Peak memory 224668 kb
Host smart-cb389b86-48eb-4ade-8be9-bb2f2ad2e272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742643839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1742643839
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2612402631
Short name T207
Test name
Test status
Simulation time 1613088127 ps
CPU time 8.76 seconds
Started Aug 14 05:29:10 PM PDT 24
Finished Aug 14 05:29:19 PM PDT 24
Peak memory 224708 kb
Host smart-8e71bee2-e560-4439-8135-cc7225d5861e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612402631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2612402631
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1070092314
Short name T1023
Test name
Test status
Simulation time 1035495638 ps
CPU time 5.57 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:29:19 PM PDT 24
Peak memory 232888 kb
Host smart-c6c5e213-9743-495a-910c-224ea82628d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070092314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1070092314
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1262676829
Short name T899
Test name
Test status
Simulation time 799452519 ps
CPU time 3.85 seconds
Started Aug 14 05:29:14 PM PDT 24
Finished Aug 14 05:29:18 PM PDT 24
Peak memory 223192 kb
Host smart-7e2fee21-6629-4733-af6c-74262c5347d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1262676829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1262676829
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.23075158
Short name T23
Test name
Test status
Simulation time 17087347695 ps
CPU time 41.5 seconds
Started Aug 14 05:29:15 PM PDT 24
Finished Aug 14 05:29:57 PM PDT 24
Peak memory 241080 kb
Host smart-9425953a-d4c0-4c56-ab37-721632317721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23075158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress
_all.23075158
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.204150582
Short name T445
Test name
Test status
Simulation time 1515464963 ps
CPU time 8.48 seconds
Started Aug 14 05:29:24 PM PDT 24
Finished Aug 14 05:29:32 PM PDT 24
Peak memory 216496 kb
Host smart-7e7c965a-5043-486b-aca0-3fcbefa27b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204150582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.204150582
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3720947288
Short name T472
Test name
Test status
Simulation time 52600983 ps
CPU time 0.68 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:29:13 PM PDT 24
Peak memory 205760 kb
Host smart-73ed53ee-6e82-4853-bacb-dbb289811500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720947288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3720947288
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3338397231
Short name T414
Test name
Test status
Simulation time 343369030 ps
CPU time 1.13 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:29:15 PM PDT 24
Peak memory 207184 kb
Host smart-21dda94b-e8e4-442b-83f1-288276709bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338397231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3338397231
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.795016966
Short name T573
Test name
Test status
Simulation time 22083483 ps
CPU time 0.74 seconds
Started Aug 14 05:29:11 PM PDT 24
Finished Aug 14 05:29:12 PM PDT 24
Peak memory 206128 kb
Host smart-7509865e-f106-49d0-9c73-5488da079b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795016966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.795016966
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2950220623
Short name T442
Test name
Test status
Simulation time 1077521467 ps
CPU time 4.31 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:29:18 PM PDT 24
Peak memory 224644 kb
Host smart-5c88ef71-97df-4abc-9c7a-0eee97d91190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950220623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2950220623
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2787391463
Short name T363
Test name
Test status
Simulation time 38118397 ps
CPU time 0.71 seconds
Started Aug 14 05:29:20 PM PDT 24
Finished Aug 14 05:29:21 PM PDT 24
Peak memory 205836 kb
Host smart-1fc9cc8e-9a76-4117-8d5e-4315c9b4a511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787391463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2787391463
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3085220232
Short name T908
Test name
Test status
Simulation time 284291156 ps
CPU time 2.17 seconds
Started Aug 14 05:29:21 PM PDT 24
Finished Aug 14 05:29:23 PM PDT 24
Peak memory 224656 kb
Host smart-e19061c8-4a44-433e-a07b-a2f752823d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085220232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3085220232
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3029939120
Short name T887
Test name
Test status
Simulation time 18456028 ps
CPU time 0.78 seconds
Started Aug 14 05:29:15 PM PDT 24
Finished Aug 14 05:29:16 PM PDT 24
Peak memory 205500 kb
Host smart-ce166fbf-a6d7-45a0-b5c0-89fc64486a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029939120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3029939120
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.756525431
Short name T171
Test name
Test status
Simulation time 1211209785 ps
CPU time 23.43 seconds
Started Aug 14 05:29:20 PM PDT 24
Finished Aug 14 05:29:44 PM PDT 24
Peak memory 239392 kb
Host smart-2585a79a-2917-475b-84fe-97ddabd090a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756525431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.756525431
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3293237068
Short name T55
Test name
Test status
Simulation time 26390306146 ps
CPU time 110.34 seconds
Started Aug 14 05:29:20 PM PDT 24
Finished Aug 14 05:31:11 PM PDT 24
Peak memory 250464 kb
Host smart-f13e7904-c015-40de-806c-addb5f6bd67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293237068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3293237068
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.479838876
Short name T251
Test name
Test status
Simulation time 69301191947 ps
CPU time 662.96 seconds
Started Aug 14 05:29:22 PM PDT 24
Finished Aug 14 05:40:26 PM PDT 24
Peak memory 263868 kb
Host smart-4752c2f3-e292-4bd1-836c-38f717e76913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479838876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.479838876
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1547081743
Short name T309
Test name
Test status
Simulation time 377202116 ps
CPU time 7.41 seconds
Started Aug 14 05:29:28 PM PDT 24
Finished Aug 14 05:29:35 PM PDT 24
Peak memory 224676 kb
Host smart-e1f0ee65-8f3c-4017-bbeb-3c7ff16e8608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547081743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1547081743
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.196456157
Short name T519
Test name
Test status
Simulation time 12639837828 ps
CPU time 68.43 seconds
Started Aug 14 05:29:19 PM PDT 24
Finished Aug 14 05:30:28 PM PDT 24
Peak memory 250832 kb
Host smart-0fbb0806-c2f3-4d4c-b9a8-4cb77a236107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196456157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.196456157
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2846811475
Short name T220
Test name
Test status
Simulation time 740134690 ps
CPU time 7.97 seconds
Started Aug 14 05:29:20 PM PDT 24
Finished Aug 14 05:29:28 PM PDT 24
Peak memory 224676 kb
Host smart-4cf005a3-1d8f-49d2-8aac-ee4552d02d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846811475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2846811475
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1852354463
Short name T521
Test name
Test status
Simulation time 6601025158 ps
CPU time 18.78 seconds
Started Aug 14 05:29:20 PM PDT 24
Finished Aug 14 05:29:38 PM PDT 24
Peak memory 234580 kb
Host smart-7fb5b0bd-d5a6-4d43-b8fe-1941c1b6cd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852354463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1852354463
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4221516591
Short name T915
Test name
Test status
Simulation time 877364198 ps
CPU time 4.4 seconds
Started Aug 14 05:29:21 PM PDT 24
Finished Aug 14 05:29:25 PM PDT 24
Peak memory 224624 kb
Host smart-4b96335c-eb55-4293-8401-65aa3be280a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221516591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4221516591
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1451982447
Short name T259
Test name
Test status
Simulation time 2095408160 ps
CPU time 7.89 seconds
Started Aug 14 05:29:22 PM PDT 24
Finished Aug 14 05:29:30 PM PDT 24
Peak memory 232844 kb
Host smart-da40bd01-3471-4b4d-963f-c6ff233f2ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451982447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1451982447
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2687958847
Short name T644
Test name
Test status
Simulation time 989613748 ps
CPU time 11.39 seconds
Started Aug 14 05:29:20 PM PDT 24
Finished Aug 14 05:29:31 PM PDT 24
Peak memory 221620 kb
Host smart-2de0d163-3be8-4af6-a0de-4fc96fe91203
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2687958847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2687958847
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1810420552
Short name T1014
Test name
Test status
Simulation time 1354433805 ps
CPU time 16.04 seconds
Started Aug 14 05:29:15 PM PDT 24
Finished Aug 14 05:29:31 PM PDT 24
Peak memory 216660 kb
Host smart-cac4f631-3f92-43b7-99f8-94e8152a14ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810420552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1810420552
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.681368516
Short name T764
Test name
Test status
Simulation time 3060904539 ps
CPU time 3.58 seconds
Started Aug 14 05:29:14 PM PDT 24
Finished Aug 14 05:29:18 PM PDT 24
Peak memory 216592 kb
Host smart-27ad404e-ac93-4744-b226-2ff854500189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681368516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.681368516
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.602436848
Short name T142
Test name
Test status
Simulation time 175177503 ps
CPU time 1.11 seconds
Started Aug 14 05:29:13 PM PDT 24
Finished Aug 14 05:29:14 PM PDT 24
Peak memory 207276 kb
Host smart-fd18bee3-d967-4375-91fd-d2f5d3fb5179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602436848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.602436848
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3659746368
Short name T354
Test name
Test status
Simulation time 1226403441 ps
CPU time 0.92 seconds
Started Aug 14 05:29:24 PM PDT 24
Finished Aug 14 05:29:25 PM PDT 24
Peak memory 206152 kb
Host smart-f50beed8-e6e5-41e3-b2e5-4a7a1aec18d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659746368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3659746368
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3666269178
Short name T502
Test name
Test status
Simulation time 438900970 ps
CPU time 3.84 seconds
Started Aug 14 05:29:20 PM PDT 24
Finished Aug 14 05:29:24 PM PDT 24
Peak memory 224736 kb
Host smart-2d93702e-6b12-41ba-93b5-3daa589b789f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666269178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3666269178
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3829170151
Short name T896
Test name
Test status
Simulation time 27677387 ps
CPU time 0.72 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:26:09 PM PDT 24
Peak memory 204980 kb
Host smart-c124a9b1-eae6-4348-9f8e-e205fae6d686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829170151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
829170151
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.886000329
Short name T187
Test name
Test status
Simulation time 1573569054 ps
CPU time 6 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:26:04 PM PDT 24
Peak memory 224656 kb
Host smart-689a4862-6b0c-4a82-a715-4d5e7b139301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886000329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.886000329
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2273692554
Short name T620
Test name
Test status
Simulation time 196881464 ps
CPU time 0.77 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:25:59 PM PDT 24
Peak memory 205684 kb
Host smart-ad694939-d6f5-452c-9f3f-7beb8673c60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273692554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2273692554
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.89306543
Short name T56
Test name
Test status
Simulation time 23198244018 ps
CPU time 73.45 seconds
Started Aug 14 05:26:14 PM PDT 24
Finished Aug 14 05:27:27 PM PDT 24
Peak memory 252664 kb
Host smart-237cd768-a83c-43ca-a5f6-9481548d5b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89306543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.89306543
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4104882682
Short name T189
Test name
Test status
Simulation time 49199787035 ps
CPU time 438.08 seconds
Started Aug 14 05:26:14 PM PDT 24
Finished Aug 14 05:33:32 PM PDT 24
Peak memory 256892 kb
Host smart-1ec9bbc4-ef90-4136-80a0-7160e86e1dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104882682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4104882682
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1795905079
Short name T344
Test name
Test status
Simulation time 6031472896 ps
CPU time 26.13 seconds
Started Aug 14 05:26:04 PM PDT 24
Finished Aug 14 05:26:30 PM PDT 24
Peak memory 232992 kb
Host smart-46f63a97-199c-46b7-bf27-5e8f379e69c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795905079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1795905079
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.926462793
Short name T548
Test name
Test status
Simulation time 290105216 ps
CPU time 3.33 seconds
Started Aug 14 05:26:00 PM PDT 24
Finished Aug 14 05:26:04 PM PDT 24
Peak memory 232900 kb
Host smart-55c43648-4ed0-42ba-9ac2-c371c9f8bb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926462793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.926462793
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3198211708
Short name T864
Test name
Test status
Simulation time 1935578224 ps
CPU time 11.64 seconds
Started Aug 14 05:26:04 PM PDT 24
Finished Aug 14 05:26:16 PM PDT 24
Peak memory 232868 kb
Host smart-daedac96-6449-4b23-82e5-145b40938b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198211708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3198211708
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.4289068662
Short name T421
Test name
Test status
Simulation time 26704835 ps
CPU time 0.98 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:25:59 PM PDT 24
Peak memory 218008 kb
Host smart-e615362c-1bcb-461c-b688-842b3c79417d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289068662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.4289068662
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1982087704
Short name T968
Test name
Test status
Simulation time 770128988 ps
CPU time 7.7 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:26:06 PM PDT 24
Peak memory 249304 kb
Host smart-8a8b1a5b-bfb6-4e06-a46c-838e83e83fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982087704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1982087704
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3127720843
Short name T727
Test name
Test status
Simulation time 1346125856 ps
CPU time 8.64 seconds
Started Aug 14 05:25:59 PM PDT 24
Finished Aug 14 05:26:08 PM PDT 24
Peak memory 249340 kb
Host smart-9914b5d5-0721-4ea2-892e-3d561bbfa3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127720843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3127720843
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3325170420
Short name T661
Test name
Test status
Simulation time 2363547809 ps
CPU time 4.32 seconds
Started Aug 14 05:26:07 PM PDT 24
Finished Aug 14 05:26:11 PM PDT 24
Peak memory 220560 kb
Host smart-bac7750a-0bc5-4c7f-b98f-c10dbcd7ecac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3325170420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3325170420
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3319236633
Short name T163
Test name
Test status
Simulation time 19214525464 ps
CPU time 193.47 seconds
Started Aug 14 05:26:09 PM PDT 24
Finished Aug 14 05:29:23 PM PDT 24
Peak memory 265836 kb
Host smart-eaaff7e9-81c2-42c5-b360-d7a891166373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319236633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3319236633
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2656273261
Short name T808
Test name
Test status
Simulation time 21387503 ps
CPU time 0.7 seconds
Started Aug 14 05:25:57 PM PDT 24
Finished Aug 14 05:25:58 PM PDT 24
Peak memory 205756 kb
Host smart-4a12a90f-3c0c-43ff-b15e-c150dd399518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656273261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2656273261
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3663855718
Short name T25
Test name
Test status
Simulation time 3186591699 ps
CPU time 7.76 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:26:06 PM PDT 24
Peak memory 216516 kb
Host smart-a8aefa98-c973-42df-83f9-63709bb8fc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663855718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3663855718
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3074516679
Short name T606
Test name
Test status
Simulation time 51796727 ps
CPU time 1.22 seconds
Started Aug 14 05:25:58 PM PDT 24
Finished Aug 14 05:26:00 PM PDT 24
Peak memory 208256 kb
Host smart-b2ee98bc-a768-418b-bb59-a6199c80ee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074516679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3074516679
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2900149489
Short name T66
Test name
Test status
Simulation time 156531506 ps
CPU time 0.83 seconds
Started Aug 14 05:25:59 PM PDT 24
Finished Aug 14 05:26:00 PM PDT 24
Peak memory 206132 kb
Host smart-eacbd784-67b9-40a9-8cac-0130a02874bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900149489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2900149489
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.219281623
Short name T208
Test name
Test status
Simulation time 9748691002 ps
CPU time 6.21 seconds
Started Aug 14 05:26:00 PM PDT 24
Finished Aug 14 05:26:07 PM PDT 24
Peak memory 232904 kb
Host smart-3f9286e9-32c4-4ba0-a775-572f79f4627b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219281623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.219281623
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1031613729
Short name T1
Test name
Test status
Simulation time 49491643 ps
CPU time 0.7 seconds
Started Aug 14 05:26:09 PM PDT 24
Finished Aug 14 05:26:09 PM PDT 24
Peak memory 205008 kb
Host smart-2045f734-6699-447d-bfc1-9920a8771be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031613729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
031613729
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3154141506
Short name T243
Test name
Test status
Simulation time 295428714 ps
CPU time 2.3 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:26:11 PM PDT 24
Peak memory 224660 kb
Host smart-9d5a125a-e25c-4b67-a51a-7a71a0236bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154141506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3154141506
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1599028649
Short name T907
Test name
Test status
Simulation time 53153578 ps
CPU time 0.78 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:26:09 PM PDT 24
Peak memory 205952 kb
Host smart-8c0f9e40-6b81-47d0-bc7f-7dd91ed5a015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599028649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1599028649
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2751897368
Short name T490
Test name
Test status
Simulation time 1240572584 ps
CPU time 25.59 seconds
Started Aug 14 05:26:15 PM PDT 24
Finished Aug 14 05:26:40 PM PDT 24
Peak memory 249324 kb
Host smart-630ada86-0b0c-44de-a457-1962641ed503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751897368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2751897368
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2316351159
Short name T601
Test name
Test status
Simulation time 15245713183 ps
CPU time 152.45 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:28:40 PM PDT 24
Peak memory 257600 kb
Host smart-691e2319-8166-44d7-8aa2-0b25f0250c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316351159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2316351159
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2042765071
Short name T212
Test name
Test status
Simulation time 6537839796 ps
CPU time 122.54 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:28:11 PM PDT 24
Peak memory 272392 kb
Host smart-508779aa-7b9b-4d68-a519-0f31b2f26e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042765071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2042765071
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3745251628
Short name T310
Test name
Test status
Simulation time 16357392702 ps
CPU time 23.72 seconds
Started Aug 14 05:26:07 PM PDT 24
Finished Aug 14 05:26:31 PM PDT 24
Peak memory 233020 kb
Host smart-9f501c0e-bc84-4c80-9fad-32df584d1c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745251628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3745251628
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.192093533
Short name T226
Test name
Test status
Simulation time 45427633216 ps
CPU time 335 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:31:43 PM PDT 24
Peak memory 273128 kb
Host smart-e503133d-ea87-4727-ace9-ff6ca79813b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192093533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
192093533
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1821564429
Short name T928
Test name
Test status
Simulation time 263638777 ps
CPU time 4.77 seconds
Started Aug 14 05:26:13 PM PDT 24
Finished Aug 14 05:26:18 PM PDT 24
Peak memory 232920 kb
Host smart-96d3b821-6cea-432d-bfcc-accba294e207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821564429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1821564429
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1904553712
Short name T637
Test name
Test status
Simulation time 888904639 ps
CPU time 12.93 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:26:21 PM PDT 24
Peak memory 224672 kb
Host smart-2028b7c0-7a54-4732-9805-9c85d37baaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904553712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1904553712
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3087132657
Short name T368
Test name
Test status
Simulation time 49837779 ps
CPU time 1.01 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:26:09 PM PDT 24
Peak memory 217992 kb
Host smart-a04093c8-0929-40df-8640-630a15d0721e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087132657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3087132657
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.654749457
Short name T787
Test name
Test status
Simulation time 2291852076 ps
CPU time 8.48 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:26:17 PM PDT 24
Peak memory 224752 kb
Host smart-61996ad6-7a08-45f9-bf66-0883bdac5892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654749457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
654749457
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.107218670
Short name T263
Test name
Test status
Simulation time 2919798921 ps
CPU time 6.92 seconds
Started Aug 14 05:26:07 PM PDT 24
Finished Aug 14 05:26:14 PM PDT 24
Peak memory 232940 kb
Host smart-ad522f62-8d7d-4242-9a61-bb6d6ef87493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107218670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.107218670
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3713562827
Short name T717
Test name
Test status
Simulation time 3532935092 ps
CPU time 13.67 seconds
Started Aug 14 05:26:09 PM PDT 24
Finished Aug 14 05:26:23 PM PDT 24
Peak memory 219444 kb
Host smart-db114079-baa8-4355-b17b-4a2b08571981
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3713562827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3713562827
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2887811739
Short name T164
Test name
Test status
Simulation time 205347755286 ps
CPU time 374.74 seconds
Started Aug 14 05:26:14 PM PDT 24
Finished Aug 14 05:32:29 PM PDT 24
Peak memory 265228 kb
Host smart-23772eb3-3349-4002-b415-174be7a093e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887811739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2887811739
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3715235961
Short name T534
Test name
Test status
Simulation time 7075675749 ps
CPU time 37.88 seconds
Started Aug 14 05:26:07 PM PDT 24
Finished Aug 14 05:26:45 PM PDT 24
Peak memory 216540 kb
Host smart-61114ee0-af96-4e14-8b60-662d8ba580d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715235961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3715235961
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1303553519
Short name T635
Test name
Test status
Simulation time 1935515710 ps
CPU time 5.82 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:26:14 PM PDT 24
Peak memory 216592 kb
Host smart-786818e9-2f5f-4841-b681-76508aa37110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303553519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1303553519
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2253566023
Short name T816
Test name
Test status
Simulation time 77671700 ps
CPU time 1.45 seconds
Started Aug 14 05:26:13 PM PDT 24
Finished Aug 14 05:26:15 PM PDT 24
Peak memory 216460 kb
Host smart-b8e91b00-d8df-4055-9bfe-d6d494cf018a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253566023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2253566023
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2034000600
Short name T487
Test name
Test status
Simulation time 21381415 ps
CPU time 0.78 seconds
Started Aug 14 05:26:16 PM PDT 24
Finished Aug 14 05:26:17 PM PDT 24
Peak memory 206104 kb
Host smart-7b8f0cd2-5b75-4d88-b8a6-755965ba1d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034000600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2034000600
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.939654495
Short name T384
Test name
Test status
Simulation time 652397356 ps
CPU time 3.64 seconds
Started Aug 14 05:26:09 PM PDT 24
Finished Aug 14 05:26:13 PM PDT 24
Peak memory 224668 kb
Host smart-1f89c129-1f82-4179-8ce2-6faea53b2da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939654495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.939654495
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3089358154
Short name T466
Test name
Test status
Simulation time 125666900 ps
CPU time 0.71 seconds
Started Aug 14 05:26:17 PM PDT 24
Finished Aug 14 05:26:20 PM PDT 24
Peak memory 205008 kb
Host smart-a51dabf6-a27e-4c48-a503-db3ed1f5751e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089358154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
089358154
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.646960593
Short name T455
Test name
Test status
Simulation time 9785276557 ps
CPU time 20.64 seconds
Started Aug 14 05:26:16 PM PDT 24
Finished Aug 14 05:26:37 PM PDT 24
Peak memory 232992 kb
Host smart-b1b856e9-cb4b-44fe-9ec0-7736663d1e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646960593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.646960593
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.156737889
Short name T530
Test name
Test status
Simulation time 13864186 ps
CPU time 0.76 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:26:09 PM PDT 24
Peak memory 206896 kb
Host smart-6d671ff6-ddde-4ef2-8f2d-ebb6e47ea949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156737889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.156737889
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1806179228
Short name T281
Test name
Test status
Simulation time 331069942182 ps
CPU time 542.5 seconds
Started Aug 14 05:26:16 PM PDT 24
Finished Aug 14 05:35:19 PM PDT 24
Peak memory 271772 kb
Host smart-549f5f47-cccc-401c-a606-052291e7b70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806179228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1806179228
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.144537582
Short name T513
Test name
Test status
Simulation time 7324361563 ps
CPU time 17.89 seconds
Started Aug 14 05:26:17 PM PDT 24
Finished Aug 14 05:26:35 PM PDT 24
Peak memory 217684 kb
Host smart-d9e5c0b7-c1d5-4ea8-9931-45c4abd05239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144537582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
144537582
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3054280747
Short name T423
Test name
Test status
Simulation time 1148332134 ps
CPU time 16.28 seconds
Started Aug 14 05:26:20 PM PDT 24
Finished Aug 14 05:26:37 PM PDT 24
Peak memory 241108 kb
Host smart-0c5bfc8e-7759-4a96-97f9-2594cac042b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054280747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3054280747
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.4109959517
Short name T277
Test name
Test status
Simulation time 57966432420 ps
CPU time 387.14 seconds
Started Aug 14 05:26:27 PM PDT 24
Finished Aug 14 05:32:54 PM PDT 24
Peak memory 257484 kb
Host smart-b9e3c33a-e7d6-4aee-898c-23e1d8a1ca4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109959517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.4109959517
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.233024059
Short name T837
Test name
Test status
Simulation time 1004617058 ps
CPU time 7.47 seconds
Started Aug 14 05:26:16 PM PDT 24
Finished Aug 14 05:26:24 PM PDT 24
Peak memory 224700 kb
Host smart-d16d7d40-1539-492e-ad44-2755ddb8a48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233024059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.233024059
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.4008336387
Short name T876
Test name
Test status
Simulation time 5734359448 ps
CPU time 29.82 seconds
Started Aug 14 05:26:16 PM PDT 24
Finished Aug 14 05:26:46 PM PDT 24
Peak memory 232984 kb
Host smart-31f947da-cb0c-4029-a0b3-54be136fcf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008336387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.4008336387
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1363006110
Short name T751
Test name
Test status
Simulation time 270595054 ps
CPU time 1.01 seconds
Started Aug 14 05:26:07 PM PDT 24
Finished Aug 14 05:26:08 PM PDT 24
Peak memory 218048 kb
Host smart-8fc33f03-4f62-4a4c-91e9-6debfe77818c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363006110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1363006110
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2076420726
Short name T429
Test name
Test status
Simulation time 149382326 ps
CPU time 2.82 seconds
Started Aug 14 05:26:17 PM PDT 24
Finished Aug 14 05:26:20 PM PDT 24
Peak memory 232928 kb
Host smart-0d2c75df-dff9-4080-b077-8459c289d5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076420726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2076420726
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1002119794
Short name T641
Test name
Test status
Simulation time 7116109268 ps
CPU time 12.09 seconds
Started Aug 14 05:26:18 PM PDT 24
Finished Aug 14 05:26:32 PM PDT 24
Peak memory 232944 kb
Host smart-3cd16ba2-e135-49dc-b814-84643091d733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002119794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1002119794
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2991782372
Short name T690
Test name
Test status
Simulation time 1056881573 ps
CPU time 5.49 seconds
Started Aug 14 05:26:16 PM PDT 24
Finished Aug 14 05:26:21 PM PDT 24
Peak memory 223308 kb
Host smart-fde1bb24-18ed-488d-bb78-0691cad51d60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2991782372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2991782372
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2797602577
Short name T479
Test name
Test status
Simulation time 10810021637 ps
CPU time 62.97 seconds
Started Aug 14 05:26:19 PM PDT 24
Finished Aug 14 05:27:23 PM PDT 24
Peak memory 264132 kb
Host smart-3880fcb3-d21d-4098-84ea-971ad707d2d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797602577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2797602577
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2863504335
Short name T722
Test name
Test status
Simulation time 14019013 ps
CPU time 0.72 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:26:09 PM PDT 24
Peak memory 205752 kb
Host smart-86f57561-7b0d-4c40-a23c-dcdac29f2ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863504335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2863504335
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3946082326
Short name T981
Test name
Test status
Simulation time 9034240374 ps
CPU time 20.87 seconds
Started Aug 14 05:26:08 PM PDT 24
Finished Aug 14 05:26:29 PM PDT 24
Peak memory 216560 kb
Host smart-cc023db1-2c35-4ce7-a9e3-ae7e28f26fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946082326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3946082326
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.204076049
Short name T381
Test name
Test status
Simulation time 579516512 ps
CPU time 2.19 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:28 PM PDT 24
Peak memory 216472 kb
Host smart-c8ab6693-5363-4150-b161-ebed4e39d285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204076049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.204076049
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.246951711
Short name T569
Test name
Test status
Simulation time 87554138 ps
CPU time 0.87 seconds
Started Aug 14 05:26:28 PM PDT 24
Finished Aug 14 05:26:29 PM PDT 24
Peak memory 206084 kb
Host smart-ca921406-9567-4177-bf71-54c8e70b458b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246951711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.246951711
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.979387359
Short name T859
Test name
Test status
Simulation time 14940083593 ps
CPU time 8.47 seconds
Started Aug 14 05:26:17 PM PDT 24
Finished Aug 14 05:26:28 PM PDT 24
Peak memory 224732 kb
Host smart-42e82f37-3eda-4e46-9e94-54c0c14e5620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979387359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.979387359
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.767858671
Short name T616
Test name
Test status
Simulation time 31751913 ps
CPU time 0.76 seconds
Started Aug 14 05:26:21 PM PDT 24
Finished Aug 14 05:26:22 PM PDT 24
Peak memory 205924 kb
Host smart-c1d1506a-ebc9-4726-bb5f-7dfd4beb6928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767858671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.767858671
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2976670863
Short name T847
Test name
Test status
Simulation time 712337425 ps
CPU time 2.77 seconds
Started Aug 14 05:26:18 PM PDT 24
Finished Aug 14 05:26:23 PM PDT 24
Peak memory 224692 kb
Host smart-59088bc2-0fe1-4b19-a623-75792ddb7502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976670863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2976670863
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1532183920
Short name T380
Test name
Test status
Simulation time 59320024 ps
CPU time 0.77 seconds
Started Aug 14 05:26:18 PM PDT 24
Finished Aug 14 05:26:20 PM PDT 24
Peak memory 205612 kb
Host smart-812853a2-afed-4959-9290-56f18e72c820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532183920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1532183920
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3405797466
Short name T623
Test name
Test status
Simulation time 11633712146 ps
CPU time 122.18 seconds
Started Aug 14 05:26:15 PM PDT 24
Finished Aug 14 05:28:17 PM PDT 24
Peak memory 251260 kb
Host smart-1c7923f0-7cf7-4a53-a869-e110d71976f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405797466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3405797466
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1392769188
Short name T52
Test name
Test status
Simulation time 4886021076 ps
CPU time 37.93 seconds
Started Aug 14 05:26:18 PM PDT 24
Finished Aug 14 05:26:58 PM PDT 24
Peak memory 251900 kb
Host smart-e86c4eb9-a550-4cdf-a74f-bdc730cf30ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392769188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1392769188
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3232498750
Short name T64
Test name
Test status
Simulation time 33067445904 ps
CPU time 25.7 seconds
Started Aug 14 05:26:18 PM PDT 24
Finished Aug 14 05:26:46 PM PDT 24
Peak memory 217880 kb
Host smart-b0bb1cea-ba68-4129-9366-06b89a64b87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232498750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3232498750
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1305116417
Short name T306
Test name
Test status
Simulation time 3114751455 ps
CPU time 40.77 seconds
Started Aug 14 05:26:18 PM PDT 24
Finished Aug 14 05:27:00 PM PDT 24
Peak memory 232980 kb
Host smart-e85301a5-ee52-4662-a182-67caebcc0124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305116417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1305116417
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1185947286
Short name T284
Test name
Test status
Simulation time 19725424477 ps
CPU time 96.25 seconds
Started Aug 14 05:26:18 PM PDT 24
Finished Aug 14 05:27:56 PM PDT 24
Peak memory 255400 kb
Host smart-31edb5be-0263-4495-bfb3-011b7cf1e7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185947286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1185947286
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2056236462
Short name T229
Test name
Test status
Simulation time 14454958063 ps
CPU time 31.45 seconds
Started Aug 14 05:26:16 PM PDT 24
Finished Aug 14 05:26:47 PM PDT 24
Peak memory 229388 kb
Host smart-4f98e574-208a-4faf-b897-7137bb0b2a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056236462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2056236462
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.526172887
Short name T453
Test name
Test status
Simulation time 62093718777 ps
CPU time 110.35 seconds
Started Aug 14 05:26:24 PM PDT 24
Finished Aug 14 05:28:14 PM PDT 24
Peak memory 240040 kb
Host smart-a2f24d93-bda5-41bb-b4c9-485f13b00ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526172887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.526172887
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3842732286
Short name T621
Test name
Test status
Simulation time 44161916 ps
CPU time 1.1 seconds
Started Aug 14 05:26:28 PM PDT 24
Finished Aug 14 05:26:29 PM PDT 24
Peak memory 216688 kb
Host smart-2ecc1165-f3cb-4542-88e3-0c16428b948d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842732286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3842732286
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3216717400
Short name T143
Test name
Test status
Simulation time 3218690364 ps
CPU time 11.02 seconds
Started Aug 14 05:26:23 PM PDT 24
Finished Aug 14 05:26:35 PM PDT 24
Peak memory 240676 kb
Host smart-ee074486-a5b0-4ccc-a71e-ab683538217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216717400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3216717400
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.718210627
Short name T494
Test name
Test status
Simulation time 7476767686 ps
CPU time 8.32 seconds
Started Aug 14 05:26:16 PM PDT 24
Finished Aug 14 05:26:24 PM PDT 24
Peak memory 224688 kb
Host smart-9b0ea94e-ead4-4d79-b6e5-45cb19041424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718210627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.718210627
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.365553236
Short name T702
Test name
Test status
Simulation time 760072275 ps
CPU time 5.51 seconds
Started Aug 14 05:26:15 PM PDT 24
Finished Aug 14 05:26:21 PM PDT 24
Peak memory 220292 kb
Host smart-5d973f22-0fa8-4d26-abd0-9f05ae770d77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=365553236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.365553236
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.425656096
Short name T280
Test name
Test status
Simulation time 8976087889 ps
CPU time 69.03 seconds
Started Aug 14 05:26:28 PM PDT 24
Finished Aug 14 05:27:37 PM PDT 24
Peak memory 249808 kb
Host smart-b6265bf6-3000-4c5d-8c98-95adcd4527b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425656096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.425656096
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2279576356
Short name T492
Test name
Test status
Simulation time 2307880824 ps
CPU time 11.22 seconds
Started Aug 14 05:26:19 PM PDT 24
Finished Aug 14 05:26:31 PM PDT 24
Peak memory 216608 kb
Host smart-14ac491f-d182-4545-b1c9-796e40f72618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279576356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2279576356
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.602558959
Short name T652
Test name
Test status
Simulation time 4353131555 ps
CPU time 3.59 seconds
Started Aug 14 05:26:17 PM PDT 24
Finished Aug 14 05:26:21 PM PDT 24
Peak memory 216612 kb
Host smart-ed355f60-be9e-4b67-8a56-d8a053b661da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602558959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.602558959
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.156230133
Short name T888
Test name
Test status
Simulation time 97811950 ps
CPU time 1.4 seconds
Started Aug 14 05:26:18 PM PDT 24
Finished Aug 14 05:26:21 PM PDT 24
Peak memory 216516 kb
Host smart-d445398c-ffde-4e7d-8245-a54fbd430a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156230133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.156230133
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.591717452
Short name T779
Test name
Test status
Simulation time 292853264 ps
CPU time 0.95 seconds
Started Aug 14 05:26:25 PM PDT 24
Finished Aug 14 05:26:26 PM PDT 24
Peak memory 206104 kb
Host smart-829e5fb0-9c6f-4edd-ad09-501e9ce2b3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591717452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.591717452
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4076006300
Short name T1022
Test name
Test status
Simulation time 143995371 ps
CPU time 2.59 seconds
Started Aug 14 05:26:16 PM PDT 24
Finished Aug 14 05:26:19 PM PDT 24
Peak memory 224688 kb
Host smart-cc4f132e-0f17-40b0-8f12-cdb067eaabf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076006300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4076006300
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3318740581
Short name T853
Test name
Test status
Simulation time 50286163 ps
CPU time 0.75 seconds
Started Aug 14 05:26:30 PM PDT 24
Finished Aug 14 05:26:31 PM PDT 24
Peak memory 205020 kb
Host smart-0022244d-cac0-4ac4-905e-5f4407a049c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318740581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
318740581
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2046725396
Short name T417
Test name
Test status
Simulation time 140278884 ps
CPU time 3.99 seconds
Started Aug 14 05:26:25 PM PDT 24
Finished Aug 14 05:26:29 PM PDT 24
Peak memory 224616 kb
Host smart-0dc2d09e-2a67-4997-81fe-cdbf31847a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046725396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2046725396
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3478129528
Short name T432
Test name
Test status
Simulation time 18815184 ps
CPU time 0.78 seconds
Started Aug 14 05:26:20 PM PDT 24
Finished Aug 14 05:26:21 PM PDT 24
Peak memory 205952 kb
Host smart-e9678ca6-8273-4320-b3bb-eba0c63b6497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478129528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3478129528
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.854102947
Short name T430
Test name
Test status
Simulation time 69332621902 ps
CPU time 140.74 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:28:47 PM PDT 24
Peak memory 249376 kb
Host smart-426f5d2e-4199-45d6-8c6a-780db1e225e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854102947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.854102947
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2367823414
Short name T636
Test name
Test status
Simulation time 8656212139 ps
CPU time 61.69 seconds
Started Aug 14 05:26:28 PM PDT 24
Finished Aug 14 05:27:30 PM PDT 24
Peak memory 249388 kb
Host smart-3a71c723-33d8-478a-bacd-974230bb37ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367823414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2367823414
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3998562877
Short name T982
Test name
Test status
Simulation time 2797345517 ps
CPU time 48.99 seconds
Started Aug 14 05:26:24 PM PDT 24
Finished Aug 14 05:27:13 PM PDT 24
Peak memory 252044 kb
Host smart-04fa2584-08a4-4c47-a894-6f3cefe1a34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998562877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3998562877
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1199755512
Short name T823
Test name
Test status
Simulation time 1100065493 ps
CPU time 12.15 seconds
Started Aug 14 05:26:24 PM PDT 24
Finished Aug 14 05:26:36 PM PDT 24
Peak memory 232896 kb
Host smart-647ad2a6-2621-4ac9-950f-154f019907c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199755512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1199755512
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3501714160
Short name T630
Test name
Test status
Simulation time 3128717839 ps
CPU time 10.28 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:37 PM PDT 24
Peak memory 234756 kb
Host smart-60c14cad-9dbd-4826-985c-e807d91e423b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501714160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3501714160
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1498464192
Short name T615
Test name
Test status
Simulation time 2831448682 ps
CPU time 24.26 seconds
Started Aug 14 05:26:25 PM PDT 24
Finished Aug 14 05:26:50 PM PDT 24
Peak memory 224744 kb
Host smart-458b4e5b-e264-48a8-8d8a-fb6c395e5132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498464192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1498464192
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2759591616
Short name T1018
Test name
Test status
Simulation time 4602899768 ps
CPU time 20.17 seconds
Started Aug 14 05:26:24 PM PDT 24
Finished Aug 14 05:26:44 PM PDT 24
Peak memory 250456 kb
Host smart-7a5f254e-d4de-4acf-b08e-e292bf0fac69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759591616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2759591616
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3282749554
Short name T36
Test name
Test status
Simulation time 47569953 ps
CPU time 1.01 seconds
Started Aug 14 05:26:17 PM PDT 24
Finished Aug 14 05:26:18 PM PDT 24
Peak memory 217988 kb
Host smart-a6f9c37f-cee3-4683-ae5d-2ca65471c04e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282749554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3282749554
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1910007067
Short name T428
Test name
Test status
Simulation time 619432755 ps
CPU time 2.29 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:28 PM PDT 24
Peak memory 223048 kb
Host smart-038a6333-2423-4d83-978e-bac2e6c23ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910007067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1910007067
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.142134864
Short name T1015
Test name
Test status
Simulation time 1176820842 ps
CPU time 6.34 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:32 PM PDT 24
Peak memory 237744 kb
Host smart-4578ba68-d94e-4728-ae59-6fd003969671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142134864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.142134864
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3064783528
Short name T401
Test name
Test status
Simulation time 1154439680 ps
CPU time 3.72 seconds
Started Aug 14 05:26:29 PM PDT 24
Finished Aug 14 05:26:33 PM PDT 24
Peak memory 219320 kb
Host smart-2b2a6138-acf9-44a6-971a-89d85506a306
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3064783528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3064783528
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.872632622
Short name T1010
Test name
Test status
Simulation time 148238851545 ps
CPU time 581.51 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:36:08 PM PDT 24
Peak memory 281644 kb
Host smart-8fdaf547-d7ab-4a46-baa3-0c37194d76eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872632622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.872632622
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1919873684
Short name T313
Test name
Test status
Simulation time 7389586383 ps
CPU time 21.38 seconds
Started Aug 14 05:26:16 PM PDT 24
Finished Aug 14 05:26:38 PM PDT 24
Peak memory 220404 kb
Host smart-7650781e-edfc-431b-9150-a008578d5be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919873684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1919873684
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4027902935
Short name T781
Test name
Test status
Simulation time 9513831288 ps
CPU time 10.1 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:37 PM PDT 24
Peak memory 216536 kb
Host smart-2c8cd4ea-2fd0-4889-b94d-72eee58c53af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027902935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4027902935
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2385855621
Short name T964
Test name
Test status
Simulation time 179541912 ps
CPU time 1.94 seconds
Started Aug 14 05:26:18 PM PDT 24
Finished Aug 14 05:26:22 PM PDT 24
Peak memory 216420 kb
Host smart-33787e31-e596-4f08-b0ea-6a0eb144f718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385855621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2385855621
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2071721925
Short name T889
Test name
Test status
Simulation time 89222369 ps
CPU time 0.93 seconds
Started Aug 14 05:26:17 PM PDT 24
Finished Aug 14 05:26:18 PM PDT 24
Peak memory 207252 kb
Host smart-ade43d4b-107e-4984-bc90-eafd0d2c5c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071721925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2071721925
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3905446117
Short name T450
Test name
Test status
Simulation time 657659621 ps
CPU time 9.47 seconds
Started Aug 14 05:26:26 PM PDT 24
Finished Aug 14 05:26:36 PM PDT 24
Peak memory 234736 kb
Host smart-5fe6e2fa-00f7-495a-b266-f353e26b802f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905446117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3905446117
Directory /workspace/9.spi_device_upload/latest
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