Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2677019	1			T1	1		T2	1		T3	1897
all_values[1]	2677019	1			T1	1		T2	1		T3	1897
all_values[2]	2677019	1			T1	1		T2	1		T3	1897
all_values[3]	2677019	1			T1	1		T2	1		T3	1897
all_values[4]	2677019	1			T1	1		T2	1		T3	1897
all_values[5]	2677019	1			T1	1		T2	1		T3	1897
all_values[6]	2677019	1			T1	1		T2	1		T3	1897
all_values[7]	2677019	1			T1	1		T2	1		T3	1897

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20980459

1

T1

8

T2

8

T3

15176

auto[1]

435693

1

T16

79

T18

38

T19

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21388452

1

T1

8

T2

8

T3

15146

auto[1]

27700

1

T3

30

T32

90

T33

339

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2586141	1			T1	1		T2	1		T3	1880
all_values[0]	auto[0]	auto[1]	13121	1			T3	17		T32	54		T33	172
all_values[0]	auto[1]	auto[0]	77093	1			T16	5		T18	3		T21	3
all_values[0]	auto[1]	auto[1]	664	1			T16	4		T18	2		T19	1
all_values[1]	auto[0]	auto[0]	2606887	1			T1	1		T2	1		T3	1884
all_values[1]	auto[0]	auto[1]	7962	1			T3	13		T32	18		T33	111
all_values[1]	auto[1]	auto[0]	61716	1			T16	3		T18	5		T19	2
all_values[1]	auto[1]	auto[1]	454	1			T16	1		T18	3		T21	1
all_values[2]	auto[0]	auto[0]	2592749	1			T1	1		T2	1		T3	1897
all_values[2]	auto[0]	auto[1]	3204	1			T32	18		T33	56		T14	25
all_values[2]	auto[1]	auto[0]	80722	1			T16	7		T18	3		T19	1
all_values[2]	auto[1]	auto[1]	344	1			T16	7		T18	3		T19	1
all_values[3]	auto[0]	auto[0]	2631589	1			T1	1		T2	1		T3	1897
all_values[3]	auto[0]	auto[1]	203	1			T16	2		T18	1		T19	1
all_values[3]	auto[1]	auto[0]	45041	1			T16	13		T18	4		T19	4
all_values[3]	auto[1]	auto[1]	186	1			T16	3		T21	1		T22	4
all_values[4]	auto[0]	auto[0]	2585961	1			T1	1		T2	1		T3	1897
all_values[4]	auto[0]	auto[1]	210	1			T16	2		T18	4		T21	3
all_values[4]	auto[1]	auto[0]	90640	1			T16	6		T18	1		T21	5
all_values[4]	auto[1]	auto[1]	208	1			T16	3		T18	1		T21	4
all_values[5]	auto[0]	auto[0]	2644464	1			T1	1		T2	1		T3	1897
all_values[5]	auto[0]	auto[1]	198	1			T16	3		T18	3		T19	1
all_values[5]	auto[1]	auto[0]	32185	1			T16	8		T18	1		T19	1
all_values[5]	auto[1]	auto[1]	172	1			T16	3		T18	1		T19	1
all_values[6]	auto[0]	auto[0]	2657504	1			T1	1		T2	1		T3	1897
all_values[6]	auto[0]	auto[1]	212	1			T16	7		T18	1		T19	2
all_values[6]	auto[1]	auto[0]	19117	1			T16	4		T18	2		T21	5
all_values[6]	auto[1]	auto[1]	186	1			T16	3		T18	2		T19	1
all_values[7]	auto[0]	auto[0]	2649863	1			T1	1		T2	1		T3	1897
all_values[7]	auto[0]	auto[1]	191	1			T16	5		T19	3		T21	8
all_values[7]	auto[1]	auto[0]	26780	1			T16	6		T18	5		T21	2
all_values[7]	auto[1]	auto[1]	185	1			T16	3		T18	2		T19	1