Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35657	1			T3	33		T4	106		T8	49
auto[SpiFlashAddrCfg]	7732	1			T3	15		T4	21		T8	29
auto[SpiFlashAddr3b]	9257	1			T1	1		T3	10		T4	31
auto[SpiFlashAddr4b]	7757	1			T1	1		T3	10		T4	19

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34705

1

T1

2

T3

52

T4

61

auto[1]

25698

1

T3

16

T4

116

T8

64

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33072

1

T1

1

T3

33

T4

72

auto[1]

27331

1

T1

1

T3

35

T4

105

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40515	1			T3	43		T4	117		T8	69
values[1]	1085	1			T8	1		T10	1		T13	1
values[2]	1490	1			T3	3		T4	3		T8	1
values[3]	1505	1			T4	8		T8	4		T10	9
values[4]	1420	1			T3	1		T4	2		T8	13
values[5]	1469	1			T3	3		T4	3		T8	2
values[6]	1511	1			T3	2		T4	2		T8	3
values[7]	1471	1			T3	3		T4	3		T8	11
values[8]	9937	1			T1	2		T3	13		T4	39

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30501

1

T4

177

T8

140

T11

10

auto[1]

29902

1

T1

2

T3

68

T6

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57076

1

T1

2

T3

63

T4

170

write

3327

1

T3

5

T4

7

T8

15

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19557

1

T1

1

T3

26

T4

63

valids[0x1]

40846

1

T1

1

T3

42

T4

114

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1582	1			T3	4		T4	2		T8	3
internal_process_ops[0x5a]	1573	1			T3	2		T4	7		T8	4
internal_process_ops[0x05]	21479	1			T3	10		T4	62		T8	3
internal_process_ops[0x35]	1546	1			T3	2		T4	6		T8	7
internal_process_ops[0x15]	1575	1			T3	2		T4	8		T8	13
internal_process_ops[0x03]	1058	1			T3	2		T4	3		T8	1
internal_process_ops[0x0b]	1072	1			T1	1		T4	5		T8	2
internal_process_ops[0x3b]	1048	1			T3	1		T4	4		T8	6
internal_process_ops[0x6b]	1049	1			T4	5		T6	1		T8	7
internal_process_ops[0xbb]	1067	1			T1	1		T4	3		T8	7
internal_process_ops[0xeb]	1104	1			T4	6		T6	1		T8	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58805

1

T1

2

T3

64

T4

173

auto[1]

1598

1

T3

4

T4

4

T8

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58085

1

T1

2

T3

65

T4

173

auto[1]

2318

1

T3

3

T4

4

T8

12

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10126

1

T4

28

T8

24

T11

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5995

1

T4

74

T8

20

T13

16

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2161

1

T4

13

T8

20

T12

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1858

1

T4

7

T8

6

T13

13

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2524

1

T4

9

T8

14

T11

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2233

1

T4

21

T8

16

T13

17

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2066

1

T4

9

T8

10

T12

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1916

1

T4

9

T8

15

T13

7

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

151

1

T31

1

T33

2

T42

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

85

1

T4

1

T8

2

T13

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

73

1

T4

2

T8

1

T13

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

102

1

T4

1

T8

2

T13

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

120

1

T31

1

T98

2

T78

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

96

1

T8

1

T13

3

T33

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

100

1

T4

1

T8

2

T33

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

110

1

T14

2

T18

4

T53

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

118

1

T13

1

T33

2

T166

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

77

1

T4

1

T8

2

T13

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

75

1

T8

2

T13

1

T31

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

97

1

T13

4

T19

1

T167

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

119

1

T8

3

T166

1

T98

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

110

1

T14

2

T42

3

T20

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

98

1

T13

1

T33

2

T14

7

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

91

1

T4

1

T53

1

T168

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11277

1

T3

27

T10

47

T32

25

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7398

1

T3

3

T10

21

T32

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1477

1

T3

11

T10

21

T32

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1382

1

T3

4

T10

19

T48

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1878

1

T1

1

T3

5

T6

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1836

1

T3

5

T10

18

T32

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1468

1

T1

1

T3

4

T6

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1481

1

T3

4

T10

16

T32

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

124

1

T10

2

T48

1

T82

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

123

1

T3

3

T10

4

T48

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

104

1

T82

4

T30

1

T16

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

99

1

T10

5

T82

2

T30

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

106

1

T10

3

T14

1

T30

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

97

1

T10

1

T32

1

T48

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

107

1

T10

1

T16

1

T86

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

118

1

T48

3

T82

1

T49

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

85

1

T10

1

T14

3

T30

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

93

1

T10

1

T32

1

T30

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

121

1

T10

6

T32

2

T82

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

120

1

T48

1

T82

1

T14

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

124

1

T3

1

T10

1

T48

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

100

1

T3

1

T10

2

T82

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

104

1

T10

2

T82

4

T14

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

80

1

T82

4

T30

3

T49

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4059	1			T4	20		T8	20		T13	31
auto[0]	values[0]	valids[0x1]	15147	1			T4	97		T8	49		T11	8
auto[0]	values[1]	valids[0x1]	560	1			T8	1		T13	1		T31	1
auto[0]	values[2]	valids[0x0]	566	1			T4	2		T8	1		T13	2
auto[0]	values[2]	valids[0x1]	320	1			T4	1		T13	4		T31	1
auto[0]	values[3]	valids[0x0]	569	1			T4	6		T8	4		T13	1
auto[0]	values[3]	valids[0x1]	313	1			T4	2		T13	1		T33	5
auto[0]	values[4]	valids[0x0]	530	1			T8	5		T13	4		T31	3
auto[0]	values[4]	valids[0x1]	280	1			T4	2		T8	8		T13	3
auto[0]	values[5]	valids[0x0]	565	1			T4	2		T8	2		T13	6
auto[0]	values[5]	valids[0x1]	281	1			T4	1		T13	4		T33	7
auto[0]	values[6]	valids[0x0]	569	1			T4	2		T8	2		T13	2
auto[0]	values[6]	valids[0x1]	303	1			T8	1		T13	1		T33	2
auto[0]	values[7]	valids[0x0]	549	1			T4	3		T8	6		T13	9
auto[0]	values[7]	valids[0x1]	307	1			T8	5		T13	2		T31	1
auto[0]	values[8]	valids[0x0]	3420	1			T4	28		T8	20		T12	2
auto[0]	values[8]	valids[0x1]	2163	1			T4	11		T8	16		T11	2
auto[1]	values[0]	valids[0x0]	3941	1			T3	12		T10	42		T32	9
auto[1]	values[0]	valids[0x1]	17368	1			T3	31		T10	76		T32	26
auto[1]	values[1]	valids[0x1]	525	1			T10	1		T48	4		T82	3
auto[1]	values[2]	valids[0x0]	391	1			T10	6		T82	4		T14	5
auto[1]	values[2]	valids[0x1]	213	1			T3	3		T10	4		T48	1
auto[1]	values[3]	valids[0x0]	388	1			T10	8		T48	2		T82	11
auto[1]	values[3]	valids[0x1]	235	1			T10	1		T32	1		T48	3
auto[1]	values[4]	valids[0x0]	338	1			T3	1		T48	5		T82	8
auto[1]	values[4]	valids[0x1]	272	1			T10	4		T32	1		T82	4
auto[1]	values[5]	valids[0x0]	353	1			T3	2		T48	1		T82	6
auto[1]	values[5]	valids[0x1]	270	1			T3	1		T10	6		T32	1
auto[1]	values[6]	valids[0x0]	394	1			T3	2		T10	5		T48	1
auto[1]	values[6]	valids[0x1]	245	1			T10	2		T14	1		T30	2
auto[1]	values[7]	valids[0x0]	382	1			T3	3		T10	1		T48	1
auto[1]	values[7]	valids[0x1]	233	1			T10	2		T82	7		T14	2
auto[1]	values[8]	valids[0x0]	2543	1			T1	1		T3	6		T6	2
auto[1]	values[8]	valids[0x1]	1811	1			T1	1		T3	7		T10	19