Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3494667

1

T1

1606

T3

2126

T4

16131

auto[1]

28696

1

T3

8

T4

57

T8

208

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

980441

1

T1

1606

T3

28

T4

35

auto[1]

2542922

1

T3

2106

T4

16153

T8

30206

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	655304	1			T1	1603		T3	1454		T4	3368
auto[524288:1048575]	377773	1			T3	1		T4	5475		T8	5328
auto[1048576:1572863]	412605	1			T3	130		T4	13		T8	29
auto[1572864:2097151]	373530	1			T1	1		T3	518		T6	82
auto[2097152:2621439]	432980	1			T8	6488		T10	491		T11	551
auto[2621440:3145727]	474232	1			T3	6		T8	3348		T10	3656
auto[3145728:3670015]	398080	1			T1	2		T3	25		T4	2823
auto[3670016:4194303]	398859	1			T4	4509		T8	4414		T10	1498

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2576739

1

T1

5

T3

2134

T4

16185

auto[1]

946624

1

T1

1601

T4

3

T6

289

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3108446

1

T1

1606

T3

2029

T4

13066

auto[1]

414917

1

T3

105

T4

3122

T8

3179

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	232978	1			T1	1603		T3	3		T4	3
auto[0]	auto[0]	auto[0:524287]	auto[1]	362578	1			T3	1352		T4	512		T8	4849
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	81679	1			T3	1		T4	9		T8	25
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	242931	1			T4	5430		T8	2680		T10	625
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	124101	1			T3	2		T4	4		T8	20
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	229111	1			T3	128		T4	9		T8	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	90245	1			T1	1		T3	1		T6	82
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	230799	1			T3	512		T8	1878		T10	1815
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	112601	1			T8	25		T10	13		T11	551
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	279065	1			T8	6460		T10	468		T33	6524
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	123425	1			T3	3		T8	37		T10	36
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	272969	1			T3	1		T8	3282		T10	3491
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	99578	1			T1	2		T3	9		T4	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	254260	1			T3	10		T4	2819		T8	3513
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	102895	1			T4	4		T8	14		T10	78
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	246877	1			T4	4223		T8	4297		T10	1420
auto[0]	auto[1]	auto[0:524287]	auto[0]	788	1			T3	2		T4	3		T8	17
auto[0]	auto[1]	auto[0:524287]	auto[1]	54150	1			T3	97		T4	2850		T8	512
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2797	1			T4	2		T8	15		T10	7
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	47107	1			T4	1		T8	2576		T33	257
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	407	1			T14	3		T49	1		T86	33
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	54881	1			T32	256		T14	2		T16	103
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1565	1			T3	3		T8	12		T13	15
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	47228	1			T3	1		T13	128		T33	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	629	1			T13	8		T33	4		T48	9
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	38179	1			T33	265		T82	1954		T14	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	852	1			T8	3		T82	8		T166	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	73313	1			T33	2550		T82	6520		T30	1605
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1030	1			T3	1		T8	4		T13	26
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	39241	1			T32	2		T33	641		T49	259
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1172	1			T4	2		T8	4		T14	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	45236	1			T4	256		T33	856		T49	1900
auto[1]	auto[0]	auto[0:524287]	auto[0]	462	1			T8	5		T10	16		T13	8
auto[1]	auto[0]	auto[0:524287]	auto[1]	3122	1			T33	1		T54	47		T82	94
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	358	1			T4	2		T10	10		T13	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1801	1			T4	23		T10	15		T33	28
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	392	1			T8	6		T10	6		T33	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2757	1			T10	44		T33	10		T82	62
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	355	1			T10	14		T32	1		T33	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3026	1			T10	25		T33	14		T14	48
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	405	1			T8	3		T10	10		T33	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1671	1			T33	19		T82	69		T14	44
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	394	1			T3	1		T8	19		T10	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2630	1			T3	1		T8	7		T10	122
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	394	1			T3	1		T8	6		T10	18
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2204	1			T3	4		T8	27		T33	28
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	362	1			T4	1		T8	6		T31	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2021	1			T4	23		T8	93		T33	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	81	1			T8	4		T13	3		T82	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	1145	1			T82	15		T49	2		T188	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	78	1			T4	1		T8	3		T33	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1022	1			T4	7		T8	29		T33	20
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	68	1			T14	2		T16	2		T86	5
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	888	1			T14	4		T16	5		T86	512
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	35	1			T3	1		T49	1		T16	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	277	1			T49	22		T16	19		T20	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	93	1			T33	1		T82	1		T14	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	337	1			T33	2		T82	4		T14	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	79	1			T82	1		T30	1		T49	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	570	1			T82	49		T30	24		T49	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	94	1			T13	4		T32	2		T33	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1279	1			T32	9		T33	13		T49	30
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	49	1			T20	1		T198	2		T55	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	247	1			T198	54		T55	13		T43	7

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2144996	1			T1	5		T3	2022		T4	13016
auto[0]	auto[0]	auto[1]	941096	1			T1	1601		T4	1		T6	289
auto[0]	auto[1]	auto[0]	403676	1			T3	104		T4	3113		T8	3143
auto[0]	auto[1]	auto[1]	4899	1			T4	1		T33	1		T82	3
auto[1]	auto[0]	auto[0]	21823	1			T3	7		T4	48		T8	162
auto[1]	auto[0]	auto[1]	531	1			T4	1		T8	10		T10	16
auto[1]	auto[1]	auto[0]	6244	1			T3	1		T4	8		T8	34
auto[1]	auto[1]	auto[1]	98	1			T8	2		T13	2		T49	2