Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2677019	1			T1	1		T2	1		T3	1897
all_pins[1]	2677019	1			T1	1		T2	1		T3	1897
all_pins[2]	2677019	1			T1	1		T2	1		T3	1897
all_pins[3]	2677019	1			T1	1		T2	1		T3	1897
all_pins[4]	2677019	1			T1	1		T2	1		T3	1897
all_pins[5]	2677019	1			T1	1		T2	1		T3	1897
all_pins[6]	2677019	1			T1	1		T2	1		T3	1897
all_pins[7]	2677019	1			T1	1		T2	1		T3	1897

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21394003	1			T1	8		T2	8		T3	15176
values[0x1]	22149	1			T16	27		T18	14		T19	5
transitions[0x0=>0x1]	21297	1			T16	21		T18	11		T19	2
transitions[0x1=>0x0]	21311	1			T16	21		T18	11		T19	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2676285	1			T1	1		T2	1		T3	1897
all_pins[0]	values[0x1]	734	1			T16	4		T18	2		T19	1
all_pins[0]	transitions[0x0=>0x1]	445	1			T16	3		T18	1		T19	1
all_pins[0]	transitions[0x1=>0x0]	194	1			T18	2		T21	1		T22	1
all_pins[1]	values[0x0]	2676536	1			T1	1		T2	1		T3	1897
all_pins[1]	values[0x1]	483	1			T16	1		T18	3		T21	1
all_pins[1]	transitions[0x0=>0x1]	299	1			T18	1		T22	2		T154	1
all_pins[1]	transitions[0x1=>0x0]	179	1			T16	6		T18	1		T19	1
all_pins[2]	values[0x0]	2676656	1			T1	1		T2	1		T3	1897
all_pins[2]	values[0x1]	363	1			T16	7		T18	3		T19	1
all_pins[2]	transitions[0x0=>0x1]	310	1			T16	7		T18	3		T19	1
all_pins[2]	transitions[0x1=>0x0]	133	1			T16	3		T22	2		T154	3
all_pins[3]	values[0x0]	2676833	1			T1	1		T2	1		T3	1897
all_pins[3]	values[0x1]	186	1			T16	3		T21	1		T22	4
all_pins[3]	transitions[0x0=>0x1]	142	1			T16	2		T21	1		T22	4
all_pins[3]	transitions[0x1=>0x0]	164	1			T16	2		T18	1		T21	4
all_pins[4]	values[0x0]	2676811	1			T1	1		T2	1		T3	1897
all_pins[4]	values[0x1]	208	1			T16	3		T18	1		T21	4
all_pins[4]	transitions[0x0=>0x1]	163	1			T16	3		T18	1		T21	3
all_pins[4]	transitions[0x1=>0x0]	971	1			T16	3		T18	1		T19	1
all_pins[5]	values[0x0]	2676003	1			T1	1		T2	1		T3	1897
all_pins[5]	values[0x1]	1016	1			T16	3		T18	1		T19	1
all_pins[5]	transitions[0x0=>0x1]	876	1			T16	3		T18	1		T21	4
all_pins[5]	transitions[0x1=>0x0]	18834	1			T16	3		T18	2		T21	3
all_pins[6]	values[0x0]	2658045	1			T1	1		T2	1		T3	1897
all_pins[6]	values[0x1]	18974	1			T16	3		T18	2		T19	1
all_pins[6]	transitions[0x0=>0x1]	18922	1			T16	1		T18	2		T21	3
all_pins[6]	transitions[0x1=>0x0]	133	1			T16	1		T18	2		T21	5
all_pins[7]	values[0x0]	2676834	1			T1	1		T2	1		T3	1897
all_pins[7]	values[0x1]	185	1			T16	3		T18	2		T19	1
all_pins[7]	transitions[0x0=>0x1]	140	1			T16	2		T18	2		T21	4
all_pins[7]	transitions[0x1=>0x0]	703	1			T16	3		T18	2		T21	4