Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17753

1

T4

61

T8

76

T11

10

auto[1]

12748

1

T4

116

T8

64

T13

62

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4167	1			T8	20		T13	20		T31	21
values[1]	3656	1			T8	40		T166	20		T14	20
values[2]	4190	1			T4	28		T8	20		T13	20
values[3]	4195	1			T4	65		T13	40		T33	133
values[4]	4008	1			T13	40		T33	115		T115	6
values[5]	3547	1			T4	20		T8	20		T11	10
values[6]	3343	1			T4	44		T8	20		T12	4
values[7]	3395	1			T4	20		T8	20		T13	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3618	1			T4	45		T8	60		T12	4
values[1]	3378	1			T4	20		T8	20		T115	6
values[2]	3638	1			T4	28		T8	20		T11	10
values[3]	2944	1			T4	20		T13	40		T33	39
values[4]	4422	1			T8	20		T33	26		T166	20
values[5]	3981	1			T8	20		T13	20		T33	118
values[6]	3679	1			T4	64		T13	40		T31	21
values[7]	4841	1			T31	20		T33	25		T54	73

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	668	1			T81	16		T167	33		T20	9
auto[0]	values[0]	values[1]	320	1			T225	4		T226	10		T201	12
auto[0]	values[0]	values[2]	321	1			T15	15		T18	9		T20	20
auto[0]	values[0]	values[3]	255	1			T13	15		T33	31		T42	11
auto[0]	values[0]	values[4]	216	1			T8	12		T42	16		T18	14
auto[0]	values[0]	values[5]	204	1			T33	9		T18	9		T20	12
auto[0]	values[0]	values[6]	270	1			T31	9		T14	11		T185	10
auto[0]	values[0]	values[7]	263	1			T184	49		T227	9		T228	8
auto[0]	values[1]	values[0]	151	1			T8	10		T14	11		T20	11
auto[0]	values[1]	values[1]	288	1			T8	8		T42	12		T18	9
auto[0]	values[1]	values[2]	339	1			T134	20		T184	59		T229	13
auto[0]	values[1]	values[3]	177	1			T166	15		T21	11		T194	12
auto[0]	values[1]	values[4]	419	1			T20	9		T223	49		T135	20
auto[0]	values[1]	values[5]	319	1			T167	7		T183	8		T128	36
auto[0]	values[1]	values[6]	189	1			T28	12		T20	7		T177	14
auto[0]	values[1]	values[7]	305	1			T201	15		T230	10		T178	11
auto[0]	values[2]	values[0]	156	1			T8	11		T183	11		T128	15
auto[0]	values[2]	values[1]	155	1			T231	6		T20	10		T201	7
auto[0]	values[2]	values[2]	340	1			T4	9		T167	8		T201	13
auto[0]	values[2]	values[3]	293	1			T13	8		T52	11		T53	15
auto[0]	values[2]	values[4]	413	1			T18	15		T20	13		T198	18
auto[0]	values[2]	values[5]	268	1			T52	24		T53	15		T19	13
auto[0]	values[2]	values[6]	318	1			T18	17		T20	13		T177	15
auto[0]	values[2]	values[7]	524	1			T31	4		T33	17		T98	85
auto[0]	values[3]	values[0]	268	1			T4	11		T33	30		T14	12
auto[0]	values[3]	values[1]	150	1			T4	10		T14	16		T50	14
auto[0]	values[3]	values[2]	310	1			T166	11		T14	9		T15	17
auto[0]	values[3]	values[3]	193	1			T211	16		T167	14		T20	12
auto[0]	values[3]	values[4]	458	1			T166	11		T177	13		T232	4
auto[0]	values[3]	values[5]	273	1			T13	16		T42	6		T18	10
auto[0]	values[3]	values[6]	260	1			T13	16		T218	12		T184	9
auto[0]	values[3]	values[7]	691	1			T54	73		T53	20		T167	45
auto[0]	values[4]	values[0]	235	1			T13	5		T33	15		T42	8
auto[0]	values[4]	values[1]	197	1			T115	6		T20	13		T177	14
auto[0]	values[4]	values[2]	358	1			T13	12		T53	7		T183	14
auto[0]	values[4]	values[3]	122	1			T167	26		T128	15		T178	9
auto[0]	values[4]	values[4]	444	1			T33	18		T42	8		T18	10
auto[0]	values[4]	values[5]	291	1			T233	4		T167	12		T177	12
auto[0]	values[4]	values[6]	324	1			T33	10		T18	11		T20	39
auto[0]	values[4]	values[7]	177	1			T20	11		T194	10		T234	12
auto[0]	values[5]	values[0]	263	1			T8	13		T14	10		T52	15
auto[0]	values[5]	values[1]	327	1			T14	9		T176	22		T18	20
auto[0]	values[5]	values[2]	112	1			T11	10		T14	9		T18	13
auto[0]	values[5]	values[3]	131	1			T190	23		T235	8		T236	5
auto[0]	values[5]	values[4]	266	1			T237	18		T128	12		T178	19
auto[0]	values[5]	values[5]	296	1			T210	18		T177	14		T238	4
auto[0]	values[5]	values[6]	274	1			T4	12		T18	14		T53	18
auto[0]	values[5]	values[7]	198	1			T14	15		T42	9		T20	12
auto[0]	values[6]	values[0]	201	1			T12	4		T14	21		T167	35
auto[0]	values[6]	values[1]	430	1			T198	9		T194	15		T217	68
auto[0]	values[6]	values[2]	113	1			T8	10		T201	6		T88	4
auto[0]	values[6]	values[3]	186	1			T78	18		T18	7		T183	12
auto[0]	values[6]	values[4]	351	1			T162	4		T192	16		T65	12
auto[0]	values[6]	values[5]	179	1			T53	8		T20	8		T134	11
auto[0]	values[6]	values[6]	161	1			T4	12		T27	6		T239	8
auto[0]	values[6]	values[7]	422	1			T42	17		T20	9		T22	34
auto[0]	values[7]	values[0]	214	1			T200	2		T177	25		T21	8
auto[0]	values[7]	values[1]	202	1			T167	7		T240	2		T241	4
auto[0]	values[7]	values[2]	376	1			T13	10		T183	12		T198	48
auto[0]	values[7]	values[3]	277	1			T4	7		T20	12		T223	9
auto[0]	values[7]	values[4]	183	1			T20	11		T194	11		T228	15
auto[0]	values[7]	values[5]	216	1			T8	12		T242	6		T53	14
auto[0]	values[7]	values[6]	237	1			T13	16		T33	12		T208	9
auto[0]	values[7]	values[7]	216	1			T20	8		T183	13		T175	10
auto[1]	values[0]	values[0]	231	1			T167	6		T20	33		T198	3
auto[1]	values[0]	values[1]	177	1			T226	10		T201	8		T243	39
auto[1]	values[0]	values[2]	168	1			T24	22		T15	8		T18	11
auto[1]	values[0]	values[3]	230	1			T13	5		T33	8		T42	12
auto[1]	values[0]	values[4]	165	1			T8	8		T42	7		T18	8
auto[1]	values[0]	values[5]	364	1			T33	109		T18	11		T20	10
auto[1]	values[0]	values[6]	125	1			T31	12		T14	9		T198	12
auto[1]	values[0]	values[7]	190	1			T184	8		T227	12		T228	12
auto[1]	values[1]	values[0]	126	1			T8	10		T14	9		T20	9
auto[1]	values[1]	values[1]	168	1			T8	12		T42	8		T244	4
auto[1]	values[1]	values[2]	244	1			T134	25		T184	8		T229	7
auto[1]	values[1]	values[3]	137	1			T166	5		T21	17		T194	17
auto[1]	values[1]	values[4]	248	1			T20	11		T223	8		T217	6
auto[1]	values[1]	values[5]	140	1			T167	13		T183	12		T128	28
auto[1]	values[1]	values[6]	264	1			T28	8		T20	103		T177	6
auto[1]	values[1]	values[7]	142	1			T201	5		T230	12		T178	9
auto[1]	values[2]	values[0]	116	1			T8	9		T183	9		T128	6
auto[1]	values[2]	values[1]	120	1			T20	10		T201	13		T65	11
auto[1]	values[2]	values[2]	234	1			T4	19		T167	106		T201	8
auto[1]	values[2]	values[3]	237	1			T13	12		T52	11		T53	6
auto[1]	values[2]	values[4]	241	1			T18	6		T20	7		T198	2
auto[1]	values[2]	values[5]	204	1			T52	24		T53	5		T19	9
auto[1]	values[2]	values[6]	201	1			T18	3		T20	7		T177	5
auto[1]	values[2]	values[7]	370	1			T31	16		T33	8		T14	7
auto[1]	values[3]	values[0]	310	1			T4	34		T33	103		T14	8
auto[1]	values[3]	values[1]	139	1			T4	10		T14	4		T168	12
auto[1]	values[3]	values[2]	170	1			T166	9		T14	11		T15	3
auto[1]	values[3]	values[3]	164	1			T167	6		T20	8		T194	44
auto[1]	values[3]	values[4]	187	1			T166	9		T177	7		T208	7
auto[1]	values[3]	values[5]	117	1			T13	4		T42	14		T18	12
auto[1]	values[3]	values[6]	238	1			T13	4		T184	53		T178	19
auto[1]	values[3]	values[7]	267	1			T53	22		T167	16		T205	5
auto[1]	values[4]	values[0]	246	1			T13	15		T33	43		T42	12
auto[1]	values[4]	values[1]	108	1			T20	7		T177	6		T196	4
auto[1]	values[4]	values[2]	160	1			T13	8		T53	13		T183	6
auto[1]	values[4]	values[3]	139	1			T167	27		T128	8		T178	11
auto[1]	values[4]	values[4]	315	1			T33	8		T42	12		T18	10
auto[1]	values[4]	values[5]	403	1			T167	8		T177	8		T183	12
auto[1]	values[4]	values[6]	280	1			T33	21		T18	9		T20	24
auto[1]	values[4]	values[7]	209	1			T245	24		T20	9		T194	40
auto[1]	values[5]	values[0]	202	1			T8	7		T14	10		T52	8
auto[1]	values[5]	values[1]	331	1			T14	41		T18	7		T53	9
auto[1]	values[5]	values[2]	132	1			T14	11		T18	55		T206	9
auto[1]	values[5]	values[3]	103	1			T190	8		T235	12		T236	27
auto[1]	values[5]	values[4]	172	1			T128	11		T178	9		T246	9
auto[1]	values[5]	values[5]	237	1			T177	6		T183	11		T223	7
auto[1]	values[5]	values[6]	283	1			T4	8		T18	6		T53	24
auto[1]	values[5]	values[7]	220	1			T14	10		T42	18		T20	8
auto[1]	values[6]	values[0]	120	1			T14	7		T167	16		T183	8
auto[1]	values[6]	values[1]	140	1			T198	11		T194	5		T217	20
auto[1]	values[6]	values[2]	75	1			T8	10		T201	20		T44	17
auto[1]	values[6]	values[3]	102	1			T18	21		T183	8		T184	10
auto[1]	values[6]	values[4]	172	1			T65	8		T155	37		T247	11
auto[1]	values[6]	values[5]	181	1			T53	12		T20	12		T134	10
auto[1]	values[6]	values[6]	115	1			T4	32		T208	5		T248	18
auto[1]	values[6]	values[7]	395	1			T42	3		T20	12		T222	20
auto[1]	values[7]	values[0]	111	1			T177	15		T21	12		T198	8
auto[1]	values[7]	values[1]	126	1			T167	13		T177	9		T182	8
auto[1]	values[7]	values[2]	186	1			T13	10		T249	4		T183	8
auto[1]	values[7]	values[3]	198	1			T4	13		T20	8		T213	6
auto[1]	values[7]	values[4]	172	1			T20	20		T194	9		T250	12
auto[1]	values[7]	values[5]	289	1			T8	8		T53	10		T20	5
auto[1]	values[7]	values[6]	140	1			T13	4		T33	11		T208	18
auto[1]	values[7]	values[7]	252	1			T20	17		T183	7		T128	9