Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14274

1

T4

71

T8

61

T11

5

auto[1]

46129

1

T1

2

T3

68

T4

106

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1310	1			T3	5		T4	3		T8	5
auto[4:7]	24718	1			T3	16		T4	74		T8	17
auto[8:11]	1330	1			T1	1		T4	5		T8	2
auto[12:15]	330	1			T4	2		T8	2		T13	1
auto[16:19]	343	1			T4	1		T8	6		T10	3
auto[20:23]	1825	1			T3	2		T4	8		T8	13
auto[24:27]	373	1			T3	1		T8	4		T82	1
auto[28:31]	323	1			T8	2		T10	1		T13	1
auto[32:35]	340	1			T8	1		T10	1		T13	2
auto[36:39]	340	1			T13	5		T33	2		T48	1
auto[40:43]	361	1			T8	2		T10	3		T13	1
auto[44:47]	304	1			T3	2		T4	1		T8	1
auto[48:51]	335	1			T8	3		T10	5		T32	1
auto[52:55]	1792	1			T3	2		T4	8		T8	7
auto[56:59]	1294	1			T3	1		T4	4		T8	8
auto[60:63]	317	1			T4	1		T10	2		T82	4
auto[64:67]	301	1			T3	3		T10	3		T13	4
auto[68:71]	340	1			T4	1		T8	2		T10	2
auto[72:75]	368	1			T3	1		T4	1		T10	3
auto[76:79]	341	1			T4	1		T10	1		T32	1
auto[80:83]	352	1			T4	1		T8	1		T13	2
auto[84:87]	371	1			T4	2		T33	4		T82	3
auto[88:91]	1815	1			T3	2		T4	7		T8	5
auto[92:95]	299	1			T10	3		T13	1		T33	1
auto[96:99]	308	1			T3	3		T4	1		T10	2
auto[100:103]	330	1			T8	2		T10	2		T13	1
auto[104:107]	1283	1			T3	1		T4	9		T6	1
auto[108:111]	325	1			T4	2		T8	1		T12	2
auto[112:115]	322	1			T10	1		T32	2		T33	1
auto[116:119]	315	1			T4	1		T8	1		T10	4
auto[120:123]	377	1			T12	2		T13	3		T33	1
auto[124:127]	314	1			T3	1		T8	3		T10	2
auto[128:131]	363	1			T3	1		T4	2		T8	1
auto[132:135]	337	1			T10	5		T32	1		T33	1
auto[136:139]	325	1			T3	2		T4	1		T8	2
auto[140:143]	291	1			T10	1		T14	3		T30	2
auto[144:147]	373	1			T3	3		T4	3		T10	2
auto[148:151]	329	1			T4	4		T8	1		T10	4
auto[152:155]	325	1			T4	2		T31	1		T33	3
auto[156:159]	1789	1			T3	4		T4	3		T8	3
auto[160:163]	332	1			T10	1		T48	3		T82	3
auto[164:167]	326	1			T3	2		T4	1		T10	4
auto[168:171]	315	1			T10	1		T13	1		T32	1
auto[172:175]	301	1			T8	4		T10	1		T13	1
auto[176:179]	321	1			T3	2		T8	2		T10	2
auto[180:183]	1804	1			T3	3		T4	5		T8	2
auto[184:187]	1311	1			T1	1		T4	3		T8	12
auto[188:191]	341	1			T3	2		T4	2		T8	5
auto[192:195]	330	1			T10	3		T82	1		T14	3
auto[196:199]	318	1			T4	1		T8	2		T13	2
auto[200:203]	306	1			T4	1		T13	1		T32	1
auto[204:207]	325	1			T10	2		T13	3		T82	3
auto[208:211]	362	1			T4	1		T10	2		T13	1
auto[212:215]	287	1			T4	2		T8	1		T10	1
auto[216:219]	286	1			T4	1		T10	2		T33	2
auto[220:223]	312	1			T3	2		T4	2		T13	1
auto[224:227]	360	1			T10	2		T13	1		T31	1
auto[228:231]	344	1			T3	1		T4	1		T8	1
auto[232:235]	2881	1			T3	2		T4	7		T6	1
auto[236:239]	343	1			T10	1		T13	3		T33	1
auto[240:243]	318	1			T3	2		T10	1		T48	1
auto[244:247]	347	1			T4	1		T31	1		T32	1
auto[248:251]	334	1			T8	1		T10	3		T33	6
auto[252:255]	371	1			T3	2		T4	1		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	461	1			T4	3		T8	1		T13	2
auto[0:3]	auto[1]	849	1			T3	5		T8	4		T10	11
auto[4:7]	auto[0]	4446	1			T4	11		T8	7		T11	4
auto[4:7]	auto[1]	20272	1			T3	16		T4	63		T8	10
auto[8:11]	auto[0]	516	1			T4	4		T13	3		T33	1
auto[8:11]	auto[1]	814	1			T1	1		T4	1		T8	2
auto[12:15]	auto[0]	76	1			T4	2		T8	1		T13	1
auto[12:15]	auto[1]	254	1			T8	1		T33	2		T54	2
auto[16:19]	auto[0]	92	1			T4	1		T8	4		T31	1
auto[16:19]	auto[1]	251	1			T8	2		T10	3		T13	1
auto[20:23]	auto[0]	509	1			T4	6		T8	6		T13	1
auto[20:23]	auto[1]	1316	1			T3	2		T4	2		T8	7
auto[24:27]	auto[0]	82	1			T166	1		T15	2		T52	2
auto[24:27]	auto[1]	291	1			T3	1		T8	4		T82	1
auto[28:31]	auto[0]	89	1			T31	1		T166	1		T14	3
auto[28:31]	auto[1]	234	1			T8	2		T10	1		T13	1
auto[32:35]	auto[0]	82	1			T8	1		T13	1		T33	1
auto[32:35]	auto[1]	258	1			T10	1		T13	1		T33	2
auto[36:39]	auto[0]	89	1			T33	2		T14	1		T18	1
auto[36:39]	auto[1]	251	1			T13	5		T48	1		T30	1
auto[40:43]	auto[0]	93	1			T13	1		T31	1		T33	2
auto[40:43]	auto[1]	268	1			T8	2		T10	3		T31	3
auto[44:47]	auto[0]	73	1			T4	1		T8	1		T13	2
auto[44:47]	auto[1]	231	1			T3	2		T10	3		T13	1
auto[48:51]	auto[0]	94	1			T8	1		T176	1		T210	1
auto[48:51]	auto[1]	241	1			T8	2		T10	5		T32	1
auto[52:55]	auto[0]	475	1			T4	4		T13	6		T33	3
auto[52:55]	auto[1]	1317	1			T3	2		T4	4		T8	7
auto[56:59]	auto[0]	463	1			T4	1		T8	7		T13	5
auto[56:59]	auto[1]	831	1			T3	1		T4	3		T8	1
auto[60:63]	auto[0]	68	1			T4	1		T14	2		T42	2
auto[60:63]	auto[1]	249	1			T10	2		T82	4		T14	8
auto[64:67]	auto[0]	86	1			T13	4		T33	1		T52	2
auto[64:67]	auto[1]	215	1			T3	3		T10	3		T32	1
auto[68:71]	auto[0]	84	1			T4	1		T13	2		T33	1
auto[68:71]	auto[1]	256	1			T8	2		T10	2		T13	3
auto[72:75]	auto[0]	83	1			T31	1		T33	1		T24	2
auto[72:75]	auto[1]	285	1			T3	1		T4	1		T10	3
auto[76:79]	auto[0]	87	1			T4	1		T176	2		T42	2
auto[76:79]	auto[1]	254	1			T10	1		T32	1		T14	5
auto[80:83]	auto[0]	86	1			T13	2		T24	1		T52	1
auto[80:83]	auto[1]	266	1			T4	1		T8	1		T48	1
auto[84:87]	auto[0]	92	1			T33	2		T14	3		T167	2
auto[84:87]	auto[1]	279	1			T4	2		T33	2		T82	3
auto[88:91]	auto[0]	484	1			T4	6		T8	2		T11	1
auto[88:91]	auto[1]	1331	1			T3	2		T4	1		T8	3
auto[92:95]	auto[0]	85	1			T13	1		T54	1		T14	1
auto[92:95]	auto[1]	214	1			T10	3		T33	1		T54	1
auto[96:99]	auto[0]	66	1			T31	1		T166	1		T14	2
auto[96:99]	auto[1]	242	1			T3	3		T4	1		T10	2
auto[100:103]	auto[0]	61	1			T8	2		T13	1		T33	2
auto[100:103]	auto[1]	269	1			T10	2		T33	2		T54	1
auto[104:107]	auto[0]	458	1			T4	5		T8	7		T13	4
auto[104:107]	auto[1]	825	1			T3	1		T4	4		T6	1
auto[108:111]	auto[0]	87	1			T12	1		T98	1		T78	1
auto[108:111]	auto[1]	238	1			T4	2		T8	1		T12	1
auto[112:115]	auto[0]	84	1			T33	1		T167	2		T20	1
auto[112:115]	auto[1]	238	1			T10	1		T32	2		T82	2
auto[116:119]	auto[0]	65	1			T13	1		T14	1		T18	4
auto[116:119]	auto[1]	250	1			T4	1		T8	1		T10	4
auto[120:123]	auto[0]	79	1			T12	1		T13	1		T52	1
auto[120:123]	auto[1]	298	1			T12	1		T13	2		T33	1
auto[124:127]	auto[0]	76	1			T8	3		T166	3		T14	2
auto[124:127]	auto[1]	238	1			T3	1		T10	2		T13	1
auto[128:131]	auto[0]	88	1			T8	1		T33	1		T14	2
auto[128:131]	auto[1]	275	1			T3	1		T4	2		T10	7
auto[132:135]	auto[0]	91	1			T18	7		T20	1		T201	3
auto[132:135]	auto[1]	246	1			T10	5		T32	1		T33	1
auto[136:139]	auto[0]	89	1			T4	1		T8	1		T13	2
auto[136:139]	auto[1]	236	1			T3	2		T8	1		T10	3
auto[140:143]	auto[0]	70	1			T14	3		T52	3		T18	1
auto[140:143]	auto[1]	221	1			T10	1		T30	2		T49	4
auto[144:147]	auto[0]	92	1			T4	1		T42	1		T53	2
auto[144:147]	auto[1]	281	1			T3	3		T4	2		T10	2
auto[148:151]	auto[0]	78	1			T4	3		T14	1		T28	1
auto[148:151]	auto[1]	251	1			T4	1		T8	1		T10	4
auto[152:155]	auto[0]	74	1			T4	2		T31	1		T33	1
auto[152:155]	auto[1]	251	1			T33	2		T82	4		T14	5
auto[156:159]	auto[0]	456	1			T4	1		T8	1		T13	1
auto[156:159]	auto[1]	1333	1			T3	4		T4	2		T8	2
auto[160:163]	auto[0]	81	1			T14	2		T52	1		T81	2
auto[160:163]	auto[1]	251	1			T10	1		T48	3		T82	3
auto[164:167]	auto[0]	74	1			T166	1		T14	2		T18	2
auto[164:167]	auto[1]	252	1			T3	2		T4	1		T10	4
auto[168:171]	auto[0]	82	1			T13	1		T33	2		T42	1
auto[168:171]	auto[1]	233	1			T10	1		T32	1		T16	5
auto[172:175]	auto[0]	71	1			T13	1		T166	1		T53	2
auto[172:175]	auto[1]	230	1			T8	4		T10	1		T32	1
auto[176:179]	auto[0]	56	1			T8	2		T42	2		T18	3
auto[176:179]	auto[1]	265	1			T3	2		T10	2		T48	1
auto[180:183]	auto[0]	451	1			T4	1		T13	9		T33	3
auto[180:183]	auto[1]	1353	1			T3	3		T4	4		T8	2
auto[184:187]	auto[0]	478	1			T4	2		T8	5		T13	3
auto[184:187]	auto[1]	833	1			T1	1		T4	1		T8	7
auto[188:191]	auto[0]	69	1			T4	2		T8	1		T31	3
auto[188:191]	auto[1]	272	1			T3	2		T8	4		T13	1
auto[192:195]	auto[0]	76	1			T167	1		T20	2		T183	4
auto[192:195]	auto[1]	254	1			T10	3		T82	1		T14	3
auto[196:199]	auto[0]	80	1			T4	1		T8	1		T14	1
auto[196:199]	auto[1]	238	1			T8	1		T13	2		T33	1
auto[200:203]	auto[0]	87	1			T13	1		T33	1		T14	1
auto[200:203]	auto[1]	219	1			T4	1		T32	1		T33	3
auto[204:207]	auto[0]	85	1			T13	3		T52	1		T42	3
auto[204:207]	auto[1]	240	1			T10	2		T82	3		T14	1
auto[208:211]	auto[0]	93	1			T4	1		T33	5		T166	2
auto[208:211]	auto[1]	269	1			T10	2		T13	1		T32	1
auto[212:215]	auto[0]	72	1			T14	2		T28	1		T52	1
auto[212:215]	auto[1]	215	1			T4	2		T8	1		T10	1
auto[216:219]	auto[0]	52	1			T33	1		T15	2		T18	1
auto[216:219]	auto[1]	234	1			T4	1		T10	2		T33	1
auto[220:223]	auto[0]	80	1			T4	1		T28	1		T201	1
auto[220:223]	auto[1]	232	1			T3	2		T4	1		T13	1
auto[224:227]	auto[0]	86	1			T13	1		T14	1		T52	1
auto[224:227]	auto[1]	274	1			T10	2		T31	1		T16	1
auto[228:231]	auto[0]	79	1			T4	1		T115	1		T52	1
auto[228:231]	auto[1]	265	1			T3	1		T8	1		T10	1
auto[232:235]	auto[0]	880	1			T4	6		T8	3		T13	3
auto[232:235]	auto[1]	2001	1			T3	2		T4	1		T6	1
auto[236:239]	auto[0]	89	1			T13	1		T42	5		T168	2
auto[236:239]	auto[1]	254	1			T10	1		T13	2		T33	1
auto[240:243]	auto[0]	72	1			T176	2		T78	1		T53	1
auto[240:243]	auto[1]	246	1			T3	2		T10	1		T48	1
auto[244:247]	auto[0]	98	1			T4	1		T166	2		T18	2
auto[244:247]	auto[1]	249	1			T31	1		T32	1		T48	2
auto[248:251]	auto[0]	87	1			T8	1		T33	2		T115	1
auto[248:251]	auto[1]	247	1			T10	3		T33	4		T115	1
auto[252:255]	auto[0]	87	1			T8	2		T166	1		T52	1
auto[252:255]	auto[1]	284	1			T3	2		T4	1		T13	2