Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	387	1			T4	4		T8	3		T13	5
auto[ReadAddrCrossIntoMailbox]	316	1			T4	1		T8	2		T13	2
auto[ReadAddrCrossOutOfMailbox]	310	1			T4	2		T8	3		T13	2
auto[ReadAddrCrossAllMailbox]	209	1			T13	1		T33	3		T14	1
auto[ReadAddrOutsideMailbox]	3572	1			T4	19		T8	19		T13	25

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2443

1

T4

19

T8

12

T13

14

auto[1]

2351

1

T4

7

T8

15

T13

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	776	1			T4	3		T8	1		T13	4
read_ops[0x0b]	824	1			T4	5		T8	2		T13	5
read_ops[0x3b]	768	1			T4	4		T8	6		T13	8
read_ops[0x6b]	795	1			T4	5		T8	7		T13	7
read_ops[0xbb]	795	1			T4	3		T8	7		T13	5
read_ops[0xeb]	836	1			T4	6		T8	4		T13	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T33	1		T201	1		T194	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T18	1		T20	1		T201	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T33	1		T18	1		T20	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T14	1		T20	4		T183	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T33	1		T53	1		T208	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T8	1		T177	1		T229	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T18	1		T226	1		T21	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T18	2		T167	2		T251	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T4	3		T13	2		T33	5
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T13	2		T33	1		T54	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	53	1			T4	1		T13	1		T53	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T8	1		T13	1		T31	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T33	1		T14	1		T53	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T198	1		T194	1		T134	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T4	1		T14	1		T52	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T13	1		T18	1		T223	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T53	1		T167	1		T201	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T183	1		T198	3		T194	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	327	1			T4	2		T13	2		T54	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T4	1		T8	1		T33	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T8	2		T52	1		T18	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T4	1		T18	2		T53	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T14	2		T18	1		T53	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T13	1		T53	1		T20	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T14	1		T177	2		T198	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T15	1		T18	1		T167	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T33	1		T167	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T20	1		T208	1		T243	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	298	1			T4	1		T8	2		T13	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	286	1			T4	2		T8	2		T13	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T4	1		T52	1		T167	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T13	1		T33	1		T14	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T4	1		T20	1		T177	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T8	1		T31	1		T14	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T52	1		T18	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T13	1		T18	1		T167	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T14	1		T167	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T13	1		T20	1		T201	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	294	1			T4	1		T8	5		T13	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T4	2		T8	1		T13	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T4	1		T14	1		T167	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T18	1		T183	1		T22	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T13	1		T201	1		T183	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	12	1			T53	1		T20	1		T198	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T167	1		T177	1		T183	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T8	1		T18	1		T20	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T226	1		T205	1		T128	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T33	1		T65	1		T44	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T4	1		T8	1		T13	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	317	1			T4	1		T8	5		T13	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T42	1		T18	1		T20	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T13	2		T14	1		T15	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T8	1		T33	2		T42	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T18	1		T53	2		T167	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T4	1		T8	1		T14	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T18	3		T53	1		T167	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T33	1		T60	1		T134	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T53	1		T167	2		T22	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	321	1			T4	5		T13	1		T33	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	280	1			T8	2		T13	3		T31	1