Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4072	1			T8	40		T13	20		T33	114
values[1]	3622	1			T4	20		T13	40		T15	23
values[2]	3877	1			T8	20		T12	4		T31	21
values[3]	3353	1			T8	20		T13	20		T31	20
values[4]	4002	1			T8	20		T13	20		T33	139
values[5]	3643	1			T4	45		T11	10		T166	20
values[6]	3479	1			T4	68		T8	40		T33	157
values[7]	4453	1			T4	44		T13	60		T33	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3221	1			T4	20		T12	4		T33	113
values[1]	4298	1			T4	40		T8	20		T13	40
values[2]	3605	1			T98	85		T14	20		T52	22
values[3]	3360	1			T8	20		T33	57		T115	6
values[4]	4826	1			T4	44		T13	60		T33	62
values[5]	3630	1			T8	20		T13	20		T31	21
values[6]	3848	1			T8	40		T11	10		T14	20
values[7]	3713	1			T4	73		T8	40		T13	40

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29733

1

T4

173

T8

133

T11

10

auto[1]

768

1

T4

4

T8

7

T13

12

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	323	1			T176	22		T42	18		T252	2
auto[0]	values[0]	values[1]	537	1			T33	21		T167	20		T155	47
auto[0]	values[0]	values[2]	477	1			T98	85		T53	20		T177	38
auto[0]	values[0]	values[3]	724	1			T8	20		T33	30		T198	21
auto[0]	values[0]	values[4]	527	1			T13	19		T53	24		T253	4
auto[0]	values[0]	values[5]	456	1			T200	2		T195	22		T222	12
auto[0]	values[0]	values[6]	483	1			T8	19		T192	16		T87	22
auto[0]	values[0]	values[7]	451	1			T33	58		T18	20		T53	20
auto[0]	values[1]	values[0]	384	1			T183	20		T205	20		T186	20
auto[0]	values[1]	values[1]	546	1			T4	20		T15	23		T52	26
auto[0]	values[1]	values[2]	469	1			T20	20		T201	23		T254	8
auto[0]	values[1]	values[3]	177	1			T225	4		T20	20		T183	19
auto[0]	values[1]	values[4]	713	1			T13	15		T53	19		T20	19
auto[0]	values[1]	values[5]	498	1			T13	19		T18	22		T168	8
auto[0]	values[1]	values[6]	340	1			T242	6		T20	20		T177	20
auto[0]	values[1]	values[7]	394	1			T177	20		T21	23		T194	46
auto[0]	values[2]	values[0]	227	1			T12	4		T231	6		T255	2
auto[0]	values[2]	values[1]	358	1			T18	88		T223	19		T256	46
auto[0]	values[2]	values[2]	391	1			T52	22		T42	21		T210	18
auto[0]	values[2]	values[3]	555	1			T166	20		T14	20		T167	27
auto[0]	values[2]	values[4]	652	1			T14	87		T53	20		T167	31
auto[0]	values[2]	values[5]	367	1			T31	21		T20	20		T226	20
auto[0]	values[2]	values[6]	450	1			T14	20		T52	23		T42	22
auto[0]	values[2]	values[7]	768	1			T8	16		T33	20		T14	19
auto[0]	values[3]	values[0]	362	1			T167	39		T20	20		T241	4
auto[0]	values[3]	values[1]	614	1			T31	19		T54	73		T14	20
auto[0]	values[3]	values[2]	185	1			T185	10		T21	20		T208	24
auto[0]	values[3]	values[3]	293	1			T19	23		T20	59		T257	26
auto[0]	values[3]	values[4]	299	1			T14	23		T20	127		T183	20
auto[0]	values[3]	values[5]	511	1			T162	4		T20	20		T217	20
auto[0]	values[3]	values[6]	373	1			T53	22		T20	20		T201	45
auto[0]	values[3]	values[7]	641	1			T8	20		T13	19		T14	50
auto[0]	values[4]	values[0]	481	1			T33	113		T78	18		T18	18
auto[0]	values[4]	values[1]	599	1			T8	19		T13	19		T53	20
auto[0]	values[4]	values[2]	370	1			T20	29		T201	19		T198	20
auto[0]	values[4]	values[3]	531	1			T33	25		T20	41		T128	20
auto[0]	values[4]	values[4]	675	1			T27	6		T79	12		T208	38
auto[0]	values[4]	values[5]	374	1			T20	23		T201	20		T258	6
auto[0]	values[4]	values[6]	537	1			T52	20		T81	16		T128	21
auto[0]	values[4]	values[7]	320	1			T24	22		T18	47		T251	14
auto[0]	values[5]	values[0]	513	1			T233	4		T18	20		T201	19
auto[0]	values[5]	values[1]	499	1			T14	20		T20	61		T249	4
auto[0]	values[5]	values[2]	298	1			T14	20		T167	20		T128	19
auto[0]	values[5]	values[3]	446	1			T42	24		T205	19		T223	77
auto[0]	values[5]	values[4]	605	1			T18	22		T177	19		T128	23
auto[0]	values[5]	values[5]	600	1			T166	20		T53	38		T198	20
auto[0]	values[5]	values[6]	330	1			T11	10		T15	20		T198	17
auto[0]	values[5]	values[7]	268	1			T4	44		T194	49		T217	37
auto[0]	values[6]	values[0]	365	1			T4	20		T28	20		T88	4
auto[0]	values[6]	values[1]	398	1			T4	19		T33	116		T196	4
auto[0]	values[6]	values[2]	591	1			T18	20		T167	114		T223	130
auto[0]	values[6]	values[3]	328	1			T115	6		T14	28		T18	21
auto[0]	values[6]	values[4]	491	1			T33	36		T259	10		T155	21
auto[0]	values[6]	values[5]	305	1			T8	19		T240	2		T183	18
auto[0]	values[6]	values[6]	564	1			T8	20		T52	20		T42	46
auto[0]	values[6]	values[7]	369	1			T4	27		T53	21		T167	20
auto[0]	values[7]	values[0]	504	1			T213	6		T260	31		T247	23
auto[0]	values[7]	values[1]	644	1			T13	20		T14	20		T42	20
auto[0]	values[7]	values[2]	749	1			T42	20		T245	22		T167	39
auto[0]	values[7]	values[3]	225	1			T20	22		T178	20		T138	17
auto[0]	values[7]	values[4]	752	1			T4	43		T13	19		T33	23
auto[0]	values[7]	values[5]	401	1			T18	20		T201	20		T194	40
auto[0]	values[7]	values[6]	663	1			T211	16		T167	37		T20	29
auto[0]	values[7]	values[7]	393	1			T13	18		T244	4		T19	20
auto[1]	values[0]	values[0]	4	1			T42	2		T261	2		-	-
auto[1]	values[0]	values[1]	13	1			T33	4		T247	1		T262	4
auto[1]	values[0]	values[2]	11	1			T177	2		T260	1		T236	1
auto[1]	values[0]	values[3]	16	1			T33	1		T184	1		T229	4
auto[1]	values[0]	values[4]	9	1			T13	1		T134	2		T219	1
auto[1]	values[0]	values[5]	25	1			T222	8		T177	4		T194	1
auto[1]	values[0]	values[6]	13	1			T8	1		T183	1		T223	3
auto[1]	values[0]	values[7]	3	1			T134	1		T44	2		-	-
auto[1]	values[1]	values[0]	8	1			T246	1		T179	5		T263	2
auto[1]	values[1]	values[1]	11	1			T52	2		T208	2		T190	1
auto[1]	values[1]	values[2]	8	1			T201	1		T264	3		T265	2
auto[1]	values[1]	values[3]	3	1			T183	1		T266	2		-	-
auto[1]	values[1]	values[4]	25	1			T13	5		T53	1		T20	2
auto[1]	values[1]	values[5]	17	1			T13	1		T168	4		T134	3
auto[1]	values[1]	values[6]	11	1			T44	2		T267	4		T268	3
auto[1]	values[1]	values[7]	18	1			T21	1		T206	2		T267	2
auto[1]	values[2]	values[0]	3	1			T247	1		T269	2		-	-
auto[1]	values[2]	values[1]	8	1			T223	1		T139	1		T270	1
auto[1]	values[2]	values[2]	18	1			T42	2		T183	2		T208	2
auto[1]	values[2]	values[3]	22	1			T183	3		T198	2		T194	1
auto[1]	values[2]	values[4]	23	1			T14	2		T53	2		T167	2
auto[1]	values[2]	values[5]	8	1			T208	1		T190	3		T271	4
auto[1]	values[2]	values[6]	16	1			T42	1		T53	1		T208	3
auto[1]	values[2]	values[7]	11	1			T8	4		T14	1		T184	3
auto[1]	values[3]	values[0]	5	1			T177	1		T128	2		T272	1
auto[1]	values[3]	values[1]	13	1			T31	1		T177	1		T273	2
auto[1]	values[3]	values[2]	4	1			T274	2		T275	2		-	-
auto[1]	values[3]	values[3]	3	1			T19	1		T20	1		T178	1
auto[1]	values[3]	values[4]	9	1			T14	2		T20	3		T227	2
auto[1]	values[3]	values[5]	15	1			T204	4		T276	3		T277	1
auto[1]	values[3]	values[6]	6	1			T201	2		T229	2		T138	2
auto[1]	values[3]	values[7]	20	1			T13	1		T167	3		T201	2
auto[1]	values[4]	values[0]	15	1			T18	2		T278	1		T265	3
auto[1]	values[4]	values[1]	21	1			T8	1		T13	1		T167	3
auto[1]	values[4]	values[2]	8	1			T201	3		T270	3		T279	2
auto[1]	values[4]	values[3]	21	1			T33	1		T276	1		T280	3
auto[1]	values[4]	values[4]	12	1			T208	4		T134	1		T44	1
auto[1]	values[4]	values[5]	10	1			T20	1		T205	2		T264	2
auto[1]	values[4]	values[6]	10	1			T134	4		T206	1		T180	1
auto[1]	values[4]	values[7]	18	1			T219	6		T281	1		T282	2
auto[1]	values[5]	values[0]	14	1			T201	1		T128	3		T204	1
auto[1]	values[5]	values[1]	16	1			T20	1		T223	3		T178	1
auto[1]	values[5]	values[2]	7	1			T128	2		T180	1		T283	4
auto[1]	values[5]	values[3]	9	1			T205	1		T223	4		T203	2
auto[1]	values[5]	values[4]	6	1			T177	1		T184	1		T178	1
auto[1]	values[5]	values[5]	11	1			T53	2		T273	3		T280	1
auto[1]	values[5]	values[6]	10	1			T198	3		T134	1		T217	2
auto[1]	values[5]	values[7]	11	1			T4	1		T194	1		T217	3
auto[1]	values[6]	values[0]	3	1			T227	1		T182	1		T284	1
auto[1]	values[6]	values[1]	10	1			T4	1		T33	2		T246	2
auto[1]	values[6]	values[2]	4	1			T276	1		T285	2		T286	1
auto[1]	values[6]	values[3]	1	1			T203	1		-	-		-	-
auto[1]	values[6]	values[4]	9	1			T33	3		T229	1		T287	1
auto[1]	values[6]	values[5]	14	1			T8	1		T183	2		T128	3
auto[1]	values[6]	values[6]	13	1			T42	1		T20	2		T223	4
auto[1]	values[6]	values[7]	14	1			T4	1		T194	2		T250	2
auto[1]	values[7]	values[0]	10	1			T260	1		T288	1		T289	1
auto[1]	values[7]	values[1]	11	1			T53	1		T20	1		T206	3
auto[1]	values[7]	values[2]	15	1			T245	2		T167	2		T203	1
auto[1]	values[7]	values[3]	6	1			T138	3		T290	1		T279	2
auto[1]	values[7]	values[4]	19	1			T4	1		T13	1		T18	2
auto[1]	values[7]	values[5]	18	1			T206	2		T246	7		T291	1
auto[1]	values[7]	values[6]	29	1			T167	3		T20	2		T201	2
auto[1]	values[7]	values[7]	14	1			T13	2		T19	2		T128	2