Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	847	1			T16	17		T18	7		T19	4
all_values[1]	847	1			T16	17		T18	7		T19	4
all_values[2]	847	1			T16	17		T18	7		T19	4
all_values[3]	847	1			T16	17		T18	7		T19	4
all_values[4]	847	1			T16	17		T18	7		T19	4
all_values[5]	847	1			T16	17		T18	7		T19	4
all_values[6]	847	1			T16	17		T18	7		T19	4
all_values[7]	847	1			T16	17		T18	7		T19	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3658

1

T16

61

T18

27

T19

25

auto[1]

3118

1

T16

75

T18

29

T19

7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2724

1

T16

60

T18

18

T19

12

auto[1]

4052

1

T16

76

T18

38

T19

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3836

1

T16

76

T18

30

T19

18

auto[1]

2940

1

T16

60

T18

26

T19

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	184	1			T16	2		T21	1		T22	1
all_values[0]	auto[0]	auto[0]	auto[1]	78	1			T16	1		T18	2		T19	2
all_values[0]	auto[0]	auto[1]	auto[0]	143	1			T16	4		T18	1		T21	1
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T16	2		T18	3		T21	2
all_values[0]	auto[1]	auto[0]	auto[1]	193	1			T16	4		T18	1		T19	1
all_values[0]	auto[1]	auto[1]	auto[1]	167	1			T16	4		T19	1		T21	3
all_values[1]	auto[0]	auto[0]	auto[0]	188	1			T16	5		T18	1		T19	3
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T16	1		T21	3		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	144	1			T16	3		T18	2		T19	1
all_values[1]	auto[0]	auto[1]	auto[1]	67	1			T16	1		T18	1		T22	1
all_values[1]	auto[1]	auto[0]	auto[1]	205	1			T16	6		T21	2		T22	2
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T16	1		T18	3		T21	5
all_values[2]	auto[0]	auto[0]	auto[0]	165	1			T16	2		T19	1		T21	2
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T18	1		T19	2		T22	1
all_values[2]	auto[0]	auto[1]	auto[0]	145	1			T16	4		T18	1		T21	3
all_values[2]	auto[0]	auto[1]	auto[1]	91	1			T16	2		T18	1		T21	1
all_values[2]	auto[1]	auto[0]	auto[1]	206	1			T16	4		T18	3		T21	2
all_values[2]	auto[1]	auto[1]	auto[1]	158	1			T16	5		T18	1		T19	1
all_values[3]	auto[0]	auto[0]	auto[0]	164	1			T16	1		T18	1		T21	1
all_values[3]	auto[0]	auto[0]	auto[1]	86	1			T21	2		T22	1		T23	1
all_values[3]	auto[0]	auto[1]	auto[0]	153	1			T16	7		T18	3		T19	1
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T16	1		T21	2		T22	3
all_values[3]	auto[1]	auto[0]	auto[1]	200	1			T16	3		T18	2		T19	1
all_values[3]	auto[1]	auto[1]	auto[1]	164	1			T16	5		T18	1		T19	2
all_values[4]	auto[0]	auto[0]	auto[0]	181	1			T16	5		T18	1		T19	3
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T16	1		T18	2		T21	1
all_values[4]	auto[0]	auto[1]	auto[0]	138	1			T16	5		T21	4		T22	2
all_values[4]	auto[0]	auto[1]	auto[1]	86	1			T16	1		T21	2		T55	1
all_values[4]	auto[1]	auto[0]	auto[1]	193	1			T16	2		T18	1		T19	1
all_values[4]	auto[1]	auto[1]	auto[1]	168	1			T16	3		T18	3		T21	3
all_values[5]	auto[0]	auto[0]	auto[0]	248	1			T16	3		T18	2		T19	2
all_values[5]	auto[0]	auto[1]	auto[0]	229	1			T16	8		T18	1		T21	3
all_values[5]	auto[1]	auto[0]	auto[1]	213	1			T16	2		T18	3		T19	1
all_values[5]	auto[1]	auto[1]	auto[1]	157	1			T16	4		T18	1		T19	1
all_values[6]	auto[0]	auto[0]	auto[0]	152	1			T16	3		T18	2		T19	1
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T16	1		T18	1		T19	1
all_values[6]	auto[0]	auto[1]	auto[0]	154	1			T16	2		T21	4		T22	5
all_values[6]	auto[0]	auto[1]	auto[1]	75	1			T16	1		T18	1		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	219	1			T16	6		T18	2		T19	2
all_values[6]	auto[1]	auto[1]	auto[1]	165	1			T16	4		T18	1		T21	2
all_values[7]	auto[0]	auto[0]	auto[0]	192	1			T16	3		T18	1		T23	2
all_values[7]	auto[0]	auto[0]	auto[1]	65	1			T16	2		T19	1		T21	4
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T16	3		T18	2		T22	3
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T16	2		T21	1		T22	1
all_values[7]	auto[1]	auto[0]	auto[1]	196	1			T16	4		T18	1		T19	3
all_values[7]	auto[1]	auto[1]	auto[1]	178	1			T16	3		T18	3		T21	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal