Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1753

1

T2

1

T3

7

T31

4

auto[1]

1732

1

T2

2

T3

8

T31

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1909

1

T3

15

T31

5

T32

13

auto[1]

1576

1

T2

3

T32

6

T33

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2768

1

T2

3

T3

12

T31

3

auto[1]

717

1

T3

3

T31

2

T32

8

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	733	1			T3	1		T31	1		T32	6
valid[1]	659	1			T2	1		T3	2		T32	1
valid[2]	712	1			T3	4		T31	1		T32	1
valid[3]	681	1			T2	1		T3	5		T31	2
valid[4]	700	1			T2	1		T3	3		T31	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	132	1			T14	1		T15	1		T49	1
auto[0]	auto[0]	valid[0]	auto[1]	168	1			T32	1		T33	1		T35	5
auto[0]	auto[0]	valid[1]	auto[0]	121	1			T3	1		T32	1		T33	1
auto[0]	auto[0]	valid[1]	auto[1]	152	1			T34	2		T35	3		T29	1
auto[0]	auto[0]	valid[2]	auto[0]	129	1			T3	3		T33	1		T14	4
auto[0]	auto[0]	valid[2]	auto[1]	175	1			T33	1		T34	3		T35	2
auto[0]	auto[0]	valid[3]	auto[0]	107	1			T3	1		T31	1		T33	1
auto[0]	auto[0]	valid[3]	auto[1]	149	1			T32	3		T34	3		T39	1
auto[0]	auto[0]	valid[4]	auto[0]	117	1			T3	1		T31	1		T32	1
auto[0]	auto[0]	valid[4]	auto[1]	153	1			T2	1		T34	1		T35	2
auto[0]	auto[1]	valid[0]	auto[0]	123	1			T3	1		T31	1		T32	2
auto[0]	auto[1]	valid[0]	auto[1]	159	1			T49	1		T312	1		T160	3
auto[0]	auto[1]	valid[1]	auto[0]	104	1			T15	2		T52	3		T42	2
auto[0]	auto[1]	valid[1]	auto[1]	140	1			T2	1		T29	2		T49	1
auto[0]	auto[1]	valid[2]	auto[0]	118	1			T3	1		T14	1		T29	2
auto[0]	auto[1]	valid[2]	auto[1]	159	1			T34	3		T35	2		T49	1
auto[0]	auto[1]	valid[3]	auto[0]	107	1			T3	3		T36	1		T29	1
auto[0]	auto[1]	valid[3]	auto[1]	158	1			T2	1		T32	1		T34	2
auto[0]	auto[1]	valid[4]	auto[0]	134	1			T3	1		T32	1		T36	2
auto[0]	auto[1]	valid[4]	auto[1]	163	1			T32	1		T33	1		T34	3
auto[1]	auto[0]	valid[0]	auto[0]	77	1			T32	2		T33	1		T14	3
auto[1]	auto[0]	valid[1]	auto[0]	66	1			T38	1		T14	2		T29	1
auto[1]	auto[0]	valid[2]	auto[0]	64	1			T31	1		T14	1		T49	1
auto[1]	auto[0]	valid[3]	auto[0]	76	1			T31	1		T32	1		T52	1
auto[1]	auto[0]	valid[4]	auto[0]	67	1			T3	1		T33	1		T36	1
auto[1]	auto[1]	valid[0]	auto[0]	74	1			T32	1		T38	1		T15	1
auto[1]	auto[1]	valid[1]	auto[0]	76	1			T3	1		T14	1		T29	1
auto[1]	auto[1]	valid[2]	auto[0]	67	1			T32	1		T14	1		T15	2
auto[1]	auto[1]	valid[3]	auto[0]	84	1			T3	1		T32	1		T37	1
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T32	2		T14	1		T52	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal