Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50640

1

T3

393

T31

122

T32

257

auto[1]

16527

1

T2

47

T32

54

T33

73

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48520

1

T2

47

T3

260

T31

76

auto[1]

18647

1

T3

133

T31

46

T32

106

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34545	1			T2	23		T3	195		T31	71
others[1]	5715	1			T2	4		T3	45		T31	13
others[2]	5679	1			T2	2		T3	30		T31	15
others[3]	6411	1			T2	8		T3	40		T31	9
interest[1]	3634	1			T2	2		T3	19		T31	3
interest[4]	22598	1			T2	13		T3	126		T31	53
interest[64]	11183	1			T2	8		T3	64		T31	11

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16291	1			T3	129		T31	39		T32	80
auto[0]	auto[0]	others[1]	2761	1			T3	27		T31	8		T32	16
auto[0]	auto[0]	others[2]	2727	1			T3	26		T31	10		T32	14
auto[0]	auto[0]	others[3]	3047	1			T3	20		T31	8		T32	8
auto[0]	auto[0]	interest[1]	1762	1			T3	14		T31	3		T32	4
auto[0]	auto[0]	interest[4]	10539	1			T3	78		T31	30		T32	59
auto[0]	auto[0]	interest[64]	5405	1			T3	44		T31	8		T32	29
auto[0]	auto[1]	others[0]	8578	1			T2	23		T32	25		T33	30
auto[0]	auto[1]	others[1]	1363	1			T2	4		T32	6		T33	7
auto[0]	auto[1]	others[2]	1393	1			T2	2		T32	5		T33	11
auto[0]	auto[1]	others[3]	1563	1			T2	8		T32	3		T33	12
auto[0]	auto[1]	interest[1]	910	1			T2	2		T32	3		T33	2
auto[0]	auto[1]	interest[4]	5717	1			T2	13		T32	16		T33	19
auto[0]	auto[1]	interest[64]	2720	1			T2	8		T32	12		T33	11
auto[1]	auto[0]	others[0]	9676	1			T3	66		T31	32		T32	60
auto[1]	auto[0]	others[1]	1591	1			T3	18		T31	5		T32	9
auto[1]	auto[0]	others[2]	1559	1			T3	4		T31	5		T32	12
auto[1]	auto[0]	others[3]	1801	1			T3	20		T31	1		T32	9
auto[1]	auto[0]	interest[1]	962	1			T3	5		T32	6		T33	9
auto[1]	auto[0]	interest[4]	6342	1			T3	48		T31	23		T32	38
auto[1]	auto[0]	interest[64]	3058	1			T3	20		T31	3		T32	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal