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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.11 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1149
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T114 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2238256412 Aug 15 04:30:36 PM PDT 24 Aug 15 04:30:51 PM PDT 24 3160709829 ps
T112 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2866739864 Aug 15 04:29:33 PM PDT 24 Aug 15 04:29:59 PM PDT 24 4618820661 ps
T1033 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4108195657 Aug 15 04:29:34 PM PDT 24 Aug 15 04:29:37 PM PDT 24 455507681 ps
T109 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1133425401 Aug 15 04:30:14 PM PDT 24 Aug 15 04:30:18 PM PDT 24 54128997 ps
T1034 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.399129319 Aug 15 04:29:38 PM PDT 24 Aug 15 04:29:39 PM PDT 24 23115494 ps
T152 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.369844686 Aug 15 04:29:39 PM PDT 24 Aug 15 04:29:43 PM PDT 24 773075427 ps
T97 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2683784300 Aug 15 04:30:30 PM PDT 24 Aug 15 04:30:34 PM PDT 24 211189074 ps
T101 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3530519059 Aug 15 04:29:47 PM PDT 24 Aug 15 04:29:51 PM PDT 24 415030856 ps
T1035 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4233182660 Aug 15 04:29:33 PM PDT 24 Aug 15 04:29:35 PM PDT 24 359733497 ps
T1036 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4031919798 Aug 15 04:30:24 PM PDT 24 Aug 15 04:30:26 PM PDT 24 56446315 ps
T153 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.408920714 Aug 15 04:29:54 PM PDT 24 Aug 15 04:30:09 PM PDT 24 1317568003 ps
T1037 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3578189392 Aug 15 04:29:56 PM PDT 24 Aug 15 04:29:57 PM PDT 24 42425885 ps
T170 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.315055306 Aug 15 04:29:43 PM PDT 24 Aug 15 04:29:57 PM PDT 24 569485300 ps
T1038 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2299511159 Aug 15 04:30:15 PM PDT 24 Aug 15 04:30:15 PM PDT 24 166790599 ps
T85 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1509255331 Aug 15 04:29:38 PM PDT 24 Aug 15 04:29:39 PM PDT 24 30835089 ps
T171 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3363255769 Aug 15 04:29:50 PM PDT 24 Aug 15 04:30:08 PM PDT 24 286372985 ps
T1039 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3858156315 Aug 15 04:29:39 PM PDT 24 Aug 15 04:29:39 PM PDT 24 14350065 ps
T1040 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.628252343 Aug 15 04:29:29 PM PDT 24 Aug 15 04:29:31 PM PDT 24 159180102 ps
T99 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1518961701 Aug 15 04:29:46 PM PDT 24 Aug 15 04:29:51 PM PDT 24 71379238 ps
T106 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3715655011 Aug 15 04:29:51 PM PDT 24 Aug 15 04:29:54 PM PDT 24 107522975 ps
T1041 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1767904213 Aug 15 04:29:59 PM PDT 24 Aug 15 04:30:00 PM PDT 24 21266562 ps
T1042 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2313797999 Aug 15 04:29:59 PM PDT 24 Aug 15 04:30:00 PM PDT 24 15411312 ps
T1043 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2464788712 Aug 15 04:29:34 PM PDT 24 Aug 15 04:29:36 PM PDT 24 276641183 ps
T1044 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3105376143 Aug 15 04:29:55 PM PDT 24 Aug 15 04:29:59 PM PDT 24 107891071 ps
T1045 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1812638243 Aug 15 04:30:20 PM PDT 24 Aug 15 04:30:23 PM PDT 24 161478691 ps
T1046 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3318849442 Aug 15 04:29:34 PM PDT 24 Aug 15 04:29:35 PM PDT 24 24582540 ps
T1047 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3498307449 Aug 15 04:30:06 PM PDT 24 Aug 15 04:30:07 PM PDT 24 39284924 ps
T1048 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3575045220 Aug 15 04:30:04 PM PDT 24 Aug 15 04:30:05 PM PDT 24 16774366 ps
T1049 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4020388503 Aug 15 04:29:38 PM PDT 24 Aug 15 04:29:38 PM PDT 24 14466917 ps
T1050 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3559108351 Aug 15 04:30:20 PM PDT 24 Aug 15 04:30:22 PM PDT 24 101426226 ps
T172 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2347355894 Aug 15 04:29:50 PM PDT 24 Aug 15 04:29:57 PM PDT 24 108339152 ps
T1051 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2040154931 Aug 15 04:30:03 PM PDT 24 Aug 15 04:30:05 PM PDT 24 222490544 ps
T1052 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1211877257 Aug 15 04:30:08 PM PDT 24 Aug 15 04:30:09 PM PDT 24 20087715 ps
T111 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1396956636 Aug 15 04:30:23 PM PDT 24 Aug 15 04:30:26 PM PDT 24 43266564 ps
T1053 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1182466170 Aug 15 04:29:39 PM PDT 24 Aug 15 04:29:41 PM PDT 24 26634171 ps
T1054 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1522848231 Aug 15 04:29:49 PM PDT 24 Aug 15 04:29:51 PM PDT 24 118505251 ps
T1055 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4248361285 Aug 15 04:29:38 PM PDT 24 Aug 15 04:29:40 PM PDT 24 57965772 ps
T1056 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2298795612 Aug 15 04:30:07 PM PDT 24 Aug 15 04:30:09 PM PDT 24 118693196 ps
T1057 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.888560577 Aug 15 04:30:04 PM PDT 24 Aug 15 04:30:06 PM PDT 24 66245150 ps
T1058 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2897540065 Aug 15 04:29:24 PM PDT 24 Aug 15 04:29:25 PM PDT 24 13691708 ps
T1059 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.997001000 Aug 15 04:29:49 PM PDT 24 Aug 15 04:29:49 PM PDT 24 20201586 ps
T1060 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3675445657 Aug 15 04:30:20 PM PDT 24 Aug 15 04:30:21 PM PDT 24 14338467 ps
T1061 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.159454223 Aug 15 04:29:57 PM PDT 24 Aug 15 04:29:58 PM PDT 24 25935033 ps
T1062 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1538231885 Aug 15 04:30:08 PM PDT 24 Aug 15 04:30:10 PM PDT 24 249109484 ps
T100 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.612118237 Aug 15 04:29:31 PM PDT 24 Aug 15 04:29:35 PM PDT 24 150280111 ps
T108 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3206841786 Aug 15 04:29:46 PM PDT 24 Aug 15 04:30:08 PM PDT 24 3945464498 ps
T1063 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1500083583 Aug 15 04:29:52 PM PDT 24 Aug 15 04:29:53 PM PDT 24 136095413 ps
T1064 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.211544403 Aug 15 04:29:36 PM PDT 24 Aug 15 04:29:39 PM PDT 24 333472722 ps
T1065 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1576572426 Aug 15 04:29:58 PM PDT 24 Aug 15 04:29:59 PM PDT 24 35189197 ps
T1066 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1639776131 Aug 15 04:30:00 PM PDT 24 Aug 15 04:30:06 PM PDT 24 22574835 ps
T1067 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1338631880 Aug 15 04:29:38 PM PDT 24 Aug 15 04:29:40 PM PDT 24 52672973 ps
T1068 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3026563607 Aug 15 04:29:57 PM PDT 24 Aug 15 04:30:01 PM PDT 24 113607710 ps
T102 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.467937174 Aug 15 04:29:39 PM PDT 24 Aug 15 04:29:42 PM PDT 24 144190378 ps
T1069 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1066079933 Aug 15 04:30:04 PM PDT 24 Aug 15 04:30:25 PM PDT 24 852345274 ps
T1070 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1591589547 Aug 15 04:29:37 PM PDT 24 Aug 15 04:29:41 PM PDT 24 93124349 ps
T107 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1743162494 Aug 15 04:29:39 PM PDT 24 Aug 15 04:29:45 PM PDT 24 1248759976 ps
T1071 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4094828775 Aug 15 04:29:51 PM PDT 24 Aug 15 04:29:59 PM PDT 24 388220435 ps
T110 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3596900614 Aug 15 04:29:50 PM PDT 24 Aug 15 04:29:56 PM PDT 24 867165646 ps
T120 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4078376752 Aug 15 04:30:13 PM PDT 24 Aug 15 04:30:15 PM PDT 24 355150411 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2716361464 Aug 15 04:29:42 PM PDT 24 Aug 15 04:30:09 PM PDT 24 6677431062 ps
T1073 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2724027621 Aug 15 04:29:48 PM PDT 24 Aug 15 04:29:50 PM PDT 24 33025392 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3139230478 Aug 15 04:29:50 PM PDT 24 Aug 15 04:29:53 PM PDT 24 170868227 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.306003233 Aug 15 04:29:32 PM PDT 24 Aug 15 04:29:48 PM PDT 24 3716161992 ps
T1076 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3651889053 Aug 15 04:29:58 PM PDT 24 Aug 15 04:29:59 PM PDT 24 15874688 ps
T1077 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1285085103 Aug 15 04:29:51 PM PDT 24 Aug 15 04:29:52 PM PDT 24 13430651 ps
T1078 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3283252779 Aug 15 04:30:18 PM PDT 24 Aug 15 04:30:18 PM PDT 24 15685204 ps
T1079 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2977701493 Aug 15 04:30:05 PM PDT 24 Aug 15 04:30:07 PM PDT 24 142233028 ps
T104 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.533518286 Aug 15 04:30:08 PM PDT 24 Aug 15 04:30:11 PM PDT 24 247279277 ps
T1080 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2107587418 Aug 15 04:30:01 PM PDT 24 Aug 15 04:30:05 PM PDT 24 39096591 ps
T121 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1154318711 Aug 15 04:29:37 PM PDT 24 Aug 15 04:29:39 PM PDT 24 30784065 ps
T1081 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.665081128 Aug 15 04:30:04 PM PDT 24 Aug 15 04:30:05 PM PDT 24 76605176 ps
T1082 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.878346084 Aug 15 04:29:36 PM PDT 24 Aug 15 04:29:57 PM PDT 24 7423554264 ps
T1083 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2307181088 Aug 15 04:29:50 PM PDT 24 Aug 15 04:29:53 PM PDT 24 217551226 ps
T1084 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1030907934 Aug 15 04:29:35 PM PDT 24 Aug 15 04:29:37 PM PDT 24 88193503 ps
T1085 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1069365877 Aug 15 04:30:20 PM PDT 24 Aug 15 04:30:22 PM PDT 24 278817799 ps
T1086 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.115709587 Aug 15 04:30:03 PM PDT 24 Aug 15 04:30:04 PM PDT 24 14365444 ps
T1087 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3029666399 Aug 15 04:30:08 PM PDT 24 Aug 15 04:30:11 PM PDT 24 675681383 ps
T122 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1208321930 Aug 15 04:29:37 PM PDT 24 Aug 15 04:29:38 PM PDT 24 142227605 ps
T1088 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1289657033 Aug 15 04:29:39 PM PDT 24 Aug 15 04:29:41 PM PDT 24 171932276 ps
T1089 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.146072483 Aug 15 04:29:38 PM PDT 24 Aug 15 04:29:47 PM PDT 24 124290702 ps
T123 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2397505858 Aug 15 04:29:35 PM PDT 24 Aug 15 04:29:38 PM PDT 24 71409828 ps
T1090 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3954999198 Aug 15 04:29:51 PM PDT 24 Aug 15 04:29:52 PM PDT 24 61226939 ps
T1091 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2689824472 Aug 15 04:30:04 PM PDT 24 Aug 15 04:30:05 PM PDT 24 11364733 ps
T1092 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2370487829 Aug 15 04:29:59 PM PDT 24 Aug 15 04:29:59 PM PDT 24 34148223 ps
T1093 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3210789094 Aug 15 04:29:29 PM PDT 24 Aug 15 04:29:30 PM PDT 24 35889561 ps
T1094 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3354828687 Aug 15 04:29:52 PM PDT 24 Aug 15 04:29:54 PM PDT 24 53923544 ps
T103 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3632825965 Aug 15 04:29:33 PM PDT 24 Aug 15 04:29:36 PM PDT 24 149071690 ps
T124 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3514641487 Aug 15 04:29:45 PM PDT 24 Aug 15 04:30:01 PM PDT 24 3269175670 ps
T1095 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3349112240 Aug 15 04:29:57 PM PDT 24 Aug 15 04:30:00 PM PDT 24 486489840 ps
T1096 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1224580455 Aug 15 04:29:59 PM PDT 24 Aug 15 04:30:00 PM PDT 24 16502844 ps
T127 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2671789070 Aug 15 04:29:43 PM PDT 24 Aug 15 04:29:45 PM PDT 24 47749780 ps
T1097 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2245491608 Aug 15 04:29:36 PM PDT 24 Aug 15 04:29:37 PM PDT 24 11514524 ps
T1098 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3999233622 Aug 15 04:29:38 PM PDT 24 Aug 15 04:29:45 PM PDT 24 54252577 ps
T173 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.168304028 Aug 15 04:30:00 PM PDT 24 Aug 15 04:30:23 PM PDT 24 20741060646 ps
T1099 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2055192155 Aug 15 04:29:27 PM PDT 24 Aug 15 04:29:28 PM PDT 24 51297623 ps
T125 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3975307718 Aug 15 04:29:54 PM PDT 24 Aug 15 04:29:57 PM PDT 24 85336796 ps
T1100 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2562674970 Aug 15 04:29:52 PM PDT 24 Aug 15 04:29:53 PM PDT 24 78467395 ps
T1101 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1287434545 Aug 15 04:30:04 PM PDT 24 Aug 15 04:30:06 PM PDT 24 45583174 ps
T1102 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.270760270 Aug 15 04:29:55 PM PDT 24 Aug 15 04:29:57 PM PDT 24 1005295570 ps
T1103 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2858213010 Aug 15 04:30:06 PM PDT 24 Aug 15 04:30:07 PM PDT 24 94575688 ps
T169 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1857222002 Aug 15 04:30:14 PM PDT 24 Aug 15 04:30:19 PM PDT 24 412246285 ps
T1104 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3611846082 Aug 15 04:29:39 PM PDT 24 Aug 15 04:29:41 PM PDT 24 30250361 ps
T1105 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3567382688 Aug 15 04:30:00 PM PDT 24 Aug 15 04:30:02 PM PDT 24 28842138 ps
T1106 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.641732638 Aug 15 04:29:52 PM PDT 24 Aug 15 04:29:53 PM PDT 24 66039945 ps
T1107 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3524770409 Aug 15 04:29:54 PM PDT 24 Aug 15 04:29:55 PM PDT 24 44569993 ps
T126 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2801326902 Aug 15 04:29:33 PM PDT 24 Aug 15 04:29:55 PM PDT 24 1588971008 ps
T174 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.87397380 Aug 15 04:29:55 PM PDT 24 Aug 15 04:30:07 PM PDT 24 825973152 ps
T1108 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.793499060 Aug 15 04:29:34 PM PDT 24 Aug 15 04:29:47 PM PDT 24 639717930 ps
T1109 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3630491112 Aug 15 04:30:05 PM PDT 24 Aug 15 04:30:09 PM PDT 24 1162587087 ps
T1110 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3161917650 Aug 15 04:29:36 PM PDT 24 Aug 15 04:30:00 PM PDT 24 1837378747 ps
T1111 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3408687464 Aug 15 04:30:08 PM PDT 24 Aug 15 04:30:12 PM PDT 24 82180427 ps
T1112 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2714738578 Aug 15 04:30:05 PM PDT 24 Aug 15 04:30:10 PM PDT 24 205492604 ps
T1113 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.12905350 Aug 15 04:30:18 PM PDT 24 Aug 15 04:30:19 PM PDT 24 21352077 ps
T1114 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2557198479 Aug 15 04:29:29 PM PDT 24 Aug 15 04:30:04 PM PDT 24 9378299643 ps
T1115 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3396289031 Aug 15 04:29:34 PM PDT 24 Aug 15 04:29:36 PM PDT 24 76733734 ps
T1116 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3802351793 Aug 15 04:29:57 PM PDT 24 Aug 15 04:29:58 PM PDT 24 11854528 ps
T1117 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3463651474 Aug 15 04:29:53 PM PDT 24 Aug 15 04:29:55 PM PDT 24 63144164 ps
T1118 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1026104241 Aug 15 04:30:00 PM PDT 24 Aug 15 04:30:01 PM PDT 24 137772024 ps
T1119 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.246418749 Aug 15 04:30:07 PM PDT 24 Aug 15 04:30:12 PM PDT 24 669647116 ps
T1120 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3639925943 Aug 15 04:29:40 PM PDT 24 Aug 15 04:29:43 PM PDT 24 595126471 ps
T1121 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.307466188 Aug 15 04:29:34 PM PDT 24 Aug 15 04:29:36 PM PDT 24 25802261 ps
T1122 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4242889408 Aug 15 04:30:03 PM PDT 24 Aug 15 04:30:04 PM PDT 24 17128999 ps
T1123 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3843787013 Aug 15 04:29:51 PM PDT 24 Aug 15 04:29:53 PM PDT 24 287600026 ps
T1124 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3554197902 Aug 15 04:29:50 PM PDT 24 Aug 15 04:30:23 PM PDT 24 527475976 ps
T1125 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.173060109 Aug 15 04:29:38 PM PDT 24 Aug 15 04:29:46 PM PDT 24 4360825255 ps
T1126 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2084111242 Aug 15 04:29:36 PM PDT 24 Aug 15 04:29:37 PM PDT 24 33847153 ps
T1127 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.621618233 Aug 15 04:29:34 PM PDT 24 Aug 15 04:29:36 PM PDT 24 53796947 ps
T1128 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1659427634 Aug 15 04:29:35 PM PDT 24 Aug 15 04:29:36 PM PDT 24 41722755 ps
T1129 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.194211296 Aug 15 04:30:37 PM PDT 24 Aug 15 04:30:39 PM PDT 24 35651432 ps
T1130 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2631804159 Aug 15 04:29:33 PM PDT 24 Aug 15 04:29:35 PM PDT 24 31152943 ps
T1131 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1826633511 Aug 15 04:29:49 PM PDT 24 Aug 15 04:29:50 PM PDT 24 87879356 ps
T1132 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2979223456 Aug 15 04:29:58 PM PDT 24 Aug 15 04:30:00 PM PDT 24 1444435124 ps
T1133 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.734425550 Aug 15 04:29:44 PM PDT 24 Aug 15 04:29:44 PM PDT 24 37119137 ps
T1134 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4119106570 Aug 15 04:29:52 PM PDT 24 Aug 15 04:29:53 PM PDT 24 23645858 ps
T1135 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3915269881 Aug 15 04:30:06 PM PDT 24 Aug 15 04:30:08 PM PDT 24 129869301 ps
T1136 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1658159912 Aug 15 04:29:57 PM PDT 24 Aug 15 04:30:00 PM PDT 24 368701553 ps
T1137 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1141113134 Aug 15 04:30:14 PM PDT 24 Aug 15 04:30:21 PM PDT 24 313503316 ps
T1138 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3810520908 Aug 15 04:29:58 PM PDT 24 Aug 15 04:30:00 PM PDT 24 150369577 ps
T1139 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2912362643 Aug 15 04:29:36 PM PDT 24 Aug 15 04:29:37 PM PDT 24 14917080 ps
T1140 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.870881637 Aug 15 04:30:19 PM PDT 24 Aug 15 04:30:39 PM PDT 24 823087640 ps
T1141 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.915833894 Aug 15 04:29:52 PM PDT 24 Aug 15 04:29:55 PM PDT 24 146399026 ps
T1142 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1838028833 Aug 15 04:30:35 PM PDT 24 Aug 15 04:30:46 PM PDT 24 766762599 ps
T1143 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.883624687 Aug 15 04:29:38 PM PDT 24 Aug 15 04:29:42 PM PDT 24 211138852 ps
T1144 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1303480886 Aug 15 04:29:58 PM PDT 24 Aug 15 04:29:59 PM PDT 24 50458921 ps
T1145 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3193319038 Aug 15 04:30:00 PM PDT 24 Aug 15 04:30:03 PM PDT 24 53378559 ps
T1146 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2259435650 Aug 15 04:29:46 PM PDT 24 Aug 15 04:29:55 PM PDT 24 193140440 ps
T1147 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3835440205 Aug 15 04:30:03 PM PDT 24 Aug 15 04:30:05 PM PDT 24 57319877 ps
T1148 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1252861261 Aug 15 04:29:39 PM PDT 24 Aug 15 04:29:40 PM PDT 24 20443114 ps
T1149 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3225950764 Aug 15 04:29:37 PM PDT 24 Aug 15 04:29:42 PM PDT 24 178734134 ps

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1558361278
Short name T3
Test name
Test status
Simulation time 2259502129 ps
CPU time 40.82 seconds
Started Aug 15 04:33:24 PM PDT 24
Finished Aug 15 04:34:05 PM PDT 24
Peak memory 237028 kb
Host smart-1f38b6d8-a554-42db-8e89-ba951cc78f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558361278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1558361278
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.436799498
Short name T33
Test name
Test status
Simulation time 4140079196 ps
CPU time 101.28 seconds
Started Aug 15 04:32:47 PM PDT 24
Finished Aug 15 04:34:29 PM PDT 24
Peak memory 266076 kb
Host smart-550fcac7-d63b-4828-8975-14379f79d4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436799498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.436799498
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4238559430
Short name T16
Test name
Test status
Simulation time 44645478979 ps
CPU time 156.7 seconds
Started Aug 15 04:32:43 PM PDT 24
Finished Aug 15 04:35:20 PM PDT 24
Peak memory 252500 kb
Host smart-59ab2148-d894-42e3-a2ee-d3f65bcd0e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238559430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4238559430
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3531973587
Short name T14
Test name
Test status
Simulation time 96061788690 ps
CPU time 492.71 seconds
Started Aug 15 04:32:43 PM PDT 24
Finished Aug 15 04:40:55 PM PDT 24
Peak memory 283496 kb
Host smart-806fed0a-ad7d-4231-ab29-ca867b4d1f78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531973587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3531973587
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1753361746
Short name T113
Test name
Test status
Simulation time 725865374 ps
CPU time 8.07 seconds
Started Aug 15 04:29:49 PM PDT 24
Finished Aug 15 04:29:57 PM PDT 24
Peak memory 215732 kb
Host smart-cdc058a5-d3f0-4de6-b55f-dab1b485eabd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753361746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1753361746
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1382226770
Short name T20
Test name
Test status
Simulation time 286461226438 ps
CPU time 1360.65 seconds
Started Aug 15 04:32:12 PM PDT 24
Finished Aug 15 04:54:53 PM PDT 24
Peak memory 301960 kb
Host smart-f3cbf683-b0e4-4203-a75e-4d255b02c60e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382226770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1382226770
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1110045078
Short name T68
Test name
Test status
Simulation time 30575657 ps
CPU time 0.75 seconds
Started Aug 15 04:31:46 PM PDT 24
Finished Aug 15 04:31:47 PM PDT 24
Peak memory 215988 kb
Host smart-36dc536d-95f3-4c26-b7f1-ddd509cde0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110045078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1110045078
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1085897999
Short name T18
Test name
Test status
Simulation time 28682079027 ps
CPU time 341.08 seconds
Started Aug 15 04:34:24 PM PDT 24
Finished Aug 15 04:40:05 PM PDT 24
Peak memory 254104 kb
Host smart-aca07277-052d-4486-bddd-0b3819977617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085897999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1085897999
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3530519059
Short name T101
Test name
Test status
Simulation time 415030856 ps
CPU time 3.83 seconds
Started Aug 15 04:29:47 PM PDT 24
Finished Aug 15 04:29:51 PM PDT 24
Peak memory 215944 kb
Host smart-1b22d8e2-f91a-4cee-a6e7-0540993e35ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530519059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
530519059
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1836452789
Short name T177
Test name
Test status
Simulation time 22759558018 ps
CPU time 150.86 seconds
Started Aug 15 04:32:09 PM PDT 24
Finished Aug 15 04:34:40 PM PDT 24
Peak memory 267096 kb
Host smart-a8e40eba-5ac6-4289-90ba-12e41faf7a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836452789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1836452789
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2332525833
Short name T17
Test name
Test status
Simulation time 105531542 ps
CPU time 1.29 seconds
Started Aug 15 04:31:54 PM PDT 24
Finished Aug 15 04:31:55 PM PDT 24
Peak memory 235332 kb
Host smart-3c6abd61-0508-4509-af3f-2109011e547b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332525833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2332525833
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3298077095
Short name T183
Test name
Test status
Simulation time 55599698569 ps
CPU time 424.15 seconds
Started Aug 15 04:31:49 PM PDT 24
Finished Aug 15 04:38:53 PM PDT 24
Peak memory 261132 kb
Host smart-cab3f9dc-653c-42d5-b047-d72b9b1e0470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298077095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3298077095
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.738966582
Short name T145
Test name
Test status
Simulation time 10353111421 ps
CPU time 42.91 seconds
Started Aug 15 04:32:31 PM PDT 24
Finished Aug 15 04:33:14 PM PDT 24
Peak memory 224652 kb
Host smart-7c469750-319d-46ac-bd9e-74641e9721c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738966582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.738966582
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.500141785
Short name T118
Test name
Test status
Simulation time 28956694 ps
CPU time 1.87 seconds
Started Aug 15 04:29:32 PM PDT 24
Finished Aug 15 04:29:34 PM PDT 24
Peak memory 215736 kb
Host smart-8976a0ec-227a-44bf-8b2c-c50deae14e14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500141785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.500141785
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3866566214
Short name T134
Test name
Test status
Simulation time 64514352924 ps
CPU time 577.44 seconds
Started Aug 15 04:33:55 PM PDT 24
Finished Aug 15 04:43:32 PM PDT 24
Peak memory 255536 kb
Host smart-0532bb58-67b1-47ad-82e8-86fab281481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866566214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3866566214
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.504172159
Short name T4
Test name
Test status
Simulation time 13163531737 ps
CPU time 113.48 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:35:02 PM PDT 24
Peak memory 250524 kb
Host smart-58cac01f-076d-4ac0-afaa-94ae90958ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504172159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.504172159
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1711350288
Short name T49
Test name
Test status
Simulation time 107354465680 ps
CPU time 243.1 seconds
Started Aug 15 04:33:26 PM PDT 24
Finished Aug 15 04:37:29 PM PDT 24
Peak memory 265612 kb
Host smart-dab7d96e-24b6-4e0b-b90c-6048f8bb32e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711350288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1711350288
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1492477101
Short name T178
Test name
Test status
Simulation time 27748592239 ps
CPU time 314.46 seconds
Started Aug 15 04:33:43 PM PDT 24
Finished Aug 15 04:38:57 PM PDT 24
Peak memory 265668 kb
Host smart-ed6202b8-2749-4410-bc70-880d0557e27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492477101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1492477101
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2451753559
Short name T203
Test name
Test status
Simulation time 51247803133 ps
CPU time 532.85 seconds
Started Aug 15 04:33:46 PM PDT 24
Finished Aug 15 04:42:39 PM PDT 24
Peak memory 265684 kb
Host smart-9e2e65d1-2746-43b3-a44c-d61a175d0f4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451753559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2451753559
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.150668871
Short name T424
Test name
Test status
Simulation time 15340830 ps
CPU time 1.07 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:31:48 PM PDT 24
Peak memory 216492 kb
Host smart-fa99c0e9-e43f-406d-998c-f363f106c4d5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150668871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.150668871
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3170059436
Short name T236
Test name
Test status
Simulation time 59905936004 ps
CPU time 420.26 seconds
Started Aug 15 04:33:41 PM PDT 24
Finished Aug 15 04:40:41 PM PDT 24
Peak memory 265676 kb
Host smart-1989bc76-ef21-4606-bbdf-37ca31a44836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170059436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3170059436
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2238256412
Short name T114
Test name
Test status
Simulation time 3160709829 ps
CPU time 14.91 seconds
Started Aug 15 04:30:36 PM PDT 24
Finished Aug 15 04:30:51 PM PDT 24
Peak memory 216216 kb
Host smart-245102c8-2334-4e93-a316-eefd616cc431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238256412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2238256412
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.826934932
Short name T260
Test name
Test status
Simulation time 12860347668 ps
CPU time 171.55 seconds
Started Aug 15 04:32:45 PM PDT 24
Finished Aug 15 04:35:36 PM PDT 24
Peak memory 252268 kb
Host smart-b83927a8-1ca1-4526-b553-9e1188625e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826934932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.826934932
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4129421878
Short name T201
Test name
Test status
Simulation time 85383420694 ps
CPU time 270.1 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:36:42 PM PDT 24
Peak memory 273028 kb
Host smart-6e6141ce-efdf-4d26-a5d9-e48747c3dd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129421878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4129421878
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4029393559
Short name T322
Test name
Test status
Simulation time 38047510 ps
CPU time 0.76 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:31:48 PM PDT 24
Peak memory 204788 kb
Host smart-f9390c83-9d77-4185-a119-4d77346d58bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029393559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
029393559
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1401133291
Short name T55
Test name
Test status
Simulation time 7309312711 ps
CPU time 53.5 seconds
Started Aug 15 04:32:21 PM PDT 24
Finished Aug 15 04:33:15 PM PDT 24
Peak memory 254316 kb
Host smart-ab6b115c-7527-46ce-8cc2-212d3a993b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401133291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1401133291
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1822815889
Short name T283
Test name
Test status
Simulation time 8665573636 ps
CPU time 94.23 seconds
Started Aug 15 04:32:39 PM PDT 24
Finished Aug 15 04:34:13 PM PDT 24
Peak memory 253964 kb
Host smart-98166276-6934-4513-83b5-c5e2be1e2a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822815889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1822815889
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3596413000
Short name T89
Test name
Test status
Simulation time 3442856004 ps
CPU time 34.65 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:42 PM PDT 24
Peak memory 257156 kb
Host smart-bae7ec95-587a-4cb8-9246-63614f34d1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596413000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3596413000
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2866739864
Short name T112
Test name
Test status
Simulation time 4618820661 ps
CPU time 25.87 seconds
Started Aug 15 04:29:33 PM PDT 24
Finished Aug 15 04:29:59 PM PDT 24
Peak memory 215020 kb
Host smart-32b75387-dc2d-432e-b727-3d7dabe2d6a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866739864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2866739864
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2928514787
Short name T29
Test name
Test status
Simulation time 3195447890 ps
CPU time 24.16 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:42 PM PDT 24
Peak memory 216336 kb
Host smart-35a08e76-c065-4694-92c9-f70769bf7aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928514787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2928514787
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1706437723
Short name T138
Test name
Test status
Simulation time 7991199634 ps
CPU time 164.8 seconds
Started Aug 15 04:32:48 PM PDT 24
Finished Aug 15 04:35:33 PM PDT 24
Peak memory 262172 kb
Host smart-0e778b9b-5e24-4939-82fb-862bb5008152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706437723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1706437723
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2296555491
Short name T297
Test name
Test status
Simulation time 4440644373 ps
CPU time 13.09 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 232764 kb
Host smart-eb36a1fd-2505-40ce-9aaa-2d8e6f9641ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296555491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2296555491
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3432633885
Short name T270
Test name
Test status
Simulation time 69884884064 ps
CPU time 284.69 seconds
Started Aug 15 04:33:04 PM PDT 24
Finished Aug 15 04:37:49 PM PDT 24
Peak memory 257328 kb
Host smart-ca0fb88a-239d-4427-bec8-18e266783f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432633885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3432633885
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1461663844
Short name T246
Test name
Test status
Simulation time 86520017868 ps
CPU time 382.04 seconds
Started Aug 15 04:34:21 PM PDT 24
Finished Aug 15 04:40:44 PM PDT 24
Peak memory 256764 kb
Host smart-904777b3-e791-4422-87a4-46432d8fd6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461663844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1461663844
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1743162494
Short name T107
Test name
Test status
Simulation time 1248759976 ps
CPU time 5.83 seconds
Started Aug 15 04:29:39 PM PDT 24
Finished Aug 15 04:29:45 PM PDT 24
Peak memory 216024 kb
Host smart-0b88c0f5-397d-4064-9f81-50f0e040be9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743162494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1743162494
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.46055124
Short name T42
Test name
Test status
Simulation time 35573151936 ps
CPU time 158.73 seconds
Started Aug 15 04:33:04 PM PDT 24
Finished Aug 15 04:35:43 PM PDT 24
Peak memory 255812 kb
Host smart-700903c4-8297-4b2c-ac93-3eb7d12ebe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46055124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.46055124
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3002991989
Short name T276
Test name
Test status
Simulation time 43663952589 ps
CPU time 120.59 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:35:43 PM PDT 24
Peak memory 267536 kb
Host smart-60f0b5c8-6612-402b-b2a1-7ff36d3f9adf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002991989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3002991989
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2443361637
Short name T274
Test name
Test status
Simulation time 185450578853 ps
CPU time 440.42 seconds
Started Aug 15 04:34:03 PM PDT 24
Finished Aug 15 04:41:24 PM PDT 24
Peak memory 256620 kb
Host smart-a1b34074-beb1-41fd-92ca-04e11bf2f411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443361637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2443361637
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1857222002
Short name T169
Test name
Test status
Simulation time 412246285 ps
CPU time 5.11 seconds
Started Aug 15 04:30:14 PM PDT 24
Finished Aug 15 04:30:19 PM PDT 24
Peak memory 216016 kb
Host smart-12b39549-bd3f-42b1-bfd1-5cdf469089fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857222002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1857222002
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.168304028
Short name T173
Test name
Test status
Simulation time 20741060646 ps
CPU time 22.59 seconds
Started Aug 15 04:30:00 PM PDT 24
Finished Aug 15 04:30:23 PM PDT 24
Peak memory 216344 kb
Host smart-e7ced791-ee0d-45d4-b832-ef6646317120
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168304028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.168304028
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3238476983
Short name T271
Test name
Test status
Simulation time 89307158520 ps
CPU time 149.33 seconds
Started Aug 15 04:31:43 PM PDT 24
Finished Aug 15 04:34:12 PM PDT 24
Peak memory 242608 kb
Host smart-39fb82b9-003a-467a-891c-f894559d0254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238476983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3238476983
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.750789177
Short name T284
Test name
Test status
Simulation time 5452414356 ps
CPU time 79.87 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:33:39 PM PDT 24
Peak memory 249292 kb
Host smart-267be30d-4363-4ff9-b340-e1f8fe6470f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750789177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.750789177
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2138422166
Short name T948
Test name
Test status
Simulation time 35293955224 ps
CPU time 45.67 seconds
Started Aug 15 04:32:22 PM PDT 24
Finished Aug 15 04:33:07 PM PDT 24
Peak memory 249224 kb
Host smart-b4474007-e5fd-4b34-8235-b1ea6cbd8afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138422166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2138422166
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3855295958
Short name T314
Test name
Test status
Simulation time 36411507960 ps
CPU time 109.37 seconds
Started Aug 15 04:33:20 PM PDT 24
Finished Aug 15 04:35:09 PM PDT 24
Peak memory 240592 kb
Host smart-ae016a20-3757-444b-9d84-52fda3196463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855295958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3855295958
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4189108697
Short name T269
Test name
Test status
Simulation time 49813724474 ps
CPU time 188.44 seconds
Started Aug 15 04:33:35 PM PDT 24
Finished Aug 15 04:36:44 PM PDT 24
Peak memory 288992 kb
Host smart-b09205f3-a283-4e8c-821b-37c360ba62e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189108697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4189108697
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1827227546
Short name T298
Test name
Test status
Simulation time 14600919795 ps
CPU time 60.2 seconds
Started Aug 15 04:33:51 PM PDT 24
Finished Aug 15 04:34:51 PM PDT 24
Peak memory 251620 kb
Host smart-6aeb65eb-23d8-4697-9552-d8a7173aec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827227546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1827227546
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2754397493
Short name T24
Test name
Test status
Simulation time 24049833203 ps
CPU time 18.61 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:32:06 PM PDT 24
Peak memory 232756 kb
Host smart-243245d4-8bdf-49ad-be8d-be8bdc8dbc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754397493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2754397493
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2162712329
Short name T84
Test name
Test status
Simulation time 30604703 ps
CPU time 1.16 seconds
Started Aug 15 04:29:54 PM PDT 24
Finished Aug 15 04:29:55 PM PDT 24
Peak memory 216740 kb
Host smart-b8e0b815-c226-4366-87ba-84d9e6051852
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162712329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2162712329
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3206841786
Short name T108
Test name
Test status
Simulation time 3945464498 ps
CPU time 21.47 seconds
Started Aug 15 04:29:46 PM PDT 24
Finished Aug 15 04:30:08 PM PDT 24
Peak memory 215852 kb
Host smart-d4dabd12-c10d-45fb-bebd-dff8215a5f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206841786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3206841786
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1030907934
Short name T1084
Test name
Test status
Simulation time 88193503 ps
CPU time 2.3 seconds
Started Aug 15 04:29:35 PM PDT 24
Finished Aug 15 04:29:37 PM PDT 24
Peak memory 215992 kb
Host smart-f5140300-3ef1-4138-9e1a-e34dd4940b47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030907934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1030907934
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2749075509
Short name T105
Test name
Test status
Simulation time 1120895393 ps
CPU time 13.66 seconds
Started Aug 15 04:29:56 PM PDT 24
Finished Aug 15 04:30:10 PM PDT 24
Peak memory 215800 kb
Host smart-c7aabaf4-5474-4c35-b011-37f015d403ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749075509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2749075509
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3514641487
Short name T124
Test name
Test status
Simulation time 3269175670 ps
CPU time 15.74 seconds
Started Aug 15 04:29:45 PM PDT 24
Finished Aug 15 04:30:01 PM PDT 24
Peak memory 207648 kb
Host smart-64556126-546f-4e87-b773-b5bfc952481c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514641487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3514641487
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2557198479
Short name T1114
Test name
Test status
Simulation time 9378299643 ps
CPU time 34.23 seconds
Started Aug 15 04:29:29 PM PDT 24
Finished Aug 15 04:30:04 PM PDT 24
Peak memory 215800 kb
Host smart-db959a4d-7808-4135-8b0a-8282d24100d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557198479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2557198479
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2084111242
Short name T1126
Test name
Test status
Simulation time 33847153 ps
CPU time 1.17 seconds
Started Aug 15 04:29:36 PM PDT 24
Finished Aug 15 04:29:37 PM PDT 24
Peak memory 216724 kb
Host smart-35e49c36-ef16-45ac-80bb-f2c218832379
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084111242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2084111242
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1182466170
Short name T1053
Test name
Test status
Simulation time 26634171 ps
CPU time 1.68 seconds
Started Aug 15 04:29:39 PM PDT 24
Finished Aug 15 04:29:41 PM PDT 24
Peak memory 215844 kb
Host smart-57806135-aa85-42b3-92fb-761c56320457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182466170 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1182466170
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.621618233
Short name T1127
Test name
Test status
Simulation time 53796947 ps
CPU time 1.32 seconds
Started Aug 15 04:29:34 PM PDT 24
Finished Aug 15 04:29:36 PM PDT 24
Peak memory 207608 kb
Host smart-a73ea490-fb7a-4cb8-962e-c29d04f7bf23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621618233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.621618233
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3802351793
Short name T1116
Test name
Test status
Simulation time 11854528 ps
CPU time 0.74 seconds
Started Aug 15 04:29:57 PM PDT 24
Finished Aug 15 04:29:58 PM PDT 24
Peak memory 204448 kb
Host smart-606feea0-4bff-471c-a175-383e8ce0dbe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802351793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
802351793
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2397505858
Short name T123
Test name
Test status
Simulation time 71409828 ps
CPU time 2.14 seconds
Started Aug 15 04:29:35 PM PDT 24
Finished Aug 15 04:29:38 PM PDT 24
Peak memory 215796 kb
Host smart-6231cb58-7a7c-42ca-a169-71779718d98a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397505858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2397505858
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1659427634
Short name T1128
Test name
Test status
Simulation time 41722755 ps
CPU time 0.62 seconds
Started Aug 15 04:29:35 PM PDT 24
Finished Aug 15 04:29:36 PM PDT 24
Peak memory 204088 kb
Host smart-c9e8de57-2fd7-454e-945b-cc98312c81f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659427634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1659427634
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2307181088
Short name T1083
Test name
Test status
Simulation time 217551226 ps
CPU time 2.67 seconds
Started Aug 15 04:29:50 PM PDT 24
Finished Aug 15 04:29:53 PM PDT 24
Peak memory 215784 kb
Host smart-6fd66acb-8165-4af6-886c-f13adde83aab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307181088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2307181088
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.315055306
Short name T170
Test name
Test status
Simulation time 569485300 ps
CPU time 13.67 seconds
Started Aug 15 04:29:43 PM PDT 24
Finished Aug 15 04:29:57 PM PDT 24
Peak memory 215720 kb
Host smart-77d8173e-f0e6-4e13-9add-33a3d0f5c956
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315055306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.315055306
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2424672334
Short name T116
Test name
Test status
Simulation time 14020866338 ps
CPU time 23.94 seconds
Started Aug 15 04:29:28 PM PDT 24
Finished Aug 15 04:29:52 PM PDT 24
Peak memory 215852 kb
Host smart-18fc428b-ccaf-4c69-876c-aaf3b0385ce7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424672334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2424672334
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3554197902
Short name T1124
Test name
Test status
Simulation time 527475976 ps
CPU time 32.75 seconds
Started Aug 15 04:29:50 PM PDT 24
Finished Aug 15 04:30:23 PM PDT 24
Peak memory 215704 kb
Host smart-e3b0ba42-4fe3-4c9e-a76c-7fb79c5006e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554197902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3554197902
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3029666399
Short name T1087
Test name
Test status
Simulation time 675681383 ps
CPU time 2.79 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:30:11 PM PDT 24
Peak memory 216880 kb
Host smart-542bc952-b7cb-47e1-a01f-108b51b4ba36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029666399 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3029666399
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.4233182660
Short name T1035
Test name
Test status
Simulation time 359733497 ps
CPU time 1.9 seconds
Started Aug 15 04:29:33 PM PDT 24
Finished Aug 15 04:29:35 PM PDT 24
Peak memory 207592 kb
Host smart-4035a2c7-a287-4ce7-9656-776ff7b1f0eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233182660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.4
233182660
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2055192155
Short name T1099
Test name
Test status
Simulation time 51297623 ps
CPU time 0.72 seconds
Started Aug 15 04:29:27 PM PDT 24
Finished Aug 15 04:29:28 PM PDT 24
Peak memory 204160 kb
Host smart-05e665f2-dd0d-49d5-b5ed-1a438c477ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055192155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
055192155
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4189044501
Short name T117
Test name
Test status
Simulation time 44051467 ps
CPU time 1.49 seconds
Started Aug 15 04:29:34 PM PDT 24
Finished Aug 15 04:29:40 PM PDT 24
Peak memory 215772 kb
Host smart-f15ad4bb-69be-4ada-a004-1ea94bc3bb59
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189044501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4189044501
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3210789094
Short name T1093
Test name
Test status
Simulation time 35889561 ps
CPU time 0.64 seconds
Started Aug 15 04:29:29 PM PDT 24
Finished Aug 15 04:29:30 PM PDT 24
Peak memory 204088 kb
Host smart-f6f109f2-aa44-4b1f-a287-ccfa867e9d65
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210789094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3210789094
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.369844686
Short name T152
Test name
Test status
Simulation time 773075427 ps
CPU time 3.88 seconds
Started Aug 15 04:29:39 PM PDT 24
Finished Aug 15 04:29:43 PM PDT 24
Peak memory 215764 kb
Host smart-571ec0f8-b3f6-497d-9ebf-586cddfa6500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369844686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.369844686
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3139230478
Short name T1074
Test name
Test status
Simulation time 170868227 ps
CPU time 2.16 seconds
Started Aug 15 04:29:50 PM PDT 24
Finished Aug 15 04:29:53 PM PDT 24
Peak memory 215928 kb
Host smart-a03394a7-d289-4574-b3ad-49a1e1250d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139230478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
139230478
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1538231885
Short name T1062
Test name
Test status
Simulation time 249109484 ps
CPU time 1.77 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:30:10 PM PDT 24
Peak memory 215892 kb
Host smart-4fc6665a-8840-4b7a-81c4-684b59d9c9a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538231885 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1538231885
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1208321930
Short name T122
Test name
Test status
Simulation time 142227605 ps
CPU time 1.34 seconds
Started Aug 15 04:29:37 PM PDT 24
Finished Aug 15 04:29:38 PM PDT 24
Peak memory 215696 kb
Host smart-07454931-d1c2-4891-b01d-7f917eff62ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208321930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1208321930
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1639776131
Short name T1066
Test name
Test status
Simulation time 22574835 ps
CPU time 0.81 seconds
Started Aug 15 04:30:00 PM PDT 24
Finished Aug 15 04:30:06 PM PDT 24
Peak memory 204032 kb
Host smart-e26db856-a699-41bb-ac11-afe349303af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639776131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1639776131
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1591589547
Short name T1070
Test name
Test status
Simulation time 93124349 ps
CPU time 3.99 seconds
Started Aug 15 04:29:37 PM PDT 24
Finished Aug 15 04:29:41 PM PDT 24
Peak memory 215780 kb
Host smart-d8321bb5-eb80-4b10-87e2-dfce4f3d5473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591589547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1591589547
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3105376143
Short name T1044
Test name
Test status
Simulation time 107891071 ps
CPU time 3.61 seconds
Started Aug 15 04:29:55 PM PDT 24
Finished Aug 15 04:29:59 PM PDT 24
Peak memory 218232 kb
Host smart-eb63a463-d725-4d73-a263-9a3bc393b0f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105376143 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3105376143
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4248361285
Short name T1055
Test name
Test status
Simulation time 57965772 ps
CPU time 1.25 seconds
Started Aug 15 04:29:38 PM PDT 24
Finished Aug 15 04:29:40 PM PDT 24
Peak memory 206712 kb
Host smart-69f3fc2f-d406-4342-84ab-fb8a3a770e8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248361285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4248361285
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3318849442
Short name T1046
Test name
Test status
Simulation time 24582540 ps
CPU time 0.7 seconds
Started Aug 15 04:29:34 PM PDT 24
Finished Aug 15 04:29:35 PM PDT 24
Peak memory 204464 kb
Host smart-154a6b00-ea9d-432f-b607-3945cbce2ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318849442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3318849442
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3349112240
Short name T1095
Test name
Test status
Simulation time 486489840 ps
CPU time 2.82 seconds
Started Aug 15 04:29:57 PM PDT 24
Finished Aug 15 04:30:00 PM PDT 24
Peak memory 215636 kb
Host smart-4d1782df-aecd-4772-b548-f540d023b7f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349112240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3349112240
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3354828687
Short name T1094
Test name
Test status
Simulation time 53923544 ps
CPU time 1.56 seconds
Started Aug 15 04:29:52 PM PDT 24
Finished Aug 15 04:29:54 PM PDT 24
Peak memory 215872 kb
Host smart-b86cbb09-1153-4a81-bb51-c65fbb743d22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354828687 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3354828687
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3841469155
Short name T119
Test name
Test status
Simulation time 27177686 ps
CPU time 1.61 seconds
Started Aug 15 04:29:34 PM PDT 24
Finished Aug 15 04:29:35 PM PDT 24
Peak memory 215764 kb
Host smart-d00b0cb6-dd97-4771-acba-5dbd2871c0dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841469155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3841469155
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3651889053
Short name T1076
Test name
Test status
Simulation time 15874688 ps
CPU time 0.72 seconds
Started Aug 15 04:29:58 PM PDT 24
Finished Aug 15 04:29:59 PM PDT 24
Peak memory 204140 kb
Host smart-9106f08d-0177-4616-8f9e-74b854c8d3ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651889053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3651889053
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3026563607
Short name T1068
Test name
Test status
Simulation time 113607710 ps
CPU time 3.36 seconds
Started Aug 15 04:29:57 PM PDT 24
Finished Aug 15 04:30:01 PM PDT 24
Peak memory 215816 kb
Host smart-a404a98f-77d5-465e-97ac-0d8bd6c5ef78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026563607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3026563607
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3463651474
Short name T1117
Test name
Test status
Simulation time 63144164 ps
CPU time 1.92 seconds
Started Aug 15 04:29:53 PM PDT 24
Finished Aug 15 04:29:55 PM PDT 24
Peak memory 215988 kb
Host smart-4b6df838-37cc-47f5-95fd-6f0571af2d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463651474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3463651474
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1838028833
Short name T1142
Test name
Test status
Simulation time 766762599 ps
CPU time 10.85 seconds
Started Aug 15 04:30:35 PM PDT 24
Finished Aug 15 04:30:46 PM PDT 24
Peak memory 215804 kb
Host smart-a62835d6-22d1-4f60-8588-f4e2657023a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838028833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1838028833
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1133425401
Short name T109
Test name
Test status
Simulation time 54128997 ps
CPU time 3.72 seconds
Started Aug 15 04:30:14 PM PDT 24
Finished Aug 15 04:30:18 PM PDT 24
Peak memory 218280 kb
Host smart-94449d29-d63f-43a9-97d8-4cd415c48642
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133425401 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1133425401
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2724027621
Short name T1073
Test name
Test status
Simulation time 33025392 ps
CPU time 2.09 seconds
Started Aug 15 04:29:48 PM PDT 24
Finished Aug 15 04:29:50 PM PDT 24
Peak memory 215724 kb
Host smart-7ab1e06c-eab0-4c19-b11a-ece46409cfae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724027621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2724027621
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3498307449
Short name T1047
Test name
Test status
Simulation time 39284924 ps
CPU time 0.77 seconds
Started Aug 15 04:30:06 PM PDT 24
Finished Aug 15 04:30:07 PM PDT 24
Peak memory 204164 kb
Host smart-d2c5378e-c6d0-4359-b52b-18a46dd78d05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498307449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3498307449
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1842505610
Short name T141
Test name
Test status
Simulation time 148810771 ps
CPU time 3.2 seconds
Started Aug 15 04:29:38 PM PDT 24
Finished Aug 15 04:29:41 PM PDT 24
Peak memory 215776 kb
Host smart-159936e7-f505-4c90-8bab-611d3af1ed80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842505610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1842505610
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3225950764
Short name T1149
Test name
Test status
Simulation time 178734134 ps
CPU time 4.08 seconds
Started Aug 15 04:29:37 PM PDT 24
Finished Aug 15 04:29:42 PM PDT 24
Peak memory 217048 kb
Host smart-5e4e7e4d-60df-4f23-9710-ccc2c1a32960
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225950764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3225950764
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1066079933
Short name T1069
Test name
Test status
Simulation time 852345274 ps
CPU time 20.08 seconds
Started Aug 15 04:30:04 PM PDT 24
Finished Aug 15 04:30:25 PM PDT 24
Peak memory 215824 kb
Host smart-7fa4aa43-e413-4f7f-9e3a-ac5c965477c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066079933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1066079933
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.116307799
Short name T95
Test name
Test status
Simulation time 167181500 ps
CPU time 4.03 seconds
Started Aug 15 04:30:38 PM PDT 24
Finished Aug 15 04:30:42 PM PDT 24
Peak memory 218232 kb
Host smart-e8adece0-67b4-4471-aed6-e339b112e523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116307799 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.116307799
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4078376752
Short name T120
Test name
Test status
Simulation time 355150411 ps
CPU time 2.39 seconds
Started Aug 15 04:30:13 PM PDT 24
Finished Aug 15 04:30:15 PM PDT 24
Peak memory 215896 kb
Host smart-505e83f5-73a1-4ac3-a71f-73ad5fe7eaec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078376752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4078376752
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3858156315
Short name T1039
Test name
Test status
Simulation time 14350065 ps
CPU time 0.66 seconds
Started Aug 15 04:29:39 PM PDT 24
Finished Aug 15 04:29:39 PM PDT 24
Peak memory 204176 kb
Host smart-6dbc498b-0e06-4ac1-928d-023eea797c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858156315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3858156315
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1812638243
Short name T1045
Test name
Test status
Simulation time 161478691 ps
CPU time 2.53 seconds
Started Aug 15 04:30:20 PM PDT 24
Finished Aug 15 04:30:23 PM PDT 24
Peak memory 215804 kb
Host smart-a9585840-dc6d-4a13-9eae-d59a84af1de7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812638243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1812638243
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3915269881
Short name T1135
Test name
Test status
Simulation time 129869301 ps
CPU time 1.49 seconds
Started Aug 15 04:30:06 PM PDT 24
Finished Aug 15 04:30:08 PM PDT 24
Peak memory 216020 kb
Host smart-a8e6c9cc-3bad-4f89-b84f-8f803fdd4ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915269881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3915269881
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3363255769
Short name T171
Test name
Test status
Simulation time 286372985 ps
CPU time 16.91 seconds
Started Aug 15 04:29:50 PM PDT 24
Finished Aug 15 04:30:08 PM PDT 24
Peak memory 215808 kb
Host smart-286931bc-c294-488b-b3e3-38e42a2ac760
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363255769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3363255769
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2040154931
Short name T1051
Test name
Test status
Simulation time 222490544 ps
CPU time 1.9 seconds
Started Aug 15 04:30:03 PM PDT 24
Finished Aug 15 04:30:05 PM PDT 24
Peak memory 215092 kb
Host smart-f5f43163-92c2-4d9e-8e43-ce914cc44c3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040154931 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2040154931
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1522848231
Short name T1054
Test name
Test status
Simulation time 118505251 ps
CPU time 1.94 seconds
Started Aug 15 04:29:49 PM PDT 24
Finished Aug 15 04:29:51 PM PDT 24
Peak memory 215720 kb
Host smart-97ffc4a5-baa2-40ff-b7eb-12569cad0b51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522848231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1522848231
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1137999952
Short name T1029
Test name
Test status
Simulation time 54654570 ps
CPU time 0.74 seconds
Started Aug 15 04:29:54 PM PDT 24
Finished Aug 15 04:29:55 PM PDT 24
Peak memory 204204 kb
Host smart-0ef0ef4f-b9ee-47e5-961b-3b70abfd14f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137999952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1137999952
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.888560577
Short name T1057
Test name
Test status
Simulation time 66245150 ps
CPU time 1.85 seconds
Started Aug 15 04:30:04 PM PDT 24
Finished Aug 15 04:30:06 PM PDT 24
Peak memory 215764 kb
Host smart-f69fe70f-86b6-4539-b8ad-008c64851994
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888560577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.888560577
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.467937174
Short name T102
Test name
Test status
Simulation time 144190378 ps
CPU time 3.53 seconds
Started Aug 15 04:29:39 PM PDT 24
Finished Aug 15 04:29:42 PM PDT 24
Peak memory 216016 kb
Host smart-5aa2f63b-f49a-4559-be3a-98914aeea913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467937174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.467937174
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.870881637
Short name T1140
Test name
Test status
Simulation time 823087640 ps
CPU time 20.28 seconds
Started Aug 15 04:30:19 PM PDT 24
Finished Aug 15 04:30:39 PM PDT 24
Peak memory 216488 kb
Host smart-c401301f-6bfb-4270-ab95-92cf2ee48e84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870881637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.870881637
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3559108351
Short name T1050
Test name
Test status
Simulation time 101426226 ps
CPU time 1.67 seconds
Started Aug 15 04:30:20 PM PDT 24
Finished Aug 15 04:30:22 PM PDT 24
Peak memory 216760 kb
Host smart-e2249729-1d4a-4855-8e0d-8f11be37519b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559108351 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3559108351
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.915833894
Short name T1141
Test name
Test status
Simulation time 146399026 ps
CPU time 2.45 seconds
Started Aug 15 04:29:52 PM PDT 24
Finished Aug 15 04:29:55 PM PDT 24
Peak memory 215784 kb
Host smart-5ea2b900-dd85-4499-8245-ddca02537e37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915833894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.915833894
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2245491608
Short name T1097
Test name
Test status
Simulation time 11514524 ps
CPU time 0.73 seconds
Started Aug 15 04:29:36 PM PDT 24
Finished Aug 15 04:29:37 PM PDT 24
Peak memory 204444 kb
Host smart-e62928c3-c099-4d02-ac80-d3c6f2e0038c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245491608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2245491608
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3810520908
Short name T1138
Test name
Test status
Simulation time 150369577 ps
CPU time 1.53 seconds
Started Aug 15 04:29:58 PM PDT 24
Finished Aug 15 04:30:00 PM PDT 24
Peak memory 215756 kb
Host smart-80ca97e6-5510-49a3-aead-66458df6dc5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810520908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3810520908
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1069365877
Short name T1085
Test name
Test status
Simulation time 278817799 ps
CPU time 2.01 seconds
Started Aug 15 04:30:20 PM PDT 24
Finished Aug 15 04:30:22 PM PDT 24
Peak memory 215948 kb
Host smart-93b7a5dc-4536-4711-a075-71c0264567bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069365877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1069365877
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.408920714
Short name T153
Test name
Test status
Simulation time 1317568003 ps
CPU time 14.83 seconds
Started Aug 15 04:29:54 PM PDT 24
Finished Aug 15 04:30:09 PM PDT 24
Peak memory 215876 kb
Host smart-11fb6907-3cd5-498a-8ef3-90ae642b9a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408920714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.408920714
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3715655011
Short name T106
Test name
Test status
Simulation time 107522975 ps
CPU time 2.8 seconds
Started Aug 15 04:29:51 PM PDT 24
Finished Aug 15 04:29:54 PM PDT 24
Peak memory 217408 kb
Host smart-3d38a71c-f362-4c32-b57d-045047748add
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715655011 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3715655011
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3611846082
Short name T1104
Test name
Test status
Simulation time 30250361 ps
CPU time 1.97 seconds
Started Aug 15 04:29:39 PM PDT 24
Finished Aug 15 04:29:41 PM PDT 24
Peak memory 207540 kb
Host smart-42d3ee4b-593b-41f3-8395-840b20e574c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611846082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3611846082
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3283252779
Short name T1078
Test name
Test status
Simulation time 15685204 ps
CPU time 0.73 seconds
Started Aug 15 04:30:18 PM PDT 24
Finished Aug 15 04:30:18 PM PDT 24
Peak memory 204476 kb
Host smart-582a8b7d-7e27-48a6-b0aa-d4d909cb6f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283252779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3283252779
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2714738578
Short name T1112
Test name
Test status
Simulation time 205492604 ps
CPU time 4.16 seconds
Started Aug 15 04:30:05 PM PDT 24
Finished Aug 15 04:30:10 PM PDT 24
Peak memory 215724 kb
Host smart-686e6a91-1368-42e4-bfe2-953df3c3dd5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714738578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2714738578
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1141113134
Short name T1137
Test name
Test status
Simulation time 313503316 ps
CPU time 7.12 seconds
Started Aug 15 04:30:14 PM PDT 24
Finished Aug 15 04:30:21 PM PDT 24
Peak memory 215808 kb
Host smart-520c22cb-9b82-4b8d-90ed-aace5ab306a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141113134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1141113134
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1396956636
Short name T111
Test name
Test status
Simulation time 43266564 ps
CPU time 2.85 seconds
Started Aug 15 04:30:23 PM PDT 24
Finished Aug 15 04:30:26 PM PDT 24
Peak memory 217388 kb
Host smart-b90814a9-f4c2-49e5-af1c-0a9860962c35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396956636 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1396956636
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.194211296
Short name T1129
Test name
Test status
Simulation time 35651432 ps
CPU time 1.31 seconds
Started Aug 15 04:30:37 PM PDT 24
Finished Aug 15 04:30:39 PM PDT 24
Peak memory 215700 kb
Host smart-e29a4edd-050a-4863-b75d-97aee18ab93e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194211296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.194211296
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3675445657
Short name T1060
Test name
Test status
Simulation time 14338467 ps
CPU time 0.74 seconds
Started Aug 15 04:30:20 PM PDT 24
Finished Aug 15 04:30:21 PM PDT 24
Peak memory 204160 kb
Host smart-ce553337-2cff-4ffc-ae62-110acecab5fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675445657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3675445657
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2358021589
Short name T142
Test name
Test status
Simulation time 569230583 ps
CPU time 3.07 seconds
Started Aug 15 04:29:55 PM PDT 24
Finished Aug 15 04:29:58 PM PDT 24
Peak memory 215780 kb
Host smart-01fdbff7-8e15-4259-99b4-69eda89dbfdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358021589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2358021589
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1289657033
Short name T1088
Test name
Test status
Simulation time 171932276 ps
CPU time 2.68 seconds
Started Aug 15 04:29:39 PM PDT 24
Finished Aug 15 04:29:41 PM PDT 24
Peak memory 216936 kb
Host smart-69c325ea-cc0e-4205-bbb4-2b40759c37a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289657033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1289657033
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.878346084
Short name T1082
Test name
Test status
Simulation time 7423554264 ps
CPU time 20.74 seconds
Started Aug 15 04:29:36 PM PDT 24
Finished Aug 15 04:29:57 PM PDT 24
Peak memory 215860 kb
Host smart-add7d81d-1603-4ba3-a72e-de030f082179
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878346084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.878346084
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.211544403
Short name T1064
Test name
Test status
Simulation time 333472722 ps
CPU time 2.73 seconds
Started Aug 15 04:29:36 PM PDT 24
Finished Aug 15 04:29:39 PM PDT 24
Peak memory 217360 kb
Host smart-0b0e35f4-b4ef-466a-85f8-a4a45a20a0b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211544403 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.211544403
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3975307718
Short name T125
Test name
Test status
Simulation time 85336796 ps
CPU time 2.39 seconds
Started Aug 15 04:29:54 PM PDT 24
Finished Aug 15 04:29:57 PM PDT 24
Peak memory 215740 kb
Host smart-cf0ee57e-ef8e-4be4-a6f3-dd3fd28eba78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975307718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3975307718
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2313797999
Short name T1042
Test name
Test status
Simulation time 15411312 ps
CPU time 0.75 seconds
Started Aug 15 04:29:59 PM PDT 24
Finished Aug 15 04:30:00 PM PDT 24
Peak memory 204140 kb
Host smart-102f9f44-da0e-4734-8ef3-4e0119f85a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313797999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2313797999
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3630491112
Short name T1109
Test name
Test status
Simulation time 1162587087 ps
CPU time 3.98 seconds
Started Aug 15 04:30:05 PM PDT 24
Finished Aug 15 04:30:09 PM PDT 24
Peak memory 215732 kb
Host smart-df6129d2-dde0-4f89-83bb-48fd31676d25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630491112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3630491112
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2683784300
Short name T97
Test name
Test status
Simulation time 211189074 ps
CPU time 3.6 seconds
Started Aug 15 04:30:30 PM PDT 24
Finished Aug 15 04:30:34 PM PDT 24
Peak memory 216032 kb
Host smart-f979358e-ec74-4f32-982c-a557e7b4d434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683784300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2683784300
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4094828775
Short name T1071
Test name
Test status
Simulation time 388220435 ps
CPU time 7.78 seconds
Started Aug 15 04:29:51 PM PDT 24
Finished Aug 15 04:29:59 PM PDT 24
Peak memory 215744 kb
Host smart-c406560c-fefd-44d1-922c-9ca7172299f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094828775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4094828775
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2716361464
Short name T1072
Test name
Test status
Simulation time 6677431062 ps
CPU time 26.92 seconds
Started Aug 15 04:29:42 PM PDT 24
Finished Aug 15 04:30:09 PM PDT 24
Peak memory 207684 kb
Host smart-4c4c4302-2d7c-40dd-af65-25b6c92a9be7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716361464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2716361464
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3390171811
Short name T83
Test name
Test status
Simulation time 23142757 ps
CPU time 1.32 seconds
Started Aug 15 04:30:23 PM PDT 24
Finished Aug 15 04:30:24 PM PDT 24
Peak memory 207520 kb
Host smart-97f1cf06-20f6-4414-ad13-1ee443c06c6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390171811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3390171811
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3193319038
Short name T1145
Test name
Test status
Simulation time 53378559 ps
CPU time 2.36 seconds
Started Aug 15 04:30:00 PM PDT 24
Finished Aug 15 04:30:03 PM PDT 24
Peak memory 217484 kb
Host smart-4cd549a6-2e6c-467c-b000-d41a5436c540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193319038 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3193319038
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3396289031
Short name T1115
Test name
Test status
Simulation time 76733734 ps
CPU time 1.89 seconds
Started Aug 15 04:29:34 PM PDT 24
Finished Aug 15 04:29:36 PM PDT 24
Peak memory 215768 kb
Host smart-84e553a5-1377-4eb1-9143-dd265cf7eeac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396289031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
396289031
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1303480886
Short name T1144
Test name
Test status
Simulation time 50458921 ps
CPU time 0.75 seconds
Started Aug 15 04:29:58 PM PDT 24
Finished Aug 15 04:29:59 PM PDT 24
Peak memory 204164 kb
Host smart-1eb8154b-c756-472e-bdc1-4d4267ddcb5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303480886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
303480886
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1826633511
Short name T1131
Test name
Test status
Simulation time 87879356 ps
CPU time 1.3 seconds
Started Aug 15 04:29:49 PM PDT 24
Finished Aug 15 04:29:50 PM PDT 24
Peak memory 215788 kb
Host smart-d39267de-a4c5-45e5-8e79-189ed1dc851c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826633511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1826633511
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.997001000
Short name T1059
Test name
Test status
Simulation time 20201586 ps
CPU time 0.67 seconds
Started Aug 15 04:29:49 PM PDT 24
Finished Aug 15 04:29:49 PM PDT 24
Peak memory 204080 kb
Host smart-30d9aa8f-e614-4ab4-9ed2-48c4b466b3ea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997001000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.997001000
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4108195657
Short name T1033
Test name
Test status
Simulation time 455507681 ps
CPU time 3.03 seconds
Started Aug 15 04:29:34 PM PDT 24
Finished Aug 15 04:29:37 PM PDT 24
Peak memory 215704 kb
Host smart-410918b1-8345-490e-b525-22066226c578
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108195657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4108195657
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1518961701
Short name T99
Test name
Test status
Simulation time 71379238 ps
CPU time 4.57 seconds
Started Aug 15 04:29:46 PM PDT 24
Finished Aug 15 04:29:51 PM PDT 24
Peak memory 216088 kb
Host smart-83db01e1-1c5d-4b03-9164-22e801e3c5df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518961701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
518961701
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2973952997
Short name T93
Test name
Test status
Simulation time 1512187938 ps
CPU time 9.23 seconds
Started Aug 15 04:30:01 PM PDT 24
Finished Aug 15 04:30:11 PM PDT 24
Peak memory 215720 kb
Host smart-0e2a446a-0732-4760-9a1e-8a0c434b58da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973952997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2973952997
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2912362643
Short name T1139
Test name
Test status
Simulation time 14917080 ps
CPU time 0.73 seconds
Started Aug 15 04:29:36 PM PDT 24
Finished Aug 15 04:29:37 PM PDT 24
Peak memory 204132 kb
Host smart-da9a6d59-6dac-472c-ae77-e91665c28215
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912362643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2912362643
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.399129319
Short name T1034
Test name
Test status
Simulation time 23115494 ps
CPU time 0.81 seconds
Started Aug 15 04:29:38 PM PDT 24
Finished Aug 15 04:29:39 PM PDT 24
Peak memory 203312 kb
Host smart-0e1144d9-f832-43df-8a60-aee3a526104a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399129319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.399129319
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2107587418
Short name T1080
Test name
Test status
Simulation time 39096591 ps
CPU time 0.74 seconds
Started Aug 15 04:30:01 PM PDT 24
Finished Aug 15 04:30:05 PM PDT 24
Peak memory 204548 kb
Host smart-688cd9d3-60d8-444f-aaea-2c360b426590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107587418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2107587418
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4020388503
Short name T1049
Test name
Test status
Simulation time 14466917 ps
CPU time 0.72 seconds
Started Aug 15 04:29:38 PM PDT 24
Finished Aug 15 04:29:38 PM PDT 24
Peak memory 204472 kb
Host smart-b091322e-f379-456d-955a-274961275d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020388503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4020388503
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2299511159
Short name T1038
Test name
Test status
Simulation time 166790599 ps
CPU time 0.69 seconds
Started Aug 15 04:30:15 PM PDT 24
Finished Aug 15 04:30:15 PM PDT 24
Peak memory 204468 kb
Host smart-36879aab-1ee1-41d1-9f52-96d142ac2ccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299511159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2299511159
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.12905350
Short name T1113
Test name
Test status
Simulation time 21352077 ps
CPU time 0.7 seconds
Started Aug 15 04:30:18 PM PDT 24
Finished Aug 15 04:30:19 PM PDT 24
Peak memory 204092 kb
Host smart-34de45d2-1c9d-4f6e-a35e-7b62bb637cad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12905350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.12905350
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.4119106570
Short name T1134
Test name
Test status
Simulation time 23645858 ps
CPU time 0.73 seconds
Started Aug 15 04:29:52 PM PDT 24
Finished Aug 15 04:29:53 PM PDT 24
Peak memory 204452 kb
Host smart-3b68b065-4d1c-4a01-b0e4-3a986f84149a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119106570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
4119106570
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1252861261
Short name T1148
Test name
Test status
Simulation time 20443114 ps
CPU time 0.77 seconds
Started Aug 15 04:29:39 PM PDT 24
Finished Aug 15 04:29:40 PM PDT 24
Peak memory 204260 kb
Host smart-361386a4-995d-4e93-bf81-90134603f809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252861261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1252861261
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2852399490
Short name T1025
Test name
Test status
Simulation time 46757416 ps
CPU time 0.72 seconds
Started Aug 15 04:30:10 PM PDT 24
Finished Aug 15 04:30:11 PM PDT 24
Peak memory 204488 kb
Host smart-a5ca3914-50ac-4c30-b2e4-a6e667980328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852399490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2852399490
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1576572426
Short name T1065
Test name
Test status
Simulation time 35189197 ps
CPU time 0.68 seconds
Started Aug 15 04:29:58 PM PDT 24
Finished Aug 15 04:29:59 PM PDT 24
Peak memory 204464 kb
Host smart-f3fd90b6-a7c5-4c7a-a5bd-9a82846f6484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576572426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1576572426
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3161917650
Short name T1110
Test name
Test status
Simulation time 1837378747 ps
CPU time 23.03 seconds
Started Aug 15 04:29:36 PM PDT 24
Finished Aug 15 04:30:00 PM PDT 24
Peak memory 215732 kb
Host smart-775477a1-6c69-407e-9af0-a2bef7131b2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161917650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3161917650
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.793499060
Short name T1108
Test name
Test status
Simulation time 639717930 ps
CPU time 13.02 seconds
Started Aug 15 04:29:34 PM PDT 24
Finished Aug 15 04:29:47 PM PDT 24
Peak memory 215736 kb
Host smart-8170cbdb-9a75-446d-90b1-1a351b9660d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793499060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.793499060
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2631804159
Short name T1130
Test name
Test status
Simulation time 31152943 ps
CPU time 1.15 seconds
Started Aug 15 04:29:33 PM PDT 24
Finished Aug 15 04:29:35 PM PDT 24
Peak memory 207448 kb
Host smart-f25b34cf-cadc-462c-8732-ee497983e7dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631804159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2631804159
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.307466188
Short name T1121
Test name
Test status
Simulation time 25802261 ps
CPU time 1.67 seconds
Started Aug 15 04:29:34 PM PDT 24
Finished Aug 15 04:29:36 PM PDT 24
Peak memory 216992 kb
Host smart-7bfcd2b8-4699-4962-9fa3-ffd21c6e82c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307466188 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.307466188
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1154318711
Short name T121
Test name
Test status
Simulation time 30784065 ps
CPU time 1.74 seconds
Started Aug 15 04:29:37 PM PDT 24
Finished Aug 15 04:29:39 PM PDT 24
Peak memory 215760 kb
Host smart-dfc32609-2a00-425f-a908-cc2243c71626
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154318711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
154318711
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2897540065
Short name T1058
Test name
Test status
Simulation time 13691708 ps
CPU time 0.77 seconds
Started Aug 15 04:29:24 PM PDT 24
Finished Aug 15 04:29:25 PM PDT 24
Peak memory 204128 kb
Host smart-a533df02-8a85-43b8-9f57-15413259e2fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897540065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
897540065
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3843787013
Short name T1123
Test name
Test status
Simulation time 287600026 ps
CPU time 2.2 seconds
Started Aug 15 04:29:51 PM PDT 24
Finished Aug 15 04:29:53 PM PDT 24
Peak memory 215712 kb
Host smart-5f06cee3-68e3-4aa0-bbde-7f8a57c28c51
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843787013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3843787013
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2370487829
Short name T1092
Test name
Test status
Simulation time 34148223 ps
CPU time 0.65 seconds
Started Aug 15 04:29:59 PM PDT 24
Finished Aug 15 04:29:59 PM PDT 24
Peak memory 204408 kb
Host smart-7bca45b9-c93d-419d-9478-ab241db33745
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370487829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2370487829
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1287434545
Short name T1101
Test name
Test status
Simulation time 45583174 ps
CPU time 2.64 seconds
Started Aug 15 04:30:04 PM PDT 24
Finished Aug 15 04:30:06 PM PDT 24
Peak memory 215696 kb
Host smart-75290cd9-a946-4648-aeb3-282fc5cea741
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287434545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1287434545
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3639925943
Short name T1120
Test name
Test status
Simulation time 595126471 ps
CPU time 2.61 seconds
Started Aug 15 04:29:40 PM PDT 24
Finished Aug 15 04:29:43 PM PDT 24
Peak memory 215908 kb
Host smart-4dbdbca8-273d-4f20-b313-6fa77dbcf411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639925943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
639925943
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4280831431
Short name T91
Test name
Test status
Simulation time 403074121 ps
CPU time 13.31 seconds
Started Aug 15 04:29:41 PM PDT 24
Finished Aug 15 04:29:55 PM PDT 24
Peak memory 215796 kb
Host smart-c86a8730-62de-43bc-977b-30a98ff0a848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280831431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4280831431
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3618368401
Short name T1026
Test name
Test status
Simulation time 14184940 ps
CPU time 0.73 seconds
Started Aug 15 04:29:57 PM PDT 24
Finished Aug 15 04:29:58 PM PDT 24
Peak memory 204088 kb
Host smart-6dceb467-4063-4106-8a33-078a24207392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618368401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3618368401
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3524770409
Short name T1107
Test name
Test status
Simulation time 44569993 ps
CPU time 0.73 seconds
Started Aug 15 04:29:54 PM PDT 24
Finished Aug 15 04:29:55 PM PDT 24
Peak memory 204080 kb
Host smart-1048c3e6-c20a-4bb4-9994-27896c9f3425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524770409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3524770409
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1767904213
Short name T1041
Test name
Test status
Simulation time 21266562 ps
CPU time 0.71 seconds
Started Aug 15 04:29:59 PM PDT 24
Finished Aug 15 04:30:00 PM PDT 24
Peak memory 204256 kb
Host smart-2271530e-a9ad-4450-8e6b-fb90cb458f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767904213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1767904213
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4242889408
Short name T1122
Test name
Test status
Simulation time 17128999 ps
CPU time 0.77 seconds
Started Aug 15 04:30:03 PM PDT 24
Finished Aug 15 04:30:04 PM PDT 24
Peak memory 204472 kb
Host smart-9cca4602-37b9-4bc7-9d5a-dea3495f3602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242889408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4242889408
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3149385242
Short name T1028
Test name
Test status
Simulation time 14712629 ps
CPU time 0.75 seconds
Started Aug 15 04:29:56 PM PDT 24
Finished Aug 15 04:29:57 PM PDT 24
Peak memory 204116 kb
Host smart-b5bac20c-7462-4597-a0eb-0743e3d35c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149385242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3149385242
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2858213010
Short name T1103
Test name
Test status
Simulation time 94575688 ps
CPU time 0.75 seconds
Started Aug 15 04:30:06 PM PDT 24
Finished Aug 15 04:30:07 PM PDT 24
Peak memory 204140 kb
Host smart-2abd4611-0fb7-4ad3-87a5-c664276c1a0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858213010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2858213010
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1211877257
Short name T1052
Test name
Test status
Simulation time 20087715 ps
CPU time 0.71 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:30:09 PM PDT 24
Peak memory 204472 kb
Host smart-2828f32d-27f6-4ee4-b409-df132349da6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211877257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1211877257
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1500083583
Short name T1063
Test name
Test status
Simulation time 136095413 ps
CPU time 0.72 seconds
Started Aug 15 04:29:52 PM PDT 24
Finished Aug 15 04:29:53 PM PDT 24
Peak memory 204372 kb
Host smart-b75ee38e-85e7-4d2c-85b4-c360d4b1e518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500083583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1500083583
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3578189392
Short name T1037
Test name
Test status
Simulation time 42425885 ps
CPU time 0.73 seconds
Started Aug 15 04:29:56 PM PDT 24
Finished Aug 15 04:29:57 PM PDT 24
Peak memory 204108 kb
Host smart-e8b486c3-5320-4660-b87c-8f0ef9112210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578189392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3578189392
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.665081128
Short name T1081
Test name
Test status
Simulation time 76605176 ps
CPU time 0.7 seconds
Started Aug 15 04:30:04 PM PDT 24
Finished Aug 15 04:30:05 PM PDT 24
Peak memory 204104 kb
Host smart-67fdb520-7b4f-4bec-9707-f04aed8dae53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665081128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.665081128
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.173060109
Short name T1125
Test name
Test status
Simulation time 4360825255 ps
CPU time 7.47 seconds
Started Aug 15 04:29:38 PM PDT 24
Finished Aug 15 04:29:46 PM PDT 24
Peak memory 207380 kb
Host smart-7f71f5ac-00e1-4bf5-a38d-12be4d533e3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173060109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.173060109
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2801326902
Short name T126
Test name
Test status
Simulation time 1588971008 ps
CPU time 22.27 seconds
Started Aug 15 04:29:33 PM PDT 24
Finished Aug 15 04:29:55 PM PDT 24
Peak memory 207476 kb
Host smart-ca61c4cc-ff37-4119-867c-93d2d07bfa01
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801326902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2801326902
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1509255331
Short name T85
Test name
Test status
Simulation time 30835089 ps
CPU time 1.13 seconds
Started Aug 15 04:29:38 PM PDT 24
Finished Aug 15 04:29:39 PM PDT 24
Peak memory 215356 kb
Host smart-ab420094-e8fd-4aee-8017-abb2badf4ca4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509255331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1509255331
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.612118237
Short name T100
Test name
Test status
Simulation time 150280111 ps
CPU time 3.69 seconds
Started Aug 15 04:29:31 PM PDT 24
Finished Aug 15 04:29:35 PM PDT 24
Peak memory 217840 kb
Host smart-49327177-b98f-4d3c-b0d2-88f03775572d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612118237 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.612118237
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2979223456
Short name T1132
Test name
Test status
Simulation time 1444435124 ps
CPU time 1.96 seconds
Started Aug 15 04:29:58 PM PDT 24
Finished Aug 15 04:30:00 PM PDT 24
Peak memory 215784 kb
Host smart-e8bf822f-0439-4588-84b8-ff675f770cf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979223456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
979223456
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1224580455
Short name T1096
Test name
Test status
Simulation time 16502844 ps
CPU time 0.74 seconds
Started Aug 15 04:29:59 PM PDT 24
Finished Aug 15 04:30:00 PM PDT 24
Peak memory 204136 kb
Host smart-5ab07e9b-135b-48a7-bff4-a72635bcdb43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224580455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
224580455
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2671789070
Short name T127
Test name
Test status
Simulation time 47749780 ps
CPU time 1.74 seconds
Started Aug 15 04:29:43 PM PDT 24
Finished Aug 15 04:29:45 PM PDT 24
Peak memory 215716 kb
Host smart-4f439a27-a119-442e-bfab-d2e8b08998b8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671789070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2671789070
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1026104241
Short name T1118
Test name
Test status
Simulation time 137772024 ps
CPU time 0.64 seconds
Started Aug 15 04:30:00 PM PDT 24
Finished Aug 15 04:30:01 PM PDT 24
Peak memory 204436 kb
Host smart-25a2c6a3-1dfc-4982-893a-39a5fa26e840
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026104241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1026104241
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1338631880
Short name T1067
Test name
Test status
Simulation time 52672973 ps
CPU time 1.69 seconds
Started Aug 15 04:29:38 PM PDT 24
Finished Aug 15 04:29:40 PM PDT 24
Peak memory 215724 kb
Host smart-9ebb06da-6d76-4992-bd36-a5e2647c6443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338631880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1338631880
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3067870751
Short name T96
Test name
Test status
Simulation time 68480755 ps
CPU time 2.03 seconds
Started Aug 15 04:29:28 PM PDT 24
Finished Aug 15 04:29:30 PM PDT 24
Peak memory 215928 kb
Host smart-94d2b3c7-86cd-45e8-a727-ff91f0d67e0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067870751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
067870751
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.306003233
Short name T1075
Test name
Test status
Simulation time 3716161992 ps
CPU time 15.99 seconds
Started Aug 15 04:29:32 PM PDT 24
Finished Aug 15 04:29:48 PM PDT 24
Peak memory 215840 kb
Host smart-5cb73126-bab9-4bb3-8614-700b5e189650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306003233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.306003233
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.683509562
Short name T1031
Test name
Test status
Simulation time 61196826 ps
CPU time 0.72 seconds
Started Aug 15 04:30:15 PM PDT 24
Finished Aug 15 04:30:15 PM PDT 24
Peak memory 204128 kb
Host smart-f4dd6552-f446-4e94-ad64-a2a1b6821030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683509562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.683509562
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.159454223
Short name T1061
Test name
Test status
Simulation time 25935033 ps
CPU time 0.75 seconds
Started Aug 15 04:29:57 PM PDT 24
Finished Aug 15 04:29:58 PM PDT 24
Peak memory 204188 kb
Host smart-30c168e6-45e5-4fb5-968a-045aceb8d5df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159454223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.159454223
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3154088939
Short name T1027
Test name
Test status
Simulation time 28129521 ps
CPU time 0.74 seconds
Started Aug 15 04:30:01 PM PDT 24
Finished Aug 15 04:30:02 PM PDT 24
Peak memory 204156 kb
Host smart-a5644028-a1a9-4928-b78c-018422f2e224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154088939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3154088939
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2298795612
Short name T1056
Test name
Test status
Simulation time 118693196 ps
CPU time 0.84 seconds
Started Aug 15 04:30:07 PM PDT 24
Finished Aug 15 04:30:09 PM PDT 24
Peak memory 202856 kb
Host smart-841656c2-25fa-443f-9ce5-1751639829d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298795612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2298795612
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4025205596
Short name T1030
Test name
Test status
Simulation time 42412300 ps
CPU time 0.72 seconds
Started Aug 15 04:30:05 PM PDT 24
Finished Aug 15 04:30:05 PM PDT 24
Peak memory 204224 kb
Host smart-1dfc539a-fa8e-4551-a063-77d103df5c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025205596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
4025205596
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3417000004
Short name T1024
Test name
Test status
Simulation time 28606725 ps
CPU time 0.79 seconds
Started Aug 15 04:29:56 PM PDT 24
Finished Aug 15 04:29:57 PM PDT 24
Peak memory 204396 kb
Host smart-602d9647-a439-40aa-a791-8b06aeebc115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417000004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3417000004
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.370085518
Short name T1032
Test name
Test status
Simulation time 16695024 ps
CPU time 0.78 seconds
Started Aug 15 04:30:01 PM PDT 24
Finished Aug 15 04:30:02 PM PDT 24
Peak memory 204248 kb
Host smart-e15c42fa-6ef9-48e3-8178-4b8dc2ba00d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370085518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.370085518
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1285085103
Short name T1077
Test name
Test status
Simulation time 13430651 ps
CPU time 0.77 seconds
Started Aug 15 04:29:51 PM PDT 24
Finished Aug 15 04:29:52 PM PDT 24
Peak memory 204156 kb
Host smart-5b0fa25e-2503-4a68-b9cd-f27d1613dc4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285085103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1285085103
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3567382688
Short name T1105
Test name
Test status
Simulation time 28842138 ps
CPU time 0.75 seconds
Started Aug 15 04:30:00 PM PDT 24
Finished Aug 15 04:30:02 PM PDT 24
Peak memory 204140 kb
Host smart-ed2759b8-b031-4b76-a457-800f173e653a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567382688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3567382688
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.115709587
Short name T1086
Test name
Test status
Simulation time 14365444 ps
CPU time 0.71 seconds
Started Aug 15 04:30:03 PM PDT 24
Finished Aug 15 04:30:04 PM PDT 24
Peak memory 204484 kb
Host smart-affee288-cfd8-4cb2-abca-906d58ee9cb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115709587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.115709587
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2259435650
Short name T1146
Test name
Test status
Simulation time 193140440 ps
CPU time 3.74 seconds
Started Aug 15 04:29:46 PM PDT 24
Finished Aug 15 04:29:55 PM PDT 24
Peak memory 218412 kb
Host smart-e967dd65-63e3-45ea-abfb-5bd4bfcce08d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259435650 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2259435650
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.641732638
Short name T1106
Test name
Test status
Simulation time 66039945 ps
CPU time 0.75 seconds
Started Aug 15 04:29:52 PM PDT 24
Finished Aug 15 04:29:53 PM PDT 24
Peak memory 204472 kb
Host smart-5aec1d15-225a-4a9f-8d88-74f52289b8d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641732638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.641732638
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2464788712
Short name T1043
Test name
Test status
Simulation time 276641183 ps
CPU time 1.82 seconds
Started Aug 15 04:29:34 PM PDT 24
Finished Aug 15 04:29:36 PM PDT 24
Peak memory 216076 kb
Host smart-19b69edb-603e-42ac-852c-53740ddc1c9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464788712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2464788712
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3408687464
Short name T1111
Test name
Test status
Simulation time 82180427 ps
CPU time 3.62 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:30:12 PM PDT 24
Peak memory 215912 kb
Host smart-a5e4220f-eb18-4aff-a4c4-817171ab7eb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408687464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
408687464
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1531893453
Short name T92
Test name
Test status
Simulation time 607125066 ps
CPU time 19.97 seconds
Started Aug 15 04:29:35 PM PDT 24
Finished Aug 15 04:29:55 PM PDT 24
Peak memory 216436 kb
Host smart-4ecbcce4-9268-4b72-b2d4-3178ba4131d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531893453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1531893453
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1528179308
Short name T94
Test name
Test status
Simulation time 58094939 ps
CPU time 1.68 seconds
Started Aug 15 04:29:36 PM PDT 24
Finished Aug 15 04:29:38 PM PDT 24
Peak memory 215876 kb
Host smart-8841e87c-09c0-4ae4-8737-1a9a76fe5fbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528179308 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1528179308
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2562674970
Short name T1100
Test name
Test status
Simulation time 78467395 ps
CPU time 1.26 seconds
Started Aug 15 04:29:52 PM PDT 24
Finished Aug 15 04:29:53 PM PDT 24
Peak memory 215720 kb
Host smart-53bb8db6-a3a5-41f5-8c1c-363d795a7ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562674970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
562674970
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3954999198
Short name T1090
Test name
Test status
Simulation time 61226939 ps
CPU time 0.76 seconds
Started Aug 15 04:29:51 PM PDT 24
Finished Aug 15 04:29:52 PM PDT 24
Peak memory 204028 kb
Host smart-1b9afbc9-6f91-438f-8be8-b45ad95874a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954999198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
954999198
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.883624687
Short name T1143
Test name
Test status
Simulation time 211138852 ps
CPU time 4 seconds
Started Aug 15 04:29:38 PM PDT 24
Finished Aug 15 04:29:42 PM PDT 24
Peak memory 215200 kb
Host smart-34817cba-11b1-4795-a079-897b7fcf6c64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883624687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.883624687
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.533518286
Short name T104
Test name
Test status
Simulation time 247279277 ps
CPU time 3.43 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:30:11 PM PDT 24
Peak memory 215836 kb
Host smart-d60b0bd5-52bf-418f-87e9-d8e2b9c062fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533518286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.533518286
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2977701493
Short name T1079
Test name
Test status
Simulation time 142233028 ps
CPU time 1.53 seconds
Started Aug 15 04:30:05 PM PDT 24
Finished Aug 15 04:30:07 PM PDT 24
Peak memory 215876 kb
Host smart-ebc1aea4-137f-430f-931b-88cc1f3f6f6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977701493 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2977701493
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.270760270
Short name T1102
Test name
Test status
Simulation time 1005295570 ps
CPU time 1.82 seconds
Started Aug 15 04:29:55 PM PDT 24
Finished Aug 15 04:29:57 PM PDT 24
Peak memory 207696 kb
Host smart-2a1b8bcb-ccd7-4980-a6c0-b62a4ce1c0d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270760270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.270760270
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3575045220
Short name T1048
Test name
Test status
Simulation time 16774366 ps
CPU time 0.74 seconds
Started Aug 15 04:30:04 PM PDT 24
Finished Aug 15 04:30:05 PM PDT 24
Peak memory 204580 kb
Host smart-d65c9c99-f9ad-4d95-b5d0-2b23f8856f6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575045220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
575045220
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.361896211
Short name T143
Test name
Test status
Simulation time 913927949 ps
CPU time 4.18 seconds
Started Aug 15 04:29:36 PM PDT 24
Finished Aug 15 04:29:40 PM PDT 24
Peak memory 215676 kb
Host smart-c0b59f87-020f-46b3-a4b9-97d7f1bfcbee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361896211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.361896211
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3596900614
Short name T110
Test name
Test status
Simulation time 867165646 ps
CPU time 5.48 seconds
Started Aug 15 04:29:50 PM PDT 24
Finished Aug 15 04:29:56 PM PDT 24
Peak memory 215788 kb
Host smart-9ab8532f-c77f-46eb-9c55-62efef0664e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596900614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
596900614
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3999233622
Short name T1098
Test name
Test status
Simulation time 54252577 ps
CPU time 1.7 seconds
Started Aug 15 04:29:38 PM PDT 24
Finished Aug 15 04:29:45 PM PDT 24
Peak memory 215892 kb
Host smart-9a6bb7db-d964-4dee-b771-3c4ae9818eb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999233622 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3999233622
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1658159912
Short name T1136
Test name
Test status
Simulation time 368701553 ps
CPU time 2.61 seconds
Started Aug 15 04:29:57 PM PDT 24
Finished Aug 15 04:30:00 PM PDT 24
Peak memory 215704 kb
Host smart-04a10622-c010-449c-8d9e-b194d677adb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658159912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
658159912
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.734425550
Short name T1133
Test name
Test status
Simulation time 37119137 ps
CPU time 0.72 seconds
Started Aug 15 04:29:44 PM PDT 24
Finished Aug 15 04:29:44 PM PDT 24
Peak memory 204136 kb
Host smart-83a50006-629e-42a0-b6e3-3918d61e0d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734425550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.734425550
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.628252343
Short name T1040
Test name
Test status
Simulation time 159180102 ps
CPU time 2.63 seconds
Started Aug 15 04:29:29 PM PDT 24
Finished Aug 15 04:29:31 PM PDT 24
Peak memory 215744 kb
Host smart-fdfcf219-3118-4440-a277-8165d99a99b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628252343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.628252343
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.246418749
Short name T1119
Test name
Test status
Simulation time 669647116 ps
CPU time 3.94 seconds
Started Aug 15 04:30:07 PM PDT 24
Finished Aug 15 04:30:12 PM PDT 24
Peak memory 214388 kb
Host smart-84c88481-8dfa-491e-9fba-bae4aeea6d87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246418749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.246418749
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2347355894
Short name T172
Test name
Test status
Simulation time 108339152 ps
CPU time 6.37 seconds
Started Aug 15 04:29:50 PM PDT 24
Finished Aug 15 04:29:57 PM PDT 24
Peak memory 216288 kb
Host smart-919ddfd8-5d98-4f5f-bc3d-379bdc9910f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347355894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2347355894
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.146072483
Short name T1089
Test name
Test status
Simulation time 124290702 ps
CPU time 3.54 seconds
Started Aug 15 04:29:38 PM PDT 24
Finished Aug 15 04:29:47 PM PDT 24
Peak memory 218368 kb
Host smart-af14c658-7f64-423c-b9c4-b942da268b84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146072483 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.146072483
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3835440205
Short name T1147
Test name
Test status
Simulation time 57319877 ps
CPU time 1.18 seconds
Started Aug 15 04:30:03 PM PDT 24
Finished Aug 15 04:30:05 PM PDT 24
Peak memory 207500 kb
Host smart-b7a261cd-ef9f-4bf2-986d-98f04ce9d3e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835440205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
835440205
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2689824472
Short name T1091
Test name
Test status
Simulation time 11364733 ps
CPU time 0.71 seconds
Started Aug 15 04:30:04 PM PDT 24
Finished Aug 15 04:30:05 PM PDT 24
Peak memory 204140 kb
Host smart-f51d7780-d181-46ea-951a-875185761277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689824472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
689824472
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4031919798
Short name T1036
Test name
Test status
Simulation time 56446315 ps
CPU time 1.74 seconds
Started Aug 15 04:30:24 PM PDT 24
Finished Aug 15 04:30:26 PM PDT 24
Peak memory 215676 kb
Host smart-faf4a85e-79a9-4e4d-ba16-b1393cc8c5db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031919798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4031919798
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3632825965
Short name T103
Test name
Test status
Simulation time 149071690 ps
CPU time 3.35 seconds
Started Aug 15 04:29:33 PM PDT 24
Finished Aug 15 04:29:36 PM PDT 24
Peak memory 216944 kb
Host smart-58e45d83-e4e8-4e0e-a478-7d5647d7261f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632825965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
632825965
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.87397380
Short name T174
Test name
Test status
Simulation time 825973152 ps
CPU time 12.12 seconds
Started Aug 15 04:29:55 PM PDT 24
Finished Aug 15 04:30:07 PM PDT 24
Peak memory 215680 kb
Host smart-d8167fcb-132a-4587-9a71-e6b851f4e577
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87397380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_t
l_intg_err.87397380
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3595226042
Short name T26
Test name
Test status
Simulation time 360559334 ps
CPU time 5.46 seconds
Started Aug 15 04:31:46 PM PDT 24
Finished Aug 15 04:31:52 PM PDT 24
Peak memory 224504 kb
Host smart-798b1f02-2da1-4a28-b0eb-bd206da74994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595226042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3595226042
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1158067662
Short name T523
Test name
Test status
Simulation time 204775815 ps
CPU time 0.83 seconds
Started Aug 15 04:31:45 PM PDT 24
Finished Aug 15 04:31:46 PM PDT 24
Peak memory 206432 kb
Host smart-d3804409-868d-42d6-8632-3fd71922e5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158067662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1158067662
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.261332225
Short name T28
Test name
Test status
Simulation time 346092879 ps
CPU time 6.97 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:31:54 PM PDT 24
Peak memory 232772 kb
Host smart-33116fe4-44da-4d06-876f-6828833b6109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261332225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.261332225
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.38779888
Short name T212
Test name
Test status
Simulation time 3997211663 ps
CPU time 46.59 seconds
Started Aug 15 04:31:46 PM PDT 24
Finished Aug 15 04:32:33 PM PDT 24
Peak memory 239516 kb
Host smart-4afbda13-5d75-44aa-9b0e-63631ee30c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38779888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.38779888
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2877642851
Short name T136
Test name
Test status
Simulation time 860536691 ps
CPU time 15.75 seconds
Started Aug 15 04:31:48 PM PDT 24
Finished Aug 15 04:32:04 PM PDT 24
Peak memory 224568 kb
Host smart-31673e7a-8b3f-40ab-b633-08b1f67e709a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877642851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2877642851
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2276755530
Short name T700
Test name
Test status
Simulation time 103105303 ps
CPU time 2.26 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:31:49 PM PDT 24
Peak memory 224500 kb
Host smart-7585f677-d40d-40bd-8575-48ddd9d66576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276755530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2276755530
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1259955866
Short name T851
Test name
Test status
Simulation time 520868458 ps
CPU time 3.81 seconds
Started Aug 15 04:31:44 PM PDT 24
Finished Aug 15 04:31:48 PM PDT 24
Peak memory 232644 kb
Host smart-96a8ddfd-c241-4ca5-ba0d-7aa54d6495b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259955866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1259955866
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2171052587
Short name T211
Test name
Test status
Simulation time 342522034 ps
CPU time 7.48 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:32:00 PM PDT 24
Peak memory 232696 kb
Host smart-c48e3abe-0d7b-44e3-985a-fcd8d0168452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171052587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2171052587
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2223479090
Short name T61
Test name
Test status
Simulation time 44163241114 ps
CPU time 28.07 seconds
Started Aug 15 04:31:50 PM PDT 24
Finished Aug 15 04:32:18 PM PDT 24
Peak memory 232664 kb
Host smart-e507a17c-79aa-4af3-9af7-0a7c52a62fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223479090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2223479090
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2319169584
Short name T972
Test name
Test status
Simulation time 637398786 ps
CPU time 5.85 seconds
Started Aug 15 04:31:48 PM PDT 24
Finished Aug 15 04:31:54 PM PDT 24
Peak memory 218696 kb
Host smart-8d2d6a3f-6b22-41d5-b674-acf4a1004c93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2319169584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2319169584
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.319143862
Short name T70
Test name
Test status
Simulation time 174938602 ps
CPU time 0.94 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:31:48 PM PDT 24
Peak memory 235836 kb
Host smart-7cc3dca8-957a-42b9-894d-71048900c306
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319143862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.319143862
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3716484353
Short name T996
Test name
Test status
Simulation time 3225595645 ps
CPU time 22.87 seconds
Started Aug 15 04:31:44 PM PDT 24
Finished Aug 15 04:32:07 PM PDT 24
Peak memory 256200 kb
Host smart-69856882-db69-415a-9314-18e8abffd699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716484353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3716484353
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3983962580
Short name T812
Test name
Test status
Simulation time 1409245641 ps
CPU time 7.44 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:31:54 PM PDT 24
Peak memory 216396 kb
Host smart-2d90892d-6594-4ab7-8f83-21558d550c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983962580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3983962580
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2587345223
Short name T810
Test name
Test status
Simulation time 4686919862 ps
CPU time 6.21 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:31:53 PM PDT 24
Peak memory 216336 kb
Host smart-4de30b29-7ffd-40ce-a593-a9ace0ff7bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587345223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2587345223
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1015171978
Short name T531
Test name
Test status
Simulation time 352758300 ps
CPU time 1.56 seconds
Started Aug 15 04:31:45 PM PDT 24
Finished Aug 15 04:31:47 PM PDT 24
Peak memory 216272 kb
Host smart-a95a56e0-6987-4a6f-beaa-0500bbe629dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015171978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1015171978
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3206795228
Short name T608
Test name
Test status
Simulation time 308852762 ps
CPU time 0.95 seconds
Started Aug 15 04:31:49 PM PDT 24
Finished Aug 15 04:31:50 PM PDT 24
Peak memory 206936 kb
Host smart-246b45d6-163e-4cf7-9011-e6b2ff78aebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206795228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3206795228
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2732113527
Short name T546
Test name
Test status
Simulation time 918490199 ps
CPU time 8.96 seconds
Started Aug 15 04:31:46 PM PDT 24
Finished Aug 15 04:31:55 PM PDT 24
Peak memory 240536 kb
Host smart-84f204d5-c100-41a7-adc1-995ff5165c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732113527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2732113527
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1254257486
Short name T334
Test name
Test status
Simulation time 16676647 ps
CPU time 0.73 seconds
Started Aug 15 04:31:54 PM PDT 24
Finished Aug 15 04:31:55 PM PDT 24
Peak memory 204780 kb
Host smart-8882f300-def3-400d-8aec-c8f57aaf9553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254257486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
254257486
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1102446053
Short name T664
Test name
Test status
Simulation time 1332355847 ps
CPU time 4.39 seconds
Started Aug 15 04:31:45 PM PDT 24
Finished Aug 15 04:31:49 PM PDT 24
Peak memory 224564 kb
Host smart-4432ea3c-da9d-4310-a8d9-ba2219e7de10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102446053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1102446053
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.512174270
Short name T841
Test name
Test status
Simulation time 19981168 ps
CPU time 0.76 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:31:53 PM PDT 24
Peak memory 206432 kb
Host smart-b44e9443-9206-41ed-9c6b-f5e3650184be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512174270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.512174270
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3320950303
Short name T839
Test name
Test status
Simulation time 204543803 ps
CPU time 0.99 seconds
Started Aug 15 04:31:45 PM PDT 24
Finished Aug 15 04:31:47 PM PDT 24
Peak memory 215856 kb
Host smart-0b536d14-3f1b-4333-86bd-2e609c1de3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320950303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3320950303
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.200379967
Short name T594
Test name
Test status
Simulation time 3594782896 ps
CPU time 71.9 seconds
Started Aug 15 04:31:49 PM PDT 24
Finished Aug 15 04:33:01 PM PDT 24
Peak memory 249884 kb
Host smart-c2c77da9-3532-48f5-817c-8ab1643ea7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200379967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.200379967
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1906285690
Short name T190
Test name
Test status
Simulation time 14108001829 ps
CPU time 97.76 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:33:24 PM PDT 24
Peak memory 251480 kb
Host smart-d5b8cc26-c3aa-474a-8c98-2179c8755be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906285690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1906285690
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3357877733
Short name T874
Test name
Test status
Simulation time 12583948220 ps
CPU time 69.36 seconds
Started Aug 15 04:31:46 PM PDT 24
Finished Aug 15 04:32:56 PM PDT 24
Peak memory 232788 kb
Host smart-539db0c5-b60b-4493-a451-0fcb49012716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357877733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3357877733
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4036025795
Short name T476
Test name
Test status
Simulation time 388837742 ps
CPU time 6.23 seconds
Started Aug 15 04:31:46 PM PDT 24
Finished Aug 15 04:31:53 PM PDT 24
Peak memory 224468 kb
Host smart-890f6418-87ab-4ae7-ae6e-3b0f833e662d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036025795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4036025795
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2655313842
Short name T467
Test name
Test status
Simulation time 1144561243 ps
CPU time 15 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:32:07 PM PDT 24
Peak memory 224476 kb
Host smart-6ba0292f-caa8-4f6e-9b11-c55f1432d578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655313842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2655313842
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3387045727
Short name T984
Test name
Test status
Simulation time 129718004 ps
CPU time 1.05 seconds
Started Aug 15 04:31:48 PM PDT 24
Finished Aug 15 04:31:49 PM PDT 24
Peak memory 216604 kb
Host smart-86b1ca66-afc0-4455-91b4-853f100253cc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387045727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3387045727
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1803893797
Short name T484
Test name
Test status
Simulation time 877099327 ps
CPU time 4.22 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:31:52 PM PDT 24
Peak memory 232652 kb
Host smart-542c2dae-f1a6-4f79-aa56-cac6d1938712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803893797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1803893797
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3840530024
Short name T234
Test name
Test status
Simulation time 3368531744 ps
CPU time 14.01 seconds
Started Aug 15 04:31:51 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 232764 kb
Host smart-f5cd5e9d-dcc9-4409-a2d1-824d649d1182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840530024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3840530024
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4176052968
Short name T714
Test name
Test status
Simulation time 760925393 ps
CPU time 4.38 seconds
Started Aug 15 04:31:45 PM PDT 24
Finished Aug 15 04:31:49 PM PDT 24
Peak memory 222980 kb
Host smart-4ce325a9-0b21-45a6-9f39-58f71717c5ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4176052968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4176052968
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3750619747
Short name T71
Test name
Test status
Simulation time 99360115 ps
CPU time 1.21 seconds
Started Aug 15 04:31:47 PM PDT 24
Finished Aug 15 04:31:48 PM PDT 24
Peak memory 235352 kb
Host smart-556a88b7-104b-435b-9a9f-fe6e8dfaeed9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750619747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3750619747
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1997721210
Short name T273
Test name
Test status
Simulation time 6099159808 ps
CPU time 106.37 seconds
Started Aug 15 04:31:46 PM PDT 24
Finished Aug 15 04:33:32 PM PDT 24
Peak memory 257380 kb
Host smart-ac459af0-4650-47f7-9ee5-4e8bca49bdca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997721210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1997721210
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2765198193
Short name T547
Test name
Test status
Simulation time 2606334453 ps
CPU time 14.58 seconds
Started Aug 15 04:31:49 PM PDT 24
Finished Aug 15 04:32:04 PM PDT 24
Peak memory 216336 kb
Host smart-9febb6c5-1223-439d-a6ac-2d831973c46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765198193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2765198193
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1320035567
Short name T587
Test name
Test status
Simulation time 102948648886 ps
CPU time 17.29 seconds
Started Aug 15 04:31:43 PM PDT 24
Finished Aug 15 04:32:01 PM PDT 24
Peak memory 216404 kb
Host smart-51d79192-cf43-4489-bf91-2819936d981e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320035567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1320035567
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2462371124
Short name T494
Test name
Test status
Simulation time 216030953 ps
CPU time 1.18 seconds
Started Aug 15 04:31:46 PM PDT 24
Finished Aug 15 04:31:47 PM PDT 24
Peak memory 207040 kb
Host smart-2b616f17-bc71-45f2-8330-ed6f3ce6d090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462371124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2462371124
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1206130595
Short name T764
Test name
Test status
Simulation time 348267561 ps
CPU time 0.83 seconds
Started Aug 15 04:31:50 PM PDT 24
Finished Aug 15 04:31:50 PM PDT 24
Peak memory 205908 kb
Host smart-2d9e6e7d-1978-476f-b6ce-8f413c97dddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206130595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1206130595
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.671714018
Short name T242
Test name
Test status
Simulation time 546055339 ps
CPU time 3.43 seconds
Started Aug 15 04:31:49 PM PDT 24
Finished Aug 15 04:31:52 PM PDT 24
Peak memory 224492 kb
Host smart-82ddb62c-4629-48ad-81b3-85c3eacbb719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671714018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.671714018
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1355114108
Short name T887
Test name
Test status
Simulation time 20569400 ps
CPU time 0.69 seconds
Started Aug 15 04:32:21 PM PDT 24
Finished Aug 15 04:32:22 PM PDT 24
Peak memory 205364 kb
Host smart-daf34fd8-966b-4ac7-90b5-400943e28744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355114108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1355114108
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.939245607
Short name T495
Test name
Test status
Simulation time 138448206 ps
CPU time 2.81 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:21 PM PDT 24
Peak memory 224440 kb
Host smart-73a94b8b-a521-42f4-a5d3-99436b39a15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939245607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.939245607
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4075304980
Short name T826
Test name
Test status
Simulation time 200201303 ps
CPU time 0.75 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:20 PM PDT 24
Peak memory 206836 kb
Host smart-57bd7b31-d9a2-4da5-bd19-8a20933ab5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075304980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4075304980
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.328207073
Short name T63
Test name
Test status
Simulation time 22382672 ps
CPU time 0.78 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:19 PM PDT 24
Peak memory 215676 kb
Host smart-001c8431-196a-4dfb-86b5-fc8e79ca6a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328207073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.328207073
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3531567987
Short name T380
Test name
Test status
Simulation time 66825776962 ps
CPU time 188.01 seconds
Started Aug 15 04:32:21 PM PDT 24
Finished Aug 15 04:35:29 PM PDT 24
Peak memory 257228 kb
Host smart-20940191-5618-4ccb-9678-94a2310b9a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531567987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3531567987
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2154247451
Short name T607
Test name
Test status
Simulation time 357505477 ps
CPU time 6.4 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:24 PM PDT 24
Peak memory 232672 kb
Host smart-494a8908-8b9e-44c4-aae7-015405991349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154247451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2154247451
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3358819534
Short name T450
Test name
Test status
Simulation time 7140873903 ps
CPU time 58.77 seconds
Started Aug 15 04:32:22 PM PDT 24
Finished Aug 15 04:33:20 PM PDT 24
Peak memory 253772 kb
Host smart-c1252c16-ed41-4a52-a89b-6ddf555cd068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358819534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3358819534
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3242315569
Short name T231
Test name
Test status
Simulation time 799148072 ps
CPU time 6.46 seconds
Started Aug 15 04:32:20 PM PDT 24
Finished Aug 15 04:32:27 PM PDT 24
Peak memory 224532 kb
Host smart-19531c43-9ee8-40be-8db3-6e697cfaebb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242315569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3242315569
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2311722910
Short name T766
Test name
Test status
Simulation time 62669074352 ps
CPU time 118.46 seconds
Started Aug 15 04:32:20 PM PDT 24
Finished Aug 15 04:34:19 PM PDT 24
Peak memory 232680 kb
Host smart-09c3f8d5-b6d1-48c2-97e1-f23b051a3522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311722910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2311722910
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1799720160
Short name T662
Test name
Test status
Simulation time 16702165 ps
CPU time 1.03 seconds
Started Aug 15 04:32:22 PM PDT 24
Finished Aug 15 04:32:23 PM PDT 24
Peak memory 217824 kb
Host smart-638cc38d-2c69-4924-868b-5d75db604168
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799720160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1799720160
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3592847778
Short name T196
Test name
Test status
Simulation time 782437906 ps
CPU time 3.59 seconds
Started Aug 15 04:32:21 PM PDT 24
Finished Aug 15 04:32:30 PM PDT 24
Peak memory 224456 kb
Host smart-7b2ea299-242a-49a7-b94c-b9e456697c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592847778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3592847778
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3547458311
Short name T873
Test name
Test status
Simulation time 1430591593 ps
CPU time 3.3 seconds
Started Aug 15 04:32:21 PM PDT 24
Finished Aug 15 04:32:24 PM PDT 24
Peak memory 224500 kb
Host smart-00c14617-b018-4e7a-bd8c-e8a60e9f317a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547458311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3547458311
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2985149159
Short name T149
Test name
Test status
Simulation time 582034277 ps
CPU time 7.16 seconds
Started Aug 15 04:32:16 PM PDT 24
Finished Aug 15 04:32:23 PM PDT 24
Peak memory 222208 kb
Host smart-7f1a0ef7-4e9d-4004-840f-bbd3bb6dfe45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2985149159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2985149159
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2153615010
Short name T626
Test name
Test status
Simulation time 10670826371 ps
CPU time 15.82 seconds
Started Aug 15 04:32:16 PM PDT 24
Finished Aug 15 04:32:32 PM PDT 24
Peak memory 216708 kb
Host smart-5f203270-b7f9-485b-a0ca-af28c015c137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153615010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2153615010
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4248449928
Short name T480
Test name
Test status
Simulation time 12415859535 ps
CPU time 9.06 seconds
Started Aug 15 04:32:17 PM PDT 24
Finished Aug 15 04:32:27 PM PDT 24
Peak memory 217380 kb
Host smart-098489d5-a8ad-4ac9-9ebf-a98e1dcc585e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248449928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4248449928
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.446155577
Short name T716
Test name
Test status
Simulation time 441307575 ps
CPU time 2.37 seconds
Started Aug 15 04:32:20 PM PDT 24
Finished Aug 15 04:32:22 PM PDT 24
Peak memory 216268 kb
Host smart-29297da5-4843-4f3d-b24e-dd54694e29ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446155577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.446155577
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.917528004
Short name T426
Test name
Test status
Simulation time 99279302 ps
CPU time 1.04 seconds
Started Aug 15 04:32:17 PM PDT 24
Finished Aug 15 04:32:18 PM PDT 24
Peak memory 207004 kb
Host smart-712432b8-f230-423d-b3a7-d0667627ca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917528004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.917528004
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.764540606
Short name T785
Test name
Test status
Simulation time 3194937563 ps
CPU time 4.49 seconds
Started Aug 15 04:32:20 PM PDT 24
Finished Aug 15 04:32:25 PM PDT 24
Peak memory 224560 kb
Host smart-29203c3c-55f9-4ca4-b1ec-68601615fd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764540606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.764540606
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.122198361
Short name T368
Test name
Test status
Simulation time 12988895 ps
CPU time 0.74 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:19 PM PDT 24
Peak memory 204808 kb
Host smart-385563f3-ebcb-4393-af2a-7d0e409b4e3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122198361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.122198361
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.138873956
Short name T389
Test name
Test status
Simulation time 257054774 ps
CPU time 4.89 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:24 PM PDT 24
Peak memory 232704 kb
Host smart-135774e0-bfe8-4ddf-a1d3-fa29ab5f38b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138873956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.138873956
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1786982590
Short name T724
Test name
Test status
Simulation time 24589118 ps
CPU time 0.78 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:19 PM PDT 24
Peak memory 206376 kb
Host smart-346e98de-5b9f-4e9e-bb5b-683138c105a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786982590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1786982590
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2903547294
Short name T286
Test name
Test status
Simulation time 9566624362 ps
CPU time 41.94 seconds
Started Aug 15 04:32:21 PM PDT 24
Finished Aug 15 04:33:03 PM PDT 24
Peak memory 254876 kb
Host smart-c939bff9-98db-450e-a674-890b0c499942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903547294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2903547294
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.969147798
Short name T985
Test name
Test status
Simulation time 128646965048 ps
CPU time 160.67 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:34:58 PM PDT 24
Peak memory 251544 kb
Host smart-66b08a38-e2b4-433f-94a1-4a038bf405ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969147798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.969147798
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1234064812
Short name T924
Test name
Test status
Simulation time 13382157081 ps
CPU time 70.44 seconds
Started Aug 15 04:32:17 PM PDT 24
Finished Aug 15 04:33:27 PM PDT 24
Peak memory 239668 kb
Host smart-a5a04625-94a5-4f7d-a08c-d3886b29ba3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234064812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1234064812
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.415045407
Short name T435
Test name
Test status
Simulation time 45808466 ps
CPU time 2.96 seconds
Started Aug 15 04:32:15 PM PDT 24
Finished Aug 15 04:32:18 PM PDT 24
Peak memory 232628 kb
Host smart-cc5bd243-24d5-473f-831b-1b6b893fde4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415045407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.415045407
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1932413732
Short name T228
Test name
Test status
Simulation time 12578658085 ps
CPU time 42.01 seconds
Started Aug 15 04:32:17 PM PDT 24
Finished Aug 15 04:32:59 PM PDT 24
Peak memory 235552 kb
Host smart-8a7fb601-71ba-48cb-a9de-1b4bf5a81641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932413732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1932413732
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1954770065
Short name T748
Test name
Test status
Simulation time 750764134 ps
CPU time 10.3 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:30 PM PDT 24
Peak memory 224432 kb
Host smart-34f7a49a-c911-4300-b133-4239acd65e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954770065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1954770065
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3912462021
Short name T882
Test name
Test status
Simulation time 24649966169 ps
CPU time 79.05 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:33:37 PM PDT 24
Peak memory 224508 kb
Host smart-e7f67cf7-93ba-4b0f-801b-33ff7d47f614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912462021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3912462021
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.606754915
Short name T470
Test name
Test status
Simulation time 15521530 ps
CPU time 1.03 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:20 PM PDT 24
Peak memory 217840 kb
Host smart-0675db72-d42b-4303-a69d-0576673edba7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606754915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.606754915
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3850297413
Short name T958
Test name
Test status
Simulation time 15062657556 ps
CPU time 16.95 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:36 PM PDT 24
Peak memory 232744 kb
Host smart-e223c589-6dee-4202-a353-781bab429cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850297413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3850297413
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.706961605
Short name T216
Test name
Test status
Simulation time 867111827 ps
CPU time 4.53 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:23 PM PDT 24
Peak memory 237504 kb
Host smart-6d30b2f0-225d-4041-aad1-a924ac8d3200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706961605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.706961605
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.866655777
Short name T497
Test name
Test status
Simulation time 3604619357 ps
CPU time 7.56 seconds
Started Aug 15 04:32:16 PM PDT 24
Finished Aug 15 04:32:24 PM PDT 24
Peak memory 222536 kb
Host smart-30d47a83-4d50-48af-b557-e82e28b4b61a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=866655777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.866655777
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.797289263
Short name T1009
Test name
Test status
Simulation time 82742569053 ps
CPU time 261.79 seconds
Started Aug 15 04:32:22 PM PDT 24
Finished Aug 15 04:36:44 PM PDT 24
Peak memory 272676 kb
Host smart-339e2aaa-e7c0-41f1-9f99-7255df3b6d5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797289263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.797289263
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2662853706
Short name T900
Test name
Test status
Simulation time 6623120643 ps
CPU time 35.05 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:53 PM PDT 24
Peak memory 216412 kb
Host smart-3b7ec8b8-4b9c-42f8-bc16-7bc2836706dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662853706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2662853706
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3751571176
Short name T160
Test name
Test status
Simulation time 20189188651 ps
CPU time 14.01 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:33 PM PDT 24
Peak memory 216320 kb
Host smart-58e02d3a-6e87-4e48-ba90-16bbed41cccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751571176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3751571176
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3483818620
Short name T446
Test name
Test status
Simulation time 58023230 ps
CPU time 0.73 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:19 PM PDT 24
Peak memory 205904 kb
Host smart-b169d5d9-edef-4bea-9973-da0ec466b032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483818620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3483818620
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2341651699
Short name T655
Test name
Test status
Simulation time 68168129 ps
CPU time 0.73 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:19 PM PDT 24
Peak memory 205944 kb
Host smart-2e098b0a-3a0c-49d9-adef-4069f5e916e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341651699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2341651699
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4006548799
Short name T522
Test name
Test status
Simulation time 10450444577 ps
CPU time 11.07 seconds
Started Aug 15 04:32:21 PM PDT 24
Finished Aug 15 04:32:32 PM PDT 24
Peak memory 224600 kb
Host smart-5d1092e5-7454-4686-b2f5-feec23d39d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006548799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4006548799
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.261232576
Short name T329
Test name
Test status
Simulation time 40810505 ps
CPU time 0.69 seconds
Started Aug 15 04:32:27 PM PDT 24
Finished Aug 15 04:32:28 PM PDT 24
Peak memory 204772 kb
Host smart-9b23c548-4580-4562-b334-8e06fe134434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261232576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.261232576
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2756063208
Short name T837
Test name
Test status
Simulation time 7494596703 ps
CPU time 10.8 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:28 PM PDT 24
Peak memory 232768 kb
Host smart-eea779cf-5a60-4d7a-8cc8-9232cbeaf15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756063208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2756063208
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.407578228
Short name T375
Test name
Test status
Simulation time 119717400 ps
CPU time 0.76 seconds
Started Aug 15 04:32:17 PM PDT 24
Finished Aug 15 04:32:18 PM PDT 24
Peak memory 205404 kb
Host smart-c8aca7aa-44ea-4aa1-99d9-637ba880a04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407578228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.407578228
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3452257837
Short name T1015
Test name
Test status
Simulation time 58130048568 ps
CPU time 203.34 seconds
Started Aug 15 04:32:21 PM PDT 24
Finished Aug 15 04:35:45 PM PDT 24
Peak memory 238404 kb
Host smart-7fc4543b-6a4b-4bb7-96fa-dbb208a4b2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452257837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3452257837
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2790937261
Short name T378
Test name
Test status
Simulation time 32374978056 ps
CPU time 184.51 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:35:23 PM PDT 24
Peak memory 257116 kb
Host smart-21850811-9a35-410c-8572-0ee3638e7715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790937261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2790937261
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2148573740
Short name T140
Test name
Test status
Simulation time 73499849251 ps
CPU time 365.51 seconds
Started Aug 15 04:32:22 PM PDT 24
Finished Aug 15 04:38:28 PM PDT 24
Peak memory 251212 kb
Host smart-874bf4ba-0215-4070-89bc-c2388a0d728d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148573740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2148573740
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3323681746
Short name T292
Test name
Test status
Simulation time 1250677520 ps
CPU time 20.48 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:40 PM PDT 24
Peak memory 233900 kb
Host smart-576b9df6-d04a-4010-a018-db6b08c05c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323681746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3323681746
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2696408695
Short name T751
Test name
Test status
Simulation time 1836883466 ps
CPU time 11.79 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:30 PM PDT 24
Peak memory 224524 kb
Host smart-f1e54756-3585-42f4-b4a4-f2f0a01da3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696408695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2696408695
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3879343584
Short name T685
Test name
Test status
Simulation time 289932148 ps
CPU time 2.06 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:21 PM PDT 24
Peak memory 222900 kb
Host smart-6244119a-e18a-4301-96eb-fd6b92327245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879343584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3879343584
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1296094001
Short name T423
Test name
Test status
Simulation time 43977087 ps
CPU time 1.07 seconds
Started Aug 15 04:32:21 PM PDT 24
Finished Aug 15 04:32:22 PM PDT 24
Peak memory 217840 kb
Host smart-8a7618b3-da3e-49be-b8c6-ec7a2b359ce8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296094001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1296094001
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4145352500
Short name T386
Test name
Test status
Simulation time 336504295 ps
CPU time 3.86 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:23 PM PDT 24
Peak memory 224480 kb
Host smart-88b3684e-54db-43dd-9c26-95c4336c289b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145352500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4145352500
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1678578961
Short name T730
Test name
Test status
Simulation time 2402135648 ps
CPU time 16.08 seconds
Started Aug 15 04:32:20 PM PDT 24
Finished Aug 15 04:32:36 PM PDT 24
Peak memory 232760 kb
Host smart-4d211680-7688-4a77-80c5-21b0871a06f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678578961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1678578961
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4268923675
Short name T148
Test name
Test status
Simulation time 1559641149 ps
CPU time 21.42 seconds
Started Aug 15 04:32:17 PM PDT 24
Finished Aug 15 04:32:38 PM PDT 24
Peak memory 223124 kb
Host smart-195b7fe0-9a53-49c3-813c-786bc1a9e8a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4268923675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4268923675
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.716223159
Short name T675
Test name
Test status
Simulation time 15365806833 ps
CPU time 170.89 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:35:11 PM PDT 24
Peak memory 282308 kb
Host smart-3105b423-aa41-4217-bdc5-fa186c5678c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716223159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.716223159
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3731978859
Short name T652
Test name
Test status
Simulation time 442825479 ps
CPU time 1.6 seconds
Started Aug 15 04:32:17 PM PDT 24
Finished Aug 15 04:32:19 PM PDT 24
Peak memory 207892 kb
Host smart-d911ebc1-ef7a-45b0-a0b2-988360fc7f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731978859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3731978859
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.452759126
Short name T930
Test name
Test status
Simulation time 103731121 ps
CPU time 1.38 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:20 PM PDT 24
Peak memory 216396 kb
Host smart-8e442b59-2843-491e-8c29-a79cb85841e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452759126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.452759126
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3971944794
Short name T834
Test name
Test status
Simulation time 302903002 ps
CPU time 0.99 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:21 PM PDT 24
Peak memory 206952 kb
Host smart-4ce1ef83-e3c9-4ec7-ab4d-f5b0a3c363e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971944794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3971944794
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1295879422
Short name T828
Test name
Test status
Simulation time 2502943808 ps
CPU time 7.06 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:26 PM PDT 24
Peak memory 232760 kb
Host smart-607431b4-4050-49e5-9c40-b0a61f35477f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295879422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1295879422
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.120000592
Short name T696
Test name
Test status
Simulation time 87976995 ps
CPU time 0.73 seconds
Started Aug 15 04:32:30 PM PDT 24
Finished Aug 15 04:32:31 PM PDT 24
Peak memory 205700 kb
Host smart-ff7794db-803b-4658-a676-76f81a00be5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120000592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.120000592
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.328540536
Short name T591
Test name
Test status
Simulation time 379982220 ps
CPU time 4.39 seconds
Started Aug 15 04:32:39 PM PDT 24
Finished Aug 15 04:32:43 PM PDT 24
Peak memory 232668 kb
Host smart-a6367c5a-d62f-487d-8eb6-d711ec12f9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328540536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.328540536
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.805860482
Short name T66
Test name
Test status
Simulation time 108350915 ps
CPU time 0.81 seconds
Started Aug 15 04:32:39 PM PDT 24
Finished Aug 15 04:32:40 PM PDT 24
Peak memory 206484 kb
Host smart-5bceb5cc-4c46-4208-a7f9-c909a6a49222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805860482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.805860482
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.221475501
Short name T1023
Test name
Test status
Simulation time 132930682 ps
CPU time 0.99 seconds
Started Aug 15 04:32:27 PM PDT 24
Finished Aug 15 04:32:28 PM PDT 24
Peak memory 215852 kb
Host smart-41f5709c-782d-4733-9a09-19b3e1a32080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221475501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.221475501
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2485827944
Short name T732
Test name
Test status
Simulation time 555142891 ps
CPU time 7.41 seconds
Started Aug 15 04:32:24 PM PDT 24
Finished Aug 15 04:32:32 PM PDT 24
Peak memory 219328 kb
Host smart-fd37cb5e-ad98-4d0a-90e2-ddd11ad4fc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485827944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2485827944
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2748028137
Short name T949
Test name
Test status
Simulation time 1677750101 ps
CPU time 8.97 seconds
Started Aug 15 04:32:42 PM PDT 24
Finished Aug 15 04:32:52 PM PDT 24
Peak memory 240968 kb
Host smart-e19e3c47-75cd-4d59-9233-b91a4455b064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748028137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2748028137
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3876793489
Short name T653
Test name
Test status
Simulation time 43536022085 ps
CPU time 183.6 seconds
Started Aug 15 04:32:32 PM PDT 24
Finished Aug 15 04:35:36 PM PDT 24
Peak memory 256908 kb
Host smart-3976704f-2e14-4cfe-87e0-a6398f58b1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876793489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3876793489
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1369378817
Short name T725
Test name
Test status
Simulation time 375249020 ps
CPU time 2.84 seconds
Started Aug 15 04:32:38 PM PDT 24
Finished Aug 15 04:32:41 PM PDT 24
Peak memory 232656 kb
Host smart-f51c35e1-54f4-4613-ad92-21346e910531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369378817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1369378817
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.80108877
Short name T192
Test name
Test status
Simulation time 31587108488 ps
CPU time 36.1 seconds
Started Aug 15 04:32:27 PM PDT 24
Finished Aug 15 04:33:03 PM PDT 24
Peak memory 224496 kb
Host smart-db330821-99d8-40c8-86e5-0097c678646b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80108877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.80108877
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2590508614
Short name T577
Test name
Test status
Simulation time 16544016 ps
CPU time 0.96 seconds
Started Aug 15 04:32:28 PM PDT 24
Finished Aug 15 04:32:29 PM PDT 24
Peak memory 217784 kb
Host smart-d637509e-0a79-468a-a0b7-269d789bb473
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590508614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2590508614
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.884589555
Short name T400
Test name
Test status
Simulation time 401055455 ps
CPU time 3.07 seconds
Started Aug 15 04:32:31 PM PDT 24
Finished Aug 15 04:32:35 PM PDT 24
Peak memory 224464 kb
Host smart-593f48d7-4675-4df3-b340-44dca5b9d5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884589555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.884589555
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1304301948
Short name T257
Test name
Test status
Simulation time 571302784 ps
CPU time 5.08 seconds
Started Aug 15 04:32:32 PM PDT 24
Finished Aug 15 04:32:37 PM PDT 24
Peak memory 232688 kb
Host smart-80b1bb06-3b23-4431-80b9-7ea76a9fb6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304301948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1304301948
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2040413286
Short name T557
Test name
Test status
Simulation time 510433375 ps
CPU time 5.14 seconds
Started Aug 15 04:32:26 PM PDT 24
Finished Aug 15 04:32:31 PM PDT 24
Peak memory 219236 kb
Host smart-cfa92f1f-20b3-4bd9-9517-4de8a4a2a5d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2040413286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2040413286
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1649105698
Short name T933
Test name
Test status
Simulation time 56989463 ps
CPU time 1.05 seconds
Started Aug 15 04:32:42 PM PDT 24
Finished Aug 15 04:32:44 PM PDT 24
Peak memory 215092 kb
Host smart-b6f9fec2-a62e-4e8d-b9a9-7ee0d90df241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649105698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1649105698
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4154303791
Short name T558
Test name
Test status
Simulation time 8683665673 ps
CPU time 23.98 seconds
Started Aug 15 04:32:33 PM PDT 24
Finished Aug 15 04:32:57 PM PDT 24
Peak memory 216408 kb
Host smart-c973b63a-4f56-41e8-880f-24b945ad4e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154303791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4154303791
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1194910793
Short name T932
Test name
Test status
Simulation time 11836675770 ps
CPU time 5.75 seconds
Started Aug 15 04:32:43 PM PDT 24
Finished Aug 15 04:32:49 PM PDT 24
Peak memory 216408 kb
Host smart-26409380-e8c3-41aa-8dee-77575ca147a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194910793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1194910793
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2506675206
Short name T396
Test name
Test status
Simulation time 64613524 ps
CPU time 0.78 seconds
Started Aug 15 04:32:32 PM PDT 24
Finished Aug 15 04:32:33 PM PDT 24
Peak memory 205900 kb
Host smart-82f128ed-10e8-42fd-a5f1-8e810abde3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506675206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2506675206
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.4070817294
Short name T707
Test name
Test status
Simulation time 12277597 ps
CPU time 0.74 seconds
Started Aug 15 04:32:43 PM PDT 24
Finished Aug 15 04:32:44 PM PDT 24
Peak memory 205416 kb
Host smart-b1638eb3-0c2c-44a6-a63c-177c227bae5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070817294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4070817294
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3908597126
Short name T464
Test name
Test status
Simulation time 11652987931 ps
CPU time 14.38 seconds
Started Aug 15 04:32:31 PM PDT 24
Finished Aug 15 04:32:46 PM PDT 24
Peak memory 237048 kb
Host smart-bbb23455-ffaa-4dd6-aeb6-cfa5fe088540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908597126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3908597126
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.777528529
Short name T631
Test name
Test status
Simulation time 12156202 ps
CPU time 0.74 seconds
Started Aug 15 04:32:32 PM PDT 24
Finished Aug 15 04:32:33 PM PDT 24
Peak memory 205352 kb
Host smart-fd3e37f0-9f05-49fb-bdf8-2a275219421e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777528529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.777528529
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.110436506
Short name T175
Test name
Test status
Simulation time 124941923 ps
CPU time 2.18 seconds
Started Aug 15 04:32:36 PM PDT 24
Finished Aug 15 04:32:39 PM PDT 24
Peak memory 224452 kb
Host smart-9e252ec7-fa73-45ca-acfd-f94616bcd8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110436506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.110436506
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3141922555
Short name T1003
Test name
Test status
Simulation time 17869824 ps
CPU time 0.79 seconds
Started Aug 15 04:32:26 PM PDT 24
Finished Aug 15 04:32:27 PM PDT 24
Peak memory 205724 kb
Host smart-e2597c89-7045-4f73-b9da-a03a89999ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141922555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3141922555
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3166617628
Short name T223
Test name
Test status
Simulation time 30495161351 ps
CPU time 107.37 seconds
Started Aug 15 04:32:26 PM PDT 24
Finished Aug 15 04:34:14 PM PDT 24
Peak memory 266632 kb
Host smart-aef4ec1d-d8da-465e-adae-3eaacd9a7fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166617628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3166617628
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2754898559
Short name T674
Test name
Test status
Simulation time 27896339184 ps
CPU time 60.43 seconds
Started Aug 15 04:32:32 PM PDT 24
Finished Aug 15 04:33:32 PM PDT 24
Peak memory 235832 kb
Host smart-96e89c9c-7008-4b94-adf1-03e6cc8e25d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754898559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2754898559
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2111086973
Short name T280
Test name
Test status
Simulation time 24320609939 ps
CPU time 68.05 seconds
Started Aug 15 04:32:29 PM PDT 24
Finished Aug 15 04:33:37 PM PDT 24
Peak memory 250780 kb
Host smart-4a145ff4-d5aa-42c7-9233-cbec74e18de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111086973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2111086973
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.838605512
Short name T489
Test name
Test status
Simulation time 2125798934 ps
CPU time 14.25 seconds
Started Aug 15 04:32:32 PM PDT 24
Finished Aug 15 04:32:46 PM PDT 24
Peak memory 232720 kb
Host smart-b0e8207c-6e14-428f-8f99-049e4b497545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838605512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.838605512
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1465699871
Short name T584
Test name
Test status
Simulation time 1909729165 ps
CPU time 5.81 seconds
Started Aug 15 04:32:37 PM PDT 24
Finished Aug 15 04:32:43 PM PDT 24
Peak memory 224468 kb
Host smart-5d342c97-f5b0-40ca-b5ca-74b6158eebf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465699871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1465699871
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3797372506
Short name T912
Test name
Test status
Simulation time 23543789014 ps
CPU time 27.33 seconds
Started Aug 15 04:32:28 PM PDT 24
Finished Aug 15 04:32:55 PM PDT 24
Peak memory 232760 kb
Host smart-5995446d-d0e5-4d8c-a7c1-5e3d0f87836b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797372506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3797372506
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.360525424
Short name T726
Test name
Test status
Simulation time 24969388 ps
CPU time 1.09 seconds
Started Aug 15 04:32:34 PM PDT 24
Finished Aug 15 04:32:35 PM PDT 24
Peak memory 216564 kb
Host smart-5016c49c-3859-4899-afe7-92e5a175f927
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360525424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.360525424
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.615718932
Short name T250
Test name
Test status
Simulation time 752036503 ps
CPU time 4.25 seconds
Started Aug 15 04:32:32 PM PDT 24
Finished Aug 15 04:32:36 PM PDT 24
Peak memory 232620 kb
Host smart-d79d1375-ff0e-4e00-8ab1-64ad7fff4baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615718932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.615718932
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1708411027
Short name T238
Test name
Test status
Simulation time 150713333 ps
CPU time 2.65 seconds
Started Aug 15 04:32:32 PM PDT 24
Finished Aug 15 04:32:35 PM PDT 24
Peak memory 232652 kb
Host smart-2a9918cf-0851-4087-a99b-ae8536abf841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708411027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1708411027
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.477948689
Short name T835
Test name
Test status
Simulation time 6551990176 ps
CPU time 19.97 seconds
Started Aug 15 04:32:32 PM PDT 24
Finished Aug 15 04:32:52 PM PDT 24
Peak memory 220440 kb
Host smart-b1465a52-d293-4bfc-a92b-e8ab0fcc5c32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=477948689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.477948689
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3476463597
Short name T733
Test name
Test status
Simulation time 13216254604 ps
CPU time 66.98 seconds
Started Aug 15 04:32:27 PM PDT 24
Finished Aug 15 04:33:34 PM PDT 24
Peak memory 256208 kb
Host smart-d8ab2d0d-2da3-4c18-9e5a-5fd321938034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476463597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3476463597
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2490532539
Short name T904
Test name
Test status
Simulation time 76637280 ps
CPU time 0.71 seconds
Started Aug 15 04:32:48 PM PDT 24
Finished Aug 15 04:32:49 PM PDT 24
Peak memory 205568 kb
Host smart-04b6f22b-54ed-4883-81e9-67a0bc793b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490532539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2490532539
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3560008853
Short name T605
Test name
Test status
Simulation time 8371905896 ps
CPU time 19.56 seconds
Started Aug 15 04:32:27 PM PDT 24
Finished Aug 15 04:32:47 PM PDT 24
Peak memory 216400 kb
Host smart-bad47f1c-d264-496b-be5c-678845cafade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560008853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3560008853
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3365407291
Short name T422
Test name
Test status
Simulation time 366022335 ps
CPU time 1.74 seconds
Started Aug 15 04:32:42 PM PDT 24
Finished Aug 15 04:32:44 PM PDT 24
Peak memory 216320 kb
Host smart-b5228b45-66db-49e3-b121-e95f2f7de741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365407291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3365407291
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.612995267
Short name T361
Test name
Test status
Simulation time 32116725 ps
CPU time 0.73 seconds
Started Aug 15 04:32:27 PM PDT 24
Finished Aug 15 04:32:28 PM PDT 24
Peak memory 205936 kb
Host smart-809da065-0f22-43c8-af31-d786952940fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612995267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.612995267
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2051353928
Short name T706
Test name
Test status
Simulation time 13119217936 ps
CPU time 17.61 seconds
Started Aug 15 04:32:39 PM PDT 24
Finished Aug 15 04:32:57 PM PDT 24
Peak memory 224496 kb
Host smart-177c6add-e8cd-4eed-8c91-b6df913baac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051353928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2051353928
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3389760476
Short name T545
Test name
Test status
Simulation time 11853402 ps
CPU time 0.71 seconds
Started Aug 15 04:32:45 PM PDT 24
Finished Aug 15 04:32:46 PM PDT 24
Peak memory 204804 kb
Host smart-313a90a8-f8c8-4a68-9d92-293327dd93d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389760476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3389760476
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1177532863
Short name T258
Test name
Test status
Simulation time 177442029 ps
CPU time 2.48 seconds
Started Aug 15 04:32:33 PM PDT 24
Finished Aug 15 04:32:36 PM PDT 24
Peak memory 224464 kb
Host smart-aa90d323-c00b-4bed-98ea-1a5a41d27afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177532863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1177532863
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1507770190
Short name T880
Test name
Test status
Simulation time 39907091 ps
CPU time 0.79 seconds
Started Aug 15 04:32:42 PM PDT 24
Finished Aug 15 04:32:43 PM PDT 24
Peak memory 206492 kb
Host smart-bf4eb169-e737-43d5-a1d9-526acadbaf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507770190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1507770190
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1306794162
Short name T923
Test name
Test status
Simulation time 24491111967 ps
CPU time 111.83 seconds
Started Aug 15 04:32:36 PM PDT 24
Finished Aug 15 04:34:28 PM PDT 24
Peak memory 267200 kb
Host smart-220e18ed-1d04-49ed-8446-84e2d79246eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306794162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1306794162
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3814692209
Short name T139
Test name
Test status
Simulation time 66136831216 ps
CPU time 673.94 seconds
Started Aug 15 04:32:34 PM PDT 24
Finished Aug 15 04:43:48 PM PDT 24
Peak memory 264156 kb
Host smart-a89707c5-a260-40d5-8af7-34e1885edd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814692209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3814692209
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3860042232
Short name T1010
Test name
Test status
Simulation time 16215305566 ps
CPU time 207.01 seconds
Started Aug 15 04:32:44 PM PDT 24
Finished Aug 15 04:36:11 PM PDT 24
Peak memory 257720 kb
Host smart-dcbfad60-7adb-49d1-b498-72b9bd3ede3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860042232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3860042232
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3177057969
Short name T855
Test name
Test status
Simulation time 9328898841 ps
CPU time 12.82 seconds
Started Aug 15 04:32:49 PM PDT 24
Finished Aug 15 04:33:02 PM PDT 24
Peak memory 238832 kb
Host smart-4ebe7f6d-29f2-4bc6-b664-f860be964028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177057969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3177057969
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3124876716
Short name T473
Test name
Test status
Simulation time 3950227182 ps
CPU time 26.87 seconds
Started Aug 15 04:32:34 PM PDT 24
Finished Aug 15 04:33:00 PM PDT 24
Peak memory 234652 kb
Host smart-67720bd6-aa89-4249-aa7c-dd247299ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124876716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3124876716
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1043575361
Short name T50
Test name
Test status
Simulation time 598556950 ps
CPU time 8.77 seconds
Started Aug 15 04:32:27 PM PDT 24
Finished Aug 15 04:32:36 PM PDT 24
Peak memory 229492 kb
Host smart-65d042b1-4bc1-4f94-b79e-6b7206b550ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043575361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1043575361
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4066726499
Short name T891
Test name
Test status
Simulation time 28640501394 ps
CPU time 35.78 seconds
Started Aug 15 04:32:35 PM PDT 24
Finished Aug 15 04:33:11 PM PDT 24
Peak memory 232688 kb
Host smart-ff29c7be-6777-4bca-a831-a6701908b60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066726499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4066726499
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2334664103
Short name T959
Test name
Test status
Simulation time 15443577 ps
CPU time 1.07 seconds
Started Aug 15 04:32:39 PM PDT 24
Finished Aug 15 04:32:40 PM PDT 24
Peak memory 216624 kb
Host smart-96d35fff-6e65-45d5-b56e-2211aa2d942f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334664103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2334664103
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1658193293
Short name T889
Test name
Test status
Simulation time 322329633 ps
CPU time 5.82 seconds
Started Aug 15 04:32:32 PM PDT 24
Finished Aug 15 04:32:38 PM PDT 24
Peak memory 231620 kb
Host smart-73d0defa-b00b-4440-a521-f7268ffe54f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658193293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1658193293
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2981908790
Short name T210
Test name
Test status
Simulation time 5403096100 ps
CPU time 14.57 seconds
Started Aug 15 04:32:46 PM PDT 24
Finished Aug 15 04:33:01 PM PDT 24
Peak memory 224512 kb
Host smart-30a4081b-ab12-498f-8289-b51dd0e8b602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981908790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2981908790
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3573655743
Short name T465
Test name
Test status
Simulation time 1588675347 ps
CPU time 7.17 seconds
Started Aug 15 04:32:35 PM PDT 24
Finished Aug 15 04:32:42 PM PDT 24
Peak memory 218680 kb
Host smart-b05e694c-fc84-4020-b368-2fd14bb64a17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3573655743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3573655743
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3698853472
Short name T440
Test name
Test status
Simulation time 474397570 ps
CPU time 4.71 seconds
Started Aug 15 04:32:41 PM PDT 24
Finished Aug 15 04:32:46 PM PDT 24
Peak memory 216236 kb
Host smart-b038398c-e163-4b9b-b119-5f3e27dff6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698853472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3698853472
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.957524220
Short name T951
Test name
Test status
Simulation time 2248947446 ps
CPU time 8.3 seconds
Started Aug 15 04:32:38 PM PDT 24
Finished Aug 15 04:32:46 PM PDT 24
Peak memory 216348 kb
Host smart-5146dc83-32d3-4a1d-8893-dd18ff2f5e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957524220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.957524220
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3744021577
Short name T501
Test name
Test status
Simulation time 107241198 ps
CPU time 0.89 seconds
Started Aug 15 04:32:27 PM PDT 24
Finished Aug 15 04:32:28 PM PDT 24
Peak memory 206432 kb
Host smart-e5e50c77-08c5-4133-97c9-03551cfd6658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744021577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3744021577
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1405860084
Short name T379
Test name
Test status
Simulation time 626887458 ps
CPU time 0.99 seconds
Started Aug 15 04:32:27 PM PDT 24
Finished Aug 15 04:32:28 PM PDT 24
Peak memory 205908 kb
Host smart-f317f3dc-485c-42c4-b1eb-38969b062de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405860084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1405860084
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2249513311
Short name T5
Test name
Test status
Simulation time 328677991 ps
CPU time 2.14 seconds
Started Aug 15 04:32:27 PM PDT 24
Finished Aug 15 04:32:30 PM PDT 24
Peak memory 223956 kb
Host smart-62be8cfe-ce0e-477c-9d50-3a55ff06e844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249513311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2249513311
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.560806819
Short name T350
Test name
Test status
Simulation time 15384318 ps
CPU time 0.73 seconds
Started Aug 15 04:32:48 PM PDT 24
Finished Aug 15 04:32:49 PM PDT 24
Peak memory 204864 kb
Host smart-6dca9009-7af7-45be-b359-1867b7a9be70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560806819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.560806819
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1638094789
Short name T88
Test name
Test status
Simulation time 1111696992 ps
CPU time 3.81 seconds
Started Aug 15 04:32:42 PM PDT 24
Finished Aug 15 04:32:46 PM PDT 24
Peak memory 224452 kb
Host smart-9ef0eba6-fac6-42a3-bf9e-802d25ef7b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638094789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1638094789
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1899579887
Short name T618
Test name
Test status
Simulation time 27775637 ps
CPU time 0.75 seconds
Started Aug 15 04:32:39 PM PDT 24
Finished Aug 15 04:32:40 PM PDT 24
Peak memory 205808 kb
Host smart-a9a81e75-5ada-415b-9196-d2004c9d2f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899579887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1899579887
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.209167665
Short name T892
Test name
Test status
Simulation time 2037566251 ps
CPU time 6.45 seconds
Started Aug 15 04:32:36 PM PDT 24
Finished Aug 15 04:32:43 PM PDT 24
Peak memory 217352 kb
Host smart-6445f7c0-7a4c-410c-b979-21a622fa266a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209167665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.209167665
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4155066167
Short name T227
Test name
Test status
Simulation time 25443726151 ps
CPU time 218.93 seconds
Started Aug 15 04:32:41 PM PDT 24
Finished Aug 15 04:36:20 PM PDT 24
Peak memory 249268 kb
Host smart-43668561-834c-4775-bc02-2abf3909243e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155066167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4155066167
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2968474871
Short name T296
Test name
Test status
Simulation time 252951180 ps
CPU time 11.17 seconds
Started Aug 15 04:32:36 PM PDT 24
Finished Aug 15 04:32:47 PM PDT 24
Peak memory 232748 kb
Host smart-011e9481-86d8-4be6-a077-7aeb21d963ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968474871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2968474871
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1512840531
Short name T768
Test name
Test status
Simulation time 39822553 ps
CPU time 0.77 seconds
Started Aug 15 04:32:46 PM PDT 24
Finished Aug 15 04:32:46 PM PDT 24
Peak memory 215664 kb
Host smart-03e3da7d-8651-4c3b-9a8a-5242a30fa518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512840531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1512840531
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.331345274
Short name T818
Test name
Test status
Simulation time 269982947 ps
CPU time 5.16 seconds
Started Aug 15 04:32:34 PM PDT 24
Finished Aug 15 04:32:39 PM PDT 24
Peak memory 224456 kb
Host smart-6c756730-7fc7-4696-92e7-a7035976e731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331345274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.331345274
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.404383544
Short name T11
Test name
Test status
Simulation time 949413259 ps
CPU time 18.62 seconds
Started Aug 15 04:32:41 PM PDT 24
Finished Aug 15 04:33:00 PM PDT 24
Peak memory 232680 kb
Host smart-c9653f68-ec1f-435b-b6a6-644b6a381ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404383544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.404383544
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1737931954
Short name T46
Test name
Test status
Simulation time 102480559 ps
CPU time 1.08 seconds
Started Aug 15 04:32:39 PM PDT 24
Finished Aug 15 04:32:41 PM PDT 24
Peak memory 216528 kb
Host smart-fad3df2f-43ea-4f44-bfd1-652b85b89f9f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737931954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1737931954
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4122490379
Short name T925
Test name
Test status
Simulation time 344057052 ps
CPU time 2.2 seconds
Started Aug 15 04:32:46 PM PDT 24
Finished Aug 15 04:32:48 PM PDT 24
Peak memory 223816 kb
Host smart-8dea0db9-23d1-4662-bba3-2878a56ece5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122490379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4122490379
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.756271701
Short name T135
Test name
Test status
Simulation time 16952029901 ps
CPU time 26.51 seconds
Started Aug 15 04:32:35 PM PDT 24
Finished Aug 15 04:33:02 PM PDT 24
Peak memory 237004 kb
Host smart-86aace41-54f7-4afb-aae5-f67f37125089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756271701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.756271701
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.900797771
Short name T51
Test name
Test status
Simulation time 2907587075 ps
CPU time 12.75 seconds
Started Aug 15 04:32:36 PM PDT 24
Finished Aug 15 04:32:49 PM PDT 24
Peak memory 222548 kb
Host smart-9dceebfc-60d9-47b6-be04-50bd5364f02e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=900797771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.900797771
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2203249284
Short name T44
Test name
Test status
Simulation time 381678067557 ps
CPU time 353.1 seconds
Started Aug 15 04:32:37 PM PDT 24
Finished Aug 15 04:38:30 PM PDT 24
Peak memory 268612 kb
Host smart-39bb9b09-1fc7-4d41-93d8-844ab256b4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203249284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2203249284
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2514479126
Short name T952
Test name
Test status
Simulation time 50033959 ps
CPU time 0.71 seconds
Started Aug 15 04:32:40 PM PDT 24
Finished Aug 15 04:32:41 PM PDT 24
Peak memory 205512 kb
Host smart-209f9616-14b0-4409-9695-0d541caacd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514479126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2514479126
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4144329002
Short name T928
Test name
Test status
Simulation time 280478670 ps
CPU time 2.33 seconds
Started Aug 15 04:32:48 PM PDT 24
Finished Aug 15 04:32:50 PM PDT 24
Peak memory 216388 kb
Host smart-785127d8-6ef3-442a-973f-1cbfada33eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144329002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4144329002
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1599043808
Short name T356
Test name
Test status
Simulation time 43913404 ps
CPU time 1.38 seconds
Started Aug 15 04:32:39 PM PDT 24
Finished Aug 15 04:32:40 PM PDT 24
Peak memory 216328 kb
Host smart-e4014814-c84b-4937-ab94-d3db035f401a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599043808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1599043808
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1425866182
Short name T374
Test name
Test status
Simulation time 224300460 ps
CPU time 0.93 seconds
Started Aug 15 04:32:44 PM PDT 24
Finished Aug 15 04:32:45 PM PDT 24
Peak memory 206008 kb
Host smart-d7e795a1-b5ac-4404-9db6-2f35995be3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425866182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1425866182
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1797356396
Short name T98
Test name
Test status
Simulation time 145948786 ps
CPU time 3.27 seconds
Started Aug 15 04:32:41 PM PDT 24
Finished Aug 15 04:32:45 PM PDT 24
Peak memory 219052 kb
Host smart-6d808d3b-f115-43ef-840c-c384aca5364a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797356396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1797356396
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2598991927
Short name T877
Test name
Test status
Simulation time 21766447 ps
CPU time 0.67 seconds
Started Aug 15 04:32:52 PM PDT 24
Finished Aug 15 04:32:53 PM PDT 24
Peak memory 204772 kb
Host smart-5e753ad6-affa-4f26-bbf7-a07c8fbff373
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598991927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2598991927
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3991980510
Short name T406
Test name
Test status
Simulation time 699061386 ps
CPU time 6.1 seconds
Started Aug 15 04:32:46 PM PDT 24
Finished Aug 15 04:32:53 PM PDT 24
Peak memory 232712 kb
Host smart-3e7fc270-9b9a-491d-b983-a30daf702047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991980510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3991980510
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.65069707
Short name T962
Test name
Test status
Simulation time 23339472 ps
CPU time 0.77 seconds
Started Aug 15 04:32:36 PM PDT 24
Finished Aug 15 04:32:37 PM PDT 24
Peak memory 205396 kb
Host smart-bd909b81-0118-4d84-b362-512c6794b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65069707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.65069707
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.374313419
Short name T230
Test name
Test status
Simulation time 9893534133 ps
CPU time 56.62 seconds
Started Aug 15 04:32:42 PM PDT 24
Finished Aug 15 04:33:39 PM PDT 24
Peak memory 224556 kb
Host smart-1227aaa2-d70f-433b-ba61-eae03bdb27ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374313419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.374313419
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.441199186
Short name T198
Test name
Test status
Simulation time 18438217238 ps
CPU time 112.51 seconds
Started Aug 15 04:32:49 PM PDT 24
Finished Aug 15 04:34:41 PM PDT 24
Peak memory 265620 kb
Host smart-fee3730a-88ca-47bd-a5ec-e180e41897bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441199186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.441199186
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1113389087
Short name T277
Test name
Test status
Simulation time 200429715118 ps
CPU time 468.2 seconds
Started Aug 15 04:32:42 PM PDT 24
Finished Aug 15 04:40:31 PM PDT 24
Peak memory 266280 kb
Host smart-5e21be3b-53fd-41e4-b7c4-ca456e5fbec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113389087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1113389087
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2995696518
Short name T1014
Test name
Test status
Simulation time 20918696647 ps
CPU time 37.94 seconds
Started Aug 15 04:32:45 PM PDT 24
Finished Aug 15 04:33:23 PM PDT 24
Peak memory 240104 kb
Host smart-23c3e2c5-3860-4b27-a1f0-d0cb75d4c8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995696518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2995696518
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.695359098
Short name T632
Test name
Test status
Simulation time 348972342 ps
CPU time 5.55 seconds
Started Aug 15 04:32:45 PM PDT 24
Finished Aug 15 04:32:51 PM PDT 24
Peak memory 224448 kb
Host smart-1808c6ef-a770-499c-a958-ac9eaff51f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695359098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.695359098
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1316327972
Short name T60
Test name
Test status
Simulation time 2506905568 ps
CPU time 16.43 seconds
Started Aug 15 04:32:34 PM PDT 24
Finished Aug 15 04:32:51 PM PDT 24
Peak memory 232736 kb
Host smart-d4127e31-aac6-429e-9c6d-710a43867db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316327972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1316327972
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2098747236
Short name T813
Test name
Test status
Simulation time 30111910 ps
CPU time 0.98 seconds
Started Aug 15 04:32:41 PM PDT 24
Finished Aug 15 04:32:42 PM PDT 24
Peak memory 217792 kb
Host smart-c5108b1c-8b84-4779-a57c-850a1170620f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098747236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2098747236
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.706296280
Short name T897
Test name
Test status
Simulation time 2691534381 ps
CPU time 6.04 seconds
Started Aug 15 04:32:44 PM PDT 24
Finished Aug 15 04:32:50 PM PDT 24
Peak memory 223512 kb
Host smart-4c988d20-298f-4406-8cf7-be352140f1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706296280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.706296280
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1169585369
Short name T514
Test name
Test status
Simulation time 4075167381 ps
CPU time 13.21 seconds
Started Aug 15 04:32:42 PM PDT 24
Finished Aug 15 04:32:56 PM PDT 24
Peak memory 224580 kb
Host smart-786ad65a-19f4-40e2-a1a1-22c542c6a1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169585369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1169585369
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2188078426
Short name T843
Test name
Test status
Simulation time 2323315562 ps
CPU time 12.86 seconds
Started Aug 15 04:32:35 PM PDT 24
Finished Aug 15 04:32:47 PM PDT 24
Peak memory 220000 kb
Host smart-39e0f5a7-209e-42af-9b4c-f1428be66805
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2188078426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2188078426
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1283136848
Short name T780
Test name
Test status
Simulation time 2208936361 ps
CPU time 12.51 seconds
Started Aug 15 04:32:50 PM PDT 24
Finished Aug 15 04:33:03 PM PDT 24
Peak memory 216484 kb
Host smart-6bf1588b-9f4a-4496-9d10-c6d05cfa0b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283136848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1283136848
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2986792894
Short name T574
Test name
Test status
Simulation time 9035851927 ps
CPU time 28.32 seconds
Started Aug 15 04:32:34 PM PDT 24
Finished Aug 15 04:33:02 PM PDT 24
Peak memory 216388 kb
Host smart-334eb7a9-cad8-4ea4-9593-7a0b8e6f593d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986792894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2986792894
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1939464707
Short name T633
Test name
Test status
Simulation time 30649527 ps
CPU time 1.18 seconds
Started Aug 15 04:32:34 PM PDT 24
Finished Aug 15 04:32:36 PM PDT 24
Peak memory 207928 kb
Host smart-52c026a1-2000-4e03-b77a-44bd9edcbe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939464707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1939464707
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.902927161
Short name T418
Test name
Test status
Simulation time 445651799 ps
CPU time 1.03 seconds
Started Aug 15 04:32:44 PM PDT 24
Finished Aug 15 04:32:45 PM PDT 24
Peak memory 207032 kb
Host smart-2e942ef4-a494-4bf5-a839-bed9349674bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902927161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.902927161
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.776620345
Short name T581
Test name
Test status
Simulation time 1353091381 ps
CPU time 4.84 seconds
Started Aug 15 04:32:50 PM PDT 24
Finished Aug 15 04:32:55 PM PDT 24
Peak memory 224516 kb
Host smart-74992638-bdca-412e-baf9-17a49f908a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776620345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.776620345
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1315222191
Short name T9
Test name
Test status
Simulation time 20936319 ps
CPU time 0.73 seconds
Started Aug 15 04:32:46 PM PDT 24
Finished Aug 15 04:32:47 PM PDT 24
Peak memory 205336 kb
Host smart-a5dbf7eb-6f18-4e2a-aeab-fddab2e3d469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315222191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1315222191
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1131502920
Short name T735
Test name
Test status
Simulation time 1086559086 ps
CPU time 5.39 seconds
Started Aug 15 04:32:53 PM PDT 24
Finished Aug 15 04:32:59 PM PDT 24
Peak memory 224512 kb
Host smart-f7f9e875-ec5d-4fe2-97b1-1b4657b45e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131502920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1131502920
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3537282180
Short name T592
Test name
Test status
Simulation time 171410204 ps
CPU time 0.75 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:32:52 PM PDT 24
Peak memory 206452 kb
Host smart-44a35c1a-a7be-4242-a374-1b78fd7f1e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537282180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3537282180
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.604543493
Short name T795
Test name
Test status
Simulation time 27288861096 ps
CPU time 69.56 seconds
Started Aug 15 04:32:43 PM PDT 24
Finished Aug 15 04:33:53 PM PDT 24
Peak memory 249112 kb
Host smart-ff2e0bed-f73f-4255-a84c-6466abd3b688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604543493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.604543493
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.584214150
Short name T825
Test name
Test status
Simulation time 24609660465 ps
CPU time 72.18 seconds
Started Aug 15 04:32:43 PM PDT 24
Finished Aug 15 04:33:55 PM PDT 24
Peak memory 249176 kb
Host smart-33b55a5a-da3c-495f-b1d5-bffa6d57f3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584214150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.584214150
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.78416238
Short name T188
Test name
Test status
Simulation time 7823988144 ps
CPU time 64.48 seconds
Started Aug 15 04:32:45 PM PDT 24
Finished Aug 15 04:33:50 PM PDT 24
Peak memory 253304 kb
Host smart-0575329e-bf59-4a6b-a8ad-bc00b9417cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78416238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.78416238
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2766421404
Short name T942
Test name
Test status
Simulation time 642960075 ps
CPU time 3.88 seconds
Started Aug 15 04:32:53 PM PDT 24
Finished Aug 15 04:32:57 PM PDT 24
Peak memory 224540 kb
Host smart-55e622e3-5257-4552-a851-fd329f29c348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766421404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2766421404
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3602620367
Short name T10
Test name
Test status
Simulation time 36158890307 ps
CPU time 243.81 seconds
Started Aug 15 04:32:46 PM PDT 24
Finished Aug 15 04:36:50 PM PDT 24
Peak memory 250184 kb
Host smart-932dbf8c-3ec1-4241-b9c9-d68896f00492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602620367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3602620367
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1270677676
Short name T207
Test name
Test status
Simulation time 1482032668 ps
CPU time 13.22 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:33:04 PM PDT 24
Peak memory 232728 kb
Host smart-7002792d-afd0-45ee-809b-20bce80c10d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270677676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1270677676
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.4096756840
Short name T705
Test name
Test status
Simulation time 281451380 ps
CPU time 4.46 seconds
Started Aug 15 04:32:53 PM PDT 24
Finished Aug 15 04:32:57 PM PDT 24
Peak memory 224416 kb
Host smart-259a73f3-5e61-453f-ab6a-3aea7da72ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096756840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4096756840
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3978738179
Short name T45
Test name
Test status
Simulation time 33148381 ps
CPU time 1.06 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:32:52 PM PDT 24
Peak memory 217776 kb
Host smart-3fec912c-4458-4778-99cf-3803b193d264
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978738179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3978738179
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.823885759
Short name T745
Test name
Test status
Simulation time 20812737712 ps
CPU time 18.01 seconds
Started Aug 15 04:32:42 PM PDT 24
Finished Aug 15 04:33:00 PM PDT 24
Peak memory 240888 kb
Host smart-941b24e6-3e5c-4519-bfaf-8bb5f04619c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823885759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.823885759
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2522572013
Short name T526
Test name
Test status
Simulation time 2795777480 ps
CPU time 10.22 seconds
Started Aug 15 04:32:48 PM PDT 24
Finished Aug 15 04:32:58 PM PDT 24
Peak memory 224512 kb
Host smart-578096af-32c6-44b2-8bfa-169a789f5710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522572013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2522572013
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1362654513
Short name T899
Test name
Test status
Simulation time 2651121936 ps
CPU time 11.62 seconds
Started Aug 15 04:32:50 PM PDT 24
Finished Aug 15 04:33:02 PM PDT 24
Peak memory 218788 kb
Host smart-3487d38a-32cf-4edc-a50f-e485ee58c4d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1362654513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1362654513
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.54700738
Short name T22
Test name
Test status
Simulation time 2707272849 ps
CPU time 40.11 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:33:32 PM PDT 24
Peak memory 251640 kb
Host smart-93b50daf-1555-4297-bde1-900609371900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54700738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress
_all.54700738
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1263715401
Short name T660
Test name
Test status
Simulation time 8896491552 ps
CPU time 43.83 seconds
Started Aug 15 04:32:52 PM PDT 24
Finished Aug 15 04:33:36 PM PDT 24
Peak memory 216296 kb
Host smart-f7db8429-fa4c-493a-8504-04ba1925622a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263715401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1263715401
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4192370334
Short name T325
Test name
Test status
Simulation time 2912084659 ps
CPU time 10.35 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:33:02 PM PDT 24
Peak memory 216328 kb
Host smart-1f5dcdf5-723a-4db1-a0ba-023e9e95ce2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192370334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4192370334
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4241877936
Short name T413
Test name
Test status
Simulation time 177926756 ps
CPU time 1.65 seconds
Started Aug 15 04:32:54 PM PDT 24
Finished Aug 15 04:32:55 PM PDT 24
Peak memory 216416 kb
Host smart-6d821ba3-7d87-4156-9376-57bd3b5715a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241877936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4241877936
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3246988545
Short name T753
Test name
Test status
Simulation time 479488439 ps
CPU time 0.82 seconds
Started Aug 15 04:32:46 PM PDT 24
Finished Aug 15 04:32:47 PM PDT 24
Peak memory 205960 kb
Host smart-d0bc32f3-5a09-42e6-a613-49879b407b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246988545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3246988545
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1929913665
Short name T737
Test name
Test status
Simulation time 19786372868 ps
CPU time 17.58 seconds
Started Aug 15 04:32:41 PM PDT 24
Finished Aug 15 04:32:58 PM PDT 24
Peak memory 232744 kb
Host smart-04daec03-2a98-47e0-8ac9-ea7a6ea1bd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929913665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1929913665
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3444341190
Short name T414
Test name
Test status
Simulation time 45712881 ps
CPU time 0.78 seconds
Started Aug 15 04:32:43 PM PDT 24
Finished Aug 15 04:32:44 PM PDT 24
Peak memory 205332 kb
Host smart-1b1d939c-cafc-43c5-b5a8-4c45a03019f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444341190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3444341190
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1498512449
Short name T563
Test name
Test status
Simulation time 2598882645 ps
CPU time 8.5 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:33:00 PM PDT 24
Peak memory 232692 kb
Host smart-1f71c7c9-5cc0-4f62-944a-bb3b9996f36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498512449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1498512449
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3288855129
Short name T498
Test name
Test status
Simulation time 18160805 ps
CPU time 0.72 seconds
Started Aug 15 04:32:50 PM PDT 24
Finished Aug 15 04:32:50 PM PDT 24
Peak memory 205392 kb
Host smart-787f5821-f57f-4672-a744-9ee93c1ff78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288855129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3288855129
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1418618227
Short name T499
Test name
Test status
Simulation time 2256306936 ps
CPU time 19.52 seconds
Started Aug 15 04:32:46 PM PDT 24
Finished Aug 15 04:33:06 PM PDT 24
Peak memory 224596 kb
Host smart-9e53db8e-d36a-4795-b608-7846a97ddaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418618227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1418618227
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1190816576
Short name T278
Test name
Test status
Simulation time 210899333392 ps
CPU time 257.91 seconds
Started Aug 15 04:32:46 PM PDT 24
Finished Aug 15 04:37:04 PM PDT 24
Peak memory 254020 kb
Host smart-265fa18f-3cfa-4c57-8c88-c918defd7ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190816576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1190816576
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1908370571
Short name T850
Test name
Test status
Simulation time 22907795710 ps
CPU time 207.17 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:36:19 PM PDT 24
Peak memory 253952 kb
Host smart-77516709-a544-4ad4-aa0c-a38d4031b700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908370571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1908370571
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3003472082
Short name T797
Test name
Test status
Simulation time 2312879557 ps
CPU time 39.3 seconds
Started Aug 15 04:32:42 PM PDT 24
Finished Aug 15 04:33:22 PM PDT 24
Peak memory 240956 kb
Host smart-8a5a59ae-141a-454d-a8af-c174eba85611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003472082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3003472082
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2920546454
Short name T957
Test name
Test status
Simulation time 31593914260 ps
CPU time 208.38 seconds
Started Aug 15 04:32:42 PM PDT 24
Finished Aug 15 04:36:11 PM PDT 24
Peak memory 252204 kb
Host smart-67ebe170-3efa-4143-9c98-caa3623a28bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920546454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2920546454
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2905273705
Short name T199
Test name
Test status
Simulation time 2723315762 ps
CPU time 11.6 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:33:03 PM PDT 24
Peak memory 224568 kb
Host smart-7a3a46d8-0706-4ef8-91cc-b8ac501adc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905273705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2905273705
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2433883066
Short name T442
Test name
Test status
Simulation time 7387441719 ps
CPU time 27.88 seconds
Started Aug 15 04:33:00 PM PDT 24
Finished Aug 15 04:33:28 PM PDT 24
Peak memory 232680 kb
Host smart-6163cce6-3328-47b1-a9b5-5fa39ac280c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433883066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2433883066
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3189420828
Short name T750
Test name
Test status
Simulation time 84324196 ps
CPU time 1.09 seconds
Started Aug 15 04:32:41 PM PDT 24
Finished Aug 15 04:32:43 PM PDT 24
Peak memory 216576 kb
Host smart-f3b5355e-df53-4bb7-99a3-b2dc51378c9e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189420828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3189420828
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2320964995
Short name T433
Test name
Test status
Simulation time 4619525158 ps
CPU time 6.71 seconds
Started Aug 15 04:32:41 PM PDT 24
Finished Aug 15 04:32:47 PM PDT 24
Peak memory 224564 kb
Host smart-f202e0bb-e1f4-4c17-a61c-3ddebf7815d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320964995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2320964995
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2573236532
Short name T471
Test name
Test status
Simulation time 12926356394 ps
CPU time 10.21 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:33:01 PM PDT 24
Peak memory 224448 kb
Host smart-8d3f513f-3edb-434a-ad8c-7590f712af48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573236532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2573236532
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.299716798
Short name T383
Test name
Test status
Simulation time 6305935609 ps
CPU time 11.77 seconds
Started Aug 15 04:32:45 PM PDT 24
Finished Aug 15 04:32:57 PM PDT 24
Peak memory 220088 kb
Host smart-8949205e-8148-4629-8ee5-232bafa972bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=299716798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.299716798
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.697965137
Short name T761
Test name
Test status
Simulation time 258435463 ps
CPU time 3.62 seconds
Started Aug 15 04:32:45 PM PDT 24
Finished Aug 15 04:32:49 PM PDT 24
Peak memory 216304 kb
Host smart-6335e579-3935-4473-8d2d-8ce43e356e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697965137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.697965137
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3234271363
Short name T769
Test name
Test status
Simulation time 3058490667 ps
CPU time 6.2 seconds
Started Aug 15 04:32:50 PM PDT 24
Finished Aug 15 04:32:56 PM PDT 24
Peak memory 216416 kb
Host smart-66e0bcca-1427-46fb-82c5-3d5a988eb6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234271363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3234271363
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.951606911
Short name T573
Test name
Test status
Simulation time 185512880 ps
CPU time 2.03 seconds
Started Aug 15 04:32:50 PM PDT 24
Finished Aug 15 04:32:52 PM PDT 24
Peak memory 216352 kb
Host smart-de6177b4-2d00-4c04-b354-1fdee2a92613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951606911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.951606911
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3144123018
Short name T596
Test name
Test status
Simulation time 79320015 ps
CPU time 0.98 seconds
Started Aug 15 04:32:41 PM PDT 24
Finished Aug 15 04:32:42 PM PDT 24
Peak memory 205972 kb
Host smart-28434526-b8a5-4319-a008-e3ceb467161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144123018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3144123018
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3976009459
Short name T193
Test name
Test status
Simulation time 800872871 ps
CPU time 2.51 seconds
Started Aug 15 04:32:50 PM PDT 24
Finished Aug 15 04:32:53 PM PDT 24
Peak memory 224504 kb
Host smart-a7df6c25-d7b0-4d2f-bc80-95298ea1efab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976009459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3976009459
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3347482971
Short name T502
Test name
Test status
Simulation time 37397602 ps
CPU time 0.76 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:31:52 PM PDT 24
Peak memory 205716 kb
Host smart-48d7cab0-1159-4df3-81ac-5f06123c38b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347482971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
347482971
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.946959235
Short name T475
Test name
Test status
Simulation time 824926273 ps
CPU time 4.32 seconds
Started Aug 15 04:31:55 PM PDT 24
Finished Aug 15 04:31:59 PM PDT 24
Peak memory 224408 kb
Host smart-9f15d4b4-bd49-4ff2-a64b-688e4d8f4a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946959235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.946959235
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2101371162
Short name T488
Test name
Test status
Simulation time 21693943 ps
CPU time 0.79 seconds
Started Aug 15 04:31:55 PM PDT 24
Finished Aug 15 04:31:56 PM PDT 24
Peak memory 206404 kb
Host smart-cae76fb7-4508-4478-9f95-4b6340675ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101371162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2101371162
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2570300547
Short name T786
Test name
Test status
Simulation time 8617112805 ps
CPU time 47.3 seconds
Started Aug 15 04:31:53 PM PDT 24
Finished Aug 15 04:32:41 PM PDT 24
Peak memory 251352 kb
Host smart-ce555303-4c2e-42e2-962c-6d290ef7a7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570300547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2570300547
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1007730364
Short name T621
Test name
Test status
Simulation time 12478104058 ps
CPU time 55.84 seconds
Started Aug 15 04:31:50 PM PDT 24
Finished Aug 15 04:32:46 PM PDT 24
Peak memory 262628 kb
Host smart-b1d5540d-b88e-4c93-a177-94ca18ec77b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007730364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1007730364
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2360514859
Short name T189
Test name
Test status
Simulation time 1623816831 ps
CPU time 39.73 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:32:32 PM PDT 24
Peak memory 249184 kb
Host smart-6f75866f-e35b-412b-b034-f78fd83bbc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360514859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2360514859
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3239780810
Short name T288
Test name
Test status
Simulation time 77741035098 ps
CPU time 30.15 seconds
Started Aug 15 04:31:53 PM PDT 24
Finished Aug 15 04:32:23 PM PDT 24
Peak memory 249172 kb
Host smart-b155a4f5-0505-486d-81b1-49ca1ae90fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239780810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3239780810
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.880316768
Short name T793
Test name
Test status
Simulation time 368760674 ps
CPU time 4.63 seconds
Started Aug 15 04:31:51 PM PDT 24
Finished Aug 15 04:31:56 PM PDT 24
Peak memory 224420 kb
Host smart-461b2c9a-d4c9-4920-8565-05936319c84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880316768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.880316768
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3248707740
Short name T253
Test name
Test status
Simulation time 12095617581 ps
CPU time 44.56 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:49 PM PDT 24
Peak memory 250972 kb
Host smart-c5acbdfa-aa88-4c41-8257-8e7aa3fb85e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248707740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3248707740
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2685244836
Short name T603
Test name
Test status
Simulation time 14602037 ps
CPU time 1.12 seconds
Started Aug 15 04:31:53 PM PDT 24
Finished Aug 15 04:31:54 PM PDT 24
Peak memory 216524 kb
Host smart-1cdc14a4-1089-4a3c-967a-f512f8fcf129
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685244836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2685244836
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.4242321520
Short name T411
Test name
Test status
Simulation time 221437061 ps
CPU time 2.13 seconds
Started Aug 15 04:31:51 PM PDT 24
Finished Aug 15 04:31:54 PM PDT 24
Peak memory 223828 kb
Host smart-75ee5727-2183-4fe4-8cc1-0d6a9ef2a859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242321520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.4242321520
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.496251407
Short name T610
Test name
Test status
Simulation time 32686710 ps
CPU time 2.29 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:06 PM PDT 24
Peak memory 232272 kb
Host smart-4cea7246-64a3-428d-8f46-144987ff9e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496251407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.496251407
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2288416633
Short name T802
Test name
Test status
Simulation time 4216002699 ps
CPU time 14.7 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:32:07 PM PDT 24
Peak memory 219408 kb
Host smart-7fa065d6-78de-4d26-ac1d-8b2e35ca32b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2288416633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2288416633
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.811134924
Short name T72
Test name
Test status
Simulation time 37577795 ps
CPU time 0.9 seconds
Started Aug 15 04:31:51 PM PDT 24
Finished Aug 15 04:31:52 PM PDT 24
Peak memory 235276 kb
Host smart-92774c57-c3c5-4b8a-ac61-670861c0c01a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811134924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.811134924
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2970589104
Short name T898
Test name
Test status
Simulation time 15663937638 ps
CPU time 164.23 seconds
Started Aug 15 04:31:54 PM PDT 24
Finished Aug 15 04:34:38 PM PDT 24
Peak memory 265540 kb
Host smart-ed9f62b9-1bfe-4cf0-932f-17161b3ecf8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970589104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2970589104
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1297989174
Short name T644
Test name
Test status
Simulation time 241952316 ps
CPU time 2.22 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:31:54 PM PDT 24
Peak memory 216664 kb
Host smart-ab367d97-9c49-450a-92fc-723664d75fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297989174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1297989174
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1475443661
Short name T2
Test name
Test status
Simulation time 3050356375 ps
CPU time 3.04 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:31:56 PM PDT 24
Peak memory 208032 kb
Host smart-5eb4969e-f2ff-480a-aa8e-4179c3457761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475443661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1475443661
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4138549770
Short name T599
Test name
Test status
Simulation time 747136144 ps
CPU time 1.55 seconds
Started Aug 15 04:31:51 PM PDT 24
Finished Aug 15 04:31:53 PM PDT 24
Peak memory 216316 kb
Host smart-721fa3d1-e386-47ea-8fc7-c3abbb437199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138549770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4138549770
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1904768619
Short name T39
Test name
Test status
Simulation time 20225359 ps
CPU time 0.72 seconds
Started Aug 15 04:31:53 PM PDT 24
Finished Aug 15 04:31:54 PM PDT 24
Peak memory 205928 kb
Host smart-443f18be-a49a-4317-becc-226c1a06acf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904768619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1904768619
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1814189381
Short name T191
Test name
Test status
Simulation time 4587217680 ps
CPU time 12.68 seconds
Started Aug 15 04:31:51 PM PDT 24
Finished Aug 15 04:32:04 PM PDT 24
Peak memory 237392 kb
Host smart-724fe062-de46-4ee1-92b2-12c422857236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814189381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1814189381
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2157081055
Short name T328
Test name
Test status
Simulation time 11013082 ps
CPU time 0.71 seconds
Started Aug 15 04:32:49 PM PDT 24
Finished Aug 15 04:32:50 PM PDT 24
Peak memory 205360 kb
Host smart-59120612-c14e-4710-9648-59eeb4bc73c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157081055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2157081055
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3279878347
Short name T482
Test name
Test status
Simulation time 2732366536 ps
CPU time 8.81 seconds
Started Aug 15 04:32:56 PM PDT 24
Finished Aug 15 04:33:05 PM PDT 24
Peak memory 232820 kb
Host smart-0924f43f-bb62-4d0c-898e-dfd287821fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279878347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3279878347
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3403636524
Short name T1021
Test name
Test status
Simulation time 38237710 ps
CPU time 0.78 seconds
Started Aug 15 04:32:46 PM PDT 24
Finished Aug 15 04:32:47 PM PDT 24
Peak memory 206764 kb
Host smart-4e40c1fa-40d2-4920-b3ec-b15241a591df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403636524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3403636524
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.165184857
Short name T205
Test name
Test status
Simulation time 16734993732 ps
CPU time 134.67 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:35:06 PM PDT 24
Peak memory 257316 kb
Host smart-e92e7ca6-3ca7-4ac1-9b11-561f40a1bf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165184857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.165184857
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1835355401
Short name T466
Test name
Test status
Simulation time 59741774839 ps
CPU time 90.45 seconds
Started Aug 15 04:32:49 PM PDT 24
Finished Aug 15 04:34:20 PM PDT 24
Peak memory 251184 kb
Host smart-3d98f6ca-3290-4dbb-a7f8-b951ad03e2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835355401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1835355401
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.502924817
Short name T398
Test name
Test status
Simulation time 8238710971 ps
CPU time 62.25 seconds
Started Aug 15 04:32:56 PM PDT 24
Finished Aug 15 04:33:58 PM PDT 24
Peak memory 250064 kb
Host smart-e20b1060-fb69-4fad-8251-843ceaec977e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502924817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.502924817
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2773054224
Short name T316
Test name
Test status
Simulation time 915915011 ps
CPU time 14.97 seconds
Started Aug 15 04:32:50 PM PDT 24
Finished Aug 15 04:33:06 PM PDT 24
Peak memory 240844 kb
Host smart-312303e0-6ef4-4432-921a-ea7450b381de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773054224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2773054224
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2747644147
Short name T537
Test name
Test status
Simulation time 11956749 ps
CPU time 0.73 seconds
Started Aug 15 04:32:52 PM PDT 24
Finished Aug 15 04:32:53 PM PDT 24
Peak memory 215708 kb
Host smart-43cc7a84-018a-4567-9349-3cfc0bb92b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747644147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2747644147
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2767125476
Short name T791
Test name
Test status
Simulation time 2497592411 ps
CPU time 14.57 seconds
Started Aug 15 04:32:57 PM PDT 24
Finished Aug 15 04:33:12 PM PDT 24
Peak memory 232804 kb
Host smart-e9328c66-f856-425d-9f1f-249e6f0b4bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767125476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2767125476
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1208392085
Short name T200
Test name
Test status
Simulation time 10306650140 ps
CPU time 39.91 seconds
Started Aug 15 04:32:52 PM PDT 24
Finished Aug 15 04:33:32 PM PDT 24
Peak memory 248732 kb
Host smart-a6d74ed9-eb92-496a-974b-bfb7e316fbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208392085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1208392085
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.4153802211
Short name T213
Test name
Test status
Simulation time 8262768185 ps
CPU time 3.99 seconds
Started Aug 15 04:32:55 PM PDT 24
Finished Aug 15 04:32:59 PM PDT 24
Peak memory 224544 kb
Host smart-8237cf78-1f8f-45ca-9661-e03156466c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153802211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.4153802211
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2415369334
Short name T921
Test name
Test status
Simulation time 1591365843 ps
CPU time 8.6 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:33:00 PM PDT 24
Peak memory 232644 kb
Host smart-0ec3b852-e82c-4a33-a4be-c0e1a5072f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415369334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2415369334
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3718444123
Short name T369
Test name
Test status
Simulation time 3224646245 ps
CPU time 5.83 seconds
Started Aug 15 04:32:49 PM PDT 24
Finished Aug 15 04:32:55 PM PDT 24
Peak memory 219268 kb
Host smart-0116d630-cdfd-4837-a02c-12d64cdbee2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3718444123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3718444123
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3731418597
Short name T815
Test name
Test status
Simulation time 7007543436 ps
CPU time 63.85 seconds
Started Aug 15 04:32:48 PM PDT 24
Finished Aug 15 04:33:52 PM PDT 24
Peak memory 249280 kb
Host smart-7d6864dd-6621-4682-95fa-94f318b13073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731418597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3731418597
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3203932532
Short name T870
Test name
Test status
Simulation time 22966544138 ps
CPU time 19.46 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:33:11 PM PDT 24
Peak memory 216304 kb
Host smart-e85d7e24-29eb-46c3-b8a7-612b4ac0d1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203932532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3203932532
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.31542918
Short name T532
Test name
Test status
Simulation time 7615698213 ps
CPU time 18.81 seconds
Started Aug 15 04:32:41 PM PDT 24
Finished Aug 15 04:33:00 PM PDT 24
Peak memory 216316 kb
Host smart-a20f3892-e2b1-4d8f-8b15-39e2c76514d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31542918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.31542918
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1202316320
Short name T757
Test name
Test status
Simulation time 549724906 ps
CPU time 4.04 seconds
Started Aug 15 04:32:46 PM PDT 24
Finished Aug 15 04:32:50 PM PDT 24
Peak memory 216320 kb
Host smart-1483dbf4-ed7d-4e27-a786-dc51c6348fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202316320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1202316320
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3757797830
Short name T408
Test name
Test status
Simulation time 59358468 ps
CPU time 0.71 seconds
Started Aug 15 04:32:49 PM PDT 24
Finished Aug 15 04:32:50 PM PDT 24
Peak memory 205876 kb
Host smart-d61bf01b-b461-46e3-9618-214220eaab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757797830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3757797830
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3368660485
Short name T989
Test name
Test status
Simulation time 250769127 ps
CPU time 3.11 seconds
Started Aug 15 04:32:52 PM PDT 24
Finished Aug 15 04:32:56 PM PDT 24
Peak memory 224472 kb
Host smart-138340e4-c2b5-4fdd-a460-040e91aecc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368660485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3368660485
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.579084246
Short name T355
Test name
Test status
Simulation time 12939666 ps
CPU time 0.72 seconds
Started Aug 15 04:32:54 PM PDT 24
Finished Aug 15 04:32:55 PM PDT 24
Peak memory 204772 kb
Host smart-906338f3-7520-4179-b698-0c807c294f51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579084246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.579084246
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1202833639
Short name T929
Test name
Test status
Simulation time 540282366 ps
CPU time 3.03 seconds
Started Aug 15 04:32:52 PM PDT 24
Finished Aug 15 04:32:55 PM PDT 24
Peak memory 224528 kb
Host smart-fd343f06-6a4b-4276-894c-f0f3e2fa5c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202833639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1202833639
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.268702348
Short name T582
Test name
Test status
Simulation time 15832196 ps
CPU time 0.77 seconds
Started Aug 15 04:32:56 PM PDT 24
Finished Aug 15 04:32:57 PM PDT 24
Peak memory 206396 kb
Host smart-06b2a071-53c1-4c40-9b99-bec0d7026b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268702348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.268702348
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2425259433
Short name T348
Test name
Test status
Simulation time 56207841109 ps
CPU time 165.94 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:35:38 PM PDT 24
Peak memory 256116 kb
Host smart-42f21c13-61a7-44ed-bf68-59f6e4c7433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425259433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2425259433
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2554067720
Short name T965
Test name
Test status
Simulation time 13241689575 ps
CPU time 48.87 seconds
Started Aug 15 04:32:58 PM PDT 24
Finished Aug 15 04:33:48 PM PDT 24
Peak memory 249316 kb
Host smart-d5c60680-9cbc-46bf-82e5-44cc6e4f45b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554067720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2554067720
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1508208327
Short name T53
Test name
Test status
Simulation time 54718942292 ps
CPU time 571.09 seconds
Started Aug 15 04:32:53 PM PDT 24
Finished Aug 15 04:42:24 PM PDT 24
Peak memory 264908 kb
Host smart-a7612d5c-cdbd-4ebc-8a77-4077f172ce77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508208327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1508208327
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3222101909
Short name T506
Test name
Test status
Simulation time 425117823 ps
CPU time 4.9 seconds
Started Aug 15 04:32:56 PM PDT 24
Finished Aug 15 04:33:01 PM PDT 24
Peak memory 224524 kb
Host smart-986ca855-378b-4354-a555-8cc53920b804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222101909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3222101909
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3515998097
Short name T264
Test name
Test status
Simulation time 36176379706 ps
CPU time 126.46 seconds
Started Aug 15 04:32:52 PM PDT 24
Finished Aug 15 04:34:59 PM PDT 24
Peak memory 251524 kb
Host smart-7c56c0f9-28df-43ac-8131-a2eb3750b8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515998097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3515998097
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2531628419
Short name T187
Test name
Test status
Simulation time 3852665399 ps
CPU time 8.37 seconds
Started Aug 15 04:32:58 PM PDT 24
Finished Aug 15 04:33:07 PM PDT 24
Peak memory 224500 kb
Host smart-feb5108e-6439-4f70-8857-92b6b495db25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531628419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2531628419
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1365228026
Short name T479
Test name
Test status
Simulation time 7495959817 ps
CPU time 32.42 seconds
Started Aug 15 04:32:58 PM PDT 24
Finished Aug 15 04:33:31 PM PDT 24
Peak memory 224596 kb
Host smart-e493c1e8-ce08-4e4a-8492-4c4e383a1ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365228026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1365228026
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1817299708
Short name T430
Test name
Test status
Simulation time 1034951882 ps
CPU time 4.99 seconds
Started Aug 15 04:32:52 PM PDT 24
Finished Aug 15 04:32:57 PM PDT 24
Peak memory 232664 kb
Host smart-624d4a0c-d7d3-49d5-b2a6-853c84ba64c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817299708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1817299708
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3860295665
Short name T550
Test name
Test status
Simulation time 32454509 ps
CPU time 2.57 seconds
Started Aug 15 04:32:54 PM PDT 24
Finished Aug 15 04:32:57 PM PDT 24
Peak memory 232420 kb
Host smart-565192ea-35f1-4568-9c32-91f48678a834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860295665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3860295665
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1085232018
Short name T365
Test name
Test status
Simulation time 803169741 ps
CPU time 10 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:33:01 PM PDT 24
Peak memory 222220 kb
Host smart-ee142323-745b-45a1-8d5b-3a1425992582
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1085232018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1085232018
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1054437560
Short name T521
Test name
Test status
Simulation time 30232500908 ps
CPU time 221.8 seconds
Started Aug 15 04:32:50 PM PDT 24
Finished Aug 15 04:36:32 PM PDT 24
Peak memory 281960 kb
Host smart-1ac66ad0-fd8d-4a21-bb6a-1e873bd7eff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054437560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1054437560
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3229876215
Short name T520
Test name
Test status
Simulation time 12567320752 ps
CPU time 68.86 seconds
Started Aug 15 04:33:03 PM PDT 24
Finished Aug 15 04:34:12 PM PDT 24
Peak memory 216396 kb
Host smart-4291569f-f5a0-4827-b737-6d9661c6e753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229876215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3229876215
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2224991009
Short name T974
Test name
Test status
Simulation time 11938640126 ps
CPU time 6.41 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:32:58 PM PDT 24
Peak memory 216308 kb
Host smart-a2d7283d-4d8f-4cf5-bb1e-ab2042b991d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224991009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2224991009
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3636212198
Short name T624
Test name
Test status
Simulation time 2005751171 ps
CPU time 7.3 seconds
Started Aug 15 04:32:53 PM PDT 24
Finished Aug 15 04:33:00 PM PDT 24
Peak memory 216304 kb
Host smart-05139a1d-2be1-4f48-9bcd-ae12b7ba9341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636212198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3636212198
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2878019884
Short name T427
Test name
Test status
Simulation time 14411240 ps
CPU time 0.69 seconds
Started Aug 15 04:32:48 PM PDT 24
Finished Aug 15 04:32:49 PM PDT 24
Peak memory 205956 kb
Host smart-1545d668-99c8-4794-a455-6b4b0cabef03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878019884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2878019884
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1693759490
Short name T176
Test name
Test status
Simulation time 37071061015 ps
CPU time 28.56 seconds
Started Aug 15 04:32:49 PM PDT 24
Finished Aug 15 04:33:18 PM PDT 24
Peak memory 224548 kb
Host smart-ed678772-6427-4b59-93e8-9f56df7ad6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693759490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1693759490
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1063377213
Short name T935
Test name
Test status
Simulation time 107493736 ps
CPU time 0.71 seconds
Started Aug 15 04:33:00 PM PDT 24
Finished Aug 15 04:33:01 PM PDT 24
Peak memory 205312 kb
Host smart-f074d30a-e7c2-494f-8ddb-037546c61612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063377213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1063377213
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3498927133
Short name T967
Test name
Test status
Simulation time 99169093 ps
CPU time 3.32 seconds
Started Aug 15 04:33:01 PM PDT 24
Finished Aug 15 04:33:05 PM PDT 24
Peak memory 224484 kb
Host smart-ea2bd923-d51d-450f-a39c-58f16f4894e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498927133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3498927133
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3273238392
Short name T566
Test name
Test status
Simulation time 90155000 ps
CPU time 0.73 seconds
Started Aug 15 04:32:50 PM PDT 24
Finished Aug 15 04:32:50 PM PDT 24
Peak memory 205368 kb
Host smart-02199bef-b125-4cc2-8809-4a9defc73349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273238392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3273238392
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2789924551
Short name T394
Test name
Test status
Simulation time 6108777388 ps
CPU time 31.58 seconds
Started Aug 15 04:33:10 PM PDT 24
Finished Aug 15 04:33:42 PM PDT 24
Peak memory 240932 kb
Host smart-ddd522fd-6091-45a2-9d0f-ada82951a82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789924551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2789924551
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.257863784
Short name T857
Test name
Test status
Simulation time 109197499016 ps
CPU time 339.08 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:38:42 PM PDT 24
Peak memory 253592 kb
Host smart-960cacba-a97f-4d4e-a8b3-56d8e3b1b8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257863784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.257863784
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.923019219
Short name T919
Test name
Test status
Simulation time 3380101320 ps
CPU time 48.59 seconds
Started Aug 15 04:33:04 PM PDT 24
Finished Aug 15 04:33:53 PM PDT 24
Peak memory 249300 kb
Host smart-96b77ce0-6052-44ae-b72b-a72b32e4be02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923019219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.923019219
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.525753521
Short name T437
Test name
Test status
Simulation time 1557852979 ps
CPU time 7.48 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:14 PM PDT 24
Peak memory 224516 kb
Host smart-431ef97b-8d2f-4d4a-9a64-31015479d53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525753521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.525753521
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.669796228
Short name T13
Test name
Test status
Simulation time 286029380746 ps
CPU time 304.6 seconds
Started Aug 15 04:33:00 PM PDT 24
Finished Aug 15 04:38:05 PM PDT 24
Peak memory 255268 kb
Host smart-f33d5437-72f9-41e5-8b93-c7559cfa107d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669796228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.669796228
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2839060350
Short name T533
Test name
Test status
Simulation time 31452643194 ps
CPU time 24.61 seconds
Started Aug 15 04:32:54 PM PDT 24
Finished Aug 15 04:33:19 PM PDT 24
Peak memory 224540 kb
Host smart-a0a562b4-1688-4fe5-9fa8-6e6b34a01a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839060350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2839060350
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3802947838
Short name T614
Test name
Test status
Simulation time 55678712271 ps
CPU time 91.63 seconds
Started Aug 15 04:32:52 PM PDT 24
Finished Aug 15 04:34:23 PM PDT 24
Peak memory 236760 kb
Host smart-af1f6c43-9c36-4035-9ad4-20607caafe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802947838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3802947838
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2027367038
Short name T711
Test name
Test status
Simulation time 377598728 ps
CPU time 5.32 seconds
Started Aug 15 04:32:56 PM PDT 24
Finished Aug 15 04:33:01 PM PDT 24
Peak memory 232676 kb
Host smart-ff38d2fc-152d-4f04-b1dc-58208fbb5621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027367038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2027367038
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3161299034
Short name T719
Test name
Test status
Simulation time 12123007367 ps
CPU time 10.96 seconds
Started Aug 15 04:32:57 PM PDT 24
Finished Aug 15 04:33:08 PM PDT 24
Peak memory 232784 kb
Host smart-51935518-c89b-499a-95c9-3d443b2a6c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161299034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3161299034
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.655999359
Short name T150
Test name
Test status
Simulation time 3390624078 ps
CPU time 11.89 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:20 PM PDT 24
Peak memory 221828 kb
Host smart-f8f000bb-67ae-4c4e-83b3-f16ad1eb1bee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=655999359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.655999359
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2066497985
Short name T910
Test name
Test status
Simulation time 213554191581 ps
CPU time 848.35 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:47:11 PM PDT 24
Peak memory 272544 kb
Host smart-670eb180-2298-43d6-820e-a77cdd2e4d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066497985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2066497985
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1915465311
Short name T511
Test name
Test status
Simulation time 6653779073 ps
CPU time 17.53 seconds
Started Aug 15 04:32:57 PM PDT 24
Finished Aug 15 04:33:15 PM PDT 24
Peak memory 216304 kb
Host smart-561b3ab0-ab94-4716-8bd2-8fef4f356dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915465311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1915465311
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1040167346
Short name T767
Test name
Test status
Simulation time 957579622 ps
CPU time 4.02 seconds
Started Aug 15 04:32:49 PM PDT 24
Finished Aug 15 04:32:54 PM PDT 24
Peak memory 216224 kb
Host smart-15bff6eb-e844-4c3a-bc39-25ef6a41e1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040167346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1040167346
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2044202508
Short name T687
Test name
Test status
Simulation time 37879112 ps
CPU time 1.75 seconds
Started Aug 15 04:32:51 PM PDT 24
Finished Aug 15 04:32:53 PM PDT 24
Peak memory 216244 kb
Host smart-515826f1-3c0a-4cb6-864c-a7ffacd006a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044202508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2044202508
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2427918771
Short name T335
Test name
Test status
Simulation time 91139674 ps
CPU time 0.85 seconds
Started Aug 15 04:32:52 PM PDT 24
Finished Aug 15 04:32:53 PM PDT 24
Peak memory 205908 kb
Host smart-f9bc7390-cd90-40cc-aeaf-9c68319440f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427918771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2427918771
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1633345625
Short name T704
Test name
Test status
Simulation time 591398021 ps
CPU time 9.08 seconds
Started Aug 15 04:33:05 PM PDT 24
Finished Aug 15 04:33:15 PM PDT 24
Peak memory 240868 kb
Host smart-a57cc380-ec41-4073-a7e3-0a9b681f32c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633345625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1633345625
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3966475551
Short name T553
Test name
Test status
Simulation time 59664561 ps
CPU time 0.77 seconds
Started Aug 15 04:33:05 PM PDT 24
Finished Aug 15 04:33:06 PM PDT 24
Peak memory 205808 kb
Host smart-a186507e-2eed-4bb8-9b16-d1fed2780ac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966475551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3966475551
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4089006951
Short name T240
Test name
Test status
Simulation time 45999354 ps
CPU time 2.75 seconds
Started Aug 15 04:33:00 PM PDT 24
Finished Aug 15 04:33:03 PM PDT 24
Peak memory 232648 kb
Host smart-f324759d-e55e-433a-a685-85e1e91a051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089006951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4089006951
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2021424179
Short name T844
Test name
Test status
Simulation time 78320810 ps
CPU time 0.82 seconds
Started Aug 15 04:33:01 PM PDT 24
Finished Aug 15 04:33:02 PM PDT 24
Peak memory 206380 kb
Host smart-24b6edcf-f5b8-40b1-986e-fe3f9e5741c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021424179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2021424179
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1075429269
Short name T217
Test name
Test status
Simulation time 115005566994 ps
CPU time 221.6 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:36:43 PM PDT 24
Peak memory 254952 kb
Host smart-1a235dc9-b932-49b1-9d93-60c0f0eaa4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075429269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1075429269
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1458906418
Short name T680
Test name
Test status
Simulation time 19064257496 ps
CPU time 172.25 seconds
Started Aug 15 04:33:06 PM PDT 24
Finished Aug 15 04:35:58 PM PDT 24
Peak memory 268012 kb
Host smart-40806ae3-3a8a-49c1-b99b-8b67e3effc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458906418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1458906418
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1221897025
Short name T281
Test name
Test status
Simulation time 15815770573 ps
CPU time 66.18 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:34:08 PM PDT 24
Peak memory 240996 kb
Host smart-54a34dcc-82ce-4171-a448-c2b784065204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221897025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1221897025
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.381623777
Short name T403
Test name
Test status
Simulation time 253284120 ps
CPU time 2.58 seconds
Started Aug 15 04:33:03 PM PDT 24
Finished Aug 15 04:33:05 PM PDT 24
Peak memory 224492 kb
Host smart-30021908-cdb1-4ee5-93e4-2428ca04f2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381623777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.381623777
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3202549909
Short name T945
Test name
Test status
Simulation time 8796162204 ps
CPU time 30.49 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:39 PM PDT 24
Peak memory 241040 kb
Host smart-661c0521-d148-4e28-baac-c1afb44d8e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202549909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3202549909
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3151958967
Short name T956
Test name
Test status
Simulation time 2185892465 ps
CPU time 7.06 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:33:09 PM PDT 24
Peak memory 232728 kb
Host smart-54bfe4a1-251c-426b-99a9-158c4e6d8a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151958967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3151958967
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3526564827
Short name T991
Test name
Test status
Simulation time 14496897814 ps
CPU time 74.09 seconds
Started Aug 15 04:33:09 PM PDT 24
Finished Aug 15 04:34:23 PM PDT 24
Peak memory 240672 kb
Host smart-2fb977fb-67df-4078-9844-a0b996c11886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526564827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3526564827
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3307403232
Short name T754
Test name
Test status
Simulation time 3447487958 ps
CPU time 21.99 seconds
Started Aug 15 04:33:04 PM PDT 24
Finished Aug 15 04:33:26 PM PDT 24
Peak memory 249092 kb
Host smart-005d1467-a8bf-4a5e-80ae-8abcf6fc2400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307403232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3307403232
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1140257246
Short name T963
Test name
Test status
Simulation time 171796682 ps
CPU time 2.24 seconds
Started Aug 15 04:32:58 PM PDT 24
Finished Aug 15 04:33:01 PM PDT 24
Peak memory 232300 kb
Host smart-23ce9bf8-d1ec-4731-a002-fd527a7e50f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140257246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1140257246
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2703172577
Short name T808
Test name
Test status
Simulation time 20485951852 ps
CPU time 14.58 seconds
Started Aug 15 04:33:09 PM PDT 24
Finished Aug 15 04:33:24 PM PDT 24
Peak memory 218784 kb
Host smart-d94727aa-0647-4e9a-8fee-52322fc30244
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2703172577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2703172577
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.309864618
Short name T156
Test name
Test status
Simulation time 137767879 ps
CPU time 1.08 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:09 PM PDT 24
Peak memory 207612 kb
Host smart-80f2a9ea-55ac-4e26-b156-c474d6665751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309864618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.309864618
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1450337902
Short name T364
Test name
Test status
Simulation time 2660178968 ps
CPU time 7.45 seconds
Started Aug 15 04:33:00 PM PDT 24
Finished Aug 15 04:33:07 PM PDT 24
Peak memory 216456 kb
Host smart-4cee14a5-881e-4345-890e-d5f2901945f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450337902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1450337902
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1817372560
Short name T656
Test name
Test status
Simulation time 14054853845 ps
CPU time 13.43 seconds
Started Aug 15 04:33:01 PM PDT 24
Finished Aug 15 04:33:14 PM PDT 24
Peak memory 216336 kb
Host smart-3a497921-4883-4246-9bcb-8bb0b7387d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817372560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1817372560
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3418455551
Short name T842
Test name
Test status
Simulation time 15166165 ps
CPU time 0.85 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:33:03 PM PDT 24
Peak memory 206972 kb
Host smart-1d5d583e-c4b4-4849-ba6e-bba918fcf3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418455551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3418455551
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3930586849
Short name T628
Test name
Test status
Simulation time 30293971 ps
CPU time 0.91 seconds
Started Aug 15 04:33:01 PM PDT 24
Finished Aug 15 04:33:02 PM PDT 24
Peak memory 206976 kb
Host smart-e21542be-5c20-40c4-b2d2-5e111b078448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930586849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3930586849
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2115093878
Short name T512
Test name
Test status
Simulation time 28016496055 ps
CPU time 21.26 seconds
Started Aug 15 04:32:58 PM PDT 24
Finished Aug 15 04:33:19 PM PDT 24
Peak memory 232772 kb
Host smart-297cefcf-adac-47c2-a7ae-23e9edc9d777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115093878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2115093878
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3921533760
Short name T755
Test name
Test status
Simulation time 13257919 ps
CPU time 0.81 seconds
Started Aug 15 04:33:04 PM PDT 24
Finished Aug 15 04:33:05 PM PDT 24
Peak memory 204740 kb
Host smart-e2aa6c4d-70eb-491b-a4f6-85a1acc350cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921533760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3921533760
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2373643675
Short name T783
Test name
Test status
Simulation time 410238076 ps
CPU time 3.01 seconds
Started Aug 15 04:33:01 PM PDT 24
Finished Aug 15 04:33:04 PM PDT 24
Peak memory 232724 kb
Host smart-30767cd1-22e1-436f-845d-b89044afb335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373643675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2373643675
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1247302397
Short name T327
Test name
Test status
Simulation time 24355608 ps
CPU time 0.74 seconds
Started Aug 15 04:33:11 PM PDT 24
Finished Aug 15 04:33:12 PM PDT 24
Peak memory 205352 kb
Host smart-f51b7c94-55d0-4f64-af2d-89e65026173c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247302397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1247302397
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3642597674
Short name T980
Test name
Test status
Simulation time 115383867942 ps
CPU time 239.15 seconds
Started Aug 15 04:33:04 PM PDT 24
Finished Aug 15 04:37:03 PM PDT 24
Peak memory 253780 kb
Host smart-9f05cee4-5f08-4f86-bd7d-ed03f4648f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642597674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3642597674
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.174265346
Short name T282
Test name
Test status
Simulation time 7537570998 ps
CPU time 57.42 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:33:59 PM PDT 24
Peak memory 251824 kb
Host smart-4770f47c-ec80-4db8-8d4b-b77afa557ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174265346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.174265346
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.991793000
Short name T940
Test name
Test status
Simulation time 1738922078 ps
CPU time 26.31 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:34 PM PDT 24
Peak memory 238936 kb
Host smart-b8c42ae6-e863-4d42-a418-696b673d06ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991793000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.991793000
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4022855172
Short name T58
Test name
Test status
Simulation time 147435821 ps
CPU time 1.95 seconds
Started Aug 15 04:33:01 PM PDT 24
Finished Aug 15 04:33:04 PM PDT 24
Peak memory 223008 kb
Host smart-e1d6d59c-7101-4003-8171-a98a43103593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022855172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4022855172
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1460646725
Short name T712
Test name
Test status
Simulation time 6755674926 ps
CPU time 70.43 seconds
Started Aug 15 04:33:01 PM PDT 24
Finished Aug 15 04:34:11 PM PDT 24
Peak memory 239896 kb
Host smart-8cb0bf34-d031-4a8a-9254-c25711209585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460646725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1460646725
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1247715523
Short name T787
Test name
Test status
Simulation time 21785863235 ps
CPU time 13.87 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:33:16 PM PDT 24
Peak memory 224528 kb
Host smart-fa0f5be8-28fc-46b4-8577-3061e9ae4ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247715523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1247715523
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2065875779
Short name T209
Test name
Test status
Simulation time 3140272666 ps
CPU time 12.31 seconds
Started Aug 15 04:33:01 PM PDT 24
Finished Aug 15 04:33:14 PM PDT 24
Peak memory 240860 kb
Host smart-d8ba1a36-8df4-418c-8125-5758367e6f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065875779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2065875779
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2694466623
Short name T862
Test name
Test status
Simulation time 1322253418 ps
CPU time 8.76 seconds
Started Aug 15 04:33:06 PM PDT 24
Finished Aug 15 04:33:15 PM PDT 24
Peak memory 222308 kb
Host smart-688ffea0-a528-4dac-8093-b37f6f6d1bd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2694466623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2694466623
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3132563917
Short name T179
Test name
Test status
Simulation time 23541987571 ps
CPU time 274.76 seconds
Started Aug 15 04:33:00 PM PDT 24
Finished Aug 15 04:37:35 PM PDT 24
Peak memory 265564 kb
Host smart-7447fe93-fc47-4cf3-9d31-56ab5b7a3bf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132563917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3132563917
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2691692645
Short name T73
Test name
Test status
Simulation time 8131716276 ps
CPU time 43.28 seconds
Started Aug 15 04:33:03 PM PDT 24
Finished Aug 15 04:33:47 PM PDT 24
Peak memory 216432 kb
Host smart-00e34f64-ff7d-4e1c-b6c8-c55ff1ff002c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691692645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2691692645
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2853484828
Short name T35
Test name
Test status
Simulation time 58020620079 ps
CPU time 9.66 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:33:12 PM PDT 24
Peak memory 216764 kb
Host smart-af62380f-7494-4c23-b990-3c0cef78cabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853484828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2853484828
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1228836142
Short name T694
Test name
Test status
Simulation time 235296430 ps
CPU time 1.84 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:33:04 PM PDT 24
Peak memory 216304 kb
Host smart-7235a4b2-c9dd-4cf4-94d7-58b11b6f5034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228836142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1228836142
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3909435253
Short name T165
Test name
Test status
Simulation time 13922311 ps
CPU time 0.7 seconds
Started Aug 15 04:33:05 PM PDT 24
Finished Aug 15 04:33:05 PM PDT 24
Peak memory 205404 kb
Host smart-81686010-b60c-4be7-9351-f8f81c7191f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909435253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3909435253
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2981380762
Short name T54
Test name
Test status
Simulation time 3360492156 ps
CPU time 8.43 seconds
Started Aug 15 04:33:01 PM PDT 24
Finished Aug 15 04:33:09 PM PDT 24
Peak memory 232756 kb
Host smart-878ea3c3-70e5-4eaf-bb09-8590347e45aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981380762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2981380762
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3883185485
Short name T387
Test name
Test status
Simulation time 45311433 ps
CPU time 0.76 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:09 PM PDT 24
Peak memory 205684 kb
Host smart-bb956239-4300-4dd9-b990-1893386212dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883185485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3883185485
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2954547451
Short name T1022
Test name
Test status
Simulation time 1484217261 ps
CPU time 4 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:11 PM PDT 24
Peak memory 224404 kb
Host smart-f13ce036-f37d-4a74-9325-352556eeaa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954547451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2954547451
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3396867161
Short name T352
Test name
Test status
Simulation time 20712804 ps
CPU time 0.8 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:09 PM PDT 24
Peak memory 206404 kb
Host smart-45548777-4526-462b-b5f6-d174b14509ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396867161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3396867161
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1895831898
Short name T82
Test name
Test status
Simulation time 25993914838 ps
CPU time 92.08 seconds
Started Aug 15 04:33:05 PM PDT 24
Finished Aug 15 04:34:38 PM PDT 24
Peak memory 255244 kb
Host smart-6c21545e-fd49-4d80-aa59-07d08914fb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895831898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1895831898
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.574161445
Short name T202
Test name
Test status
Simulation time 122738240680 ps
CPU time 213.05 seconds
Started Aug 15 04:33:11 PM PDT 24
Finished Aug 15 04:36:44 PM PDT 24
Peak memory 262804 kb
Host smart-783e00d2-f9f5-4d8a-a83a-d66d7ccb8327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574161445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.574161445
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.959606168
Short name T950
Test name
Test status
Simulation time 152650901493 ps
CPU time 326.05 seconds
Started Aug 15 04:33:09 PM PDT 24
Finished Aug 15 04:38:35 PM PDT 24
Peak memory 249564 kb
Host smart-dd20b6cf-d0e2-415e-b9cc-53ab31c93023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959606168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.959606168
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1748901841
Short name T968
Test name
Test status
Simulation time 747720558 ps
CPU time 20.02 seconds
Started Aug 15 04:33:10 PM PDT 24
Finished Aug 15 04:33:30 PM PDT 24
Peak memory 249252 kb
Host smart-79f378f3-6247-4d12-bdb8-f715bb5a7cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748901841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1748901841
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.64386889
Short name T846
Test name
Test status
Simulation time 2736767550 ps
CPU time 11.52 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:19 PM PDT 24
Peak memory 224592 kb
Host smart-0cfbf7f6-ada3-46a6-a682-f25bf4504518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64386889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.64386889
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1889960165
Short name T504
Test name
Test status
Simulation time 615684835 ps
CPU time 7.23 seconds
Started Aug 15 04:33:11 PM PDT 24
Finished Aug 15 04:33:19 PM PDT 24
Peak memory 224544 kb
Host smart-0ab75d87-aa09-4fd9-8de9-5a4cb4e8908b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889960165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1889960165
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.732318754
Short name T773
Test name
Test status
Simulation time 2226672143 ps
CPU time 14 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:22 PM PDT 24
Peak memory 248164 kb
Host smart-dbe3498b-6c51-434c-8eeb-ec920c860577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732318754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.732318754
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2053115065
Short name T794
Test name
Test status
Simulation time 8802858547 ps
CPU time 29 seconds
Started Aug 15 04:33:09 PM PDT 24
Finished Aug 15 04:33:38 PM PDT 24
Peak memory 251004 kb
Host smart-1e6c0652-24d4-412c-8306-96302045bad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053115065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2053115065
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1848614552
Short name T392
Test name
Test status
Simulation time 668199022 ps
CPU time 9.92 seconds
Started Aug 15 04:33:06 PM PDT 24
Finished Aug 15 04:33:16 PM PDT 24
Peak memory 223100 kb
Host smart-f10c8b2f-5b92-41a7-a148-b35227e4143c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1848614552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1848614552
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.77755113
Short name T830
Test name
Test status
Simulation time 79729215208 ps
CPU time 223.7 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:36:52 PM PDT 24
Peak memory 268580 kb
Host smart-959670d3-0cca-4950-b2b5-087e589e5278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77755113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress
_all.77755113
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4291392796
Short name T37
Test name
Test status
Simulation time 704741457 ps
CPU time 4.92 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:33:08 PM PDT 24
Peak memory 216332 kb
Host smart-6fe30ed2-e228-4a83-bfe0-8e7b542470cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291392796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4291392796
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3115828503
Short name T353
Test name
Test status
Simulation time 34050954 ps
CPU time 0.72 seconds
Started Aug 15 04:33:05 PM PDT 24
Finished Aug 15 04:33:06 PM PDT 24
Peak memory 205540 kb
Host smart-2764ffef-e2a7-4ff6-bb47-31732b005a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115828503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3115828503
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.770371039
Short name T926
Test name
Test status
Simulation time 39538457 ps
CPU time 0.69 seconds
Started Aug 15 04:33:03 PM PDT 24
Finished Aug 15 04:33:04 PM PDT 24
Peak memory 205460 kb
Host smart-880dba0c-b2d2-4f9b-b42f-267dcec7ccee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770371039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.770371039
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1686578294
Short name T421
Test name
Test status
Simulation time 25971746 ps
CPU time 0.9 seconds
Started Aug 15 04:33:02 PM PDT 24
Finished Aug 15 04:33:03 PM PDT 24
Peak memory 206348 kb
Host smart-9b3de4cb-3a26-4989-9a03-8b0101190dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686578294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1686578294
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4050612829
Short name T131
Test name
Test status
Simulation time 532887339 ps
CPU time 3.6 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:11 PM PDT 24
Peak memory 224476 kb
Host smart-bc9ad20b-681b-4a88-b478-a0612d46a372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050612829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4050612829
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2568693610
Short name T1019
Test name
Test status
Simulation time 42182534 ps
CPU time 0.73 seconds
Started Aug 15 04:33:04 PM PDT 24
Finished Aug 15 04:33:05 PM PDT 24
Peak memory 205324 kb
Host smart-276fc419-f75d-4891-a537-45e04b1044c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568693610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2568693610
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2251641488
Short name T646
Test name
Test status
Simulation time 174292664 ps
CPU time 2.6 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:10 PM PDT 24
Peak memory 224404 kb
Host smart-c5fd13e4-937b-469e-a31d-468c3b4da7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251641488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2251641488
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2148380240
Short name T939
Test name
Test status
Simulation time 28123556 ps
CPU time 0.78 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:09 PM PDT 24
Peak memory 206412 kb
Host smart-6329da0d-8a65-4e29-9af5-7f91d6a79fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148380240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2148380240
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2208252274
Short name T77
Test name
Test status
Simulation time 108416415 ps
CPU time 0.87 seconds
Started Aug 15 04:33:09 PM PDT 24
Finished Aug 15 04:33:10 PM PDT 24
Peak memory 215892 kb
Host smart-71c4eb24-067e-4eb1-adfc-4152dead524b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208252274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2208252274
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3751405117
Short name T266
Test name
Test status
Simulation time 4507269675 ps
CPU time 74.59 seconds
Started Aug 15 04:33:12 PM PDT 24
Finished Aug 15 04:34:27 PM PDT 24
Peak memory 254252 kb
Host smart-71c0af8e-65e2-4d4c-87eb-b68f96fac893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751405117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3751405117
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3609093998
Short name T32
Test name
Test status
Simulation time 8770078041 ps
CPU time 41.26 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:48 PM PDT 24
Peak memory 232840 kb
Host smart-08140ce7-11ae-4e6b-bbf3-9ba0f29d1775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609093998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3609093998
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2749975932
Short name T485
Test name
Test status
Simulation time 205613940 ps
CPU time 5.14 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:13 PM PDT 24
Peak memory 233292 kb
Host smart-bc512209-aa91-4e55-beb0-41a9a63b0b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749975932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2749975932
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2785837753
Short name T647
Test name
Test status
Simulation time 93239310 ps
CPU time 0.74 seconds
Started Aug 15 04:33:06 PM PDT 24
Finished Aug 15 04:33:07 PM PDT 24
Peak memory 215692 kb
Host smart-348e5fcf-e2c7-4661-bbd7-5cfe9fa96a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785837753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2785837753
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3781304014
Short name T636
Test name
Test status
Simulation time 418169251 ps
CPU time 2.9 seconds
Started Aug 15 04:33:06 PM PDT 24
Finished Aug 15 04:33:09 PM PDT 24
Peak memory 224460 kb
Host smart-e7e1ae85-73ce-443b-85fb-36783f15766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781304014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3781304014
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2033963155
Short name T251
Test name
Test status
Simulation time 11066117108 ps
CPU time 18.78 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:27 PM PDT 24
Peak memory 224616 kb
Host smart-6562e0d7-fd0a-4d8a-9409-bd4102aaa213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033963155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2033963155
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1777863041
Short name T920
Test name
Test status
Simulation time 4075012420 ps
CPU time 7.31 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:15 PM PDT 24
Peak memory 232700 kb
Host smart-7763a534-03d3-484b-95f2-7f6708205496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777863041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1777863041
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1595077061
Short name T684
Test name
Test status
Simulation time 654525527 ps
CPU time 3.43 seconds
Started Aug 15 04:33:06 PM PDT 24
Finished Aug 15 04:33:10 PM PDT 24
Peak memory 224448 kb
Host smart-363b2a59-5061-47f2-891d-9136c65173db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595077061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1595077061
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2297619133
Short name T410
Test name
Test status
Simulation time 2426711382 ps
CPU time 9.76 seconds
Started Aug 15 04:33:09 PM PDT 24
Finished Aug 15 04:33:19 PM PDT 24
Peak memory 222580 kb
Host smart-410fa413-859d-40b5-acde-9a4a290c00a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2297619133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2297619133
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1254249846
Short name T836
Test name
Test status
Simulation time 33581468061 ps
CPU time 343.9 seconds
Started Aug 15 04:33:11 PM PDT 24
Finished Aug 15 04:38:55 PM PDT 24
Peak memory 265252 kb
Host smart-4ebee045-ec92-43fa-8a9f-1961036790f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254249846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1254249846
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2684948141
Short name T445
Test name
Test status
Simulation time 2403698063 ps
CPU time 16.93 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:24 PM PDT 24
Peak memory 216308 kb
Host smart-bcc43117-e889-4db9-8d0a-0b0f94772141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684948141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2684948141
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2576185364
Short name T318
Test name
Test status
Simulation time 65661343 ps
CPU time 1.11 seconds
Started Aug 15 04:33:06 PM PDT 24
Finished Aug 15 04:33:07 PM PDT 24
Peak memory 206980 kb
Host smart-c8896035-4ca1-4817-b987-facc74b40900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576185364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2576185364
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2596870832
Short name T347
Test name
Test status
Simulation time 21412325 ps
CPU time 0.72 seconds
Started Aug 15 04:33:06 PM PDT 24
Finished Aug 15 04:33:07 PM PDT 24
Peak memory 205960 kb
Host smart-2436ce43-cff4-4142-9f40-d7d5df50b17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596870832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2596870832
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1542872802
Short name T40
Test name
Test status
Simulation time 14371531 ps
CPU time 0.74 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:09 PM PDT 24
Peak memory 205500 kb
Host smart-69d5b25b-13af-4c7e-a227-54fa9cdd1c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542872802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1542872802
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.285408173
Short name T407
Test name
Test status
Simulation time 364406008 ps
CPU time 3.44 seconds
Started Aug 15 04:33:06 PM PDT 24
Finished Aug 15 04:33:10 PM PDT 24
Peak memory 224420 kb
Host smart-aade7f11-ff13-4641-94fc-88f13874b3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285408173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.285408173
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3304216864
Short name T340
Test name
Test status
Simulation time 11857307 ps
CPU time 0.7 seconds
Started Aug 15 04:33:18 PM PDT 24
Finished Aug 15 04:33:18 PM PDT 24
Peak memory 205372 kb
Host smart-33f0cf26-8be0-4fbc-b062-4a7c3f72f720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304216864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3304216864
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3936658943
Short name T580
Test name
Test status
Simulation time 508256362 ps
CPU time 8.26 seconds
Started Aug 15 04:33:09 PM PDT 24
Finished Aug 15 04:33:17 PM PDT 24
Peak memory 232596 kb
Host smart-5693a0e0-03c4-44a5-9fd5-8e6ceb696d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936658943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3936658943
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.517686885
Short name T345
Test name
Test status
Simulation time 51022411 ps
CPU time 0.74 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:09 PM PDT 24
Peak memory 205760 kb
Host smart-0f0bed9c-1ba0-450e-9c44-4a55a2fd81ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517686885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.517686885
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2428904737
Short name T983
Test name
Test status
Simulation time 15642495995 ps
CPU time 134.73 seconds
Started Aug 15 04:33:13 PM PDT 24
Finished Aug 15 04:35:28 PM PDT 24
Peak memory 240524 kb
Host smart-851a5d78-1c3e-488f-971d-10ad3dd1d83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428904737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2428904737
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2014329763
Short name T905
Test name
Test status
Simulation time 46584266704 ps
CPU time 207.07 seconds
Started Aug 15 04:33:12 PM PDT 24
Finished Aug 15 04:36:39 PM PDT 24
Peak memory 257088 kb
Host smart-73086e4b-9cff-4621-967c-6801a9e44474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014329763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2014329763
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3392433220
Short name T701
Test name
Test status
Simulation time 3636849642 ps
CPU time 15.23 seconds
Started Aug 15 04:33:09 PM PDT 24
Finished Aug 15 04:33:25 PM PDT 24
Peak memory 224644 kb
Host smart-79c38f58-109f-45b7-b6b6-338f7d018127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392433220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3392433220
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.233825995
Short name T272
Test name
Test status
Simulation time 157011439100 ps
CPU time 256.09 seconds
Started Aug 15 04:33:10 PM PDT 24
Finished Aug 15 04:37:26 PM PDT 24
Peak memory 249156 kb
Host smart-09facca8-052d-4cb9-9972-4131e4ca872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233825995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.233825995
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2871479039
Short name T649
Test name
Test status
Simulation time 114565409 ps
CPU time 2.88 seconds
Started Aug 15 04:33:09 PM PDT 24
Finished Aug 15 04:33:12 PM PDT 24
Peak memory 224460 kb
Host smart-c6cdded6-1c2b-4f2c-9a61-94435f3751a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871479039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2871479039
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3964048661
Short name T487
Test name
Test status
Simulation time 3805630411 ps
CPU time 10.12 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:18 PM PDT 24
Peak memory 240748 kb
Host smart-3c29ca81-7ec4-489d-9fca-fa8b716408fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964048661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3964048661
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3705672735
Short name T262
Test name
Test status
Simulation time 10035736639 ps
CPU time 28.23 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:37 PM PDT 24
Peak memory 248884 kb
Host smart-401508c7-3947-4217-9d22-736fea9ecab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705672735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3705672735
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3167143631
Short name T601
Test name
Test status
Simulation time 7242436736 ps
CPU time 10.67 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:19 PM PDT 24
Peak memory 232740 kb
Host smart-35bf2267-3c68-4ae7-a50b-c8ae09c3b2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167143631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3167143631
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.795988304
Short name T679
Test name
Test status
Simulation time 1892254246 ps
CPU time 17.31 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:26 PM PDT 24
Peak memory 220236 kb
Host smart-ec09632d-cc11-4c32-b8a9-f964f6c3feac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=795988304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.795988304
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1372877115
Short name T896
Test name
Test status
Simulation time 10760120012 ps
CPU time 54.63 seconds
Started Aug 15 04:33:19 PM PDT 24
Finished Aug 15 04:34:14 PM PDT 24
Peak memory 249208 kb
Host smart-df6aef71-73ce-4d4b-883f-1f91d500edaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372877115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1372877115
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3291872295
Short name T556
Test name
Test status
Simulation time 40457462 ps
CPU time 0.73 seconds
Started Aug 15 04:33:12 PM PDT 24
Finished Aug 15 04:33:13 PM PDT 24
Peak memory 205536 kb
Host smart-764a8c36-54fe-4e19-9750-794013b54092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291872295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3291872295
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2409345005
Short name T886
Test name
Test status
Simulation time 23286230 ps
CPU time 0.75 seconds
Started Aug 15 04:33:09 PM PDT 24
Finished Aug 15 04:33:10 PM PDT 24
Peak memory 205504 kb
Host smart-368fafb9-ae4f-4a45-bb75-e8d5f66afac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409345005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2409345005
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3820749654
Short name T308
Test name
Test status
Simulation time 102407042 ps
CPU time 3.24 seconds
Started Aug 15 04:33:07 PM PDT 24
Finished Aug 15 04:33:10 PM PDT 24
Peak memory 216284 kb
Host smart-4e7e244f-e672-49c3-ad1b-819189a65d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820749654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3820749654
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.23848206
Short name T715
Test name
Test status
Simulation time 801732959 ps
CPU time 0.89 seconds
Started Aug 15 04:33:12 PM PDT 24
Finished Aug 15 04:33:13 PM PDT 24
Peak memory 205896 kb
Host smart-a4d60c77-d224-4d48-a7a8-f54e20ceed78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23848206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.23848206
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.93827965
Short name T998
Test name
Test status
Simulation time 31025467355 ps
CPU time 26.53 seconds
Started Aug 15 04:33:08 PM PDT 24
Finished Aug 15 04:33:35 PM PDT 24
Peak memory 224504 kb
Host smart-63ce2d7c-22fb-4939-9589-d2dfa620a984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93827965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.93827965
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.908918765
Short name T444
Test name
Test status
Simulation time 38285876 ps
CPU time 0.79 seconds
Started Aug 15 04:33:17 PM PDT 24
Finished Aug 15 04:33:18 PM PDT 24
Peak memory 205320 kb
Host smart-5b2ae22b-303e-41a9-9cef-1c877c19bf63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908918765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.908918765
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1136485530
Short name T995
Test name
Test status
Simulation time 508049631 ps
CPU time 3.45 seconds
Started Aug 15 04:33:20 PM PDT 24
Finished Aug 15 04:33:24 PM PDT 24
Peak memory 232696 kb
Host smart-80248b7d-d2dc-469f-bb54-bcc5b8753ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136485530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1136485530
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.866437723
Short name T64
Test name
Test status
Simulation time 36044747 ps
CPU time 0.77 seconds
Started Aug 15 04:33:19 PM PDT 24
Finished Aug 15 04:33:20 PM PDT 24
Peak memory 205340 kb
Host smart-a34b44be-c7f3-4f0f-803b-34bf29c2784f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866437723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.866437723
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1293875908
Short name T937
Test name
Test status
Simulation time 4038093706 ps
CPU time 32.6 seconds
Started Aug 15 04:33:18 PM PDT 24
Finished Aug 15 04:33:51 PM PDT 24
Peak memory 232852 kb
Host smart-de38f49e-6ccc-46f6-b1af-0b1ecb4bbdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293875908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1293875908
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3224496210
Short name T313
Test name
Test status
Simulation time 33275758864 ps
CPU time 106.21 seconds
Started Aug 15 04:33:20 PM PDT 24
Finished Aug 15 04:35:07 PM PDT 24
Peak memory 253676 kb
Host smart-fa51bc50-7467-4080-80cd-748d4f262d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224496210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3224496210
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2551213717
Short name T677
Test name
Test status
Simulation time 134973338 ps
CPU time 2.61 seconds
Started Aug 15 04:33:19 PM PDT 24
Finished Aug 15 04:33:22 PM PDT 24
Peak memory 224460 kb
Host smart-a4cda78f-f085-450d-9445-a328702002f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551213717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2551213717
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.114961688
Short name T676
Test name
Test status
Simulation time 577009420 ps
CPU time 8.28 seconds
Started Aug 15 04:33:20 PM PDT 24
Finished Aug 15 04:33:29 PM PDT 24
Peak memory 224420 kb
Host smart-475ae581-8a04-47cb-8e33-1fa32a0119d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114961688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.114961688
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2330724212
Short name T722
Test name
Test status
Simulation time 238147512 ps
CPU time 4.95 seconds
Started Aug 15 04:33:17 PM PDT 24
Finished Aug 15 04:33:22 PM PDT 24
Peak memory 224508 kb
Host smart-a004bbc1-49fe-4b15-b7cd-1e362e0aebd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330724212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2330724212
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1126002234
Short name T448
Test name
Test status
Simulation time 73537073619 ps
CPU time 39.16 seconds
Started Aug 15 04:33:24 PM PDT 24
Finished Aug 15 04:34:03 PM PDT 24
Peak memory 256580 kb
Host smart-0f6e8071-cc32-48d4-ab1a-956243771eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126002234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1126002234
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.371296520
Short name T622
Test name
Test status
Simulation time 18857305816 ps
CPU time 7.41 seconds
Started Aug 15 04:33:20 PM PDT 24
Finished Aug 15 04:33:28 PM PDT 24
Peak memory 224500 kb
Host smart-b51dd319-f28f-4f3e-a18b-99a312cee8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371296520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.371296520
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3832128458
Short name T770
Test name
Test status
Simulation time 1791506764 ps
CPU time 18.49 seconds
Started Aug 15 04:33:20 PM PDT 24
Finished Aug 15 04:33:39 PM PDT 24
Peak memory 222012 kb
Host smart-2f0b7907-1e41-4735-a95b-6749390b668e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3832128458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3832128458
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.381911115
Short name T944
Test name
Test status
Simulation time 7556342006 ps
CPU time 147.89 seconds
Started Aug 15 04:33:18 PM PDT 24
Finished Aug 15 04:35:46 PM PDT 24
Peak memory 262592 kb
Host smart-1babe532-4b2d-4411-940a-484ded5362be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381911115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.381911115
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1213185689
Short name T529
Test name
Test status
Simulation time 619634707 ps
CPU time 6.22 seconds
Started Aug 15 04:33:23 PM PDT 24
Finished Aug 15 04:33:29 PM PDT 24
Peak memory 216380 kb
Host smart-6999ebbb-78bb-4d10-ac05-b01549191349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213185689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1213185689
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3400674919
Short name T964
Test name
Test status
Simulation time 120925457 ps
CPU time 1.17 seconds
Started Aug 15 04:33:20 PM PDT 24
Finished Aug 15 04:33:21 PM PDT 24
Peak memory 207316 kb
Host smart-67833596-a45f-4247-84b2-83ed35a5382e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400674919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3400674919
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3319543948
Short name T402
Test name
Test status
Simulation time 1600372596 ps
CPU time 5.62 seconds
Started Aug 15 04:33:20 PM PDT 24
Finished Aug 15 04:33:25 PM PDT 24
Peak memory 216088 kb
Host smart-215b7a88-2540-410f-abd6-8c7e0330ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319543948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3319543948
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2625073289
Short name T336
Test name
Test status
Simulation time 67833769 ps
CPU time 0.72 seconds
Started Aug 15 04:33:21 PM PDT 24
Finished Aug 15 04:33:21 PM PDT 24
Peak memory 205928 kb
Host smart-44387a6a-8836-4c7f-a041-99859238e58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625073289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2625073289
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2593473759
Short name T639
Test name
Test status
Simulation time 8739476164 ps
CPU time 11.66 seconds
Started Aug 15 04:33:23 PM PDT 24
Finished Aug 15 04:33:35 PM PDT 24
Peak memory 240272 kb
Host smart-925844a8-406e-4cf7-8dea-ba5a1cc3dccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593473759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2593473759
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.888741384
Short name T333
Test name
Test status
Simulation time 12494173 ps
CPU time 0.7 seconds
Started Aug 15 04:33:16 PM PDT 24
Finished Aug 15 04:33:17 PM PDT 24
Peak memory 204840 kb
Host smart-b2ab0183-faa3-48f7-ba46-26b0a6b70660
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888741384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.888741384
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1858708059
Short name T657
Test name
Test status
Simulation time 32088263 ps
CPU time 2.45 seconds
Started Aug 15 04:33:19 PM PDT 24
Finished Aug 15 04:33:21 PM PDT 24
Peak memory 232380 kb
Host smart-b43378eb-34b2-451d-b043-9803692b7943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858708059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1858708059
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2827788905
Short name T163
Test name
Test status
Simulation time 40046567 ps
CPU time 0.81 seconds
Started Aug 15 04:33:21 PM PDT 24
Finished Aug 15 04:33:22 PM PDT 24
Peak memory 205820 kb
Host smart-2175cfe1-7765-4fae-b4f5-66ca92dd3cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827788905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2827788905
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.13305468
Short name T772
Test name
Test status
Simulation time 8293473199 ps
CPU time 69.44 seconds
Started Aug 15 04:33:22 PM PDT 24
Finished Aug 15 04:34:32 PM PDT 24
Peak memory 249260 kb
Host smart-c355fd8a-075d-4723-a54e-0ba99795f1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13305468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.13305468
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1804023865
Short name T953
Test name
Test status
Simulation time 12597830655 ps
CPU time 169.04 seconds
Started Aug 15 04:33:20 PM PDT 24
Finished Aug 15 04:36:09 PM PDT 24
Peak memory 257260 kb
Host smart-b9c610a0-df08-40f5-8d81-13f21aee2903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804023865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1804023865
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.173902883
Short name T147
Test name
Test status
Simulation time 1435673919 ps
CPU time 11.25 seconds
Started Aug 15 04:33:19 PM PDT 24
Finished Aug 15 04:33:30 PM PDT 24
Peak memory 232700 kb
Host smart-cf3a696a-f941-4bc9-9eba-29aaf47af95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173902883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.173902883
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.314698115
Short name T416
Test name
Test status
Simulation time 19402299460 ps
CPU time 136.27 seconds
Started Aug 15 04:33:19 PM PDT 24
Finished Aug 15 04:35:36 PM PDT 24
Peak memory 249184 kb
Host smart-2bd11aa5-ff26-4e1c-9421-6c3c06e5e9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314698115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.314698115
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4196176334
Short name T840
Test name
Test status
Simulation time 2006205657 ps
CPU time 8.52 seconds
Started Aug 15 04:33:22 PM PDT 24
Finished Aug 15 04:33:31 PM PDT 24
Peak memory 232808 kb
Host smart-0c87faeb-36d7-4a84-8d2d-c75837579693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196176334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4196176334
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.362298
Short name T232
Test name
Test status
Simulation time 31188418771 ps
CPU time 72.75 seconds
Started Aug 15 04:33:17 PM PDT 24
Finished Aug 15 04:34:30 PM PDT 24
Peak memory 232728 kb
Host smart-c01d9cb7-7606-47a9-a664-85aab60cf306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.362298
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2405222843
Short name T222
Test name
Test status
Simulation time 12813982285 ps
CPU time 17.43 seconds
Started Aug 15 04:33:20 PM PDT 24
Finished Aug 15 04:33:38 PM PDT 24
Peak memory 233744 kb
Host smart-9fb37505-24b0-46d4-9e4c-dffd51188b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405222843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2405222843
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3196264623
Short name T431
Test name
Test status
Simulation time 7959826727 ps
CPU time 14.91 seconds
Started Aug 15 04:33:19 PM PDT 24
Finished Aug 15 04:33:34 PM PDT 24
Peak memory 240932 kb
Host smart-0fb7d7ba-f535-47f0-acc0-5c6270a92132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196264623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3196264623
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3192309133
Short name T538
Test name
Test status
Simulation time 1661682410 ps
CPU time 9.07 seconds
Started Aug 15 04:33:18 PM PDT 24
Finished Aug 15 04:33:27 PM PDT 24
Peak memory 222200 kb
Host smart-49f4784b-a2b1-4dfa-8dab-3c6853a18d5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3192309133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3192309133
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1637263942
Short name T307
Test name
Test status
Simulation time 61539241022 ps
CPU time 102.71 seconds
Started Aug 15 04:33:20 PM PDT 24
Finished Aug 15 04:35:02 PM PDT 24
Peak memory 224416 kb
Host smart-4b1855cb-f78b-4ea2-b436-dd3765692474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637263942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1637263942
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2298225265
Short name T474
Test name
Test status
Simulation time 5873433211 ps
CPU time 2.92 seconds
Started Aug 15 04:33:23 PM PDT 24
Finished Aug 15 04:33:26 PM PDT 24
Peak memory 216392 kb
Host smart-1237d35a-4672-40ba-9ede-c53ddb8bbc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298225265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2298225265
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2759711521
Short name T913
Test name
Test status
Simulation time 320090458 ps
CPU time 2.34 seconds
Started Aug 15 04:33:17 PM PDT 24
Finished Aug 15 04:33:19 PM PDT 24
Peak memory 216280 kb
Host smart-b1d60747-362c-4e1d-90b5-6505adfd315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759711521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2759711521
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.659570977
Short name T669
Test name
Test status
Simulation time 978972106 ps
CPU time 3.4 seconds
Started Aug 15 04:33:22 PM PDT 24
Finished Aug 15 04:33:26 PM PDT 24
Peak memory 216396 kb
Host smart-b0d19c8c-792e-411d-b97e-b90a596132a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659570977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.659570977
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.821892725
Short name T371
Test name
Test status
Simulation time 19502915 ps
CPU time 0.79 seconds
Started Aug 15 04:33:22 PM PDT 24
Finished Aug 15 04:33:23 PM PDT 24
Peak memory 205892 kb
Host smart-9c83c0a6-269c-43f2-aef1-f5aef3b98240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821892725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.821892725
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1608554434
Short name T195
Test name
Test status
Simulation time 2099798399 ps
CPU time 8.47 seconds
Started Aug 15 04:33:18 PM PDT 24
Finished Aug 15 04:33:26 PM PDT 24
Peak memory 232672 kb
Host smart-d9d19760-3c5d-4f6b-a373-8ee7b95c70e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608554434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1608554434
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.783209460
Short name T689
Test name
Test status
Simulation time 12501590 ps
CPU time 0.72 seconds
Started Aug 15 04:31:56 PM PDT 24
Finished Aug 15 04:31:56 PM PDT 24
Peak memory 205780 kb
Host smart-2f5e62ed-7bbb-4f48-9be5-9ced7ef6a147
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783209460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.783209460
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1347403276
Short name T459
Test name
Test status
Simulation time 403974973 ps
CPU time 3.25 seconds
Started Aug 15 04:31:53 PM PDT 24
Finished Aug 15 04:31:56 PM PDT 24
Peak memory 232648 kb
Host smart-ee7c4f49-aa4e-4146-b03d-daf36c454f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347403276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1347403276
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2885276010
Short name T505
Test name
Test status
Simulation time 22677471 ps
CPU time 0.77 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:31:53 PM PDT 24
Peak memory 205360 kb
Host smart-12a6dd70-4df2-4b29-a751-6eaec62b979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885276010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2885276010
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3387573666
Short name T287
Test name
Test status
Simulation time 16225596250 ps
CPU time 107.4 seconds
Started Aug 15 04:31:53 PM PDT 24
Finished Aug 15 04:33:41 PM PDT 24
Peak memory 255836 kb
Host smart-df33b713-c1e8-42bb-8164-4dd5274e6087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387573666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3387573666
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3254428612
Short name T492
Test name
Test status
Simulation time 4180949755 ps
CPU time 27.79 seconds
Started Aug 15 04:31:53 PM PDT 24
Finished Aug 15 04:32:21 PM PDT 24
Peak memory 239464 kb
Host smart-73bc38b3-ac03-4e54-8c30-c96d6cf3cd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254428612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3254428612
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3454427783
Short name T847
Test name
Test status
Simulation time 34345337999 ps
CPU time 267.94 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:36:20 PM PDT 24
Peak memory 250956 kb
Host smart-3f08a6ab-7e68-46d9-88bf-011e24421556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454427783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3454427783
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.121256627
Short name T294
Test name
Test status
Simulation time 9124055237 ps
CPU time 30.76 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:32:23 PM PDT 24
Peak memory 240900 kb
Host smart-8201fe21-ff2e-4994-bb70-a3c092333324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121256627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.121256627
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2049170862
Short name T888
Test name
Test status
Simulation time 321560617 ps
CPU time 5.25 seconds
Started Aug 15 04:31:55 PM PDT 24
Finished Aug 15 04:32:01 PM PDT 24
Peak memory 235888 kb
Host smart-ed0b021a-a0f4-4f6c-9775-722c72c423e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049170862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2049170862
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2543329475
Short name T320
Test name
Test status
Simulation time 101660271 ps
CPU time 2.16 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:31:54 PM PDT 24
Peak memory 223212 kb
Host smart-b011dc07-75a7-4992-9f3c-64c1c2b50e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543329475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2543329475
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.493208817
Short name T629
Test name
Test status
Simulation time 160982643 ps
CPU time 2.81 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:31:55 PM PDT 24
Peak memory 232652 kb
Host smart-5eda6ab5-d467-41da-a5d6-e24c74e62bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493208817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.493208817
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3359290130
Short name T817
Test name
Test status
Simulation time 14531165 ps
CPU time 1.02 seconds
Started Aug 15 04:31:49 PM PDT 24
Finished Aug 15 04:31:50 PM PDT 24
Peak memory 216560 kb
Host smart-5991f8ae-9a8d-4cc6-a94a-ac44567170ea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359290130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3359290130
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.919895645
Short name T549
Test name
Test status
Simulation time 38034681994 ps
CPU time 28.09 seconds
Started Aug 15 04:31:51 PM PDT 24
Finished Aug 15 04:32:19 PM PDT 24
Peak memory 233908 kb
Host smart-4e6778a9-7dd2-4d7d-8e5b-b09e074b5d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919895645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
919895645
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.179108030
Short name T747
Test name
Test status
Simulation time 599172444 ps
CPU time 3.61 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:08 PM PDT 24
Peak memory 224412 kb
Host smart-4065f879-98df-4e86-9b2b-4a797343539c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179108030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.179108030
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1654749984
Short name T858
Test name
Test status
Simulation time 728292967 ps
CPU time 8.25 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:32:01 PM PDT 24
Peak memory 222012 kb
Host smart-144b490d-6508-492b-87a6-195245b911cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1654749984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1654749984
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2852273274
Short name T290
Test name
Test status
Simulation time 233372932102 ps
CPU time 520.59 seconds
Started Aug 15 04:31:55 PM PDT 24
Finished Aug 15 04:40:36 PM PDT 24
Peak memory 281936 kb
Host smart-c5b6771a-64c2-4057-99bf-6253423f1a73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852273274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2852273274
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.706608367
Short name T80
Test name
Test status
Simulation time 12366857733 ps
CPU time 18.35 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:32:10 PM PDT 24
Peak memory 216464 kb
Host smart-35ab0aa6-c460-4cad-8d2a-c75f3c94be42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706608367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.706608367
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1733586783
Short name T454
Test name
Test status
Simulation time 2222357666 ps
CPU time 4.64 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:09 PM PDT 24
Peak memory 216064 kb
Host smart-8c9c6032-faa9-4ba3-933a-561f759731fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733586783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1733586783
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3301367058
Short name T777
Test name
Test status
Simulation time 15248839 ps
CPU time 0.91 seconds
Started Aug 15 04:31:51 PM PDT 24
Finished Aug 15 04:31:52 PM PDT 24
Peak memory 206932 kb
Host smart-c6db91de-da8b-46bb-8c6f-80065c4c3e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301367058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3301367058
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.125427984
Short name T405
Test name
Test status
Simulation time 72145813 ps
CPU time 0.79 seconds
Started Aug 15 04:31:51 PM PDT 24
Finished Aug 15 04:31:52 PM PDT 24
Peak memory 205900 kb
Host smart-6d8bf437-4ffb-4c23-9c6c-a05bdab7c5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125427984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.125427984
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3797497031
Short name T519
Test name
Test status
Simulation time 770300574 ps
CPU time 6.17 seconds
Started Aug 15 04:31:53 PM PDT 24
Finished Aug 15 04:31:59 PM PDT 24
Peak memory 232664 kb
Host smart-b16d2d8e-4ad4-497c-b09d-c4889e8e6e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797497031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3797497031
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.115366651
Short name T536
Test name
Test status
Simulation time 16599750 ps
CPU time 0.73 seconds
Started Aug 15 04:33:27 PM PDT 24
Finished Aug 15 04:33:28 PM PDT 24
Peak memory 205436 kb
Host smart-6dd67eb4-a064-4d52-b3a0-b2604e8d80f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115366651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.115366651
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1097108591
Short name T373
Test name
Test status
Simulation time 5404818561 ps
CPU time 11.41 seconds
Started Aug 15 04:33:24 PM PDT 24
Finished Aug 15 04:33:35 PM PDT 24
Peak memory 232716 kb
Host smart-ee5ba11c-efff-4c07-94c7-a957c45d7c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097108591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1097108591
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3649073787
Short name T749
Test name
Test status
Simulation time 22912693 ps
CPU time 0.79 seconds
Started Aug 15 04:33:19 PM PDT 24
Finished Aug 15 04:33:20 PM PDT 24
Peak memory 206404 kb
Host smart-55d472c3-c93e-4212-a323-f906ab9a3fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649073787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3649073787
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3003427853
Short name T243
Test name
Test status
Simulation time 5375904863 ps
CPU time 25.11 seconds
Started Aug 15 04:33:25 PM PDT 24
Finished Aug 15 04:33:50 PM PDT 24
Peak memory 239304 kb
Host smart-be750744-43cd-4d33-9dc4-3a8ad6af4e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003427853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3003427853
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2751314472
Short name T306
Test name
Test status
Simulation time 3035328466 ps
CPU time 60.64 seconds
Started Aug 15 04:33:25 PM PDT 24
Finished Aug 15 04:34:26 PM PDT 24
Peak memory 250248 kb
Host smart-4ae17c73-f5ea-4de6-8670-bef0cf99e494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751314472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2751314472
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1838702836
Short name T441
Test name
Test status
Simulation time 39409142733 ps
CPU time 388.46 seconds
Started Aug 15 04:33:27 PM PDT 24
Finished Aug 15 04:39:56 PM PDT 24
Peak memory 270012 kb
Host smart-fcddd1bd-8b37-4a4a-b6c9-85494b5a0a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838702836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1838702836
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2308229339
Short name T1
Test name
Test status
Simulation time 597302769 ps
CPU time 6.15 seconds
Started Aug 15 04:33:35 PM PDT 24
Finished Aug 15 04:33:42 PM PDT 24
Peak memory 224580 kb
Host smart-dddb9201-0297-461e-97bc-eba8c13a88da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308229339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2308229339
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1910980506
Short name T8
Test name
Test status
Simulation time 140063986096 ps
CPU time 254.6 seconds
Started Aug 15 04:33:27 PM PDT 24
Finished Aug 15 04:37:41 PM PDT 24
Peak memory 257128 kb
Host smart-a29a1710-e822-4d83-a1b0-35845ba4a33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910980506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1910980506
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1773651696
Short name T699
Test name
Test status
Simulation time 814502909 ps
CPU time 5.87 seconds
Started Aug 15 04:33:27 PM PDT 24
Finished Aug 15 04:33:34 PM PDT 24
Peak memory 232696 kb
Host smart-fc969494-01ae-4412-b35d-5421fca0c487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773651696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1773651696
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1685141183
Short name T239
Test name
Test status
Simulation time 1458692828 ps
CPU time 13.38 seconds
Started Aug 15 04:33:29 PM PDT 24
Finished Aug 15 04:33:43 PM PDT 24
Peak memory 232704 kb
Host smart-baed5104-8bc3-4005-9954-382fe31607d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685141183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1685141183
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1549914806
Short name T800
Test name
Test status
Simulation time 3703440752 ps
CPU time 11.03 seconds
Started Aug 15 04:33:28 PM PDT 24
Finished Aug 15 04:33:39 PM PDT 24
Peak memory 232680 kb
Host smart-c89a5dfa-2cf4-4d96-bbe9-8b18331c558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549914806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1549914806
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1147249754
Short name T432
Test name
Test status
Simulation time 53616490201 ps
CPU time 39.28 seconds
Started Aug 15 04:33:28 PM PDT 24
Finished Aug 15 04:34:08 PM PDT 24
Peak memory 233752 kb
Host smart-73961cd3-5113-4ab4-8b1f-63a4e45b7513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147249754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1147249754
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1542593525
Short name T1007
Test name
Test status
Simulation time 198156273 ps
CPU time 4.01 seconds
Started Aug 15 04:33:29 PM PDT 24
Finished Aug 15 04:33:33 PM PDT 24
Peak memory 220036 kb
Host smart-a9fd5ac6-a520-40e4-aa6e-a07853d35069
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1542593525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1542593525
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2833770594
Short name T137
Test name
Test status
Simulation time 362299974467 ps
CPU time 281.4 seconds
Started Aug 15 04:33:31 PM PDT 24
Finished Aug 15 04:38:12 PM PDT 24
Peak memory 252452 kb
Host smart-a9eb9c91-42cc-456e-8a65-2616365bead2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833770594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2833770594
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4281021161
Short name T643
Test name
Test status
Simulation time 8864076998 ps
CPU time 9.36 seconds
Started Aug 15 04:33:19 PM PDT 24
Finished Aug 15 04:33:29 PM PDT 24
Peak memory 216544 kb
Host smart-0a98522a-3a69-4468-9645-e39a5e2333f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281021161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4281021161
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1458932408
Short name T671
Test name
Test status
Simulation time 58602802 ps
CPU time 1.23 seconds
Started Aug 15 04:33:19 PM PDT 24
Finished Aug 15 04:33:21 PM PDT 24
Peak memory 207760 kb
Host smart-e9ea3130-a772-4c78-ace0-5f6986c7f847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458932408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1458932408
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.78768871
Short name T483
Test name
Test status
Simulation time 97112972 ps
CPU time 1.62 seconds
Started Aug 15 04:33:26 PM PDT 24
Finished Aug 15 04:33:27 PM PDT 24
Peak memory 216208 kb
Host smart-6392798d-9d43-40cf-b414-9745401659cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78768871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.78768871
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4041216397
Short name T878
Test name
Test status
Simulation time 272207199 ps
CPU time 0.85 seconds
Started Aug 15 04:33:22 PM PDT 24
Finished Aug 15 04:33:23 PM PDT 24
Peak memory 205892 kb
Host smart-11b0ac37-1a7d-4ac4-98d5-c421660118b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041216397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4041216397
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3149997970
Short name T827
Test name
Test status
Simulation time 66551116 ps
CPU time 2.4 seconds
Started Aug 15 04:33:28 PM PDT 24
Finished Aug 15 04:33:31 PM PDT 24
Peak memory 232656 kb
Host smart-e5ba7259-7e01-4c3f-a1ac-50cd7dd11bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149997970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3149997970
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3870046951
Short name T164
Test name
Test status
Simulation time 13026091 ps
CPU time 0.7 seconds
Started Aug 15 04:33:31 PM PDT 24
Finished Aug 15 04:33:32 PM PDT 24
Peak memory 205372 kb
Host smart-bffe6a11-708a-454d-b608-8d1bb5bcc7a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870046951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3870046951
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3220025555
Short name T241
Test name
Test status
Simulation time 99869073 ps
CPU time 2.65 seconds
Started Aug 15 04:33:27 PM PDT 24
Finished Aug 15 04:33:30 PM PDT 24
Peak memory 224452 kb
Host smart-5802d2ff-11d0-4afc-8190-9455d60ff52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220025555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3220025555
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1732259807
Short name T331
Test name
Test status
Simulation time 39121614 ps
CPU time 0.83 seconds
Started Aug 15 04:33:26 PM PDT 24
Finished Aug 15 04:33:27 PM PDT 24
Peak memory 206456 kb
Host smart-7eba9c55-0931-47a1-9040-11ee30e3d652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732259807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1732259807
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1571592173
Short name T215
Test name
Test status
Simulation time 13657491734 ps
CPU time 134.77 seconds
Started Aug 15 04:33:25 PM PDT 24
Finished Aug 15 04:35:40 PM PDT 24
Peak memory 254508 kb
Host smart-d3ba4642-9355-4272-9a5c-f051c853f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571592173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1571592173
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3215043552
Short name T221
Test name
Test status
Simulation time 186812708 ps
CPU time 3.78 seconds
Started Aug 15 04:33:25 PM PDT 24
Finished Aug 15 04:33:29 PM PDT 24
Peak memory 232724 kb
Host smart-abfa1f04-3650-4604-9656-04835f11a8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215043552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3215043552
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2071466527
Short name T267
Test name
Test status
Simulation time 9148180558 ps
CPU time 52.42 seconds
Started Aug 15 04:33:27 PM PDT 24
Finished Aug 15 04:34:19 PM PDT 24
Peak memory 254148 kb
Host smart-7294a5a8-ebde-407e-921a-312f73556213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071466527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2071466527
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.94475022
Short name T941
Test name
Test status
Simulation time 7113204853 ps
CPU time 16.21 seconds
Started Aug 15 04:33:29 PM PDT 24
Finished Aug 15 04:33:45 PM PDT 24
Peak memory 232756 kb
Host smart-2ea08915-b4d0-48fb-94be-503ca400d548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94475022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.94475022
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.751320250
Short name T79
Test name
Test status
Simulation time 11377183818 ps
CPU time 96.59 seconds
Started Aug 15 04:33:28 PM PDT 24
Finished Aug 15 04:35:05 PM PDT 24
Peak memory 232720 kb
Host smart-cf9d217d-7975-4ce3-9ed8-131f67a3a46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751320250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.751320250
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2697165487
Short name T736
Test name
Test status
Simulation time 217282672 ps
CPU time 4.22 seconds
Started Aug 15 04:33:30 PM PDT 24
Finished Aug 15 04:33:35 PM PDT 24
Peak memory 232712 kb
Host smart-0e3f1fbb-950a-47ad-835d-34f7053ff7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697165487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2697165487
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.628533691
Short name T623
Test name
Test status
Simulation time 249472696 ps
CPU time 3.36 seconds
Started Aug 15 04:33:27 PM PDT 24
Finished Aug 15 04:33:30 PM PDT 24
Peak memory 219592 kb
Host smart-fdd0f242-c896-4a68-9ee9-5b78c585566e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628533691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.628533691
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1832582813
Short name T845
Test name
Test status
Simulation time 4293072384 ps
CPU time 15.85 seconds
Started Aug 15 04:33:25 PM PDT 24
Finished Aug 15 04:33:41 PM PDT 24
Peak memory 220040 kb
Host smart-dc17fe17-1afd-4d2a-b88d-52b3f56f21ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1832582813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1832582813
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2576592773
Short name T180
Test name
Test status
Simulation time 27619128583 ps
CPU time 325.38 seconds
Started Aug 15 04:33:28 PM PDT 24
Finished Aug 15 04:38:54 PM PDT 24
Peak memory 284884 kb
Host smart-1e1d45e4-90a5-4d3f-8d47-2a8ba571403b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576592773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2576592773
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3517208811
Short name T981
Test name
Test status
Simulation time 17493564 ps
CPU time 0.74 seconds
Started Aug 15 04:33:26 PM PDT 24
Finished Aug 15 04:33:27 PM PDT 24
Peak memory 205524 kb
Host smart-4f05d90c-1995-4101-9700-89faee5a7d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517208811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3517208811
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3334260708
Short name T34
Test name
Test status
Simulation time 3478154071 ps
CPU time 11.05 seconds
Started Aug 15 04:33:29 PM PDT 24
Finished Aug 15 04:33:40 PM PDT 24
Peak memory 216464 kb
Host smart-2689c323-0a90-499f-8a86-a3690fb419ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334260708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3334260708
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3564816991
Short name T500
Test name
Test status
Simulation time 248522581 ps
CPU time 2.51 seconds
Started Aug 15 04:33:35 PM PDT 24
Finished Aug 15 04:33:38 PM PDT 24
Peak memory 216408 kb
Host smart-9ed3946a-a709-40e2-9aa0-043547eba6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564816991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3564816991
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3977287339
Short name T534
Test name
Test status
Simulation time 15440160 ps
CPU time 0.71 seconds
Started Aug 15 04:33:24 PM PDT 24
Finished Aug 15 04:33:25 PM PDT 24
Peak memory 205964 kb
Host smart-6cdb7713-89cb-41da-ac70-a2fc883ae3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977287339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3977287339
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2212381131
Short name T259
Test name
Test status
Simulation time 1087991623 ps
CPU time 6.02 seconds
Started Aug 15 04:33:31 PM PDT 24
Finished Aug 15 04:33:38 PM PDT 24
Peak memory 233712 kb
Host smart-d7ecb1b8-6347-4893-ae1f-66037845335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212381131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2212381131
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1901087209
Short name T902
Test name
Test status
Simulation time 13641345 ps
CPU time 0.7 seconds
Started Aug 15 04:33:34 PM PDT 24
Finished Aug 15 04:33:34 PM PDT 24
Peak memory 205708 kb
Host smart-de6f270c-7480-48fb-84e9-2d5efa50a50d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901087209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1901087209
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1635456264
Short name T798
Test name
Test status
Simulation time 938041935 ps
CPU time 3.83 seconds
Started Aug 15 04:33:32 PM PDT 24
Finished Aug 15 04:33:36 PM PDT 24
Peak memory 232668 kb
Host smart-7f3becc0-3dcd-4775-a790-cd76056f957c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635456264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1635456264
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.607491100
Short name T360
Test name
Test status
Simulation time 20332546 ps
CPU time 0.78 seconds
Started Aug 15 04:33:29 PM PDT 24
Finished Aug 15 04:33:30 PM PDT 24
Peak memory 205384 kb
Host smart-d237acac-53a2-4ec1-a120-95bafb74adcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607491100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.607491100
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.562268089
Short name T738
Test name
Test status
Simulation time 11420534956 ps
CPU time 120.81 seconds
Started Aug 15 04:33:32 PM PDT 24
Finished Aug 15 04:35:33 PM PDT 24
Peak memory 249236 kb
Host smart-12e71bad-7a7d-41ff-8c94-2d3908eb8c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562268089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.562268089
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1034192618
Short name T863
Test name
Test status
Simulation time 201457637042 ps
CPU time 462.85 seconds
Started Aug 15 04:33:32 PM PDT 24
Finished Aug 15 04:41:15 PM PDT 24
Peak memory 263924 kb
Host smart-4b043360-fe72-4739-ae06-b1996ea47fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034192618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1034192618
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1847515842
Short name T620
Test name
Test status
Simulation time 7116895696 ps
CPU time 36.99 seconds
Started Aug 15 04:33:36 PM PDT 24
Finished Aug 15 04:34:13 PM PDT 24
Peak memory 235920 kb
Host smart-637aba6a-f034-41f1-a4bd-fcdd3346461b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847515842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1847515842
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.424856555
Short name T619
Test name
Test status
Simulation time 1871669243 ps
CPU time 7.31 seconds
Started Aug 15 04:33:38 PM PDT 24
Finished Aug 15 04:33:45 PM PDT 24
Peak memory 239804 kb
Host smart-b226e9da-3042-478d-b60e-c8ef2f75403c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424856555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.424856555
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3953688324
Short name T76
Test name
Test status
Simulation time 50930010 ps
CPU time 0.94 seconds
Started Aug 15 04:33:37 PM PDT 24
Finished Aug 15 04:33:38 PM PDT 24
Peak memory 215904 kb
Host smart-325f4ce5-7f1f-4d79-aa9b-a43f94eae18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953688324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3953688324
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3722239497
Short name T702
Test name
Test status
Simulation time 764401529 ps
CPU time 9.45 seconds
Started Aug 15 04:33:24 PM PDT 24
Finished Aug 15 04:33:33 PM PDT 24
Peak memory 232688 kb
Host smart-ad837f38-aba4-4cc7-b3f5-24d4647b8cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722239497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3722239497
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.657386663
Short name T233
Test name
Test status
Simulation time 22845866225 ps
CPU time 14.14 seconds
Started Aug 15 04:33:26 PM PDT 24
Finished Aug 15 04:33:41 PM PDT 24
Peak memory 239756 kb
Host smart-ad3fa91a-938b-4983-b08c-dba2f444cc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657386663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.657386663
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2479580994
Short name T756
Test name
Test status
Simulation time 1206951448 ps
CPU time 5.18 seconds
Started Aug 15 04:33:29 PM PDT 24
Finished Aug 15 04:33:34 PM PDT 24
Peak memory 232692 kb
Host smart-e96abca5-88df-464c-9e79-77b2ef268833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479580994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2479580994
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3528396824
Short name T57
Test name
Test status
Simulation time 550301413 ps
CPU time 5.31 seconds
Started Aug 15 04:33:26 PM PDT 24
Finished Aug 15 04:33:31 PM PDT 24
Peak memory 224440 kb
Host smart-0cb433d8-a281-4557-863c-62b376a9a855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528396824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3528396824
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1408071642
Short name T564
Test name
Test status
Simulation time 536291210 ps
CPU time 4.3 seconds
Started Aug 15 04:33:35 PM PDT 24
Finished Aug 15 04:33:40 PM PDT 24
Peak memory 220476 kb
Host smart-23256488-12f8-42e8-bcfe-ec7981b729d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1408071642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1408071642
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4077989752
Short name T721
Test name
Test status
Simulation time 228553936 ps
CPU time 1.06 seconds
Started Aug 15 04:33:39 PM PDT 24
Finished Aug 15 04:33:41 PM PDT 24
Peak memory 206708 kb
Host smart-c158e884-ce5f-4695-9941-ba27d554188e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077989752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4077989752
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2051084146
Short name T895
Test name
Test status
Simulation time 8411948050 ps
CPU time 22.43 seconds
Started Aug 15 04:33:26 PM PDT 24
Finished Aug 15 04:33:49 PM PDT 24
Peak memory 216452 kb
Host smart-30029ab9-4ec6-4b65-aa10-723bf1099230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051084146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2051084146
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.578441334
Short name T460
Test name
Test status
Simulation time 3603164514 ps
CPU time 9.69 seconds
Started Aug 15 04:33:25 PM PDT 24
Finished Aug 15 04:33:35 PM PDT 24
Peak memory 216316 kb
Host smart-89fbd8d8-b784-4937-9a04-99dca722370c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578441334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.578441334
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4243268313
Short name T595
Test name
Test status
Simulation time 126992219 ps
CPU time 2.24 seconds
Started Aug 15 04:33:27 PM PDT 24
Finished Aug 15 04:33:29 PM PDT 24
Peak memory 216268 kb
Host smart-8485ff7e-3b14-472d-a927-ee134912fe8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243268313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4243268313
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.17367024
Short name T428
Test name
Test status
Simulation time 21820862 ps
CPU time 0.71 seconds
Started Aug 15 04:33:24 PM PDT 24
Finished Aug 15 04:33:25 PM PDT 24
Peak memory 205524 kb
Host smart-a39040bd-df98-4531-b443-e45d9e4e5162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17367024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.17367024
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1358063107
Short name T62
Test name
Test status
Simulation time 1741377380 ps
CPU time 5.72 seconds
Started Aug 15 04:33:31 PM PDT 24
Finished Aug 15 04:33:37 PM PDT 24
Peak memory 224408 kb
Host smart-f10e2681-5005-4ddf-8bba-2fc214eadf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358063107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1358063107
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.953442050
Short name T883
Test name
Test status
Simulation time 15377737 ps
CPU time 0.74 seconds
Started Aug 15 04:33:34 PM PDT 24
Finished Aug 15 04:33:35 PM PDT 24
Peak memory 205352 kb
Host smart-f749af66-b6b3-4858-a40f-3a7042d30689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953442050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.953442050
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4130633480
Short name T803
Test name
Test status
Simulation time 71094538 ps
CPU time 2.57 seconds
Started Aug 15 04:33:31 PM PDT 24
Finished Aug 15 04:33:34 PM PDT 24
Peak memory 232660 kb
Host smart-7b6a5dae-aa30-43c4-b4d2-25c43169a7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130633480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4130633480
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1474640155
Short name T338
Test name
Test status
Simulation time 18794020 ps
CPU time 0.82 seconds
Started Aug 15 04:33:31 PM PDT 24
Finished Aug 15 04:33:32 PM PDT 24
Peak memory 206152 kb
Host smart-801ffed9-d928-4193-9cf8-1137207e0620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474640155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1474640155
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.908333879
Short name T486
Test name
Test status
Simulation time 27900243892 ps
CPU time 18.43 seconds
Started Aug 15 04:33:33 PM PDT 24
Finished Aug 15 04:33:52 PM PDT 24
Peak memory 224520 kb
Host smart-344edd8e-f987-480d-96af-fe222d45395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908333879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.908333879
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.119776745
Short name T310
Test name
Test status
Simulation time 2060927029 ps
CPU time 9.89 seconds
Started Aug 15 04:33:34 PM PDT 24
Finished Aug 15 04:33:44 PM PDT 24
Peak memory 217740 kb
Host smart-0f80eabf-e4d2-421b-96f6-408c9a1fdfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119776745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.119776745
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3153257605
Short name T412
Test name
Test status
Simulation time 266280207546 ps
CPU time 363.85 seconds
Started Aug 15 04:33:34 PM PDT 24
Finished Aug 15 04:39:38 PM PDT 24
Peak memory 253052 kb
Host smart-7987315a-1c36-4047-9014-fdf23140aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153257605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3153257605
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.165995606
Short name T6
Test name
Test status
Simulation time 355174839 ps
CPU time 3.72 seconds
Started Aug 15 04:33:32 PM PDT 24
Finished Aug 15 04:33:36 PM PDT 24
Peak memory 224488 kb
Host smart-2fd239ce-c545-4d1f-a76f-1ea30b9df8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165995606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.165995606
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.4101731031
Short name T866
Test name
Test status
Simulation time 49858354 ps
CPU time 0.75 seconds
Started Aug 15 04:33:31 PM PDT 24
Finished Aug 15 04:33:32 PM PDT 24
Peak memory 215668 kb
Host smart-7ee717a6-3291-45d9-af46-5decc30d4144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101731031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.4101731031
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1393503020
Short name T961
Test name
Test status
Simulation time 567633063 ps
CPU time 4.73 seconds
Started Aug 15 04:33:32 PM PDT 24
Finished Aug 15 04:33:37 PM PDT 24
Peak memory 230216 kb
Host smart-aa8676a0-80ba-4184-965e-78083839adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393503020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1393503020
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.722579123
Short name T218
Test name
Test status
Simulation time 3158853544 ps
CPU time 17.21 seconds
Started Aug 15 04:33:37 PM PDT 24
Finished Aug 15 04:33:54 PM PDT 24
Peak memory 224544 kb
Host smart-32809170-3de9-45ed-9a63-bf47d5a0492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722579123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.722579123
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1123268206
Short name T763
Test name
Test status
Simulation time 106347984 ps
CPU time 2.68 seconds
Started Aug 15 04:33:33 PM PDT 24
Finished Aug 15 04:33:36 PM PDT 24
Peak memory 232676 kb
Host smart-dfaf4751-ed45-45eb-a94a-813eb90ba823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123268206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1123268206
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.603217877
Short name T78
Test name
Test status
Simulation time 4843994585 ps
CPU time 10.52 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:53 PM PDT 24
Peak memory 240620 kb
Host smart-6f4ea066-45ea-4523-888f-2a848e6e0c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603217877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.603217877
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2209709953
Short name T366
Test name
Test status
Simulation time 144029665 ps
CPU time 4.17 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:46 PM PDT 24
Peak memory 220284 kb
Host smart-5eea1f13-2780-4367-962f-12bb79e7a290
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2209709953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2209709953
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2262658311
Short name T727
Test name
Test status
Simulation time 51595565 ps
CPU time 1.04 seconds
Started Aug 15 04:33:32 PM PDT 24
Finished Aug 15 04:33:33 PM PDT 24
Peak memory 206868 kb
Host smart-7b947ad2-6781-4d96-9965-e68a0674261c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262658311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2262658311
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.814907386
Short name T865
Test name
Test status
Simulation time 7174111484 ps
CPU time 24.03 seconds
Started Aug 15 04:33:32 PM PDT 24
Finished Aug 15 04:33:56 PM PDT 24
Peak memory 216748 kb
Host smart-f2cdb65c-54f1-4166-b36f-e4ffe62d3893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814907386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.814907386
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3556982545
Short name T515
Test name
Test status
Simulation time 312964404 ps
CPU time 3.01 seconds
Started Aug 15 04:33:34 PM PDT 24
Finished Aug 15 04:33:37 PM PDT 24
Peak memory 216232 kb
Host smart-4e0761bd-842a-4b38-aaf1-ed041ed5a032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556982545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3556982545
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2685973141
Short name T609
Test name
Test status
Simulation time 180303074 ps
CPU time 2.05 seconds
Started Aug 15 04:33:31 PM PDT 24
Finished Aug 15 04:33:34 PM PDT 24
Peak memory 216260 kb
Host smart-238ddb3d-6a77-49fa-a11d-880f844123e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685973141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2685973141
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1299244378
Short name T881
Test name
Test status
Simulation time 63506772 ps
CPU time 0.85 seconds
Started Aug 15 04:33:32 PM PDT 24
Finished Aug 15 04:33:33 PM PDT 24
Peak memory 205944 kb
Host smart-2a687138-ce5e-4f32-a06e-d50bafafd631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299244378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1299244378
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1523785457
Short name T458
Test name
Test status
Simulation time 978030031 ps
CPU time 4.07 seconds
Started Aug 15 04:33:31 PM PDT 24
Finished Aug 15 04:33:35 PM PDT 24
Peak memory 232476 kb
Host smart-5f9390f9-89f0-43b9-89a8-65557ea40c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523785457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1523785457
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1751635990
Short name T853
Test name
Test status
Simulation time 10243229 ps
CPU time 0.69 seconds
Started Aug 15 04:33:33 PM PDT 24
Finished Aug 15 04:33:34 PM PDT 24
Peak memory 204796 kb
Host smart-2bea8248-4c09-41d5-8c22-b487d84a1bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751635990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1751635990
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2320389855
Short name T349
Test name
Test status
Simulation time 279942461 ps
CPU time 3.79 seconds
Started Aug 15 04:33:40 PM PDT 24
Finished Aug 15 04:33:44 PM PDT 24
Peak memory 224480 kb
Host smart-308d1fb5-0fb2-4eba-9fcf-17939ed46cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320389855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2320389855
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3899593293
Short name T876
Test name
Test status
Simulation time 42901075 ps
CPU time 0.76 seconds
Started Aug 15 04:33:38 PM PDT 24
Finished Aug 15 04:33:38 PM PDT 24
Peak memory 205380 kb
Host smart-ca9dd857-b136-4217-a021-58e1644545ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899593293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3899593293
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.515916339
Short name T630
Test name
Test status
Simulation time 1034802178 ps
CPU time 14.29 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:56 PM PDT 24
Peak memory 234728 kb
Host smart-6ece805f-440e-4ea1-a153-c1b5875c39b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515916339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.515916339
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1639547520
Short name T279
Test name
Test status
Simulation time 13133106670 ps
CPU time 115.25 seconds
Started Aug 15 04:33:36 PM PDT 24
Finished Aug 15 04:35:31 PM PDT 24
Peak memory 254768 kb
Host smart-460322b1-ac1a-44ef-87fd-7cef6a23083d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639547520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1639547520
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3712928797
Short name T781
Test name
Test status
Simulation time 10701926040 ps
CPU time 107.12 seconds
Started Aug 15 04:33:53 PM PDT 24
Finished Aug 15 04:35:41 PM PDT 24
Peak memory 254392 kb
Host smart-1fdae39d-f4d9-4689-ba27-b8686b3736d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712928797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3712928797
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1289411388
Short name T943
Test name
Test status
Simulation time 7602717695 ps
CPU time 27.35 seconds
Started Aug 15 04:33:36 PM PDT 24
Finished Aug 15 04:34:03 PM PDT 24
Peak memory 224492 kb
Host smart-c0da749a-91a9-4b0c-8f80-b57433eb87f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289411388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1289411388
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1792744939
Short name T922
Test name
Test status
Simulation time 169040406971 ps
CPU time 256.75 seconds
Started Aug 15 04:33:35 PM PDT 24
Finished Aug 15 04:37:52 PM PDT 24
Peak memory 267560 kb
Host smart-83653c16-7f75-45d9-8c7d-4c758d7ebb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792744939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1792744939
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1046818460
Short name T648
Test name
Test status
Simulation time 1553338596 ps
CPU time 9.09 seconds
Started Aug 15 04:33:51 PM PDT 24
Finished Aug 15 04:34:00 PM PDT 24
Peak memory 224416 kb
Host smart-2f62a804-f058-47f4-82e3-d7a3f6881403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046818460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1046818460
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.4111760150
Short name T341
Test name
Test status
Simulation time 34519366 ps
CPU time 2.39 seconds
Started Aug 15 04:33:34 PM PDT 24
Finished Aug 15 04:33:37 PM PDT 24
Peak memory 232392 kb
Host smart-2267e75e-d3f8-4c16-af40-5bf6b531f404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111760150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.4111760150
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2594737268
Short name T799
Test name
Test status
Simulation time 366649848 ps
CPU time 2.65 seconds
Started Aug 15 04:33:37 PM PDT 24
Finished Aug 15 04:33:44 PM PDT 24
Peak memory 224492 kb
Host smart-6105e1a8-3977-4011-bc4f-fbbfde0d7ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594737268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2594737268
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3669364635
Short name T771
Test name
Test status
Simulation time 4772884694 ps
CPU time 13.72 seconds
Started Aug 15 04:33:34 PM PDT 24
Finished Aug 15 04:33:48 PM PDT 24
Peak memory 224532 kb
Host smart-91e88698-c536-4947-87d0-40d5285e949d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669364635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3669364635
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2715987152
Short name T461
Test name
Test status
Simulation time 1961078598 ps
CPU time 9.98 seconds
Started Aug 15 04:33:36 PM PDT 24
Finished Aug 15 04:33:46 PM PDT 24
Peak memory 220424 kb
Host smart-566df153-4b24-49ad-a5f5-fd66732f4592
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2715987152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2715987152
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3128039908
Short name T936
Test name
Test status
Simulation time 60705596853 ps
CPU time 146.72 seconds
Started Aug 15 04:33:35 PM PDT 24
Finished Aug 15 04:36:02 PM PDT 24
Peak memory 249244 kb
Host smart-59ce8025-3d5c-4409-b7ba-7ea4acfa930b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128039908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3128039908
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3576020398
Short name T161
Test name
Test status
Simulation time 449218677 ps
CPU time 5.32 seconds
Started Aug 15 04:33:35 PM PDT 24
Finished Aug 15 04:33:41 PM PDT 24
Peak memory 216528 kb
Host smart-39b79e04-11e9-41bf-b48b-833df663dd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576020398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3576020398
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2049753989
Short name T395
Test name
Test status
Simulation time 28576965 ps
CPU time 0.68 seconds
Started Aug 15 04:33:39 PM PDT 24
Finished Aug 15 04:33:40 PM PDT 24
Peak memory 205548 kb
Host smart-5d5a46ed-194a-4c28-a3ea-feca9779d667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049753989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2049753989
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2197644053
Short name T324
Test name
Test status
Simulation time 72104916 ps
CPU time 0.99 seconds
Started Aug 15 04:33:36 PM PDT 24
Finished Aug 15 04:33:37 PM PDT 24
Peak memory 207928 kb
Host smart-5ac49ac6-63b9-44f8-910a-a9016cd090f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197644053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2197644053
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2570926905
Short name T1005
Test name
Test status
Simulation time 103914342 ps
CPU time 1.01 seconds
Started Aug 15 04:33:33 PM PDT 24
Finished Aug 15 04:33:34 PM PDT 24
Peak memory 206968 kb
Host smart-c6aea342-e8bd-4045-be4d-132e1d5ba75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570926905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2570926905
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4054058953
Short name T782
Test name
Test status
Simulation time 9130173777 ps
CPU time 26.1 seconds
Started Aug 15 04:33:34 PM PDT 24
Finished Aug 15 04:34:01 PM PDT 24
Peak memory 232784 kb
Host smart-66d8c1de-09d2-4967-ba86-8377609f09b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054058953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4054058953
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1929905204
Short name T683
Test name
Test status
Simulation time 16285251 ps
CPU time 0.77 seconds
Started Aug 15 04:33:53 PM PDT 24
Finished Aug 15 04:33:54 PM PDT 24
Peak memory 205328 kb
Host smart-4a152559-825e-48f6-ba4a-7232b5c1193b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929905204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1929905204
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.625638055
Short name T992
Test name
Test status
Simulation time 114758992 ps
CPU time 2.55 seconds
Started Aug 15 04:33:37 PM PDT 24
Finished Aug 15 04:33:40 PM PDT 24
Peak memory 232300 kb
Host smart-056b3bb4-f06f-4acb-9484-992c28870613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625638055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.625638055
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3463970205
Short name T869
Test name
Test status
Simulation time 22318655 ps
CPU time 0.8 seconds
Started Aug 15 04:33:37 PM PDT 24
Finished Aug 15 04:33:38 PM PDT 24
Peak memory 206432 kb
Host smart-a654b360-2957-4f97-8f8e-e6aadf328b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463970205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3463970205
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2906948254
Short name T204
Test name
Test status
Simulation time 15316489825 ps
CPU time 114.79 seconds
Started Aug 15 04:33:56 PM PDT 24
Finished Aug 15 04:35:50 PM PDT 24
Peak memory 257000 kb
Host smart-018a0bad-96fc-49d6-a565-73c00a685e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906948254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2906948254
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1361634517
Short name T659
Test name
Test status
Simulation time 26677651183 ps
CPU time 234.42 seconds
Started Aug 15 04:33:39 PM PDT 24
Finished Aug 15 04:37:34 PM PDT 24
Peak memory 257420 kb
Host smart-0bfaf137-3d35-4b17-858d-c4a77f0630c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361634517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1361634517
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.659577126
Short name T635
Test name
Test status
Simulation time 1130067243 ps
CPU time 3.76 seconds
Started Aug 15 04:33:40 PM PDT 24
Finished Aug 15 04:33:44 PM PDT 24
Peak memory 232692 kb
Host smart-f06ab67a-eaba-43be-8295-816b5430ce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659577126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.659577126
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3776944782
Short name T48
Test name
Test status
Simulation time 10630822318 ps
CPU time 76.93 seconds
Started Aug 15 04:33:37 PM PDT 24
Finished Aug 15 04:34:54 PM PDT 24
Peak memory 250144 kb
Host smart-aa3812f9-cdee-468e-97a9-a0dd8073502d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776944782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3776944782
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2485206990
Short name T723
Test name
Test status
Simulation time 8855494287 ps
CPU time 12.45 seconds
Started Aug 15 04:33:34 PM PDT 24
Finished Aug 15 04:33:47 PM PDT 24
Peak memory 224592 kb
Host smart-08c4b69e-aeeb-46ad-8b26-78f6f66ca23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485206990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2485206990
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3367703086
Short name T758
Test name
Test status
Simulation time 1627376955 ps
CPU time 9.88 seconds
Started Aug 15 04:33:52 PM PDT 24
Finished Aug 15 04:34:02 PM PDT 24
Peak memory 233744 kb
Host smart-35fb3437-c405-421f-ac01-93dd1f9d309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367703086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3367703086
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1533998122
Short name T245
Test name
Test status
Simulation time 380553485 ps
CPU time 5.16 seconds
Started Aug 15 04:33:54 PM PDT 24
Finished Aug 15 04:34:00 PM PDT 24
Peak memory 232704 kb
Host smart-fafd3b22-0846-4b0e-b743-13d24371af26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533998122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1533998122
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.63457782
Short name T816
Test name
Test status
Simulation time 5141424746 ps
CPU time 7.47 seconds
Started Aug 15 04:33:34 PM PDT 24
Finished Aug 15 04:33:42 PM PDT 24
Peak memory 232720 kb
Host smart-06dc4a4b-f1a8-432a-8f05-33d845a6c45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63457782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.63457782
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.398105809
Short name T658
Test name
Test status
Simulation time 3409138102 ps
CPU time 7.98 seconds
Started Aug 15 04:33:41 PM PDT 24
Finished Aug 15 04:33:49 PM PDT 24
Peak memory 222056 kb
Host smart-8a7ce18e-456f-41e6-8563-2fddfb1decd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=398105809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.398105809
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2807690686
Short name T586
Test name
Test status
Simulation time 1896054478 ps
CPU time 22.76 seconds
Started Aug 15 04:33:43 PM PDT 24
Finished Aug 15 04:34:06 PM PDT 24
Peak memory 216360 kb
Host smart-6521fe4a-f8a1-452f-8958-1cc8eed48732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807690686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2807690686
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1093513308
Short name T790
Test name
Test status
Simulation time 879684974 ps
CPU time 3.89 seconds
Started Aug 15 04:33:40 PM PDT 24
Finished Aug 15 04:33:45 PM PDT 24
Peak memory 216276 kb
Host smart-a7591514-98bf-4a9d-83b6-b6d7dd8f95ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093513308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1093513308
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2885422889
Short name T490
Test name
Test status
Simulation time 157857003 ps
CPU time 1.17 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:43 PM PDT 24
Peak memory 208024 kb
Host smart-d1266fb2-8ed9-49e7-b0d8-77d798bac402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885422889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2885422889
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3306970164
Short name T885
Test name
Test status
Simulation time 139188061 ps
CPU time 1.01 seconds
Started Aug 15 04:33:39 PM PDT 24
Finished Aug 15 04:33:40 PM PDT 24
Peak memory 206984 kb
Host smart-6cbc82b4-633e-46ca-a469-8ed10756d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306970164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3306970164
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2438525486
Short name T399
Test name
Test status
Simulation time 1829239322 ps
CPU time 7.15 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:50 PM PDT 24
Peak memory 224480 kb
Host smart-631f9125-f59f-452e-a2d0-5d114ca98d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438525486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2438525486
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1007566852
Short name T709
Test name
Test status
Simulation time 48661895 ps
CPU time 0.73 seconds
Started Aug 15 04:33:41 PM PDT 24
Finished Aug 15 04:33:41 PM PDT 24
Peak memory 205704 kb
Host smart-7ca830bf-597f-4e99-a0ed-4b91b4a2c7f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007566852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1007566852
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.934294778
Short name T404
Test name
Test status
Simulation time 1350848546 ps
CPU time 3.69 seconds
Started Aug 15 04:33:45 PM PDT 24
Finished Aug 15 04:33:48 PM PDT 24
Peak memory 232632 kb
Host smart-56d8c49a-851e-479c-bf3a-5ec6b21e2864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934294778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.934294778
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1760846784
Short name T579
Test name
Test status
Simulation time 16666906 ps
CPU time 0.77 seconds
Started Aug 15 04:33:56 PM PDT 24
Finished Aug 15 04:33:56 PM PDT 24
Peak memory 206776 kb
Host smart-a62a77b0-d27e-4a3b-8950-a347ad147830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760846784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1760846784
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.184515910
Short name T543
Test name
Test status
Simulation time 4366257865 ps
CPU time 11.09 seconds
Started Aug 15 04:33:41 PM PDT 24
Finished Aug 15 04:33:52 PM PDT 24
Peak memory 224564 kb
Host smart-44c6142d-2552-4749-8b79-b75701be3671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184515910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.184515910
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.147064280
Short name T263
Test name
Test status
Simulation time 8491660227 ps
CPU time 71.04 seconds
Started Aug 15 04:33:43 PM PDT 24
Finished Aug 15 04:34:55 PM PDT 24
Peak memory 232784 kb
Host smart-49efdff1-50f3-4992-948c-c1b7e9ff824d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147064280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.147064280
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1753744772
Short name T303
Test name
Test status
Simulation time 5912995767 ps
CPU time 28.94 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:34:11 PM PDT 24
Peak memory 232776 kb
Host smart-6f7f4105-3f01-429e-9f1a-c8482f9eb4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753744772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1753744772
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3528447392
Short name T301
Test name
Test status
Simulation time 195226275 ps
CPU time 6.98 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:49 PM PDT 24
Peak memory 232736 kb
Host smart-ef56e106-b291-43ab-9a0f-62b49d39dc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528447392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3528447392
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.390038058
Short name T186
Test name
Test status
Simulation time 11758367688 ps
CPU time 36.53 seconds
Started Aug 15 04:33:39 PM PDT 24
Finished Aug 15 04:34:16 PM PDT 24
Peak memory 237160 kb
Host smart-7988f6be-0a3b-47a9-9747-3a788b656266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390038058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds
.390038058
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2588423600
Short name T185
Test name
Test status
Simulation time 2488631462 ps
CPU time 17.16 seconds
Started Aug 15 04:33:40 PM PDT 24
Finished Aug 15 04:33:58 PM PDT 24
Peak memory 232812 kb
Host smart-10f83f51-5168-4cf5-a779-157268f30b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588423600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2588423600
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.24403907
Short name T823
Test name
Test status
Simulation time 701772724 ps
CPU time 17.35 seconds
Started Aug 15 04:33:54 PM PDT 24
Finished Aug 15 04:34:12 PM PDT 24
Peak memory 239920 kb
Host smart-563b1f57-6df9-433b-996b-dbad0b0ac6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24403907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.24403907
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1237540166
Short name T1011
Test name
Test status
Simulation time 5374806324 ps
CPU time 16.76 seconds
Started Aug 15 04:33:38 PM PDT 24
Finished Aug 15 04:33:55 PM PDT 24
Peak memory 238124 kb
Host smart-f6934dd4-f034-420a-988a-0a8d34c93698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237540166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1237540166
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2889499328
Short name T776
Test name
Test status
Simulation time 2200985185 ps
CPU time 7.65 seconds
Started Aug 15 04:33:38 PM PDT 24
Finished Aug 15 04:33:45 PM PDT 24
Peak memory 232676 kb
Host smart-6d4ddc5c-4335-4283-80cb-5615fc22651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889499328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2889499328
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1816751814
Short name T359
Test name
Test status
Simulation time 709717447 ps
CPU time 4.4 seconds
Started Aug 15 04:33:45 PM PDT 24
Finished Aug 15 04:33:49 PM PDT 24
Peak memory 218664 kb
Host smart-e5b123b0-27d2-4e49-ad87-9be1e005b33b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1816751814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1816751814
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1246441603
Short name T805
Test name
Test status
Simulation time 10710147909 ps
CPU time 55.71 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:34:38 PM PDT 24
Peak memory 249672 kb
Host smart-655b0467-af7a-4b61-bf9e-49232142996a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246441603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1246441603
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3503659283
Short name T358
Test name
Test status
Simulation time 503518166 ps
CPU time 4.56 seconds
Started Aug 15 04:33:41 PM PDT 24
Finished Aug 15 04:33:46 PM PDT 24
Peak memory 216372 kb
Host smart-01c1342f-a496-4697-9178-41e8840fdda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503659283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3503659283
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2240181498
Short name T367
Test name
Test status
Simulation time 22959011293 ps
CPU time 21.99 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:34:04 PM PDT 24
Peak memory 216280 kb
Host smart-60b88844-634a-475e-a87b-e460e41c07bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240181498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2240181498
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3984703915
Short name T309
Test name
Test status
Simulation time 264127381 ps
CPU time 4.89 seconds
Started Aug 15 04:33:54 PM PDT 24
Finished Aug 15 04:33:59 PM PDT 24
Peak memory 216348 kb
Host smart-fc04ea14-567a-40b6-931e-9bb783ebdcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984703915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3984703915
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3007200730
Short name T382
Test name
Test status
Simulation time 92244706 ps
CPU time 0.77 seconds
Started Aug 15 04:33:47 PM PDT 24
Finished Aug 15 04:33:48 PM PDT 24
Peak memory 205888 kb
Host smart-171189ac-bc3e-4e66-8af2-4c098472febc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007200730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3007200730
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1614712949
Short name T612
Test name
Test status
Simulation time 11787429750 ps
CPU time 18.05 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:34:00 PM PDT 24
Peak memory 232748 kb
Host smart-65324554-3734-4b2a-8d28-cf842d7199c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614712949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1614712949
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1930912759
Short name T668
Test name
Test status
Simulation time 12125215 ps
CPU time 0.73 seconds
Started Aug 15 04:33:43 PM PDT 24
Finished Aug 15 04:33:44 PM PDT 24
Peak memory 205440 kb
Host smart-a5424e8d-c4a8-49a1-89d5-c5a450521afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930912759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1930912759
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.389858230
Short name T824
Test name
Test status
Simulation time 216380826 ps
CPU time 2.44 seconds
Started Aug 15 04:33:41 PM PDT 24
Finished Aug 15 04:33:43 PM PDT 24
Peak memory 232768 kb
Host smart-1163b1db-472f-469e-9ad6-4f460dc46332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389858230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.389858230
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3173104069
Short name T879
Test name
Test status
Simulation time 15141370 ps
CPU time 0.79 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:43 PM PDT 24
Peak memory 206396 kb
Host smart-04618c2f-39ac-4515-8b26-4117f652013a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173104069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3173104069
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2429208706
Short name T128
Test name
Test status
Simulation time 148223893351 ps
CPU time 783.17 seconds
Started Aug 15 04:33:41 PM PDT 24
Finished Aug 15 04:46:44 PM PDT 24
Peak memory 264824 kb
Host smart-df193af0-d1ad-411c-92bf-34ce4393aebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429208706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2429208706
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.843755619
Short name T469
Test name
Test status
Simulation time 18842576612 ps
CPU time 49.48 seconds
Started Aug 15 04:33:40 PM PDT 24
Finished Aug 15 04:34:29 PM PDT 24
Peak memory 240948 kb
Host smart-fd95e29c-15c0-4264-b6b4-7e3194c5a7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843755619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.843755619
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.4071363219
Short name T293
Test name
Test status
Simulation time 3378079961 ps
CPU time 28.73 seconds
Started Aug 15 04:33:39 PM PDT 24
Finished Aug 15 04:34:07 PM PDT 24
Peak memory 236336 kb
Host smart-cae6e14b-c1cf-4bc2-ad4a-5345ff0bbae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071363219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4071363219
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1351483
Short name T289
Test name
Test status
Simulation time 27198082946 ps
CPU time 124.03 seconds
Started Aug 15 04:33:41 PM PDT 24
Finished Aug 15 04:35:45 PM PDT 24
Peak memory 252164 kb
Host smart-0e0d5069-8a93-4105-beca-d796b4c5501a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.1351483
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4018833534
Short name T1008
Test name
Test status
Simulation time 503418932 ps
CPU time 2.47 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:44 PM PDT 24
Peak memory 224460 kb
Host smart-1aa34c13-69e2-4998-a61c-0cb319a48c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018833534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4018833534
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1372486425
Short name T973
Test name
Test status
Simulation time 260404285 ps
CPU time 2.96 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:46 PM PDT 24
Peak memory 232712 kb
Host smart-f87d5b8d-ce9f-48c7-b2fb-e7a391d2d787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372486425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1372486425
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2485464316
Short name T244
Test name
Test status
Simulation time 353581531 ps
CPU time 3.7 seconds
Started Aug 15 04:33:46 PM PDT 24
Finished Aug 15 04:33:50 PM PDT 24
Peak memory 224476 kb
Host smart-62f5ee4c-0b26-42c4-867c-28cc593435e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485464316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2485464316
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.390245931
Short name T598
Test name
Test status
Simulation time 5184409637 ps
CPU time 17.19 seconds
Started Aug 15 04:33:39 PM PDT 24
Finished Aug 15 04:33:56 PM PDT 24
Peak memory 232844 kb
Host smart-74b9e4bd-ab7e-4921-b935-6b4387ec8707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390245931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.390245931
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.374596193
Short name T911
Test name
Test status
Simulation time 5646286921 ps
CPU time 5.6 seconds
Started Aug 15 04:33:40 PM PDT 24
Finished Aug 15 04:33:51 PM PDT 24
Peak memory 222796 kb
Host smart-95c57a0a-4aec-4d39-8c97-5b7cdcda7190
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=374596193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.374596193
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2850154664
Short name T155
Test name
Test status
Simulation time 96034467240 ps
CPU time 172.13 seconds
Started Aug 15 04:33:44 PM PDT 24
Finished Aug 15 04:36:36 PM PDT 24
Peak memory 257064 kb
Host smart-30552a2e-e304-412f-bf07-3850bf61a660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850154664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2850154664
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1951883102
Short name T650
Test name
Test status
Simulation time 827758448 ps
CPU time 12.52 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:55 PM PDT 24
Peak memory 216296 kb
Host smart-fdba1fb8-14d6-40be-b49d-e4fae9c44aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951883102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1951883102
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4231468193
Short name T417
Test name
Test status
Simulation time 1717765125 ps
CPU time 3.06 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:45 PM PDT 24
Peak memory 207856 kb
Host smart-5164ce20-78ce-468e-9183-2dc3c150cd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231468193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4231468193
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3509925543
Short name T819
Test name
Test status
Simulation time 43990958 ps
CPU time 2.45 seconds
Started Aug 15 04:33:41 PM PDT 24
Finished Aug 15 04:33:43 PM PDT 24
Peak memory 216280 kb
Host smart-90eb3c84-dbfc-4112-9076-46a78c6e1847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509925543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3509925543
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1107648524
Short name T986
Test name
Test status
Simulation time 109652197 ps
CPU time 0.77 seconds
Started Aug 15 04:33:47 PM PDT 24
Finished Aug 15 04:33:48 PM PDT 24
Peak memory 205884 kb
Host smart-56627e2e-f58d-4962-b3be-da161daf6eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107648524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1107648524
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3199485544
Short name T645
Test name
Test status
Simulation time 22837909125 ps
CPU time 20.51 seconds
Started Aug 15 04:33:39 PM PDT 24
Finished Aug 15 04:34:00 PM PDT 24
Peak memory 240984 kb
Host smart-e6d024c0-0158-4e29-8a7b-90249b159081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199485544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3199485544
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.331570322
Short name T576
Test name
Test status
Simulation time 12563919 ps
CPU time 0.7 seconds
Started Aug 15 04:33:52 PM PDT 24
Finished Aug 15 04:33:52 PM PDT 24
Peak memory 204752 kb
Host smart-41a10c30-9112-41a0-a280-7561a6511208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331570322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.331570322
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4030103586
Short name T625
Test name
Test status
Simulation time 237071105 ps
CPU time 2.47 seconds
Started Aug 15 04:33:46 PM PDT 24
Finished Aug 15 04:33:48 PM PDT 24
Peak memory 232720 kb
Host smart-2e31975e-5b4c-4174-ba43-85bf9f55d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030103586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4030103586
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3718044043
Short name T451
Test name
Test status
Simulation time 36683032 ps
CPU time 0.74 seconds
Started Aug 15 04:33:52 PM PDT 24
Finished Aug 15 04:33:53 PM PDT 24
Peak memory 206780 kb
Host smart-868c2a35-c487-4b07-bf0d-aa26d5945931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718044043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3718044043
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3020776932
Short name T455
Test name
Test status
Simulation time 12393114 ps
CPU time 0.73 seconds
Started Aug 15 04:33:45 PM PDT 24
Finished Aug 15 04:33:46 PM PDT 24
Peak memory 215756 kb
Host smart-fe10e51f-62d6-41cb-8300-16daba8ad430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020776932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3020776932
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.160607185
Short name T285
Test name
Test status
Simulation time 84065898364 ps
CPU time 807.74 seconds
Started Aug 15 04:33:45 PM PDT 24
Finished Aug 15 04:47:12 PM PDT 24
Peak memory 272620 kb
Host smart-be4f4d2c-7695-4de4-9a4b-0eca61e9a8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160607185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.160607185
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2448582079
Short name T52
Test name
Test status
Simulation time 169711868822 ps
CPU time 384.52 seconds
Started Aug 15 04:33:51 PM PDT 24
Finished Aug 15 04:40:15 PM PDT 24
Peak memory 238068 kb
Host smart-62049f3b-7c8b-45c4-901f-78d06c358989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448582079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2448582079
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2914294926
Short name T151
Test name
Test status
Simulation time 146378602 ps
CPU time 6.21 seconds
Started Aug 15 04:33:51 PM PDT 24
Finished Aug 15 04:33:57 PM PDT 24
Peak memory 232672 kb
Host smart-c5902e0b-2e2d-475b-b939-235628bfd923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914294926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2914294926
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.54097011
Short name T86
Test name
Test status
Simulation time 10069890699 ps
CPU time 51.49 seconds
Started Aug 15 04:33:48 PM PDT 24
Finished Aug 15 04:34:40 PM PDT 24
Peak memory 249144 kb
Host smart-fa9e0547-19fa-4a74-8eb9-5f802d8eff4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54097011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.54097011
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.176417990
Short name T728
Test name
Test status
Simulation time 310259263 ps
CPU time 7.35 seconds
Started Aug 15 04:33:57 PM PDT 24
Finished Aug 15 04:34:04 PM PDT 24
Peak memory 232676 kb
Host smart-199c9841-015e-48c8-aec9-dc1ba8215ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176417990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.176417990
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.195628671
Short name T792
Test name
Test status
Simulation time 473390285 ps
CPU time 5.73 seconds
Started Aug 15 04:33:46 PM PDT 24
Finished Aug 15 04:33:52 PM PDT 24
Peak memory 224480 kb
Host smart-e40bc6db-6b93-4dc4-a82e-417a3e3cbbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195628671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.195628671
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2420434221
Short name T977
Test name
Test status
Simulation time 1586836506 ps
CPU time 3.67 seconds
Started Aug 15 04:33:47 PM PDT 24
Finished Aug 15 04:33:51 PM PDT 24
Peak memory 232680 kb
Host smart-9cd5c169-60b7-4dce-8a79-5518e92f88e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420434221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2420434221
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.810073417
Short name T938
Test name
Test status
Simulation time 75149622 ps
CPU time 2.36 seconds
Started Aug 15 04:33:51 PM PDT 24
Finished Aug 15 04:33:54 PM PDT 24
Peak memory 223776 kb
Host smart-ba8dc0b6-1cf5-4ceb-b21c-089ae97f1b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810073417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.810073417
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2572659639
Short name T370
Test name
Test status
Simulation time 1267215894 ps
CPU time 6.23 seconds
Started Aug 15 04:33:49 PM PDT 24
Finished Aug 15 04:33:56 PM PDT 24
Peak memory 222924 kb
Host smart-03c08fe4-f3dc-4a49-9dc1-a85d737844c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2572659639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2572659639
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3847585582
Short name T717
Test name
Test status
Simulation time 1777441835 ps
CPU time 8.14 seconds
Started Aug 15 04:33:45 PM PDT 24
Finished Aug 15 04:33:53 PM PDT 24
Peak memory 218044 kb
Host smart-e792e1a5-d950-4025-938c-5092695f89e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847585582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3847585582
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1592041566
Short name T552
Test name
Test status
Simulation time 572553234 ps
CPU time 4.17 seconds
Started Aug 15 04:33:47 PM PDT 24
Finished Aug 15 04:33:51 PM PDT 24
Peak memory 216244 kb
Host smart-3bc41d50-6525-459c-8a4d-e0aa775f04fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592041566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1592041566
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2155709451
Short name T627
Test name
Test status
Simulation time 166548984 ps
CPU time 1.37 seconds
Started Aug 15 04:33:45 PM PDT 24
Finished Aug 15 04:33:46 PM PDT 24
Peak memory 208072 kb
Host smart-5ed49eaf-4c07-482b-b56b-a3328ddfa658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155709451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2155709451
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.349195953
Short name T806
Test name
Test status
Simulation time 38361523 ps
CPU time 0.77 seconds
Started Aug 15 04:33:42 PM PDT 24
Finished Aug 15 04:33:43 PM PDT 24
Peak memory 205912 kb
Host smart-ef27d3db-f073-4b16-bac3-53fd07b8f53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349195953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.349195953
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1708658030
Short name T997
Test name
Test status
Simulation time 251340591 ps
CPU time 2.26 seconds
Started Aug 15 04:33:56 PM PDT 24
Finished Aug 15 04:33:59 PM PDT 24
Peak memory 223296 kb
Host smart-c784c778-8e71-48ea-b040-69eaa8c74a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708658030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1708658030
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2454097808
Short name T987
Test name
Test status
Simulation time 45310670 ps
CPU time 0.68 seconds
Started Aug 15 04:33:46 PM PDT 24
Finished Aug 15 04:33:47 PM PDT 24
Peak memory 204748 kb
Host smart-bc54d5e2-593c-42a0-8c75-0167d4da925d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454097808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2454097808
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3590550977
Short name T673
Test name
Test status
Simulation time 296335743 ps
CPU time 5.43 seconds
Started Aug 15 04:33:54 PM PDT 24
Finished Aug 15 04:33:59 PM PDT 24
Peak memory 224412 kb
Host smart-87f6146b-027f-4544-95d2-04b5c0478ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590550977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3590550977
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4202087995
Short name T415
Test name
Test status
Simulation time 61795332 ps
CPU time 0.82 seconds
Started Aug 15 04:33:44 PM PDT 24
Finished Aug 15 04:33:45 PM PDT 24
Peak memory 206432 kb
Host smart-8d86c232-0e97-46df-800b-ca2986b1f239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202087995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4202087995
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1477999927
Short name T457
Test name
Test status
Simulation time 495018081 ps
CPU time 10.79 seconds
Started Aug 15 04:33:51 PM PDT 24
Finished Aug 15 04:34:02 PM PDT 24
Peak memory 240884 kb
Host smart-16936927-c1de-45fa-9afe-acd9ac3764ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477999927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1477999927
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1297321582
Short name T291
Test name
Test status
Simulation time 64118695740 ps
CPU time 551.02 seconds
Started Aug 15 04:33:58 PM PDT 24
Finished Aug 15 04:43:10 PM PDT 24
Peak memory 264716 kb
Host smart-ec9836fa-1c0a-4b64-82a7-df04d7c13f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297321582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1297321582
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1164070513
Short name T493
Test name
Test status
Simulation time 3226272060 ps
CPU time 47.69 seconds
Started Aug 15 04:33:48 PM PDT 24
Finished Aug 15 04:34:36 PM PDT 24
Peak memory 240972 kb
Host smart-5da9fafa-16b4-4ef6-bd54-8bf7f7e18b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164070513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1164070513
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.976057814
Short name T295
Test name
Test status
Simulation time 7927451534 ps
CPU time 27.98 seconds
Started Aug 15 04:33:50 PM PDT 24
Finished Aug 15 04:34:19 PM PDT 24
Peak memory 224608 kb
Host smart-43a31a5d-d3b5-4d7e-91ac-899467bd1014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976057814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.976057814
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.676538714
Short name T832
Test name
Test status
Simulation time 6866151035 ps
CPU time 40.44 seconds
Started Aug 15 04:33:51 PM PDT 24
Finished Aug 15 04:34:32 PM PDT 24
Peak memory 253724 kb
Host smart-cec79a36-a27a-4bad-9ef3-eec92f7f03a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676538714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.676538714
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1559684112
Short name T848
Test name
Test status
Simulation time 566894964 ps
CPU time 3.49 seconds
Started Aug 15 04:33:47 PM PDT 24
Finished Aug 15 04:33:50 PM PDT 24
Peak memory 224444 kb
Host smart-cbf14ffc-11d9-49f5-9fed-2c7ec1680966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559684112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1559684112
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2633971553
Short name T342
Test name
Test status
Simulation time 6753020087 ps
CPU time 29.7 seconds
Started Aug 15 04:33:50 PM PDT 24
Finished Aug 15 04:34:20 PM PDT 24
Peak memory 223840 kb
Host smart-d45c6059-f59e-4282-ad4c-821f9743a77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633971553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2633971553
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1769711515
Short name T401
Test name
Test status
Simulation time 2987263816 ps
CPU time 9.65 seconds
Started Aug 15 04:33:48 PM PDT 24
Finished Aug 15 04:33:58 PM PDT 24
Peak memory 224508 kb
Host smart-8460f23a-6a18-414c-9a18-00d89a77ec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769711515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1769711515
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.955749015
Short name T778
Test name
Test status
Simulation time 203943957 ps
CPU time 3.74 seconds
Started Aug 15 04:33:49 PM PDT 24
Finished Aug 15 04:33:52 PM PDT 24
Peak memory 224468 kb
Host smart-bff3dcec-d6c6-4295-9487-fafb6b700012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955749015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.955749015
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1989560177
Short name T146
Test name
Test status
Simulation time 362692070 ps
CPU time 7.54 seconds
Started Aug 15 04:33:51 PM PDT 24
Finished Aug 15 04:33:59 PM PDT 24
Peak memory 220340 kb
Host smart-76819930-e22f-4874-8f3c-71e4ba5f5283
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1989560177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1989560177
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2010738249
Short name T157
Test name
Test status
Simulation time 154453446 ps
CPU time 0.92 seconds
Started Aug 15 04:33:51 PM PDT 24
Finished Aug 15 04:33:52 PM PDT 24
Peak memory 205528 kb
Host smart-9bf36a44-8430-4ff3-a43b-ef2d7f0ab6cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010738249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2010738249
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1961583604
Short name T38
Test name
Test status
Simulation time 259540087 ps
CPU time 2.58 seconds
Started Aug 15 04:33:46 PM PDT 24
Finished Aug 15 04:33:49 PM PDT 24
Peak memory 216376 kb
Host smart-23a1bbc7-d62d-4940-878b-34c9f50f3c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961583604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1961583604
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.711145152
Short name T615
Test name
Test status
Simulation time 446102672 ps
CPU time 2.76 seconds
Started Aug 15 04:33:46 PM PDT 24
Finished Aug 15 04:33:49 PM PDT 24
Peak memory 216368 kb
Host smart-168f4166-b476-4158-aea6-0f5da937e8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711145152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.711145152
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.44315092
Short name T970
Test name
Test status
Simulation time 44044685 ps
CPU time 1 seconds
Started Aug 15 04:33:50 PM PDT 24
Finished Aug 15 04:33:51 PM PDT 24
Peak memory 206996 kb
Host smart-aa7b9d9c-be9d-4380-9be6-59623705b694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44315092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.44315092
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1515606755
Short name T312
Test name
Test status
Simulation time 141702508 ps
CPU time 0.83 seconds
Started Aug 15 04:33:52 PM PDT 24
Finished Aug 15 04:33:53 PM PDT 24
Peak memory 205956 kb
Host smart-d019287e-57d9-46f8-a09f-4649639b3fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515606755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1515606755
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2271791502
Short name T820
Test name
Test status
Simulation time 577872326 ps
CPU time 3.39 seconds
Started Aug 15 04:33:47 PM PDT 24
Finished Aug 15 04:33:50 PM PDT 24
Peak memory 232740 kb
Host smart-9bd3d7e2-7b3e-40bf-8953-967cfbf666b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271791502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2271791502
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1175089554
Short name T343
Test name
Test status
Simulation time 13083833 ps
CPU time 0.82 seconds
Started Aug 15 04:32:01 PM PDT 24
Finished Aug 15 04:32:02 PM PDT 24
Peak memory 205308 kb
Host smart-b2f16398-9842-4852-98f3-53d04a635567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175089554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
175089554
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.326289285
Short name T578
Test name
Test status
Simulation time 52135349 ps
CPU time 2.61 seconds
Started Aug 15 04:32:01 PM PDT 24
Finished Aug 15 04:32:04 PM PDT 24
Peak memory 232664 kb
Host smart-4fc00753-ca88-47b4-beab-8ad8f2110dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326289285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.326289285
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.896694231
Short name T409
Test name
Test status
Simulation time 53614114 ps
CPU time 0.79 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 206360 kb
Host smart-afbcb403-6772-44e5-978a-9980ed31d56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896694231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.896694231
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3635556259
Short name T528
Test name
Test status
Simulation time 18674386058 ps
CPU time 158.95 seconds
Started Aug 15 04:32:03 PM PDT 24
Finished Aug 15 04:34:42 PM PDT 24
Peak memory 251084 kb
Host smart-f9e3571d-cad8-41e3-8a88-d7ab57466670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635556259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3635556259
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.52138706
Short name T30
Test name
Test status
Simulation time 9912230335 ps
CPU time 78.24 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:33:22 PM PDT 24
Peak memory 259448 kb
Host smart-a304d747-44e3-4a6e-a36f-7862c5816fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52138706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.52138706
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.606429348
Short name T305
Test name
Test status
Simulation time 2213010982 ps
CPU time 28.77 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:33 PM PDT 24
Peak memory 232852 kb
Host smart-dfe55c00-1ba8-4e2a-b068-391f0f3bb9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606429348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
606429348
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3858154959
Short name T638
Test name
Test status
Simulation time 150047987 ps
CPU time 4.49 seconds
Started Aug 15 04:32:03 PM PDT 24
Finished Aug 15 04:32:08 PM PDT 24
Peak memory 224436 kb
Host smart-8af0b9d3-d2e4-4368-a61a-735f9dfee272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858154959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3858154959
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1878722275
Short name T718
Test name
Test status
Simulation time 58267251628 ps
CPU time 389.24 seconds
Started Aug 15 04:32:01 PM PDT 24
Finished Aug 15 04:38:31 PM PDT 24
Peak memory 265876 kb
Host smart-697cdf91-8128-4e5e-a279-818d0f71491f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878722275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1878722275
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3634923417
Short name T129
Test name
Test status
Simulation time 2136363455 ps
CPU time 9.68 seconds
Started Aug 15 04:31:53 PM PDT 24
Finished Aug 15 04:32:03 PM PDT 24
Peak memory 224460 kb
Host smart-deada263-483b-41fa-84a5-7380e801dc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634923417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3634923417
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2146243171
Short name T560
Test name
Test status
Simulation time 513912353 ps
CPU time 11.35 seconds
Started Aug 15 04:31:53 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 232712 kb
Host smart-33dcbedb-7c4b-4fe2-9101-3d9e66d91017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146243171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2146243171
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2841420260
Short name T606
Test name
Test status
Simulation time 46867442 ps
CPU time 1.15 seconds
Started Aug 15 04:31:55 PM PDT 24
Finished Aug 15 04:31:56 PM PDT 24
Peak memory 216536 kb
Host smart-45a8cbbd-b8aa-47ce-9513-dc59adec49cb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841420260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2841420260
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3395583576
Short name T634
Test name
Test status
Simulation time 257707563 ps
CPU time 2.86 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:07 PM PDT 24
Peak memory 232440 kb
Host smart-3a5cef8e-b1ca-4549-9723-86397b241dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395583576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3395583576
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2401390745
Short name T463
Test name
Test status
Simulation time 42810964 ps
CPU time 2.54 seconds
Started Aug 15 04:31:54 PM PDT 24
Finished Aug 15 04:31:57 PM PDT 24
Peak memory 232672 kb
Host smart-4c267f4b-0dcc-44f7-9014-0928eabd0b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401390745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2401390745
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.253242339
Short name T559
Test name
Test status
Simulation time 1247587902 ps
CPU time 15.01 seconds
Started Aug 15 04:32:01 PM PDT 24
Finished Aug 15 04:32:16 PM PDT 24
Peak memory 221968 kb
Host smart-ab1b8369-e49c-4e2b-9623-74250ed1d972
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=253242339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.253242339
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2155475576
Short name T69
Test name
Test status
Simulation time 121683502 ps
CPU time 1.11 seconds
Started Aug 15 04:32:02 PM PDT 24
Finished Aug 15 04:32:03 PM PDT 24
Peak memory 234996 kb
Host smart-35ac3e0e-86bb-437d-9ac9-28dda0eef952
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155475576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2155475576
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3307388658
Short name T666
Test name
Test status
Simulation time 109325090 ps
CPU time 1.16 seconds
Started Aug 15 04:32:03 PM PDT 24
Finished Aug 15 04:32:04 PM PDT 24
Peak memory 206944 kb
Host smart-b0a88992-8203-4a59-b2e2-c5d3711db8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307388658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3307388658
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.669524990
Short name T330
Test name
Test status
Simulation time 724099528 ps
CPU time 4.6 seconds
Started Aug 15 04:31:54 PM PDT 24
Finished Aug 15 04:31:59 PM PDT 24
Peak memory 216348 kb
Host smart-5277f809-8d07-46a6-9b9c-237a1fa62851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669524990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.669524990
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2005334828
Short name T861
Test name
Test status
Simulation time 12340194057 ps
CPU time 7.66 seconds
Started Aug 15 04:31:52 PM PDT 24
Finished Aug 15 04:32:00 PM PDT 24
Peak memory 216340 kb
Host smart-bb699f07-2faf-4a0b-9872-bc5bda09a4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005334828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2005334828
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1689294020
Short name T456
Test name
Test status
Simulation time 26776218 ps
CPU time 1.26 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 216160 kb
Host smart-f4b0da6c-0a8e-48ff-8490-29c9f9724cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689294020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1689294020
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1399744594
Short name T695
Test name
Test status
Simulation time 82816132 ps
CPU time 0.94 seconds
Started Aug 15 04:31:51 PM PDT 24
Finished Aug 15 04:31:52 PM PDT 24
Peak memory 204888 kb
Host smart-b7d35be0-2e81-4d57-b7a1-c07d05cf9937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399744594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1399744594
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3960670045
Short name T425
Test name
Test status
Simulation time 6356592589 ps
CPU time 12.61 seconds
Started Aug 15 04:32:03 PM PDT 24
Finished Aug 15 04:32:15 PM PDT 24
Peak memory 224660 kb
Host smart-055075f0-8bca-4ba7-bc7a-511c7f4d81f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960670045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3960670045
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.928287690
Short name T25
Test name
Test status
Simulation time 23008206 ps
CPU time 0.7 seconds
Started Aug 15 04:33:54 PM PDT 24
Finished Aug 15 04:33:54 PM PDT 24
Peak memory 205384 kb
Host smart-0ecec6d2-9242-43aa-bf36-99d897955b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928287690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.928287690
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.276153941
Short name T821
Test name
Test status
Simulation time 5029962103 ps
CPU time 10.37 seconds
Started Aug 15 04:33:53 PM PDT 24
Finished Aug 15 04:34:04 PM PDT 24
Peak memory 224536 kb
Host smart-2cf745a0-c15e-4655-a15b-487f89b513e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276153941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.276153941
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1048819167
Short name T589
Test name
Test status
Simulation time 29180783 ps
CPU time 0.79 seconds
Started Aug 15 04:33:52 PM PDT 24
Finished Aug 15 04:33:53 PM PDT 24
Peak memory 205772 kb
Host smart-7debaec0-b2df-436f-bcc5-f0338428b120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048819167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1048819167
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.886139644
Short name T784
Test name
Test status
Simulation time 84399119212 ps
CPU time 184.68 seconds
Started Aug 15 04:33:48 PM PDT 24
Finished Aug 15 04:36:53 PM PDT 24
Peak memory 257312 kb
Host smart-553100fc-ab1b-4c37-9bda-f4e80a68f507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886139644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.886139644
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2066385850
Short name T31
Test name
Test status
Simulation time 4454688250 ps
CPU time 35.2 seconds
Started Aug 15 04:33:46 PM PDT 24
Finished Aug 15 04:34:22 PM PDT 24
Peak memory 257120 kb
Host smart-1cfa1e17-e059-455e-9585-1d78fb553d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066385850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2066385850
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1359139276
Short name T906
Test name
Test status
Simulation time 33268158354 ps
CPU time 125.3 seconds
Started Aug 15 04:33:49 PM PDT 24
Finished Aug 15 04:35:55 PM PDT 24
Peak memory 249232 kb
Host smart-d0453b4c-a3bd-4968-b6ff-13f07f921fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359139276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1359139276
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1877743124
Short name T265
Test name
Test status
Simulation time 71278895710 ps
CPU time 459.58 seconds
Started Aug 15 04:33:45 PM PDT 24
Finished Aug 15 04:41:25 PM PDT 24
Peak memory 263892 kb
Host smart-93035b2c-90fd-453d-bcaf-420ac93541e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877743124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1877743124
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.115440130
Short name T789
Test name
Test status
Simulation time 349349503 ps
CPU time 6.7 seconds
Started Aug 15 04:33:49 PM PDT 24
Finished Aug 15 04:33:56 PM PDT 24
Peak memory 224488 kb
Host smart-cfc60f4e-277c-4313-bea7-026b1c65f0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115440130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.115440130
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3583729655
Short name T698
Test name
Test status
Simulation time 5981413932 ps
CPU time 11.67 seconds
Started Aug 15 04:33:51 PM PDT 24
Finished Aug 15 04:34:02 PM PDT 24
Peak memory 224532 kb
Host smart-51487acc-0758-47da-ac41-7aaa2f07283e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583729655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3583729655
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3515184424
Short name T654
Test name
Test status
Simulation time 4841594808 ps
CPU time 7.29 seconds
Started Aug 15 04:33:52 PM PDT 24
Finished Aug 15 04:34:00 PM PDT 24
Peak memory 240560 kb
Host smart-632f4fa7-fabd-43c0-9b74-c6c51ae2b130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515184424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3515184424
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4056663498
Short name T915
Test name
Test status
Simulation time 257289579 ps
CPU time 4.63 seconds
Started Aug 15 04:33:54 PM PDT 24
Finished Aug 15 04:33:59 PM PDT 24
Peak memory 224460 kb
Host smart-58a7c815-f052-4c03-ae11-1eebda5e7726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056663498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4056663498
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.862718394
Short name T7
Test name
Test status
Simulation time 13109191375 ps
CPU time 6.84 seconds
Started Aug 15 04:33:45 PM PDT 24
Finished Aug 15 04:33:52 PM PDT 24
Peak memory 223040 kb
Host smart-615902a2-979f-486c-85fd-8f41aef27cb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=862718394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.862718394
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.931854284
Short name T158
Test name
Test status
Simulation time 111365604731 ps
CPU time 231.38 seconds
Started Aug 15 04:33:55 PM PDT 24
Finished Aug 15 04:37:46 PM PDT 24
Peak memory 266380 kb
Host smart-0b7fec84-9f38-40aa-985f-3a0fde807b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931854284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.931854284
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2374888154
Short name T927
Test name
Test status
Simulation time 5358035818 ps
CPU time 18.81 seconds
Started Aug 15 04:33:48 PM PDT 24
Finished Aug 15 04:34:07 PM PDT 24
Peak memory 216364 kb
Host smart-2b6f07ff-e360-44f3-85a6-f6850010b31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374888154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2374888154
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3014423606
Short name T319
Test name
Test status
Simulation time 14934178382 ps
CPU time 8.88 seconds
Started Aug 15 04:33:47 PM PDT 24
Finished Aug 15 04:33:56 PM PDT 24
Peak memory 216468 kb
Host smart-770311a0-2933-42c5-ae75-24fbb0c5e681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014423606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3014423606
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2098124677
Short name T1018
Test name
Test status
Simulation time 42682338 ps
CPU time 1.08 seconds
Started Aug 15 04:33:47 PM PDT 24
Finished Aug 15 04:33:49 PM PDT 24
Peak memory 207480 kb
Host smart-0ef25312-0fc7-475b-a635-0a5104cf37ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098124677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2098124677
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4223035656
Short name T377
Test name
Test status
Simulation time 62348578 ps
CPU time 0.87 seconds
Started Aug 15 04:33:49 PM PDT 24
Finished Aug 15 04:33:50 PM PDT 24
Peak memory 205912 kb
Host smart-6133dfec-bc24-42dc-acca-6c659d6733d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223035656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4223035656
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3873851688
Short name T81
Test name
Test status
Simulation time 6204163606 ps
CPU time 18.58 seconds
Started Aug 15 04:33:51 PM PDT 24
Finished Aug 15 04:34:09 PM PDT 24
Peak memory 257120 kb
Host smart-cb5a475d-fc0c-40d3-a197-9c9de9beabe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873851688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3873851688
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.907870450
Short name T554
Test name
Test status
Simulation time 22799981 ps
CPU time 0.71 seconds
Started Aug 15 04:33:59 PM PDT 24
Finished Aug 15 04:34:00 PM PDT 24
Peak memory 204764 kb
Host smart-b53ac569-fdf8-4a09-9e84-4cbbe7ba41d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907870450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.907870450
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.268768522
Short name T1001
Test name
Test status
Simulation time 1340040328 ps
CPU time 16.46 seconds
Started Aug 15 04:34:01 PM PDT 24
Finished Aug 15 04:34:18 PM PDT 24
Peak memory 232760 kb
Host smart-f79787f1-1965-4917-b0f1-960744edf233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268768522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.268768522
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3336622627
Short name T856
Test name
Test status
Simulation time 14288822 ps
CPU time 0.8 seconds
Started Aug 15 04:34:03 PM PDT 24
Finished Aug 15 04:34:04 PM PDT 24
Peak memory 206372 kb
Host smart-1a5916b0-8fe2-47d0-9cf0-50b872ec9879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336622627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3336622627
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.415502768
Short name T969
Test name
Test status
Simulation time 27263142424 ps
CPU time 72.62 seconds
Started Aug 15 04:33:58 PM PDT 24
Finished Aug 15 04:35:11 PM PDT 24
Peak memory 249216 kb
Host smart-487a1b55-ac26-4a68-9430-f92284dc6c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415502768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.415502768
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.312360294
Short name T481
Test name
Test status
Simulation time 4100337648 ps
CPU time 79.19 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:35:21 PM PDT 24
Peak memory 253512 kb
Host smart-8f717592-084f-434b-834f-661cceea910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312360294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.312360294
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1051073739
Short name T1012
Test name
Test status
Simulation time 16787984926 ps
CPU time 45.23 seconds
Started Aug 15 04:33:56 PM PDT 24
Finished Aug 15 04:34:41 PM PDT 24
Peak memory 224596 kb
Host smart-a1a74a14-4719-457d-a577-20398b8c9018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051073739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1051073739
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2381709172
Short name T166
Test name
Test status
Simulation time 6008980830 ps
CPU time 53.67 seconds
Started Aug 15 04:33:56 PM PDT 24
Finished Aug 15 04:34:49 PM PDT 24
Peak memory 249196 kb
Host smart-b8cb5852-dd5a-4279-a083-c692e80331d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381709172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2381709172
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1565986053
Short name T809
Test name
Test status
Simulation time 397180514 ps
CPU time 6.24 seconds
Started Aug 15 04:34:03 PM PDT 24
Finished Aug 15 04:34:10 PM PDT 24
Peak memory 224412 kb
Host smart-852cc044-adbd-4468-9c3c-47e0a77fcf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565986053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1565986053
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.284169351
Short name T569
Test name
Test status
Simulation time 3955658289 ps
CPU time 37.86 seconds
Started Aug 15 04:33:57 PM PDT 24
Finished Aug 15 04:34:35 PM PDT 24
Peak memory 249028 kb
Host smart-ff7b36d0-5595-414a-87e5-833b6cd0c1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284169351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.284169351
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3315867060
Short name T249
Test name
Test status
Simulation time 242591213 ps
CPU time 2.76 seconds
Started Aug 15 04:34:01 PM PDT 24
Finished Aug 15 04:34:04 PM PDT 24
Peak memory 224552 kb
Host smart-b57fed8c-845c-4410-95f3-cea4db2419b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315867060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3315867060
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2936631127
Short name T254
Test name
Test status
Simulation time 1268776873 ps
CPU time 3.94 seconds
Started Aug 15 04:33:57 PM PDT 24
Finished Aug 15 04:34:01 PM PDT 24
Peak memory 224400 kb
Host smart-4e4f6aec-3182-4967-aec9-d07edd9f7cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936631127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2936631127
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.332780561
Short name T337
Test name
Test status
Simulation time 2153371051 ps
CPU time 6.26 seconds
Started Aug 15 04:33:56 PM PDT 24
Finished Aug 15 04:34:02 PM PDT 24
Peak memory 221796 kb
Host smart-a24beb8d-41dc-4b05-a6c4-ff46e6af6bc7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=332780561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.332780561
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2833555778
Short name T21
Test name
Test status
Simulation time 35054747228 ps
CPU time 111.74 seconds
Started Aug 15 04:33:56 PM PDT 24
Finished Aug 15 04:35:48 PM PDT 24
Peak memory 251468 kb
Host smart-5be9a88b-9b9d-4943-8d44-55e520f6987e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833555778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2833555778
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1832979585
Short name T894
Test name
Test status
Simulation time 1413260852 ps
CPU time 17.93 seconds
Started Aug 15 04:33:58 PM PDT 24
Finished Aug 15 04:34:16 PM PDT 24
Peak memory 216584 kb
Host smart-fbfd057a-3f97-4f9d-aaeb-c9da82ffbf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832979585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1832979585
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3141520607
Short name T332
Test name
Test status
Simulation time 1363713932 ps
CPU time 6.45 seconds
Started Aug 15 04:34:03 PM PDT 24
Finished Aug 15 04:34:09 PM PDT 24
Peak memory 216288 kb
Host smart-b51a5f4b-d995-46e9-9187-ff681a816e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141520607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3141520607
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.827209100
Short name T1016
Test name
Test status
Simulation time 123509094 ps
CPU time 2.35 seconds
Started Aug 15 04:33:59 PM PDT 24
Finished Aug 15 04:34:02 PM PDT 24
Peak memory 216288 kb
Host smart-c9ba4e2b-bc15-4658-b628-2499650883ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827209100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.827209100
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3843651720
Short name T530
Test name
Test status
Simulation time 127447122 ps
CPU time 0.91 seconds
Started Aug 15 04:34:00 PM PDT 24
Finished Aug 15 04:34:01 PM PDT 24
Peak memory 205928 kb
Host smart-10dd055d-5798-4b8b-abb8-ac427dbd7c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843651720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3843651720
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1243174679
Short name T12
Test name
Test status
Simulation time 4343194797 ps
CPU time 8.97 seconds
Started Aug 15 04:33:59 PM PDT 24
Finished Aug 15 04:34:08 PM PDT 24
Peak memory 232808 kb
Host smart-9f6f0597-c952-465f-b318-6e1e62056261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243174679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1243174679
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1403642425
Short name T743
Test name
Test status
Simulation time 16254787 ps
CPU time 0.79 seconds
Started Aug 15 04:33:58 PM PDT 24
Finished Aug 15 04:33:59 PM PDT 24
Peak memory 204800 kb
Host smart-a18d0751-3a8a-449b-82be-774a4c543d41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403642425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1403642425
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2926600256
Short name T918
Test name
Test status
Simulation time 107671297 ps
CPU time 3.04 seconds
Started Aug 15 04:33:56 PM PDT 24
Finished Aug 15 04:33:59 PM PDT 24
Peak memory 232688 kb
Host smart-8e9c9f14-168b-4f34-81bc-60bb9d3d7d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926600256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2926600256
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3746140037
Short name T562
Test name
Test status
Simulation time 17269714 ps
CPU time 0.77 seconds
Started Aug 15 04:33:59 PM PDT 24
Finished Aug 15 04:34:00 PM PDT 24
Peak memory 206492 kb
Host smart-5dc72542-c570-44d2-a414-6ba6e23530a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746140037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3746140037
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.807922679
Short name T775
Test name
Test status
Simulation time 1223054034 ps
CPU time 18.45 seconds
Started Aug 15 04:34:03 PM PDT 24
Finished Aug 15 04:34:22 PM PDT 24
Peak memory 240096 kb
Host smart-1ea4e9ae-32e7-4eb6-a3bc-24ea3e74aaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807922679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.807922679
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3449454451
Short name T903
Test name
Test status
Simulation time 10022589129 ps
CPU time 81.89 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:35:24 PM PDT 24
Peak memory 250188 kb
Host smart-1102e510-c43d-47f5-b85d-2356d116c93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449454451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3449454451
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3737465383
Short name T849
Test name
Test status
Simulation time 12688722980 ps
CPU time 52.18 seconds
Started Aug 15 04:33:53 PM PDT 24
Finished Aug 15 04:34:45 PM PDT 24
Peak memory 224584 kb
Host smart-ba15f69d-f277-4fbb-8d5a-b72c002df019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737465383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3737465383
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2933788987
Short name T1017
Test name
Test status
Simulation time 7178143729 ps
CPU time 49.54 seconds
Started Aug 15 04:33:55 PM PDT 24
Finished Aug 15 04:34:45 PM PDT 24
Peak memory 235284 kb
Host smart-fe1eff2a-e036-4173-aa16-25cd7e6e1d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933788987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2933788987
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.928275742
Short name T868
Test name
Test status
Simulation time 712130172 ps
CPU time 5 seconds
Started Aug 15 04:34:00 PM PDT 24
Finished Aug 15 04:34:05 PM PDT 24
Peak memory 232704 kb
Host smart-94b714db-b8c3-40d7-85eb-c2671aa9e4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928275742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.928275742
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1904139942
Short name T181
Test name
Test status
Simulation time 36320229516 ps
CPU time 162.2 seconds
Started Aug 15 04:34:01 PM PDT 24
Finished Aug 15 04:36:43 PM PDT 24
Peak memory 232772 kb
Host smart-e8cfec45-face-40c4-a4e0-4da062ae7f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904139942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1904139942
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1584286815
Short name T261
Test name
Test status
Simulation time 738854577 ps
CPU time 3.23 seconds
Started Aug 15 04:34:01 PM PDT 24
Finished Aug 15 04:34:04 PM PDT 24
Peak memory 224444 kb
Host smart-7e5f2d8c-5e7a-444d-8338-c825018262ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584286815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1584286815
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3679203849
Short name T908
Test name
Test status
Simulation time 581867685 ps
CPU time 3.6 seconds
Started Aug 15 04:33:58 PM PDT 24
Finished Aug 15 04:34:02 PM PDT 24
Peak memory 232672 kb
Host smart-8357db05-576f-4f15-8bf0-0e52f7b0b4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679203849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3679203849
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1443195022
Short name T540
Test name
Test status
Simulation time 1465067418 ps
CPU time 17.01 seconds
Started Aug 15 04:33:59 PM PDT 24
Finished Aug 15 04:34:16 PM PDT 24
Peak memory 221828 kb
Host smart-946e3257-be59-4ff6-84e0-089b98e1d3a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1443195022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1443195022
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2153162559
Short name T807
Test name
Test status
Simulation time 56038814778 ps
CPU time 466.42 seconds
Started Aug 15 04:33:54 PM PDT 24
Finished Aug 15 04:41:41 PM PDT 24
Peak memory 271392 kb
Host smart-57f5bbb1-0741-4904-956d-70d5ea2021ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153162559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2153162559
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2683670904
Short name T438
Test name
Test status
Simulation time 579224552 ps
CPU time 9.68 seconds
Started Aug 15 04:33:59 PM PDT 24
Finished Aug 15 04:34:09 PM PDT 24
Peak memory 216300 kb
Host smart-33b58554-1eed-4280-8d2d-4a8bbb8adf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683670904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2683670904
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.930349848
Short name T434
Test name
Test status
Simulation time 413973523 ps
CPU time 3.07 seconds
Started Aug 15 04:33:54 PM PDT 24
Finished Aug 15 04:33:57 PM PDT 24
Peak memory 216304 kb
Host smart-af60e0e5-c6de-4a92-be89-b466c805ce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930349848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.930349848
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4217748873
Short name T682
Test name
Test status
Simulation time 152914770 ps
CPU time 1.7 seconds
Started Aug 15 04:33:52 PM PDT 24
Finished Aug 15 04:33:54 PM PDT 24
Peak memory 216312 kb
Host smart-37cd6744-a8b7-4825-a288-0f5b229419a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217748873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4217748873
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1511950277
Short name T572
Test name
Test status
Simulation time 249192373 ps
CPU time 0.79 seconds
Started Aug 15 04:33:54 PM PDT 24
Finished Aug 15 04:33:55 PM PDT 24
Peak memory 205936 kb
Host smart-27ea3abc-f9cd-463d-92a1-ae7afcac9e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511950277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1511950277
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1546644621
Short name T713
Test name
Test status
Simulation time 3269201607 ps
CPU time 14.76 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:34:17 PM PDT 24
Peak memory 232744 kb
Host smart-78f77a73-c931-46a9-b0fa-c0dbed3c8137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546644621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1546644621
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.502295754
Short name T617
Test name
Test status
Simulation time 14824486 ps
CPU time 0.76 seconds
Started Aug 15 04:34:01 PM PDT 24
Finished Aug 15 04:34:01 PM PDT 24
Peak memory 205676 kb
Host smart-6802725a-6e72-4f23-9786-3e151a3e902f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502295754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.502295754
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.526760622
Short name T955
Test name
Test status
Simulation time 78022199 ps
CPU time 2.38 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:34:05 PM PDT 24
Peak memory 232756 kb
Host smart-052ac49c-1cff-4bc4-83f4-e1bd5f501c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526760622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.526760622
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2154031220
Short name T420
Test name
Test status
Simulation time 57536178 ps
CPU time 0.77 seconds
Started Aug 15 04:33:57 PM PDT 24
Finished Aug 15 04:33:58 PM PDT 24
Peak memory 205396 kb
Host smart-5afe41f4-273b-4bcc-8d27-4deb72899ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154031220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2154031220
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.213894673
Short name T194
Test name
Test status
Simulation time 56364196851 ps
CPU time 413 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:40:55 PM PDT 24
Peak memory 255736 kb
Host smart-7ad53ba5-d6b8-47f0-a2e0-c47f46c7200d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213894673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.213894673
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1913906952
Short name T548
Test name
Test status
Simulation time 6753434732 ps
CPU time 78.34 seconds
Started Aug 15 04:34:01 PM PDT 24
Finished Aug 15 04:35:20 PM PDT 24
Peak memory 255412 kb
Host smart-accc55a5-7063-415f-8556-6b553c80b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913906952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1913906952
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.30020599
Short name T326
Test name
Test status
Simulation time 2683597572 ps
CPU time 23.37 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:34:25 PM PDT 24
Peak memory 219736 kb
Host smart-ece60d3c-5399-4add-bb47-424b300bbdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30020599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.30020599
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.338208504
Short name T41
Test name
Test status
Simulation time 7888754901 ps
CPU time 48.36 seconds
Started Aug 15 04:34:05 PM PDT 24
Finished Aug 15 04:34:54 PM PDT 24
Peak memory 232756 kb
Host smart-f4bb96d5-a8cb-4673-8e94-56ea93a6660e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338208504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.338208504
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.524831077
Short name T268
Test name
Test status
Simulation time 4626851238 ps
CPU time 80.17 seconds
Started Aug 15 04:34:06 PM PDT 24
Finished Aug 15 04:35:26 PM PDT 24
Peak memory 252236 kb
Host smart-4fecb9a1-a9ab-4e8f-85a1-77b49e300f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524831077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.524831077
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2337977277
Short name T130
Test name
Test status
Simulation time 6966175695 ps
CPU time 16.5 seconds
Started Aug 15 04:34:11 PM PDT 24
Finished Aug 15 04:34:28 PM PDT 24
Peak memory 232692 kb
Host smart-1d2129bc-a479-41ec-b617-3e4acad128ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337977277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2337977277
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.537323232
Short name T966
Test name
Test status
Simulation time 3292852176 ps
CPU time 11.24 seconds
Started Aug 15 04:34:03 PM PDT 24
Finished Aug 15 04:34:15 PM PDT 24
Peak memory 240084 kb
Host smart-8a217ff7-05bc-4b02-9733-9b81032f8fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537323232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.537323232
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4127612364
Short name T491
Test name
Test status
Simulation time 27516278588 ps
CPU time 8.22 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:34:10 PM PDT 24
Peak memory 232744 kb
Host smart-a8dbce6f-2ff1-4f67-a827-7fb53794f62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127612364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4127612364
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.680329572
Short name T376
Test name
Test status
Simulation time 378166887 ps
CPU time 2.16 seconds
Started Aug 15 04:34:07 PM PDT 24
Finished Aug 15 04:34:10 PM PDT 24
Peak memory 223636 kb
Host smart-89244de6-d128-49cd-81cb-a6e44b32c18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680329572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.680329572
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1623333226
Short name T344
Test name
Test status
Simulation time 1285253710 ps
CPU time 4.45 seconds
Started Aug 15 04:34:00 PM PDT 24
Finished Aug 15 04:34:04 PM PDT 24
Peak memory 220608 kb
Host smart-e0409580-ea6d-4723-82bc-99419b86c192
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1623333226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1623333226
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3951990035
Short name T616
Test name
Test status
Simulation time 12851902107 ps
CPU time 51.11 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:34:53 PM PDT 24
Peak memory 240984 kb
Host smart-8a2cda9d-99f4-4066-83f7-7ac410ce6124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951990035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3951990035
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1310004475
Short name T541
Test name
Test status
Simulation time 9552289683 ps
CPU time 43.77 seconds
Started Aug 15 04:33:55 PM PDT 24
Finished Aug 15 04:34:39 PM PDT 24
Peak memory 216776 kb
Host smart-0233fda8-6391-4a2f-95b9-eb1a648e77c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310004475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1310004475
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.946920636
Short name T472
Test name
Test status
Simulation time 3074539225 ps
CPU time 3.75 seconds
Started Aug 15 04:34:00 PM PDT 24
Finished Aug 15 04:34:04 PM PDT 24
Peak memory 216300 kb
Host smart-435420b3-b0b7-4400-873d-dc8893cc4878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946920636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.946920636
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2991074917
Short name T746
Test name
Test status
Simulation time 211885056 ps
CPU time 1.29 seconds
Started Aug 15 04:34:12 PM PDT 24
Finished Aug 15 04:34:14 PM PDT 24
Peak memory 216344 kb
Host smart-69e9a7d4-e12d-4d4d-8118-4b926c829c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991074917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2991074917
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3817774669
Short name T132
Test name
Test status
Simulation time 24148483 ps
CPU time 0.8 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:34:03 PM PDT 24
Peak memory 206024 kb
Host smart-7fbe876c-751d-40b8-b981-4f79e0c03b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817774669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3817774669
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3341843421
Short name T946
Test name
Test status
Simulation time 110018545 ps
CPU time 2.74 seconds
Started Aug 15 04:34:05 PM PDT 24
Finished Aug 15 04:34:08 PM PDT 24
Peak memory 232664 kb
Host smart-27ce8a04-77bb-49c3-a1b8-8676f7caeff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341843421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3341843421
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3253160955
Short name T75
Test name
Test status
Simulation time 38332529 ps
CPU time 0.71 seconds
Started Aug 15 04:34:05 PM PDT 24
Finished Aug 15 04:34:05 PM PDT 24
Peak memory 205364 kb
Host smart-711048d2-2948-41b0-be9b-aae927b34d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253160955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3253160955
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2050688617
Short name T796
Test name
Test status
Simulation time 169626552 ps
CPU time 3.19 seconds
Started Aug 15 04:34:04 PM PDT 24
Finished Aug 15 04:34:07 PM PDT 24
Peak memory 224564 kb
Host smart-82b6f5a0-a751-41e3-a943-505780ca101f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050688617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2050688617
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3682894376
Short name T419
Test name
Test status
Simulation time 47914365 ps
CPU time 0.81 seconds
Started Aug 15 04:34:05 PM PDT 24
Finished Aug 15 04:34:05 PM PDT 24
Peak memory 206428 kb
Host smart-cf0b8e1d-763c-44f3-99de-de1dc9e32185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682894376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3682894376
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3133940097
Short name T184
Test name
Test status
Simulation time 12957094709 ps
CPU time 129.08 seconds
Started Aug 15 04:34:06 PM PDT 24
Finished Aug 15 04:36:15 PM PDT 24
Peak memory 249160 kb
Host smart-10296100-819e-4596-b2da-dd20fd484227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133940097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3133940097
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3752633552
Short name T315
Test name
Test status
Simulation time 81264247586 ps
CPU time 159.48 seconds
Started Aug 15 04:34:04 PM PDT 24
Finished Aug 15 04:36:43 PM PDT 24
Peak memory 262828 kb
Host smart-4d8f6664-982c-4a13-9d63-3c34e988e265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752633552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3752633552
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1575417899
Short name T275
Test name
Test status
Simulation time 18191537743 ps
CPU time 119.34 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:36:02 PM PDT 24
Peak memory 265284 kb
Host smart-9602176f-55d5-4325-ab91-bd6bbb5f7c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575417899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1575417899
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3595282273
Short name T300
Test name
Test status
Simulation time 196356976 ps
CPU time 7.79 seconds
Started Aug 15 04:34:05 PM PDT 24
Finished Aug 15 04:34:13 PM PDT 24
Peak memory 232720 kb
Host smart-b58bd29d-a972-4b7a-a890-7c9c60c3c9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595282273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3595282273
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.763704884
Short name T220
Test name
Test status
Simulation time 53223904773 ps
CPU time 221.22 seconds
Started Aug 15 04:34:03 PM PDT 24
Finished Aug 15 04:37:44 PM PDT 24
Peak memory 256560 kb
Host smart-7f7fcbf4-0383-49c1-84b9-1e2b1a9e8e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763704884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.763704884
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2664724670
Short name T854
Test name
Test status
Simulation time 107197433 ps
CPU time 2.28 seconds
Started Aug 15 04:34:03 PM PDT 24
Finished Aug 15 04:34:06 PM PDT 24
Peak memory 224492 kb
Host smart-968718ac-c353-4cc9-8cb7-bf79b2d9b141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664724670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2664724670
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2714704315
Short name T357
Test name
Test status
Simulation time 7530825204 ps
CPU time 23.83 seconds
Started Aug 15 04:34:03 PM PDT 24
Finished Aug 15 04:34:27 PM PDT 24
Peak memory 232752 kb
Host smart-b2a5cb24-d10e-44f7-b62b-2a20c89add91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714704315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2714704315
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1091940939
Short name T542
Test name
Test status
Simulation time 1576772352 ps
CPU time 7.87 seconds
Started Aug 15 04:34:04 PM PDT 24
Finished Aug 15 04:34:12 PM PDT 24
Peak memory 224452 kb
Host smart-43a800c1-5a69-4b21-b6c5-61b505f2b73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091940939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1091940939
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4014141769
Short name T583
Test name
Test status
Simulation time 4924215096 ps
CPU time 16.46 seconds
Started Aug 15 04:34:03 PM PDT 24
Finished Aug 15 04:34:20 PM PDT 24
Peak memory 236328 kb
Host smart-0ec5d456-a6c7-46c2-b800-a86e757e5090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014141769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4014141769
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1272714178
Short name T567
Test name
Test status
Simulation time 2252294873 ps
CPU time 8.38 seconds
Started Aug 15 04:34:05 PM PDT 24
Finished Aug 15 04:34:14 PM PDT 24
Peak memory 222816 kb
Host smart-92273060-a1ed-4867-b43f-1b81fa04b86f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1272714178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1272714178
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1591353822
Short name T159
Test name
Test status
Simulation time 3212187432 ps
CPU time 83.37 seconds
Started Aug 15 04:34:05 PM PDT 24
Finished Aug 15 04:35:28 PM PDT 24
Peak memory 254580 kb
Host smart-58ed9d5d-2a17-4318-9988-c54cd33b73db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591353822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1591353822
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1343226849
Short name T311
Test name
Test status
Simulation time 50961296655 ps
CPU time 30.77 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:34:33 PM PDT 24
Peak memory 216476 kb
Host smart-0d7415c4-41e8-415d-87ef-afb119d43cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343226849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1343226849
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4097140789
Short name T731
Test name
Test status
Simulation time 5690456247 ps
CPU time 17.15 seconds
Started Aug 15 04:34:06 PM PDT 24
Finished Aug 15 04:34:23 PM PDT 24
Peak memory 216432 kb
Host smart-67a88852-337d-44bf-9592-b831597d7a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097140789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4097140789
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3522529243
Short name T513
Test name
Test status
Simulation time 24155112 ps
CPU time 1.47 seconds
Started Aug 15 04:34:06 PM PDT 24
Finished Aug 15 04:34:08 PM PDT 24
Peak memory 216308 kb
Host smart-b958d43d-f131-494f-be76-9503c71e84b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522529243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3522529243
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3979735905
Short name T452
Test name
Test status
Simulation time 131885107 ps
CPU time 0.9 seconds
Started Aug 15 04:34:02 PM PDT 24
Finished Aug 15 04:34:03 PM PDT 24
Peak memory 205928 kb
Host smart-6950992d-83c4-42d1-a69e-96a8415d7dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979735905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3979735905
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4027723939
Short name T901
Test name
Test status
Simulation time 2760094619 ps
CPU time 6.83 seconds
Started Aug 15 04:34:03 PM PDT 24
Finished Aug 15 04:34:10 PM PDT 24
Peak memory 232704 kb
Host smart-3242b255-08aa-4387-9318-8f85eb31a2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027723939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4027723939
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.358158054
Short name T67
Test name
Test status
Simulation time 22518756 ps
CPU time 0.71 seconds
Started Aug 15 04:34:09 PM PDT 24
Finished Aug 15 04:34:10 PM PDT 24
Peak memory 204816 kb
Host smart-d0fd781b-4d99-4315-b1ee-1a7d12f069ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358158054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.358158054
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1825492162
Short name T975
Test name
Test status
Simulation time 8104985514 ps
CPU time 6.49 seconds
Started Aug 15 04:34:09 PM PDT 24
Finished Aug 15 04:34:16 PM PDT 24
Peak memory 224632 kb
Host smart-beadfdba-c671-4069-a114-5c20175eef65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825492162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1825492162
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.960540066
Short name T710
Test name
Test status
Simulation time 43744734 ps
CPU time 0.87 seconds
Started Aug 15 04:34:05 PM PDT 24
Finished Aug 15 04:34:06 PM PDT 24
Peak memory 206408 kb
Host smart-ee6d38b5-9109-4ffc-8d9c-afdfa54e131c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960540066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.960540066
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2720850300
Short name T641
Test name
Test status
Simulation time 13545563251 ps
CPU time 106.46 seconds
Started Aug 15 04:34:12 PM PDT 24
Finished Aug 15 04:35:58 PM PDT 24
Peak memory 249152 kb
Host smart-5e4c4e88-f149-4545-bea1-b890e9a43447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720850300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2720850300
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.26548078
Short name T510
Test name
Test status
Simulation time 16613238828 ps
CPU time 129.11 seconds
Started Aug 15 04:34:19 PM PDT 24
Finished Aug 15 04:36:28 PM PDT 24
Peak memory 248708 kb
Host smart-9ae6593b-ea25-4e5c-859e-8e381b6468eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26548078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.26548078
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2518281300
Short name T503
Test name
Test status
Simulation time 15349786951 ps
CPU time 163.9 seconds
Started Aug 15 04:34:13 PM PDT 24
Finished Aug 15 04:36:57 PM PDT 24
Peak memory 249352 kb
Host smart-d6dd7db2-ca07-4db3-a6ee-e2fe7439f9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518281300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2518281300
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3385676342
Short name T524
Test name
Test status
Simulation time 873098798 ps
CPU time 5.72 seconds
Started Aug 15 04:34:16 PM PDT 24
Finished Aug 15 04:34:22 PM PDT 24
Peak memory 224496 kb
Host smart-f3fb8eb8-bb12-488e-9dc0-9b5095baeac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385676342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3385676342
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3226292243
Short name T864
Test name
Test status
Simulation time 23076676065 ps
CPU time 121.37 seconds
Started Aug 15 04:34:15 PM PDT 24
Finished Aug 15 04:36:16 PM PDT 24
Peak memory 250840 kb
Host smart-0a6732f5-f0e7-484e-94df-49c541c5828d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226292243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3226292243
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.281415418
Short name T90
Test name
Test status
Simulation time 5462846925 ps
CPU time 5.49 seconds
Started Aug 15 04:34:12 PM PDT 24
Finished Aug 15 04:34:18 PM PDT 24
Peak memory 232740 kb
Host smart-a6761d56-93dd-4c32-a518-bd127c7b34a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281415418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.281415418
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1847014044
Short name T774
Test name
Test status
Simulation time 133401925 ps
CPU time 3.17 seconds
Started Aug 15 04:34:11 PM PDT 24
Finished Aug 15 04:34:15 PM PDT 24
Peak memory 232800 kb
Host smart-1c7dfd7e-1435-4c94-8228-0e0553ff489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847014044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1847014044
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3272142858
Short name T917
Test name
Test status
Simulation time 311554368 ps
CPU time 3.68 seconds
Started Aug 15 04:34:11 PM PDT 24
Finished Aug 15 04:34:14 PM PDT 24
Peak memory 232672 kb
Host smart-ada85afb-c9be-4db7-9fe0-577b0d36a766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272142858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3272142858
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2649807934
Short name T744
Test name
Test status
Simulation time 2904887472 ps
CPU time 10.29 seconds
Started Aug 15 04:34:11 PM PDT 24
Finished Aug 15 04:34:21 PM PDT 24
Peak memory 248708 kb
Host smart-24d8cb5b-9ac3-4708-9211-2fea9ac9fcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649807934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2649807934
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.853211627
Short name T1004
Test name
Test status
Simulation time 352059344 ps
CPU time 3.62 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:22 PM PDT 24
Peak memory 219972 kb
Host smart-686fbb3e-2426-4a91-ba1c-db1ace9f5019
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=853211627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.853211627
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1089490411
Short name T19
Test name
Test status
Simulation time 65045441733 ps
CPU time 148.54 seconds
Started Aug 15 04:34:13 PM PDT 24
Finished Aug 15 04:36:42 PM PDT 24
Peak memory 241052 kb
Host smart-a5694de8-2ff9-4fc8-aaf6-e49104e2cd1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089490411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1089490411
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1001573494
Short name T304
Test name
Test status
Simulation time 17147495156 ps
CPU time 20.73 seconds
Started Aug 15 04:33:59 PM PDT 24
Finished Aug 15 04:34:20 PM PDT 24
Peak memory 216344 kb
Host smart-23206c3e-4749-4013-ba59-3332d14c92b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001573494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1001573494
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.4253546638
Short name T74
Test name
Test status
Simulation time 32769706075 ps
CPU time 15.74 seconds
Started Aug 15 04:34:05 PM PDT 24
Finished Aug 15 04:34:21 PM PDT 24
Peak memory 216316 kb
Host smart-8b81590b-bc13-42cf-8bd8-307d6591de58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253546638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.4253546638
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1422570383
Short name T637
Test name
Test status
Simulation time 89722748 ps
CPU time 3.49 seconds
Started Aug 15 04:34:11 PM PDT 24
Finished Aug 15 04:34:15 PM PDT 24
Peak memory 216228 kb
Host smart-a4048a21-384b-49a3-b11f-0fcc3da5e419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422570383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1422570383
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.178491674
Short name T496
Test name
Test status
Simulation time 449068668 ps
CPU time 0.84 seconds
Started Aug 15 04:34:06 PM PDT 24
Finished Aug 15 04:34:07 PM PDT 24
Peak memory 205888 kb
Host smart-7a5f22d3-c361-466b-9236-3051e5c430b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178491674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.178491674
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3894609187
Short name T439
Test name
Test status
Simulation time 438999551 ps
CPU time 2.08 seconds
Started Aug 15 04:34:12 PM PDT 24
Finished Aug 15 04:34:14 PM PDT 24
Peak memory 224028 kb
Host smart-b921980a-8c45-4372-98cf-9a4bf9b5eb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894609187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3894609187
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4083393325
Short name T971
Test name
Test status
Simulation time 15161365 ps
CPU time 0.73 seconds
Started Aug 15 04:34:14 PM PDT 24
Finished Aug 15 04:34:15 PM PDT 24
Peak memory 205360 kb
Host smart-bc46a423-f432-40c1-8d35-a11e6da8e299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083393325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4083393325
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1711710232
Short name T384
Test name
Test status
Simulation time 131826863 ps
CPU time 2.47 seconds
Started Aug 15 04:34:11 PM PDT 24
Finished Aug 15 04:34:14 PM PDT 24
Peak memory 232620 kb
Host smart-03e63d1c-5e98-431d-9b6f-6715b2e3e3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711710232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1711710232
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1033501852
Short name T604
Test name
Test status
Simulation time 63307110 ps
CPU time 0.77 seconds
Started Aug 15 04:34:20 PM PDT 24
Finished Aug 15 04:34:21 PM PDT 24
Peak memory 206752 kb
Host smart-1a010f85-b08f-4439-982e-de679e74005d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033501852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1033501852
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2501402449
Short name T235
Test name
Test status
Simulation time 11499397180 ps
CPU time 94.28 seconds
Started Aug 15 04:34:11 PM PDT 24
Finished Aug 15 04:35:46 PM PDT 24
Peak memory 254408 kb
Host smart-5b271a82-4bb9-48c4-82c3-eb34f6864893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501402449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2501402449
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1912417718
Short name T206
Test name
Test status
Simulation time 8498377040 ps
CPU time 119.77 seconds
Started Aug 15 04:34:21 PM PDT 24
Finished Aug 15 04:36:21 PM PDT 24
Peak memory 257192 kb
Host smart-f6616d17-b9b4-47f3-a900-78d0a4439a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912417718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1912417718
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1824330230
Short name T665
Test name
Test status
Simulation time 57187376354 ps
CPU time 152.19 seconds
Started Aug 15 04:34:12 PM PDT 24
Finished Aug 15 04:36:44 PM PDT 24
Peak memory 249204 kb
Host smart-6d1debe7-fdc6-4210-862b-bc14cc08fb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824330230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1824330230
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.477435755
Short name T931
Test name
Test status
Simulation time 1010456410 ps
CPU time 6.55 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:24 PM PDT 24
Peak memory 232820 kb
Host smart-edc7c573-5673-49dd-9a46-e033d05338a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477435755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.477435755
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2000077606
Short name T801
Test name
Test status
Simulation time 22216656093 ps
CPU time 113.96 seconds
Started Aug 15 04:34:17 PM PDT 24
Finished Aug 15 04:36:11 PM PDT 24
Peak memory 254168 kb
Host smart-6044c81d-a83c-4519-81aa-bce48cf29370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000077606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2000077606
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.492560548
Short name T225
Test name
Test status
Simulation time 1150540714 ps
CPU time 8.19 seconds
Started Aug 15 04:34:11 PM PDT 24
Finished Aug 15 04:34:19 PM PDT 24
Peak memory 232668 kb
Host smart-be62ebe0-e691-493d-86ea-4e977cd4e295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492560548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.492560548
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2315742190
Short name T385
Test name
Test status
Simulation time 75822493 ps
CPU time 2.32 seconds
Started Aug 15 04:34:14 PM PDT 24
Finished Aug 15 04:34:16 PM PDT 24
Peak memory 223196 kb
Host smart-aee370ee-dc2c-4083-8c73-4bb6c069d177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315742190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2315742190
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.986989245
Short name T351
Test name
Test status
Simulation time 166801008 ps
CPU time 2.61 seconds
Started Aug 15 04:34:15 PM PDT 24
Finished Aug 15 04:34:18 PM PDT 24
Peak memory 224500 kb
Host smart-da875c6c-e206-41d8-aef3-24a574a985bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986989245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.986989245
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1389494731
Short name T871
Test name
Test status
Simulation time 50088816393 ps
CPU time 11.48 seconds
Started Aug 15 04:34:13 PM PDT 24
Finished Aug 15 04:34:24 PM PDT 24
Peak memory 232752 kb
Host smart-a751f3e3-0253-4650-acd6-ccee2bc8d877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389494731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1389494731
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.994290705
Short name T814
Test name
Test status
Simulation time 980557610 ps
CPU time 5.58 seconds
Started Aug 15 04:34:15 PM PDT 24
Finished Aug 15 04:34:20 PM PDT 24
Peak memory 220568 kb
Host smart-5bf48382-e053-480e-ae84-7874ffdefc98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=994290705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.994290705
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3971705000
Short name T23
Test name
Test status
Simulation time 17177007511 ps
CPU time 15.01 seconds
Started Aug 15 04:34:14 PM PDT 24
Finished Aug 15 04:34:29 PM PDT 24
Peak memory 217524 kb
Host smart-5f17bc91-9606-40fc-8dff-00392b7673c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971705000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3971705000
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1418689137
Short name T133
Test name
Test status
Simulation time 983481836 ps
CPU time 12.19 seconds
Started Aug 15 04:34:20 PM PDT 24
Finished Aug 15 04:34:32 PM PDT 24
Peak memory 218952 kb
Host smart-1e622efd-bb43-4564-a33d-4638a958bc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418689137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1418689137
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3669205458
Short name T323
Test name
Test status
Simulation time 1748678436 ps
CPU time 1.76 seconds
Started Aug 15 04:34:12 PM PDT 24
Finished Aug 15 04:34:14 PM PDT 24
Peak memory 207872 kb
Host smart-216abf45-6e9b-40bf-906c-7a65651eb786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669205458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3669205458
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1000314918
Short name T688
Test name
Test status
Simulation time 22855815 ps
CPU time 1.26 seconds
Started Aug 15 04:34:10 PM PDT 24
Finished Aug 15 04:34:12 PM PDT 24
Peak memory 216288 kb
Host smart-41dc34ee-e858-4392-ae32-a416194ca78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000314918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1000314918
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3877904278
Short name T539
Test name
Test status
Simulation time 57747711 ps
CPU time 0.68 seconds
Started Aug 15 04:34:15 PM PDT 24
Finished Aug 15 04:34:15 PM PDT 24
Peak memory 205468 kb
Host smart-fac71d7e-fd52-4867-b86b-0964e3e674ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877904278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3877904278
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3883960651
Short name T613
Test name
Test status
Simulation time 701508579 ps
CPU time 6.98 seconds
Started Aug 15 04:34:21 PM PDT 24
Finished Aug 15 04:34:28 PM PDT 24
Peak memory 238784 kb
Host smart-7e61d37b-e143-4fff-83db-540808478fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883960651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3883960651
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2537845907
Short name T759
Test name
Test status
Simulation time 28531059 ps
CPU time 0.81 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:19 PM PDT 24
Peak memory 204744 kb
Host smart-821b4cfa-457b-4f8f-b03e-d1f5de8171fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537845907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2537845907
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.874711892
Short name T527
Test name
Test status
Simulation time 537878433 ps
CPU time 7.67 seconds
Started Aug 15 04:34:16 PM PDT 24
Finished Aug 15 04:34:23 PM PDT 24
Peak memory 224468 kb
Host smart-bbb02c27-7db5-446c-b89e-48f6845ceb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874711892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.874711892
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3671594141
Short name T575
Test name
Test status
Simulation time 19675857 ps
CPU time 0.82 seconds
Started Aug 15 04:34:09 PM PDT 24
Finished Aug 15 04:34:10 PM PDT 24
Peak memory 206796 kb
Host smart-99be80ae-2028-4183-8c01-e1144b9431d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671594141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3671594141
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2316768693
Short name T640
Test name
Test status
Simulation time 26165909400 ps
CPU time 190.62 seconds
Started Aug 15 04:34:23 PM PDT 24
Finished Aug 15 04:37:34 PM PDT 24
Peak memory 249124 kb
Host smart-74a28efa-ec19-46ce-996b-df51a3c9a718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316768693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2316768693
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3698503109
Short name T988
Test name
Test status
Simulation time 12170388815 ps
CPU time 114.84 seconds
Started Aug 15 04:34:17 PM PDT 24
Finished Aug 15 04:36:12 PM PDT 24
Peak memory 249252 kb
Host smart-cb639185-f65a-49cf-a591-22ea28e605be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698503109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3698503109
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2698401128
Short name T593
Test name
Test status
Simulation time 2931160049 ps
CPU time 78.84 seconds
Started Aug 15 04:34:21 PM PDT 24
Finished Aug 15 04:35:40 PM PDT 24
Peak memory 257528 kb
Host smart-6cc554db-38ab-40ed-a63e-5ce45d5463c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698401128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2698401128
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3075658323
Short name T59
Test name
Test status
Simulation time 2356044168 ps
CPU time 29.23 seconds
Started Aug 15 04:34:24 PM PDT 24
Finished Aug 15 04:34:53 PM PDT 24
Peak memory 233844 kb
Host smart-fe2ece17-4138-4783-aa5d-6a3d4d02c0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075658323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3075658323
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.46936325
Short name T651
Test name
Test status
Simulation time 24124486710 ps
CPU time 104.67 seconds
Started Aug 15 04:34:20 PM PDT 24
Finished Aug 15 04:36:05 PM PDT 24
Peak memory 252812 kb
Host smart-f3193338-cad7-4c1f-9baa-dc41c633974e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46936325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.46936325
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3325450428
Short name T982
Test name
Test status
Simulation time 3296526997 ps
CPU time 11.01 seconds
Started Aug 15 04:34:20 PM PDT 24
Finished Aug 15 04:34:41 PM PDT 24
Peak memory 224596 kb
Host smart-5bd8bd28-0720-4cbc-b65a-d6f2edf3d61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325450428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3325450428
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2352132272
Short name T1020
Test name
Test status
Simulation time 7888591650 ps
CPU time 29.44 seconds
Started Aug 15 04:34:16 PM PDT 24
Finished Aug 15 04:34:45 PM PDT 24
Peak memory 232740 kb
Host smart-8f861aa7-6307-4723-ade5-38412b7161ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352132272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2352132272
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.555309839
Short name T168
Test name
Test status
Simulation time 1047593817 ps
CPU time 9.53 seconds
Started Aug 15 04:34:19 PM PDT 24
Finished Aug 15 04:34:29 PM PDT 24
Peak memory 240752 kb
Host smart-08d28043-9834-4c39-a828-7036b0c8d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555309839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.555309839
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2216952126
Short name T642
Test name
Test status
Simulation time 9094867805 ps
CPU time 19.28 seconds
Started Aug 15 04:34:22 PM PDT 24
Finished Aug 15 04:34:41 PM PDT 24
Peak memory 233548 kb
Host smart-b2575ad0-3a6b-4412-b249-712c88a4a57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216952126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2216952126
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.218270182
Short name T729
Test name
Test status
Simulation time 2464996155 ps
CPU time 4.78 seconds
Started Aug 15 04:34:23 PM PDT 24
Finished Aug 15 04:34:28 PM PDT 24
Peak memory 220616 kb
Host smart-8df97a08-8e7f-4955-a456-59e1ad71e160
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=218270182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.218270182
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2796779192
Short name T36
Test name
Test status
Simulation time 14424576900 ps
CPU time 19.9 seconds
Started Aug 15 04:34:09 PM PDT 24
Finished Aug 15 04:34:29 PM PDT 24
Peak memory 216308 kb
Host smart-6bd70ac3-2803-456b-9c97-3c1342104a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796779192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2796779192
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.154362337
Short name T508
Test name
Test status
Simulation time 1754937809 ps
CPU time 4.99 seconds
Started Aug 15 04:34:19 PM PDT 24
Finished Aug 15 04:34:24 PM PDT 24
Peak memory 215912 kb
Host smart-7e4e30ad-6ce2-459b-bbd3-2f7ac761ffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154362337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.154362337
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2789412571
Short name T681
Test name
Test status
Simulation time 959650305 ps
CPU time 2.35 seconds
Started Aug 15 04:34:36 PM PDT 24
Finished Aug 15 04:34:39 PM PDT 24
Peak memory 216288 kb
Host smart-7aab6e14-78d4-4e8a-a76e-f8e2ac9a0194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789412571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2789412571
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2854774779
Short name T381
Test name
Test status
Simulation time 129610011 ps
CPU time 0.87 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:19 PM PDT 24
Peak memory 205888 kb
Host smart-4a8ea414-74c6-41db-b598-5e0fe8d519dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854774779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2854774779
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2928159584
Short name T788
Test name
Test status
Simulation time 50457920870 ps
CPU time 34.83 seconds
Started Aug 15 04:34:20 PM PDT 24
Finished Aug 15 04:34:55 PM PDT 24
Peak memory 233760 kb
Host smart-ad84ae99-e8ca-4923-b5b7-f304d37dcb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928159584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2928159584
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.96162790
Short name T978
Test name
Test status
Simulation time 12290232 ps
CPU time 0.75 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:19 PM PDT 24
Peak memory 204840 kb
Host smart-47cfa0aa-352f-4050-9615-816e887531b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96162790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.96162790
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.150938473
Short name T860
Test name
Test status
Simulation time 446235255 ps
CPU time 3.25 seconds
Started Aug 15 04:34:19 PM PDT 24
Finished Aug 15 04:34:22 PM PDT 24
Peak memory 224424 kb
Host smart-d53456dc-7b09-454f-b8f3-17537ea4853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150938473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.150938473
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3519112302
Short name T597
Test name
Test status
Simulation time 33276808 ps
CPU time 0.76 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:19 PM PDT 24
Peak memory 205404 kb
Host smart-a9999bf2-c6a1-4e69-bfe2-2f28ddb8050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519112302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3519112302
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2046899301
Short name T884
Test name
Test status
Simulation time 907255314 ps
CPU time 15.83 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:34 PM PDT 24
Peak memory 249096 kb
Host smart-fc005957-be6f-4e7f-9b64-2ff5ac9ad2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046899301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2046899301
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.4178578989
Short name T692
Test name
Test status
Simulation time 2409510511 ps
CPU time 44.27 seconds
Started Aug 15 04:34:17 PM PDT 24
Finished Aug 15 04:35:01 PM PDT 24
Peak memory 249140 kb
Host smart-f1f45b56-cd37-4ab8-a1e0-b0cca1226f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178578989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.4178578989
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3524258818
Short name T65
Test name
Test status
Simulation time 65081969863 ps
CPU time 132.89 seconds
Started Aug 15 04:34:19 PM PDT 24
Finished Aug 15 04:36:32 PM PDT 24
Peak memory 249208 kb
Host smart-0f310c46-bc26-443a-be0a-4f80bb8920de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524258818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3524258818
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.4290377728
Short name T390
Test name
Test status
Simulation time 1221169267 ps
CPU time 21.22 seconds
Started Aug 15 04:34:21 PM PDT 24
Finished Aug 15 04:34:42 PM PDT 24
Peak memory 251520 kb
Host smart-ca0e8143-a6d1-4eac-b1ed-b47a5dbf86d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290377728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4290377728
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1071734099
Short name T226
Test name
Test status
Simulation time 30448500718 ps
CPU time 56.82 seconds
Started Aug 15 04:34:16 PM PDT 24
Finished Aug 15 04:35:13 PM PDT 24
Peak memory 232692 kb
Host smart-ff55c646-84c0-409f-96dd-8f58121fa737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071734099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1071734099
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3089522612
Short name T429
Test name
Test status
Simulation time 6199357689 ps
CPU time 17.01 seconds
Started Aug 15 04:34:22 PM PDT 24
Finished Aug 15 04:34:39 PM PDT 24
Peak memory 232868 kb
Host smart-db079a65-31b7-4695-bf0d-9c6d64192779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089522612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3089522612
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1190490205
Short name T765
Test name
Test status
Simulation time 964395076 ps
CPU time 12.13 seconds
Started Aug 15 04:34:16 PM PDT 24
Finished Aug 15 04:34:28 PM PDT 24
Peak memory 232684 kb
Host smart-e960159a-5d5c-4a98-a86e-64294b89d04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190490205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1190490205
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2962794888
Short name T535
Test name
Test status
Simulation time 270069736 ps
CPU time 4.37 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:23 PM PDT 24
Peak memory 224592 kb
Host smart-187d8c37-ef8f-41c7-ba1e-56e7890f1a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962794888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2962794888
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3701934037
Short name T397
Test name
Test status
Simulation time 32898147 ps
CPU time 2.28 seconds
Started Aug 15 04:34:21 PM PDT 24
Finished Aug 15 04:34:23 PM PDT 24
Peak memory 232312 kb
Host smart-6a20944f-aea4-4177-a53a-a8ff6b35b084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701934037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3701934037
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2866755987
Short name T363
Test name
Test status
Simulation time 161200685 ps
CPU time 3.77 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:22 PM PDT 24
Peak memory 219776 kb
Host smart-7caea2fc-4517-4e71-97bf-1e89f3f10e9b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2866755987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2866755987
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.101836502
Short name T15
Test name
Test status
Simulation time 39464396726 ps
CPU time 52.46 seconds
Started Aug 15 04:34:24 PM PDT 24
Finished Aug 15 04:35:18 PM PDT 24
Peak memory 239928 kb
Host smart-a0f91e43-d77f-4ceb-823b-5ee134f0b7c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101836502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.101836502
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1056784254
Short name T672
Test name
Test status
Simulation time 1065625902 ps
CPU time 8.56 seconds
Started Aug 15 04:34:20 PM PDT 24
Finished Aug 15 04:34:29 PM PDT 24
Peak memory 216256 kb
Host smart-861e4e33-2fd0-499e-bcab-2a369318a759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056784254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1056784254
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1113928978
Short name T1006
Test name
Test status
Simulation time 5513889504 ps
CPU time 7.73 seconds
Started Aug 15 04:34:20 PM PDT 24
Finished Aug 15 04:34:28 PM PDT 24
Peak memory 216328 kb
Host smart-afda3fff-fee2-4bda-9ed8-951ebac3e125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113928978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1113928978
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.611437080
Short name T590
Test name
Test status
Simulation time 2183017449 ps
CPU time 2.81 seconds
Started Aug 15 04:34:29 PM PDT 24
Finished Aug 15 04:34:32 PM PDT 24
Peak memory 216360 kb
Host smart-c32c70fa-99a9-4754-b309-f91e12b3a9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611437080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.611437080
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3032006675
Short name T317
Test name
Test status
Simulation time 23298850 ps
CPU time 0.72 seconds
Started Aug 15 04:34:24 PM PDT 24
Finished Aug 15 04:34:24 PM PDT 24
Peak memory 205960 kb
Host smart-f6795fbf-ae68-4ae9-a434-d8efe46cfc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032006675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3032006675
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3600519619
Short name T739
Test name
Test status
Simulation time 733731674 ps
CPU time 5 seconds
Started Aug 15 04:34:24 PM PDT 24
Finished Aug 15 04:34:29 PM PDT 24
Peak memory 240380 kb
Host smart-1ba63235-d222-4c80-a599-3ac7624cc432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600519619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3600519619
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.666706364
Short name T740
Test name
Test status
Simulation time 38467889 ps
CPU time 0.78 seconds
Started Aug 15 04:34:21 PM PDT 24
Finished Aug 15 04:34:22 PM PDT 24
Peak memory 205320 kb
Host smart-2b1d33a1-f696-4ae9-a15b-aeaa998b7a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666706364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.666706364
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.861346695
Short name T703
Test name
Test status
Simulation time 1176831320 ps
CPU time 3.62 seconds
Started Aug 15 04:34:20 PM PDT 24
Finished Aug 15 04:34:24 PM PDT 24
Peak memory 224452 kb
Host smart-c8f58a8e-c168-4a99-89f9-5c9d6c57d2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861346695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.861346695
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.823256826
Short name T760
Test name
Test status
Simulation time 21535503 ps
CPU time 0.78 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:19 PM PDT 24
Peak memory 205816 kb
Host smart-db32ab12-0827-4616-9216-fe54e574ce1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823256826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.823256826
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2440817917
Short name T934
Test name
Test status
Simulation time 104098586528 ps
CPU time 123.48 seconds
Started Aug 15 04:34:20 PM PDT 24
Finished Aug 15 04:36:24 PM PDT 24
Peak memory 254760 kb
Host smart-d9b83b1b-8167-4195-befd-f65c6fff75ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440817917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2440817917
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1794940596
Short name T976
Test name
Test status
Simulation time 80804049 ps
CPU time 2.84 seconds
Started Aug 15 04:34:24 PM PDT 24
Finished Aug 15 04:34:27 PM PDT 24
Peak memory 232692 kb
Host smart-c7630ab7-0741-4ce4-a44f-9e8e9c6e406b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794940596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1794940596
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3701845305
Short name T477
Test name
Test status
Simulation time 6175635063 ps
CPU time 38.75 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:57 PM PDT 24
Peak memory 265544 kb
Host smart-d4ce7b69-9bfb-40bf-946f-9db5c9da3963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701845305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3701845305
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.900142133
Short name T663
Test name
Test status
Simulation time 102558070 ps
CPU time 2.11 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:20 PM PDT 24
Peak memory 223068 kb
Host smart-bfc6623c-24a4-4148-83fb-8ff8fa7368e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900142133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.900142133
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2059992959
Short name T907
Test name
Test status
Simulation time 1113134044 ps
CPU time 9.42 seconds
Started Aug 15 04:34:23 PM PDT 24
Finished Aug 15 04:34:33 PM PDT 24
Peak memory 224532 kb
Host smart-ee42fb50-42c3-4a8c-b461-c54dc0d6bb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059992959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2059992959
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3555105888
Short name T509
Test name
Test status
Simulation time 591509587 ps
CPU time 6.22 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:25 PM PDT 24
Peak memory 232688 kb
Host smart-18d066de-51c7-427a-915c-c735bf56dda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555105888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3555105888
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.249730655
Short name T690
Test name
Test status
Simulation time 10407106904 ps
CPU time 27.02 seconds
Started Aug 15 04:34:17 PM PDT 24
Finished Aug 15 04:34:45 PM PDT 24
Peak memory 224564 kb
Host smart-003b10a6-0a14-409d-acfe-412895dc0a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249730655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.249730655
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3980634768
Short name T391
Test name
Test status
Simulation time 8843433791 ps
CPU time 13.22 seconds
Started Aug 15 04:34:22 PM PDT 24
Finished Aug 15 04:34:35 PM PDT 24
Peak memory 223068 kb
Host smart-50e62540-07c8-423b-9eec-51c22c49cbf4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3980634768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3980634768
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2918601442
Short name T154
Test name
Test status
Simulation time 503190031 ps
CPU time 0.89 seconds
Started Aug 15 04:34:25 PM PDT 24
Finished Aug 15 04:34:26 PM PDT 24
Peak memory 205420 kb
Host smart-6de49554-3ecd-4428-942b-c7520f3ea07d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918601442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2918601442
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2518155221
Short name T571
Test name
Test status
Simulation time 4367134071 ps
CPU time 15.09 seconds
Started Aug 15 04:34:19 PM PDT 24
Finished Aug 15 04:34:34 PM PDT 24
Peak memory 216408 kb
Host smart-24b4b3bb-eafe-48ec-9240-69d1f997ddbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518155221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2518155221
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.557044414
Short name T362
Test name
Test status
Simulation time 36153302 ps
CPU time 0.71 seconds
Started Aug 15 04:34:17 PM PDT 24
Finished Aug 15 04:34:18 PM PDT 24
Peak memory 205504 kb
Host smart-8df9ae07-2076-4374-b87f-aaf147b1b63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557044414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.557044414
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1890448769
Short name T453
Test name
Test status
Simulation time 69414091 ps
CPU time 1.15 seconds
Started Aug 15 04:34:18 PM PDT 24
Finished Aug 15 04:34:20 PM PDT 24
Peak memory 207812 kb
Host smart-1a501917-a540-4c06-8dbe-a6240b303ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890448769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1890448769
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.4203979839
Short name T555
Test name
Test status
Simulation time 89385943 ps
CPU time 0.78 seconds
Started Aug 15 04:34:15 PM PDT 24
Finished Aug 15 04:34:16 PM PDT 24
Peak memory 205940 kb
Host smart-1e7e7349-53e8-4891-8606-619335d417f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203979839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.4203979839
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2651148640
Short name T585
Test name
Test status
Simulation time 446836119 ps
CPU time 5.82 seconds
Started Aug 15 04:34:26 PM PDT 24
Finished Aug 15 04:34:32 PM PDT 24
Peak memory 224536 kb
Host smart-0cb0a6ed-9ba5-4767-95b5-7a7dfdf2e8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651148640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2651148640
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2765425285
Short name T916
Test name
Test status
Simulation time 23604037 ps
CPU time 0.73 seconds
Started Aug 15 04:32:03 PM PDT 24
Finished Aug 15 04:32:04 PM PDT 24
Peak memory 204872 kb
Host smart-18240452-d5f5-4844-a3d8-ab6e5893a30a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765425285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
765425285
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.361937282
Short name T661
Test name
Test status
Simulation time 99949922 ps
CPU time 2.24 seconds
Started Aug 15 04:32:02 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 224520 kb
Host smart-a2e7c833-a645-4cad-9446-87f999814d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361937282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.361937282
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1056677331
Short name T516
Test name
Test status
Simulation time 59860860 ps
CPU time 0.84 seconds
Started Aug 15 04:32:00 PM PDT 24
Finished Aug 15 04:32:01 PM PDT 24
Peak memory 205392 kb
Host smart-2fde1215-1097-4654-9d6e-fcc4e301d6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056677331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1056677331
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3519375975
Short name T611
Test name
Test status
Simulation time 38120777376 ps
CPU time 114.82 seconds
Started Aug 15 04:32:02 PM PDT 24
Finished Aug 15 04:33:57 PM PDT 24
Peak memory 257352 kb
Host smart-489ba8fd-a15c-4883-92eb-37110e14a7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519375975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3519375975
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2537672649
Short name T208
Test name
Test status
Simulation time 25434727757 ps
CPU time 94.55 seconds
Started Aug 15 04:32:03 PM PDT 24
Finished Aug 15 04:33:38 PM PDT 24
Peak memory 253464 kb
Host smart-d8190222-3f6f-468e-bbe5-d2c6d48a32e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537672649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2537672649
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3215385641
Short name T197
Test name
Test status
Simulation time 17738783218 ps
CPU time 69.83 seconds
Started Aug 15 04:32:02 PM PDT 24
Finished Aug 15 04:33:12 PM PDT 24
Peak memory 249220 kb
Host smart-a0a0d9cc-79a7-40ef-b6f6-cebe397f6ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215385641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3215385641
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2654029009
Short name T693
Test name
Test status
Simulation time 7727972673 ps
CPU time 42.25 seconds
Started Aug 15 04:32:02 PM PDT 24
Finished Aug 15 04:32:44 PM PDT 24
Peak memory 232824 kb
Host smart-c8c67f28-94f7-4c56-89cd-121afef215f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654029009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2654029009
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.518734929
Short name T182
Test name
Test status
Simulation time 5638062461 ps
CPU time 73.88 seconds
Started Aug 15 04:32:02 PM PDT 24
Finished Aug 15 04:33:16 PM PDT 24
Peak memory 249740 kb
Host smart-129c5334-21f2-4f29-a2ca-077b4ca22f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518734929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.
518734929
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3741485152
Short name T27
Test name
Test status
Simulation time 5767538692 ps
CPU time 19.07 seconds
Started Aug 15 04:32:03 PM PDT 24
Finished Aug 15 04:32:22 PM PDT 24
Peak memory 224596 kb
Host smart-b7a82150-a181-4591-ab90-341e2483706d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741485152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3741485152
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3493553995
Short name T994
Test name
Test status
Simulation time 961101042 ps
CPU time 8.58 seconds
Started Aug 15 04:32:05 PM PDT 24
Finished Aug 15 04:32:13 PM PDT 24
Peak memory 232720 kb
Host smart-786b851b-99d1-44e8-808d-cd7a066a420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493553995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3493553995
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.72628644
Short name T588
Test name
Test status
Simulation time 14087026 ps
CPU time 1.05 seconds
Started Aug 15 04:32:01 PM PDT 24
Finished Aug 15 04:32:03 PM PDT 24
Peak memory 216524 kb
Host smart-6f0c0ee3-434e-4159-8954-b23c586547c3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72628644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.72628644
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2452752179
Short name T224
Test name
Test status
Simulation time 4609211263 ps
CPU time 8.8 seconds
Started Aug 15 04:32:01 PM PDT 24
Finished Aug 15 04:32:10 PM PDT 24
Peak memory 232724 kb
Host smart-a2940388-b884-4c08-98d1-7739540bf3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452752179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2452752179
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1287046518
Short name T252
Test name
Test status
Simulation time 1694461386 ps
CPU time 3.43 seconds
Started Aug 15 04:32:05 PM PDT 24
Finished Aug 15 04:32:08 PM PDT 24
Peak memory 232672 kb
Host smart-185b6d4d-df07-4e13-915c-1f1f06bc2289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287046518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1287046518
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4142145897
Short name T822
Test name
Test status
Simulation time 1339959707 ps
CPU time 12.78 seconds
Started Aug 15 04:32:01 PM PDT 24
Finished Aug 15 04:32:14 PM PDT 24
Peak memory 220024 kb
Host smart-663720b4-9946-4d00-bfbe-96c1deee5e40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4142145897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4142145897
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3133091966
Short name T990
Test name
Test status
Simulation time 8619653863 ps
CPU time 44.05 seconds
Started Aug 15 04:32:02 PM PDT 24
Finished Aug 15 04:32:46 PM PDT 24
Peak memory 248736 kb
Host smart-6ef02fe8-fc28-4561-882f-1bfe78547d44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133091966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3133091966
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2510786566
Short name T302
Test name
Test status
Simulation time 5591134934 ps
CPU time 8.15 seconds
Started Aug 15 04:32:03 PM PDT 24
Finished Aug 15 04:32:11 PM PDT 24
Peak memory 216332 kb
Host smart-c3c4cbdc-b28e-4a3f-9f07-4a42a8011d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510786566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2510786566
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3402115947
Short name T999
Test name
Test status
Simulation time 3390446438 ps
CPU time 11.67 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:16 PM PDT 24
Peak memory 216380 kb
Host smart-35e0c4dc-2d86-45c3-bf30-08cdfa2f3b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402115947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3402115947
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.610534214
Short name T852
Test name
Test status
Simulation time 38082827 ps
CPU time 0.71 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 205456 kb
Host smart-35de8adb-d56f-4ca9-af9e-b0f41f5141b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610534214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.610534214
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1634680168
Short name T339
Test name
Test status
Simulation time 290154067 ps
CPU time 0.71 seconds
Started Aug 15 04:32:00 PM PDT 24
Finished Aug 15 04:32:01 PM PDT 24
Peak memory 205944 kb
Host smart-059d0f14-15a8-4800-b271-53251e6bd811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634680168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1634680168
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2636709072
Short name T947
Test name
Test status
Simulation time 7875018577 ps
CPU time 31.59 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:36 PM PDT 24
Peak memory 249204 kb
Host smart-2e236e2b-b714-4845-8862-fb07fcd80dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636709072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2636709072
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2856360181
Short name T686
Test name
Test status
Simulation time 30715245 ps
CPU time 0.7 seconds
Started Aug 15 04:32:09 PM PDT 24
Finished Aug 15 04:32:10 PM PDT 24
Peak memory 204760 kb
Host smart-84dd2415-230d-423a-993a-495f3a5cdb4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856360181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
856360181
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3524888273
Short name T447
Test name
Test status
Simulation time 76819259 ps
CPU time 2.22 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:13 PM PDT 24
Peak memory 224488 kb
Host smart-f0b16018-a3f0-4d92-910d-49577710467d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524888273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3524888273
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3513149318
Short name T443
Test name
Test status
Simulation time 14980238 ps
CPU time 0.76 seconds
Started Aug 15 04:32:02 PM PDT 24
Finished Aug 15 04:32:03 PM PDT 24
Peak memory 205716 kb
Host smart-53765e5b-6a79-492c-88f0-89ea3d660cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513149318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3513149318
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.948840198
Short name T565
Test name
Test status
Simulation time 23493760070 ps
CPU time 63.73 seconds
Started Aug 15 04:32:12 PM PDT 24
Finished Aug 15 04:33:16 PM PDT 24
Peak memory 254804 kb
Host smart-37307f1e-d505-43c8-839e-72e20276dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948840198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.948840198
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3284462106
Short name T219
Test name
Test status
Simulation time 21386320255 ps
CPU time 73.23 seconds
Started Aug 15 04:32:09 PM PDT 24
Finished Aug 15 04:33:23 PM PDT 24
Peak memory 264620 kb
Host smart-0c2c2505-315f-4df3-b064-3d4e2010d10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284462106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3284462106
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2303907519
Short name T247
Test name
Test status
Simulation time 89603019108 ps
CPU time 187.46 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:35:18 PM PDT 24
Peak memory 239776 kb
Host smart-40b06465-7283-4d4c-973d-49ef4006e471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303907519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2303907519
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1592477294
Short name T299
Test name
Test status
Simulation time 11754848257 ps
CPU time 31.79 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:43 PM PDT 24
Peak memory 232784 kb
Host smart-0a5d8f32-8207-4c99-bc60-eb0eff171252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592477294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1592477294
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.18882996
Short name T507
Test name
Test status
Simulation time 3813525540 ps
CPU time 52.05 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:33:03 PM PDT 24
Peak memory 250256 kb
Host smart-bd5ea18d-0c8f-45c3-a2dd-5f7a4b911f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18882996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.18882996
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3694713106
Short name T468
Test name
Test status
Simulation time 569288349 ps
CPU time 6.28 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:11 PM PDT 24
Peak memory 224456 kb
Host smart-21e19839-b1e8-4dd7-927c-0edcb26d77c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694713106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3694713106
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2023842268
Short name T811
Test name
Test status
Simulation time 4956134608 ps
CPU time 44.89 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:56 PM PDT 24
Peak memory 238876 kb
Host smart-4246c00a-6a58-4d3f-9793-4dcb96963426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023842268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2023842268
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1410521898
Short name T600
Test name
Test status
Simulation time 15687529 ps
CPU time 1.01 seconds
Started Aug 15 04:32:04 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 217848 kb
Host smart-fc2d2e91-d876-4c55-b65c-956b55085832
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410521898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1410521898
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1725870703
Short name T838
Test name
Test status
Simulation time 1536016186 ps
CPU time 12.01 seconds
Started Aug 15 04:32:03 PM PDT 24
Finished Aug 15 04:32:15 PM PDT 24
Peak memory 248992 kb
Host smart-634fa707-0271-4766-9422-2af4bab06373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725870703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1725870703
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1845526114
Short name T979
Test name
Test status
Simulation time 129917131770 ps
CPU time 26.24 seconds
Started Aug 15 04:32:03 PM PDT 24
Finished Aug 15 04:32:29 PM PDT 24
Peak memory 240620 kb
Host smart-b4753522-bfea-4ffc-b520-e0b03a75045a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845526114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1845526114
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.616935429
Short name T890
Test name
Test status
Simulation time 179502666 ps
CPU time 3.92 seconds
Started Aug 15 04:32:10 PM PDT 24
Finished Aug 15 04:32:14 PM PDT 24
Peak memory 220720 kb
Host smart-61553269-df11-4dca-8fdd-cb5ac0916ae6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=616935429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.616935429
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3722763273
Short name T43
Test name
Test status
Simulation time 25578684162 ps
CPU time 251.47 seconds
Started Aug 15 04:32:16 PM PDT 24
Finished Aug 15 04:36:28 PM PDT 24
Peak memory 260284 kb
Host smart-3ab7ce31-fdd7-4098-8dbc-6d08ed2d4ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722763273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3722763273
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2483656294
Short name T517
Test name
Test status
Simulation time 41595919 ps
CPU time 0.8 seconds
Started Aug 15 04:32:01 PM PDT 24
Finished Aug 15 04:32:02 PM PDT 24
Peak memory 205552 kb
Host smart-b6dc0e5a-26c6-4f14-99e7-5beb0233d9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483656294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2483656294
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.246827542
Short name T872
Test name
Test status
Simulation time 5597521732 ps
CPU time 14.63 seconds
Started Aug 15 04:32:02 PM PDT 24
Finished Aug 15 04:32:17 PM PDT 24
Peak memory 216316 kb
Host smart-f9d076f1-0ac4-41d0-b746-61cdb2f36e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246827542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.246827542
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.717632587
Short name T720
Test name
Test status
Simulation time 89361338 ps
CPU time 1 seconds
Started Aug 15 04:32:03 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 206944 kb
Host smart-f477536c-6d95-4090-8db1-82c19773cbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717632587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.717632587
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.439182522
Short name T734
Test name
Test status
Simulation time 238460835 ps
CPU time 1.01 seconds
Started Aug 15 04:32:02 PM PDT 24
Finished Aug 15 04:32:03 PM PDT 24
Peak memory 207012 kb
Host smart-12d1dae9-9de5-4ad1-9e51-7d11b6e456fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439182522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.439182522
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2205016443
Short name T762
Test name
Test status
Simulation time 185509750 ps
CPU time 2.68 seconds
Started Aug 15 04:32:08 PM PDT 24
Finished Aug 15 04:32:11 PM PDT 24
Peak memory 232680 kb
Host smart-de0f4287-3436-4e02-853e-807936d47ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205016443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2205016443
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.568770966
Short name T779
Test name
Test status
Simulation time 28539132 ps
CPU time 0.7 seconds
Started Aug 15 04:32:10 PM PDT 24
Finished Aug 15 04:32:11 PM PDT 24
Peak memory 205288 kb
Host smart-b8170277-1b1a-40b3-ada4-0856914bf551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568770966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.568770966
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1973408116
Short name T255
Test name
Test status
Simulation time 478827272 ps
CPU time 3.97 seconds
Started Aug 15 04:32:12 PM PDT 24
Finished Aug 15 04:32:17 PM PDT 24
Peak memory 232720 kb
Host smart-138d9a95-0a08-4749-9bb8-cc0eacc080cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973408116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1973408116
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.354322468
Short name T804
Test name
Test status
Simulation time 69247161 ps
CPU time 0.85 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:12 PM PDT 24
Peak memory 206432 kb
Host smart-75f5e5b2-4414-430f-9105-f94a62908922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354322468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.354322468
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2162420936
Short name T256
Test name
Test status
Simulation time 8858089104 ps
CPU time 38.43 seconds
Started Aug 15 04:32:15 PM PDT 24
Finished Aug 15 04:32:53 PM PDT 24
Peak memory 232748 kb
Host smart-9848c031-7ae2-4ad2-aa38-b2057ec4a6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162420936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2162420936
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.132827
Short name T436
Test name
Test status
Simulation time 13546398413 ps
CPU time 115.6 seconds
Started Aug 15 04:32:08 PM PDT 24
Finished Aug 15 04:34:04 PM PDT 24
Peak memory 249652 kb
Host smart-6e98f409-8066-41a7-97a3-58fca20298c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.132827
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.310648171
Short name T1013
Test name
Test status
Simulation time 236060641 ps
CPU time 5.28 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:17 PM PDT 24
Peak memory 232680 kb
Host smart-150d0f26-c8c6-4cd4-87c5-6827d9e545e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310648171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.310648171
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1241041650
Short name T570
Test name
Test status
Simulation time 11286644653 ps
CPU time 14.33 seconds
Started Aug 15 04:32:09 PM PDT 24
Finished Aug 15 04:32:24 PM PDT 24
Peak memory 224488 kb
Host smart-0ab6a417-d1b8-46f5-879d-61cbec17fdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241041650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1241041650
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2000640402
Short name T914
Test name
Test status
Simulation time 287322778 ps
CPU time 2.72 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:14 PM PDT 24
Peak memory 224416 kb
Host smart-a26d9f38-4469-4027-a510-f6985a851a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000640402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2000640402
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.266847971
Short name T993
Test name
Test status
Simulation time 23768628 ps
CPU time 1.04 seconds
Started Aug 15 04:32:14 PM PDT 24
Finished Aug 15 04:32:15 PM PDT 24
Peak memory 217788 kb
Host smart-206ccbe7-feda-477e-826b-553d346ba671
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266847971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.266847971
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3896996148
Short name T248
Test name
Test status
Simulation time 3659537672 ps
CPU time 13.09 seconds
Started Aug 15 04:32:16 PM PDT 24
Finished Aug 15 04:32:29 PM PDT 24
Peak memory 232756 kb
Host smart-9500c116-04eb-4992-b87f-2d52a1505206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896996148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3896996148
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3714817733
Short name T667
Test name
Test status
Simulation time 7816962738 ps
CPU time 16.34 seconds
Started Aug 15 04:32:12 PM PDT 24
Finished Aug 15 04:32:28 PM PDT 24
Peak memory 249068 kb
Host smart-9310e450-9e10-4561-b852-50ba6dd69f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714817733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3714817733
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4089659060
Short name T144
Test name
Test status
Simulation time 743807757 ps
CPU time 6.83 seconds
Started Aug 15 04:32:10 PM PDT 24
Finished Aug 15 04:32:17 PM PDT 24
Peak memory 220024 kb
Host smart-d7e1e793-5c17-4f0f-bf68-b0308b683db7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4089659060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4089659060
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2339915267
Short name T56
Test name
Test status
Simulation time 20245810125 ps
CPU time 72.97 seconds
Started Aug 15 04:32:15 PM PDT 24
Finished Aug 15 04:33:28 PM PDT 24
Peak memory 253328 kb
Host smart-18a68c1c-2183-44f9-ad71-c795f1bfc6fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339915267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2339915267
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4240805427
Short name T561
Test name
Test status
Simulation time 15755146286 ps
CPU time 46.63 seconds
Started Aug 15 04:32:10 PM PDT 24
Finished Aug 15 04:32:56 PM PDT 24
Peak memory 216324 kb
Host smart-41c20069-30b6-4f76-bd91-bf6e8217b8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240805427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4240805427
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3576410273
Short name T708
Test name
Test status
Simulation time 3230670896 ps
CPU time 9.88 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:22 PM PDT 24
Peak memory 216300 kb
Host smart-3292a69c-8684-415c-b71b-d216d7acf9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576410273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3576410273
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1196615233
Short name T697
Test name
Test status
Simulation time 13321844 ps
CPU time 0.81 seconds
Started Aug 15 04:32:09 PM PDT 24
Finished Aug 15 04:32:10 PM PDT 24
Peak memory 205912 kb
Host smart-5d89faeb-513b-4c6b-bd3e-f6deadb21710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196615233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1196615233
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.763542029
Short name T1002
Test name
Test status
Simulation time 37351218 ps
CPU time 0.76 seconds
Started Aug 15 04:32:15 PM PDT 24
Finished Aug 15 04:32:16 PM PDT 24
Peak memory 205928 kb
Host smart-eba55d75-87ad-4013-be35-61281b92f60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763542029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.763542029
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2749227661
Short name T115
Test name
Test status
Simulation time 392917318 ps
CPU time 3.55 seconds
Started Aug 15 04:32:24 PM PDT 24
Finished Aug 15 04:32:27 PM PDT 24
Peak memory 232684 kb
Host smart-f5ac7694-505a-49c5-9b75-3d7e6dea549e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749227661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2749227661
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.4053895429
Short name T518
Test name
Test status
Simulation time 34298996 ps
CPU time 0.69 seconds
Started Aug 15 04:32:15 PM PDT 24
Finished Aug 15 04:32:16 PM PDT 24
Peak memory 204764 kb
Host smart-cc025705-134f-4b84-9281-2709ddec285e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053895429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4
053895429
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4118639110
Short name T87
Test name
Test status
Simulation time 2313872226 ps
CPU time 4.09 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:23 PM PDT 24
Peak memory 232672 kb
Host smart-0b0d461a-300d-4526-b807-1e81cc3261d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118639110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4118639110
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.398606423
Short name T893
Test name
Test status
Simulation time 86310389 ps
CPU time 0.76 seconds
Started Aug 15 04:32:15 PM PDT 24
Finished Aug 15 04:32:16 PM PDT 24
Peak memory 206416 kb
Host smart-882517a5-9b31-4626-b98b-8fbc9d9d6fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398606423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.398606423
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3474847180
Short name T214
Test name
Test status
Simulation time 19672850202 ps
CPU time 158.65 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:34:49 PM PDT 24
Peak memory 259588 kb
Host smart-3f966957-abca-4784-b7e8-b25621c4bccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474847180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3474847180
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1833425955
Short name T229
Test name
Test status
Simulation time 19714943005 ps
CPU time 113.06 seconds
Started Aug 15 04:32:12 PM PDT 24
Finished Aug 15 04:34:05 PM PDT 24
Peak memory 264760 kb
Host smart-36270263-ba46-40a1-aee9-247f4dde77cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833425955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1833425955
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2394531544
Short name T167
Test name
Test status
Simulation time 55918255535 ps
CPU time 223.45 seconds
Started Aug 15 04:32:09 PM PDT 24
Finished Aug 15 04:35:52 PM PDT 24
Peak memory 262384 kb
Host smart-d3ff4927-85df-43bf-8ee6-4473d2ab4925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394531544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2394531544
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1081865384
Short name T831
Test name
Test status
Simulation time 7964005159 ps
CPU time 24.9 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:36 PM PDT 24
Peak memory 240856 kb
Host smart-4ee3db97-ad61-4b0d-81f8-b835e8a8867d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081865384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1081865384
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1830346552
Short name T388
Test name
Test status
Simulation time 38036128882 ps
CPU time 258.04 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:36:29 PM PDT 24
Peak memory 250672 kb
Host smart-7f7b974c-c1ee-48ec-b0a2-04c723484713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830346552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1830346552
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.45571074
Short name T867
Test name
Test status
Simulation time 332969486 ps
CPU time 5.39 seconds
Started Aug 15 04:32:13 PM PDT 24
Finished Aug 15 04:32:18 PM PDT 24
Peak memory 224512 kb
Host smart-4569e689-186a-4724-aca3-da290b6354c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45571074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.45571074
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.413534011
Short name T602
Test name
Test status
Simulation time 7593134589 ps
CPU time 8.48 seconds
Started Aug 15 04:32:10 PM PDT 24
Finished Aug 15 04:32:19 PM PDT 24
Peak memory 224508 kb
Host smart-85ab2837-5d32-4dd7-8529-2d96530dbeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413534011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.413534011
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2866069182
Short name T47
Test name
Test status
Simulation time 35914189 ps
CPU time 1.15 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:13 PM PDT 24
Peak memory 216508 kb
Host smart-c12274c7-c311-4b8c-b912-654f990826f8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866069182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2866069182
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2529657506
Short name T829
Test name
Test status
Simulation time 1139493928 ps
CPU time 4.15 seconds
Started Aug 15 04:32:12 PM PDT 24
Finished Aug 15 04:32:17 PM PDT 24
Peak memory 224484 kb
Host smart-dac3a45e-fc73-448e-bbb7-39b7713578e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529657506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2529657506
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3967938113
Short name T237
Test name
Test status
Simulation time 725770623 ps
CPU time 11 seconds
Started Aug 15 04:32:10 PM PDT 24
Finished Aug 15 04:32:21 PM PDT 24
Peak memory 232768 kb
Host smart-cd3f556e-c9c8-43e1-b7bd-dfcf8740ab5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967938113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3967938113
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.794455530
Short name T478
Test name
Test status
Simulation time 1099336399 ps
CPU time 7.55 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:19 PM PDT 24
Peak memory 221372 kb
Host smart-86467f00-bbb0-438b-b7d6-8814fd2a95c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=794455530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.794455530
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.955196542
Short name T909
Test name
Test status
Simulation time 2075507431 ps
CPU time 20.5 seconds
Started Aug 15 04:32:09 PM PDT 24
Finished Aug 15 04:32:30 PM PDT 24
Peak memory 216332 kb
Host smart-b172e39f-f587-4b3d-bf7c-651bd62dd19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955196542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.955196542
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.922761440
Short name T752
Test name
Test status
Simulation time 61610415 ps
CPU time 0.73 seconds
Started Aug 15 04:32:10 PM PDT 24
Finished Aug 15 04:32:11 PM PDT 24
Peak memory 205536 kb
Host smart-c1d8af4f-0daa-4195-974c-7bd01177fe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922761440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.922761440
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3872001434
Short name T321
Test name
Test status
Simulation time 225486484 ps
CPU time 1.17 seconds
Started Aug 15 04:32:10 PM PDT 24
Finished Aug 15 04:32:12 PM PDT 24
Peak memory 207220 kb
Host smart-22385e58-2d33-4e98-815f-d9e8bceef895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872001434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3872001434
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2051093505
Short name T960
Test name
Test status
Simulation time 144617729 ps
CPU time 0.88 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:12 PM PDT 24
Peak memory 205928 kb
Host smart-925c888a-1ae4-4369-afa0-7eb1e299eb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051093505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2051093505
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1225832364
Short name T833
Test name
Test status
Simulation time 842996776 ps
CPU time 6.07 seconds
Started Aug 15 04:32:16 PM PDT 24
Finished Aug 15 04:32:23 PM PDT 24
Peak memory 240188 kb
Host smart-82310e09-0c91-4774-9e6c-8a835efb3565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225832364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1225832364
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1185665537
Short name T551
Test name
Test status
Simulation time 14885034 ps
CPU time 0.71 seconds
Started Aug 15 04:32:21 PM PDT 24
Finished Aug 15 04:32:22 PM PDT 24
Peak memory 205448 kb
Host smart-f06106d0-63f1-466d-a69c-1ff95568d584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185665537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
185665537
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2637443558
Short name T462
Test name
Test status
Simulation time 117275568 ps
CPU time 3.41 seconds
Started Aug 15 04:32:17 PM PDT 24
Finished Aug 15 04:32:20 PM PDT 24
Peak memory 232660 kb
Host smart-c3b9ae60-a824-44a1-9735-2beda7e0697e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637443558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2637443558
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2168606644
Short name T354
Test name
Test status
Simulation time 44443874 ps
CPU time 0.75 seconds
Started Aug 15 04:32:15 PM PDT 24
Finished Aug 15 04:32:16 PM PDT 24
Peak memory 206756 kb
Host smart-85054aab-3819-4b3e-a3a6-3c0d6f33b1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168606644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2168606644
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4232542030
Short name T393
Test name
Test status
Simulation time 2883686875 ps
CPU time 50.28 seconds
Started Aug 15 04:32:21 PM PDT 24
Finished Aug 15 04:33:11 PM PDT 24
Peak memory 249180 kb
Host smart-426a9878-2b45-4345-a9e2-df7f105cb5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232542030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4232542030
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3450028907
Short name T741
Test name
Test status
Simulation time 24145231712 ps
CPU time 258.4 seconds
Started Aug 15 04:32:16 PM PDT 24
Finished Aug 15 04:36:35 PM PDT 24
Peak memory 265356 kb
Host smart-ec1333a5-f634-4268-b5ae-93a84c9503c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450028907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3450028907
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.307680342
Short name T875
Test name
Test status
Simulation time 29748128821 ps
CPU time 152.51 seconds
Started Aug 15 04:32:20 PM PDT 24
Finished Aug 15 04:34:52 PM PDT 24
Peak memory 254156 kb
Host smart-f70c92fc-3d00-4224-b8b1-ecf7b634f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307680342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
307680342
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1456318119
Short name T568
Test name
Test status
Simulation time 309073680 ps
CPU time 4.46 seconds
Started Aug 15 04:32:19 PM PDT 24
Finished Aug 15 04:32:24 PM PDT 24
Peak memory 224436 kb
Host smart-aa8911cd-2ca2-4331-9a64-be77655d6e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456318119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1456318119
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2518113316
Short name T954
Test name
Test status
Simulation time 15251595 ps
CPU time 0.74 seconds
Started Aug 15 04:32:15 PM PDT 24
Finished Aug 15 04:32:16 PM PDT 24
Peak memory 215676 kb
Host smart-10eb2169-5b01-411c-b2ae-00cf05502ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518113316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2518113316
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2129301840
Short name T162
Test name
Test status
Simulation time 587277085 ps
CPU time 3.57 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:14 PM PDT 24
Peak memory 232660 kb
Host smart-7f372bc8-942d-470f-acf0-ef4e2a491e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129301840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2129301840
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2126664189
Short name T346
Test name
Test status
Simulation time 604017896 ps
CPU time 8.14 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:19 PM PDT 24
Peak memory 240876 kb
Host smart-289356fb-8ca5-41a4-96a4-69accd3de6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126664189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2126664189
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2211259998
Short name T678
Test name
Test status
Simulation time 44053128 ps
CPU time 1.08 seconds
Started Aug 15 04:32:12 PM PDT 24
Finished Aug 15 04:32:13 PM PDT 24
Peak memory 217776 kb
Host smart-cc9a6a31-5a71-48b4-ac2a-09c86da831cf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211259998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2211259998
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1904570921
Short name T525
Test name
Test status
Simulation time 910615623 ps
CPU time 4.25 seconds
Started Aug 15 04:32:09 PM PDT 24
Finished Aug 15 04:32:13 PM PDT 24
Peak memory 224892 kb
Host smart-e7fc72d1-9657-4526-a8de-0c4b7618cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904570921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1904570921
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2138686059
Short name T670
Test name
Test status
Simulation time 370342612 ps
CPU time 4.37 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:15 PM PDT 24
Peak memory 227220 kb
Host smart-4343b287-0796-47be-9a9e-2b6d20d9da80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138686059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2138686059
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2309488363
Short name T449
Test name
Test status
Simulation time 818105307 ps
CPU time 9.58 seconds
Started Aug 15 04:32:18 PM PDT 24
Finished Aug 15 04:32:27 PM PDT 24
Peak memory 221968 kb
Host smart-cb148fbc-bd13-4951-8e39-7cbde239dded
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2309488363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2309488363
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3419390311
Short name T742
Test name
Test status
Simulation time 43847297989 ps
CPU time 146.99 seconds
Started Aug 15 04:32:17 PM PDT 24
Finished Aug 15 04:34:45 PM PDT 24
Peak memory 265580 kb
Host smart-174ddd23-0c76-45e2-9aa4-7bf6ba835746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419390311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3419390311
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1513937030
Short name T1000
Test name
Test status
Simulation time 2718584559 ps
CPU time 18.37 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:30 PM PDT 24
Peak memory 216412 kb
Host smart-d585676d-8669-4937-8e31-37f5ee74625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513937030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1513937030
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3939177667
Short name T372
Test name
Test status
Simulation time 63266324 ps
CPU time 0.76 seconds
Started Aug 15 04:32:10 PM PDT 24
Finished Aug 15 04:32:11 PM PDT 24
Peak memory 205508 kb
Host smart-c7fcbeee-0e9e-44d3-9757-6f6ca0159212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939177667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3939177667
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.599626440
Short name T691
Test name
Test status
Simulation time 185722463 ps
CPU time 7.93 seconds
Started Aug 15 04:32:14 PM PDT 24
Finished Aug 15 04:32:22 PM PDT 24
Peak memory 216280 kb
Host smart-c41746ef-bc2f-4cc6-b726-f927e1ec5cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599626440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.599626440
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2496208435
Short name T544
Test name
Test status
Simulation time 102839488 ps
CPU time 0.84 seconds
Started Aug 15 04:32:09 PM PDT 24
Finished Aug 15 04:32:10 PM PDT 24
Peak memory 205852 kb
Host smart-50ef80bb-43ec-4605-aac2-45d66a5efc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496208435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2496208435
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.902502544
Short name T859
Test name
Test status
Simulation time 1562114016 ps
CPU time 6.56 seconds
Started Aug 15 04:32:11 PM PDT 24
Finished Aug 15 04:32:17 PM PDT 24
Peak memory 224556 kb
Host smart-c638263d-223c-46f6-88f2-816f3f0fd2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902502544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.902502544
Directory /workspace/9.spi_device_upload/latest
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