Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2310899	1			T1	934		T2	145		T3	1
all_values[1]	2310899	1			T1	934		T2	145		T3	1
all_values[2]	2310899	1			T1	934		T2	145		T3	1
all_values[3]	2310899	1			T1	934		T2	145		T3	1
all_values[4]	2310899	1			T1	934		T2	145		T3	1
all_values[5]	2310899	1			T1	934		T2	145		T3	1
all_values[6]	2310899	1			T1	934		T2	145		T3	1
all_values[7]	2310899	1			T1	934		T2	145		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17671691

1

T1

7472

T2

1160

T3

8

auto[1]

815501

1

T15

230863

T16

49

T17

997

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18463030

1

T1

7472

T2

1160

T3

8

auto[1]

24162

1

T5

457

T26

21

T15

123

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2208068	1			T1	934		T2	145		T3	1
all_values[0]	auto[0]	auto[1]	10873	1			T5	217		T26	21		T15	25
all_values[0]	auto[1]	auto[0]	91124	1			T17	165		T18	5		T19	458
all_values[0]	auto[1]	auto[1]	834	1			T15	5		T16	3		T17	1
all_values[1]	auto[0]	auto[0]	2213010	1			T1	934		T2	145		T3	1
all_values[1]	auto[0]	auto[1]	6824	1			T5	216		T15	25		T40	11
all_values[1]	auto[1]	auto[0]	90324	1			T15	6		T16	3		T17	163
all_values[1]	auto[1]	auto[1]	741	1			T15	2		T17	2		T20	3
all_values[2]	auto[0]	auto[0]	2191180	1			T1	934		T2	145		T3	1
all_values[2]	auto[0]	auto[1]	2346	1			T5	24		T15	6		T16	3
all_values[2]	auto[1]	auto[0]	116916	1			T15	57688		T16	3		T17	165
all_values[2]	auto[1]	auto[1]	457	1			T15	23		T16	3		T17	1
all_values[3]	auto[0]	auto[0]	2240359	1			T1	934		T2	145		T3	1
all_values[3]	auto[0]	auto[1]	214	1			T15	8		T16	3		T17	2
all_values[3]	auto[1]	auto[0]	70100	1			T15	1		T16	4		T18	5
all_values[3]	auto[1]	auto[1]	226	1			T15	1		T16	1		T17	2
all_values[4]	auto[0]	auto[0]	2137553	1			T1	934		T2	145		T3	1
all_values[4]	auto[0]	auto[1]	214	1			T15	4		T16	3		T17	1
all_values[4]	auto[1]	auto[0]	172940	1			T15	57707		T16	1		T17	165
all_values[4]	auto[1]	auto[1]	192	1			T15	4		T16	3		T17	1
all_values[5]	auto[0]	auto[0]	2190805	1			T1	934		T2	145		T3	1
all_values[5]	auto[0]	auto[1]	178	1			T15	4		T16	1		T17	1
all_values[5]	auto[1]	auto[0]	119725	1			T15	57709		T16	8		T17	164
all_values[5]	auto[1]	auto[1]	191	1			T15	3		T16	2		T17	2
all_values[6]	auto[0]	auto[0]	2222769	1			T1	934		T2	145		T3	1
all_values[6]	auto[0]	auto[1]	217	1			T15	6		T16	2		T17	1
all_values[6]	auto[1]	auto[0]	87686	1			T15	3		T16	3		T18	1
all_values[6]	auto[1]	auto[1]	227	1			T16	6		T18	1		T19	1
all_values[7]	auto[0]	auto[0]	2246877	1			T1	934		T2	145		T3	1
all_values[7]	auto[0]	auto[1]	204	1			T15	4		T16	2		T18	1
all_values[7]	auto[1]	auto[0]	63594	1			T15	57708		T16	6		T17	165
all_values[7]	auto[1]	auto[1]	224	1			T15	3		T16	3		T17	1