Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34725	1			T3	8		T5	372		T7	2
auto[SpiFlashAddrCfg]	7178	1			T2	2		T4	6		T5	62
auto[SpiFlashAddr3b]	8614	1			T2	2		T4	12		T5	59
auto[SpiFlashAddr4b]	7248	1			T2	2		T4	4		T5	51

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33257

1

T2

6

T3

8

T5

415

auto[1]

24508

1

T4

22

T5

129

T12

12

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31608

1

T2

2

T3

8

T4

4

auto[1]

26157

1

T2

4

T4

18

T5

293

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39055	1			T3	8		T4	2		T5	415
values[1]	1034	1			T4	6		T5	4		T13	9
values[2]	1304	1			T2	2		T5	5		T13	8
values[3]	1417	1			T5	11		T7	2		T13	10
values[4]	1363	1			T4	2		T5	6		T13	5
values[5]	1397	1			T5	7		T13	5		T35	3
values[6]	1418	1			T4	2		T5	14		T13	6
values[7]	1392	1			T5	9		T13	7		T35	10
values[8]	9385	1			T2	4		T4	10		T5	73

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31172

1

T2

6

T3

8

T4

22

auto[1]

26593

1

T5

544

T35

240

T26

21

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54608

1

T2

6

T3

8

T4

22

write

3157

1

T5

50

T7

2

T12

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18060

1

T2

4

T3

8

T4

10

valids[0x1]

39705

1

T2

2

T4

12

T5

419

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1399	1			T5	12		T13	7		T35	12
internal_process_ops[0x5a]	1497	1			T4	6		T5	11		T12	2
internal_process_ops[0x05]	21734	1			T5	236		T13	9		T35	9
internal_process_ops[0x35]	1528	1			T5	23		T7	2		T12	2
internal_process_ops[0x15]	1489	1			T5	20		T13	2		T35	7
internal_process_ops[0x03]	976	1			T5	3		T13	10		T35	3
internal_process_ops[0x0b]	1013	1			T12	4		T13	8		T14	2
internal_process_ops[0x3b]	980	1			T5	2		T13	3		T35	1
internal_process_ops[0x6b]	999	1			T2	2		T4	2		T5	4
internal_process_ops[0xbb]	1080	1			T2	2		T5	3		T13	9
internal_process_ops[0xeb]	1021	1			T5	3		T7	2		T13	11

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56208

1

T2

6

T3

8

T4

22

auto[1]

1557

1

T5

17

T12

2

T13

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55384

1

T2

6

T3

8

T4

22

auto[1]

2381

1

T5

34

T13

9

T35

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11071

1

T3

8

T7

2

T9

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6099

1

T12

2

T13

11

T15

29

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2067

1

T2

2

T13

17

T14

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1806

1

T4

6

T12

2

T13

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2496

1

T2

2

T7

2

T13

30

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2147

1

T4

12

T12

6

T13

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2059

1

T2

2

T13

19

T15

21

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1840

1

T4

4

T13

16

T15

17

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

105

1

T13

1

T43

1

T44

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

95

1

T15

1

T41

1

T45

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

87

1

T41

3

T49

2

T18

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

112

1

T15

2

T41

1

T18

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

108

1

T13

4

T41

1

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

95

1

T13

1

T15

2

T48

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T13

1

T41

1

T42

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

89

1

T166

2

T167

3

T168

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

124

1

T13

1

T15

4

T45

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

79

1

T13

2

T15

1

T48

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

92

1

T41

1

T45

2

T48

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

114

1

T13

2

T43

1

T50

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

103

1

T7

2

T49

2

T44

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

98

1

T13

2

T15

2

T45

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

98

1

T13

1

T166

2

T169

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

93

1

T12

2

T41

2

T48

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9899

1

T5

316

T35

69

T26

8

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6863

1

T5

51

T35

29

T26

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1231

1

T5

19

T35

16

T26

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1265

1

T5

23

T35

14

T26

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1594

1

T5

27

T35

27

T40

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1586

1

T5

20

T35

24

T26

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1271

1

T5

18

T35

24

T40

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1314

1

T5

20

T35

19

T40

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

100

1

T5

5

T35

1

T17

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

94

1

T35

1

T17

1

T170

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

86

1

T26

1

T171

3

T36

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

114

1

T35

1

T17

2

T171

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

103

1

T5

9

T35

1

T171

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

80

1

T5

1

T35

2

T172

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

137

1

T5

10

T35

3

T17

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

102

1

T40

2

T17

1

T171

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

97

1

T5

7

T35

1

T17

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

104

1

T5

1

T35

4

T40

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

87

1

T5

1

T171

2

T36

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

94

1

T5

3

T40

2

T170

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

87

1

T5

1

T35

1

T17

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

97

1

T5

11

T35

1

T94

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

91

1

T35

1

T17

2

T36

6

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

97

1

T5

1

T35

1

T17

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3837	1			T3	8		T9	10		T13	27
auto[0]	values[0]	valids[0x1]	16138	1			T4	2		T7	4		T12	8
auto[0]	values[1]	valids[0x1]	553	1			T4	6		T13	9		T15	2
auto[0]	values[2]	valids[0x0]	521	1			T2	2		T13	5		T15	2
auto[0]	values[2]	valids[0x1]	278	1			T13	3		T15	1		T45	1
auto[0]	values[3]	valids[0x0]	516	1			T7	2		T13	10		T15	6
auto[0]	values[3]	valids[0x1]	296	1			T15	1		T93	2		T41	3
auto[0]	values[4]	valids[0x0]	465	1			T13	1		T15	5		T92	6
auto[0]	values[4]	valids[0x1]	323	1			T4	2		T13	4		T15	1
auto[0]	values[5]	valids[0x0]	569	1			T13	4		T15	7		T93	2
auto[0]	values[5]	valids[0x1]	266	1			T13	1		T41	10		T45	1
auto[0]	values[6]	valids[0x0]	559	1			T14	2		T15	5		T47	2
auto[0]	values[6]	valids[0x1]	335	1			T4	2		T13	6		T15	1
auto[0]	values[7]	valids[0x0]	534	1			T13	5		T15	6		T47	6
auto[0]	values[7]	valids[0x1]	319	1			T13	2		T15	5		T41	2
auto[0]	values[8]	valids[0x0]	3534	1			T2	2		T4	10		T12	2
auto[0]	values[8]	valids[0x1]	2129	1			T2	2		T12	2		T13	18
auto[1]	values[0]	valids[0x0]	3353	1			T5	64		T35	49		T26	5
auto[1]	values[0]	valids[0x1]	15727	1			T5	351		T35	74		T26	8
auto[1]	values[1]	valids[0x1]	481	1			T5	4		T35	8		T26	1
auto[1]	values[2]	valids[0x0]	279	1			T5	3		T35	1		T26	2
auto[1]	values[2]	valids[0x1]	226	1			T5	2		T35	7		T17	1
auto[1]	values[3]	valids[0x0]	376	1			T5	6		T35	8		T40	1
auto[1]	values[3]	valids[0x1]	229	1			T5	5		T35	3		T17	4
auto[1]	values[4]	valids[0x0]	351	1			T5	5		T35	6		T173	1
auto[1]	values[4]	valids[0x1]	224	1			T5	1		T35	3		T40	1
auto[1]	values[5]	valids[0x0]	343	1			T5	4		T35	1		T174	1
auto[1]	values[5]	valids[0x1]	219	1			T5	3		T35	2		T40	2
auto[1]	values[6]	valids[0x0]	297	1			T5	4		T35	3		T26	1
auto[1]	values[6]	valids[0x1]	227	1			T5	10		T35	7		T26	1
auto[1]	values[7]	valids[0x0]	317	1			T5	6		T35	9		T40	2
auto[1]	values[7]	valids[0x1]	222	1			T5	3		T35	1		T17	2
auto[1]	values[8]	valids[0x0]	2209	1			T5	33		T35	29		T26	2
auto[1]	values[8]	valids[0x1]	1513	1			T5	40		T35	29		T26	1