Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3370286

1

T2

1

T3

1378

T4

1

auto[1]

32797

1

T5

224

T13

141

T35

508

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1087168

1

T2

1

T3

1378

T4

1

auto[1]

2315915

1

T5

19454

T7

5670

T13

12053

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	665074	1			T2	1		T3	2		T4	1
auto[524288:1048575]	420787	1			T3	149		T5	2621		T13	3950
auto[1048576:1572863]	440557	1			T5	6976		T13	617		T35	281
auto[1572864:2097151]	373504	1			T5	1595		T13	1460		T35	904
auto[2097152:2621439]	389556	1			T3	578		T5	817		T13	4204
auto[2621440:3145727]	344613	1			T3	4		T5	2272		T13	1893
auto[3145728:3670015]	389193	1			T3	264		T5	1286		T9	3
auto[3670016:4194303]	379799	1			T3	381		T5	1181		T13	299

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2349696

1

T2

1

T3

107

T4

1

auto[1]

1053387

1

T3

1271

T5

14

T9

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2864991

1

T2

1

T3

1216

T4

1

auto[1]

538092

1

T3

162

T5

3828

T9

3

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	244691	1			T2	1		T3	1		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	332538	1			T5	1155		T7	5670		T13	8
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	130799	1			T3	144		T5	13		T13	82
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	210846	1			T5	2407		T13	907		T35	893
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	118509	1			T5	8		T13	83		T35	16
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	242274	1			T5	6950		T13	263		T35	256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	119338	1			T5	3		T13	60		T35	32
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	185349	1			T5	1191		T13	1322		T35	477
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	127961	1			T3	578		T5	1		T13	33
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	203908	1			T5	816		T13	4095		T35	512
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	103049	1			T3	4		T5	4		T13	20
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	185774	1			T5	2009		T13	1864		T35	256
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	127752	1			T3	264		T5	5		T13	8
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	195537	1			T5	133		T35	1397		T15	514
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	97821	1			T3	225		T5	11		T13	12
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	212065	1			T5	904		T13	287		T35	892
auto[0]	auto[1]	auto[0:524287]	auto[0]	1890	1			T3	1		T5	4		T26	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	81659	1			T5	1592		T26	1		T15	2931
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2112	1			T3	5		T5	2		T13	19
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	74087	1			T5	129		T13	2939		T41	30
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	709	1			T13	10		T15	2		T45	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	75730	1			T13	256		T45	4		T42	2758
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2251	1			T5	1		T35	3		T45	7
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	61812	1			T5	384		T45	5		T49	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	3706	1			T13	30		T35	14		T15	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	49668	1			T41	6		T48	3308		T17	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	544	1			T5	3		T44	1		T171	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	51555	1			T5	256		T44	1		T36	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1144	1			T5	2		T9	3		T35	6
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	59353	1			T5	1082		T15	513		T40	129
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	857	1			T3	156		T42	1		T48	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	64998	1			T5	256		T26	2042		T48	969
auto[1]	auto[0]	auto[0:524287]	auto[0]	520	1			T5	3		T35	19		T48	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3035	1			T5	12		T85	45		T17	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	337	1			T5	10		T13	3		T15	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1838	1			T5	36		T15	2		T41	20
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	341	1			T5	2		T13	5		T35	9
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1633	1			T5	16		T40	2		T41	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	429	1			T5	4		T13	9		T35	8
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3611	1			T5	12		T13	69		T35	384
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	387	1			T13	3		T35	9		T40	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3449	1			T13	43		T40	16		T49	46
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	393	1			T13	9		T35	11		T40	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2746	1			T40	4		T45	33		T42	13
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	487	1			T5	1		T35	39		T48	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3794	1			T5	1		T17	4		T171	17
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	404	1			T5	2		T35	12		T15	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3376	1			T5	8		T15	2		T40	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	93	1			T5	4		T26	1		T40	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	648	1			T5	27		T40	6		T171	29
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	99	1			T5	1		T171	2		T166	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	669	1			T5	23		T171	34		T166	58
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	85	1			T36	1		T203	1		T215	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1276	1			T203	1		T204	35		T19	18
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	98	1			T45	2		T49	1		T17	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	616	1			T45	73		T49	12		T17	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	102	1			T35	17		T41	1		T17	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	375	1			T41	28		T17	7		T215	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	93	1			T44	1		T94	2		T215	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	459	1			T215	5		T19	12		T249	7
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	114	1			T5	7		T15	1		T40	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1012	1			T5	55		T15	1		T40	10
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	53	1			T44	2		T209	1		T170	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	225	1			T209	3		T170	13		T169	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1793918	1			T2	1		T3	101		T4	1
auto[0]	auto[0]	auto[1]	1044293	1			T3	1115		T9	1		T92	19051
auto[0]	auto[1]	auto[0]	523696	1			T3	6		T5	3711		T9	3
auto[0]	auto[1]	auto[1]	8379	1			T3	156		T45	2		T49	1
auto[1]	auto[0]	auto[0]	26196	1			T5	100		T13	133		T35	485
auto[1]	auto[0]	auto[1]	584	1			T5	7		T13	8		T35	6
auto[1]	auto[1]	auto[0]	5886	1			T5	110		T35	16		T26	1
auto[1]	auto[1]	auto[1]	131	1			T5	7		T35	1		T15	1