Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2310899	1			T1	934		T2	145		T3	1
all_pins[1]	2310899	1			T1	934		T2	145		T3	1
all_pins[2]	2310899	1			T1	934		T2	145		T3	1
all_pins[3]	2310899	1			T1	934		T2	145		T3	1
all_pins[4]	2310899	1			T1	934		T2	145		T3	1
all_pins[5]	2310899	1			T1	934		T2	145		T3	1
all_pins[6]	2310899	1			T1	934		T2	145		T3	1
all_pins[7]	2310899	1			T1	934		T2	145		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18395338	1			T1	7472		T2	1160		T3	8
values[0x1]	91854	1			T15	470		T16	21		T17	13
transitions[0x0=>0x1]	90128	1			T15	465		T16	15		T17	9
transitions[0x1=>0x0]	90138	1			T15	465		T16	15		T17	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2309964	1			T1	934		T2	145		T3	1
all_pins[0]	values[0x1]	935	1			T15	5		T16	3		T17	3
all_pins[0]	transitions[0x0=>0x1]	645	1			T15	4		T16	3		T17	2
all_pins[0]	transitions[0x1=>0x0]	514	1			T15	1		T17	2		T20	3
all_pins[1]	values[0x0]	2310095	1			T1	934		T2	145		T3	1
all_pins[1]	values[0x1]	804	1			T15	2		T17	3		T19	4
all_pins[1]	transitions[0x0=>0x1]	531	1			T15	2		T17	3		T19	2
all_pins[1]	transitions[0x1=>0x0]	198	1			T15	24		T16	3		T17	1
all_pins[2]	values[0x0]	2310428	1			T1	934		T2	145		T3	1
all_pins[2]	values[0x1]	471	1			T15	24		T16	3		T17	1
all_pins[2]	transitions[0x0=>0x1]	395	1			T15	23		T16	2		T18	1
all_pins[2]	transitions[0x1=>0x0]	150	1			T17	1		T164	3		T165	3
all_pins[3]	values[0x0]	2310673	1			T1	934		T2	145		T3	1
all_pins[3]	values[0x1]	226	1			T15	1		T16	1		T17	2
all_pins[3]	transitions[0x0=>0x1]	175	1			T16	1		T17	1		T19	3
all_pins[3]	transitions[0x1=>0x0]	141	1			T15	3		T16	3		T18	1
all_pins[4]	values[0x0]	2310707	1			T1	934		T2	145		T3	1
all_pins[4]	values[0x1]	192	1			T15	4		T16	3		T17	1
all_pins[4]	transitions[0x0=>0x1]	152	1			T15	3		T16	2		T20	1
all_pins[4]	transitions[0x1=>0x0]	1933	1			T15	430		T16	1		T17	1
all_pins[5]	values[0x0]	2308926	1			T1	934		T2	145		T3	1
all_pins[5]	values[0x1]	1973	1			T15	431		T16	2		T17	2
all_pins[5]	transitions[0x0=>0x1]	1105	1			T15	431		T17	2		T18	2
all_pins[5]	transitions[0x1=>0x0]	86161	1			T16	4		T18	1		T19	1
all_pins[6]	values[0x0]	2223870	1			T1	934		T2	145		T3	1
all_pins[6]	values[0x1]	87029	1			T16	6		T18	1		T19	1
all_pins[6]	transitions[0x0=>0x1]	86963	1			T16	5		T18	1		T19	1
all_pins[6]	transitions[0x1=>0x0]	158	1			T15	3		T16	2		T17	1
all_pins[7]	values[0x0]	2310675	1			T1	934		T2	145		T3	1
all_pins[7]	values[0x1]	224	1			T15	3		T16	3		T17	1
all_pins[7]	transitions[0x0=>0x1]	162	1			T15	2		T16	2		T17	1
all_pins[7]	transitions[0x1=>0x0]	883	1			T15	4		T16	2		T17	3