Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18500

1

T2

6

T3

8

T7

6

auto[1]

12672

1

T4

22

T12

12

T13

59

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3570	1			T4	22		T12	12		T15	20
values[1]	4088	1			T13	20		T15	65		T45	20
values[2]	3429	1			T7	6		T9	10		T13	20
values[3]	3647	1			T3	8		T13	20		T41	130
values[4]	4475	1			T13	20		T15	43		T47	20
values[5]	3256	1			T2	6		T13	40		T14	4
values[6]	3872	1			T13	20		T15	20		T92	14
values[7]	4835	1			T13	40		T15	20		T45	115

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3737	1			T13	20		T15	20		T92	14
values[1]	4366	1			T9	10		T13	40		T15	23
values[2]	3875	1			T2	6		T3	8		T12	12
values[3]	3781	1			T14	4		T41	20		T48	23
values[4]	3648	1			T13	20		T15	40		T41	22
values[5]	3917	1			T7	6		T13	20		T214	16
values[6]	3948	1			T13	20		T15	20		T41	40
values[7]	3900	1			T4	22		T13	20		T47	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	218	1			T41	14		T199	9		T89	13
auto[0]	values[0]	values[1]	466	1			T29	23		T157	77		T165	10
auto[0]	values[0]	values[2]	251	1			T166	11		T199	84		T231	15
auto[0]	values[0]	values[3]	170	1			T169	70		T220	13		T231	18
auto[0]	values[0]	values[4]	484	1			T42	13		T199	83		T247	12
auto[0]	values[0]	values[5]	220	1			T44	16		T168	9		T19	14
auto[0]	values[0]	values[6]	367	1			T15	9		T45	16		T209	14
auto[0]	values[0]	values[7]	188	1			T48	14		T49	11		T166	18
auto[0]	values[1]	values[0]	200	1			T220	11		T89	14		T195	13
auto[0]	values[1]	values[1]	400	1			T15	6		T43	10		T229	12
auto[0]	values[1]	values[2]	274	1			T15	8		T42	10		T18	32
auto[0]	values[1]	values[3]	312	1			T46	2		T197	8		T213	13
auto[0]	values[1]	values[4]	234	1			T15	11		T167	5		T29	15
auto[0]	values[1]	values[5]	238	1			T13	18		T214	16		T43	12
auto[0]	values[1]	values[6]	304	1			T44	13		T18	37		T243	10
auto[0]	values[1]	values[7]	346	1			T45	9		T43	17		T18	18
auto[0]	values[2]	values[0]	198	1			T96	6		T48	11		T250	2
auto[0]	values[2]	values[1]	218	1			T9	10		T13	11		T232	20
auto[0]	values[2]	values[2]	138	1			T15	13		T167	11		T195	9
auto[0]	values[2]	values[3]	303	1			T48	14		T229	14		T29	33
auto[0]	values[2]	values[4]	178	1			T41	15		T45	8		T209	9
auto[0]	values[2]	values[5]	355	1			T7	6		T212	14		T199	58
auto[0]	values[2]	values[6]	256	1			T49	15		T197	14		T251	10
auto[0]	values[2]	values[7]	316	1			T245	10		T252	74		T18	12
auto[0]	values[3]	values[0]	231	1			T13	8		T41	40		T136	12
auto[0]	values[3]	values[1]	415	1			T41	6		T43	13		T18	25
auto[0]	values[3]	values[2]	159	1			T3	8		T166	11		T225	8
auto[0]	values[3]	values[3]	292	1			T166	127		T253	18		T61	13
auto[0]	values[3]	values[4]	273	1			T242	14		T254	6		T195	19
auto[0]	values[3]	values[5]	394	1			T255	6		T167	17		T29	11
auto[0]	values[3]	values[6]	200	1			T41	10		T199	5		T256	11
auto[0]	values[3]	values[7]	202	1			T201	6		T166	22		T74	12
auto[0]	values[4]	values[0]	219	1			T44	11		T199	12		T230	15
auto[0]	values[4]	values[1]	513	1			T13	13		T44	9		T205	61
auto[0]	values[4]	values[2]	271	1			T15	29		T49	8		T168	38
auto[0]	values[4]	values[3]	471	1			T44	16		T29	20		T257	4
auto[0]	values[4]	values[4]	374	1			T49	27		T43	15		T258	6
auto[0]	values[4]	values[5]	309	1			T44	23		T209	9		T166	12
auto[0]	values[4]	values[6]	222	1			T41	14		T29	13		T220	14
auto[0]	values[4]	values[7]	248	1			T47	20		T197	11		T259	11
auto[0]	values[5]	values[0]	221	1			T167	15		T137	11		T260	2
auto[0]	values[5]	values[1]	265	1			T45	9		T261	4		T19	19
auto[0]	values[5]	values[2]	312	1			T2	6		T13	13		T44	16
auto[0]	values[5]	values[3]	294	1			T14	4		T41	17		T44	16
auto[0]	values[5]	values[4]	154	1			T18	18		T74	8		T195	18
auto[0]	values[5]	values[5]	307	1			T95	16		T169	74		T19	8
auto[0]	values[5]	values[6]	214	1			T166	10		T262	6		T263	10
auto[0]	values[5]	values[7]	207	1			T13	14		T169	12		T199	57
auto[0]	values[6]	values[0]	426	1			T92	14		T202	6		T168	11
auto[0]	values[6]	values[1]	249	1			T234	12		T18	10		T197	12
auto[0]	values[6]	values[2]	566	1			T85	61		T209	14		T222	22
auto[0]	values[6]	values[3]	285	1			T168	11		T230	13		T231	10
auto[0]	values[6]	values[4]	233	1			T15	15		T166	13		T169	70
auto[0]	values[6]	values[5]	132	1			T264	16		T219	13		T265	10
auto[0]	values[6]	values[6]	296	1			T13	14		T45	49		T88	6
auto[0]	values[6]	values[7]	250	1			T93	14		T42	13		T137	13
auto[0]	values[7]	values[0]	381	1			T15	11		T45	86		T168	20
auto[0]	values[7]	values[1]	266	1			T168	5		T29	17		T230	21
auto[0]	values[7]	values[2]	220	1			T13	15		T209	7		T166	11
auto[0]	values[7]	values[3]	183	1			T44	19		T169	43		T19	52
auto[0]	values[7]	values[4]	387	1			T13	15		T44	13		T220	15
auto[0]	values[7]	values[5]	419	1			T48	10		T194	6		T213	13
auto[0]	values[7]	values[6]	445	1			T45	12		T49	13		T197	9
auto[0]	values[7]	values[7]	361	1			T197	10		T89	10		T195	46
auto[1]	values[0]	values[0]	141	1			T41	8		T199	11		T89	7
auto[1]	values[0]	values[1]	162	1			T29	10		T157	5		T165	10
auto[1]	values[0]	values[2]	145	1			T12	12		T166	9		T199	9
auto[1]	values[0]	values[3]	62	1			T169	22		T220	7		T231	2
auto[1]	values[0]	values[4]	171	1			T42	8		T266	12		T199	5
auto[1]	values[0]	values[5]	122	1			T44	4		T168	11		T19	6
auto[1]	values[0]	values[6]	226	1			T15	11		T45	4		T209	11
auto[1]	values[0]	values[7]	177	1			T4	22		T48	9		T49	9
auto[1]	values[1]	values[0]	190	1			T220	9		T89	6		T195	10
auto[1]	values[1]	values[1]	276	1			T15	17		T43	10		T229	16
auto[1]	values[1]	values[2]	257	1			T15	14		T42	24		T18	5
auto[1]	values[1]	values[3]	293	1			T197	45		T213	7		T210	17
auto[1]	values[1]	values[4]	183	1			T15	9		T246	26		T167	15
auto[1]	values[1]	values[5]	98	1			T13	2		T43	8		T165	9
auto[1]	values[1]	values[6]	165	1			T44	7		T50	6		T18	8
auto[1]	values[1]	values[7]	318	1			T45	11		T43	3		T18	9
auto[1]	values[2]	values[0]	206	1			T48	9		T195	19		T267	25
auto[1]	values[2]	values[1]	182	1			T13	9		T168	11		T230	11
auto[1]	values[2]	values[2]	94	1			T15	7		T167	9		T195	15
auto[1]	values[2]	values[3]	208	1			T48	9		T229	6		T29	24
auto[1]	values[2]	values[4]	106	1			T41	7		T45	31		T209	11
auto[1]	values[2]	values[5]	216	1			T268	8		T199	9		T89	12
auto[1]	values[2]	values[6]	271	1			T49	5		T197	13		T237	18
auto[1]	values[2]	values[7]	184	1			T18	16		T197	19		T169	15
auto[1]	values[3]	values[0]	261	1			T13	12		T41	50		T213	7
auto[1]	values[3]	values[1]	209	1			T41	14		T43	7		T18	9
auto[1]	values[3]	values[2]	125	1			T166	9		T89	4		T219	7
auto[1]	values[3]	values[3]	184	1			T166	6		T61	7		T269	7
auto[1]	values[3]	values[4]	189	1			T242	7		T195	6		T241	34
auto[1]	values[3]	values[5]	215	1			T167	3		T29	9		T199	5
auto[1]	values[3]	values[6]	163	1			T41	10		T199	15		T256	9
auto[1]	values[3]	values[7]	135	1			T166	5		T74	21		T157	25
auto[1]	values[4]	values[0]	223	1			T44	14		T199	19		T230	9
auto[1]	values[4]	values[1]	137	1			T13	7		T44	13		T205	6
auto[1]	values[4]	values[2]	306	1			T15	14		T49	12		T228	24
auto[1]	values[4]	values[3]	196	1			T44	5		T29	26		T195	10
auto[1]	values[4]	values[4]	182	1			T49	6		T43	5		T19	11
auto[1]	values[4]	values[5]	203	1			T44	1		T209	12		T166	57
auto[1]	values[4]	values[6]	327	1			T41	6		T29	10		T220	6
auto[1]	values[4]	values[7]	274	1			T197	11		T259	10		T270	6
auto[1]	values[5]	values[0]	121	1			T167	5		T137	10		T196	9
auto[1]	values[5]	values[1]	152	1			T45	11		T19	21		T231	13
auto[1]	values[5]	values[2]	236	1			T13	7		T44	5		T221	20
auto[1]	values[5]	values[3]	181	1			T41	3		T44	6		T166	11
auto[1]	values[5]	values[4]	111	1			T18	8		T74	20		T195	5
auto[1]	values[5]	values[5]	162	1			T169	10		T19	12		T213	6
auto[1]	values[5]	values[6]	172	1			T166	10		T259	14		T267	39
auto[1]	values[5]	values[7]	147	1			T13	6		T169	21		T199	9
auto[1]	values[6]	values[0]	196	1			T168	60		T29	13		T53	11
auto[1]	values[6]	values[1]	204	1			T18	10		T197	36		T166	9
auto[1]	values[6]	values[2]	282	1			T209	9		T259	11		T270	31
auto[1]	values[6]	values[3]	201	1			T168	9		T230	46		T231	11
auto[1]	values[6]	values[4]	124	1			T15	5		T166	7		T169	23
auto[1]	values[6]	values[5]	129	1			T219	8		T265	10		T271	14
auto[1]	values[6]	values[6]	107	1			T13	6		T45	5		T197	20
auto[1]	values[6]	values[7]	192	1			T42	7		T272	2		T137	7
auto[1]	values[7]	values[0]	305	1			T15	9		T45	9		T168	10
auto[1]	values[7]	values[1]	252	1			T168	15		T29	11		T230	8
auto[1]	values[7]	values[2]	239	1			T13	5		T209	16		T166	9
auto[1]	values[7]	values[3]	146	1			T44	22		T169	5		T19	11
auto[1]	values[7]	values[4]	265	1			T13	5		T44	38		T273	2
auto[1]	values[7]	values[5]	398	1			T48	10		T213	7		T210	6
auto[1]	values[7]	values[6]	213	1			T45	8		T49	55		T197	12
auto[1]	values[7]	values[7]	355	1			T197	14		T89	10		T195	6