Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	363	1			T13	4		T15	1		T92	4
auto[ReadAddrCrossIntoMailbox]	318	1			T92	2		T41	2		T45	4
auto[ReadAddrCrossOutOfMailbox]	279	1			T13	3		T41	3		T45	3
auto[ReadAddrCrossAllMailbox]	221	1			T15	2		T92	6		T41	1
auto[ReadAddrOutsideMailbox]	3508	1			T2	4		T4	2		T7	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2316

1

T2

2

T4

1

T7

1

auto[1]

2373

1

T2

2

T4

1

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	762	1			T13	10		T15	3		T92	8
read_ops[0x0b]	784	1			T12	4		T13	8		T14	2
read_ops[0x3b]	746	1			T13	3		T15	5		T41	7
read_ops[0x6b]	768	1			T2	2		T4	2		T12	2
read_ops[0xbb]	842	1			T2	2		T13	9		T15	13
read_ops[0xeb]	787	1			T7	2		T13	11		T15	9

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	17	1			T13	1		T250	1		T44	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T41	1		T250	1		T44	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T92	1		T45	1		T209	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T92	1		T41	1		T44	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T13	1		T49	1		T44	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T45	1		T197	2		T29	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T92	2		T197	1		T168	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T92	2		T18	1		T199	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T13	4		T15	1		T92	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	264	1			T13	4		T15	2		T92	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T234	2		T199	2		T200	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T234	2		T166	1		T29	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T209	1		T251	1		T199	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T209	1		T167	2		T168	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T166	1		T242	1		T157	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T44	1		T209	1		T169	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T169	1		T168	1		T251	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T251	1		T29	1		T230	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	323	1			T12	2		T13	2		T14	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T12	2		T13	6		T14	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T43	1		T212	3		T209	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T13	1		T212	3		T209	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T45	1		T43	1		T209	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T44	1		T209	1		T168	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T41	1		T45	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T41	1		T169	1		T29	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T45	1		T49	2		T44	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T197	1		T165	1		T256	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	275	1			T13	1		T41	1		T45	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	267	1			T13	1		T15	5		T41	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T234	1		T168	1		T19	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T234	1		T18	1		T168	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T45	1		T18	1		T29	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T49	2		T43	1		T166	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T41	1		T169	2		T74	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	13	1			T13	1		T18	1		T29	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T45	1		T168	2		T165	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T49	1		T169	1		T29	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T2	1		T4	1		T12	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T2	1		T4	1		T12	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T92	2		T45	2		T212	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T15	1		T92	2		T212	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T41	1		T45	1		T48	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T44	1		T169	1		T251	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T49	1		T29	1		T230	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T45	1		T18	1		T166	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T92	1		T49	1		T44	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T15	1		T92	1		T169	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T2	1		T13	6		T15	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	320	1			T2	1		T13	3		T15	8
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T13	1		T212	1		T19	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T13	1		T212	1		T44	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T167	1		T169	1		T74	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T44	1		T167	1		T199	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T42	2		T18	1		T169	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T13	1		T168	1		T220	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T15	1		T41	1		T169	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T45	1		T44	1		T199	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	258	1			T7	1		T13	2		T15	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	324	1			T7	1		T13	6		T15	5