Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4628	1			T2	6		T12	12		T92	14
values[1]	3830	1			T3	8		T9	10		T13	40
values[2]	3607	1			T13	20		T41	61		T45	40
values[3]	3945	1			T15	20		T93	14		T42	21
values[4]	4036	1			T14	4		T15	20		T202	6
values[5]	3474	1			T13	40		T15	23		T41	89
values[6]	3752	1			T4	22		T13	60		T15	22
values[7]	3900	1			T7	6		T13	20		T15	43

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4154	1			T46	2		T43	40		T44	22
values[1]	3451	1			T15	43		T202	6		T41	83
values[2]	3703	1			T13	20		T14	4		T15	22
values[3]	3496	1			T13	60		T15	20		T214	16
values[4]	4372	1			T3	8		T7	6		T15	20
values[5]	3924	1			T13	40		T15	40		T93	14
values[6]	3794	1			T2	6		T4	22		T9	10
values[7]	4278	1			T13	20		T47	20		T41	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30397

1

T2

6

T3

8

T4

22

auto[1]

775

1

T12

2

T13

7

T15

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	639	1			T209	22		T197	50		T251	10
auto[0]	values[0]	values[1]	478	1			T41	19		T45	95		T44	20
auto[0]	values[0]	values[2]	584	1			T197	38		T168	29		T205	66
auto[0]	values[0]	values[3]	514	1			T44	20		T197	24		T258	6
auto[0]	values[0]	values[4]	935	1			T220	19		T199	65		T230	16
auto[0]	values[0]	values[5]	452	1			T42	34		T197	22		T169	20
auto[0]	values[0]	values[6]	521	1			T2	6		T12	10		T92	14
auto[0]	values[0]	values[7]	388	1			T18	25		T266	12		T230	20
auto[0]	values[1]	values[0]	508	1			T46	2		T43	20		T252	74
auto[0]	values[1]	values[1]	484	1			T41	22		T137	21		T274	2
auto[0]	values[1]	values[2]	512	1			T13	20		T44	21		T234	12
auto[0]	values[1]	values[3]	311	1			T13	19		T18	25		T275	12
auto[0]	values[1]	values[4]	260	1			T3	8		T15	20		T88	6
auto[0]	values[1]	values[5]	410	1			T15	19		T166	33		T165	20
auto[0]	values[1]	values[6]	609	1			T9	10		T15	20		T166	151
auto[0]	values[1]	values[7]	632	1			T197	17		T242	20		T199	71
auto[0]	values[2]	values[0]	447	1			T267	21		T196	33		T239	65
auto[0]	values[2]	values[1]	310	1			T41	41		T166	31		T169	31
auto[0]	values[2]	values[2]	473	1			T41	19		T45	20		T18	34
auto[0]	values[2]	values[3]	508	1			T13	20		T44	20		T169	73
auto[0]	values[2]	values[4]	503	1			T45	20		T220	20		T30	20
auto[0]	values[2]	values[5]	397	1			T137	23		T267	34		T276	14
auto[0]	values[2]	values[6]	369	1			T222	22		T168	102		T29	36
auto[0]	values[2]	values[7]	515	1			T48	21		T44	70		T209	24
auto[0]	values[3]	values[0]	765	1			T168	71		T19	23		T277	2
auto[0]	values[3]	values[1]	612	1			T168	20		T133	12		T199	16
auto[0]	values[3]	values[2]	448	1			T43	19		T228	20		T89	20
auto[0]	values[3]	values[3]	340	1			T44	20		T167	20		T19	19
auto[0]	values[3]	values[4]	247	1			T205	20		T278	39		T279	4
auto[0]	values[3]	values[5]	458	1			T15	20		T93	14		T280	2
auto[0]	values[3]	values[6]	502	1			T42	21		T209	20		T18	44
auto[0]	values[3]	values[7]	478	1			T197	20		T74	57		T257	4
auto[0]	values[4]	values[0]	421	1			T43	20		T44	22		T232	20
auto[0]	values[4]	values[1]	547	1			T202	6		T49	20		T168	20
auto[0]	values[4]	values[2]	416	1			T14	4		T95	16		T44	25
auto[0]	values[4]	values[3]	432	1			T15	20		T214	16		T195	27
auto[0]	values[4]	values[4]	643	1			T246	26		T50	4		T166	20
auto[0]	values[4]	values[5]	604	1			T96	6		T74	33		T199	71
auto[0]	values[4]	values[6]	305	1			T229	20		T166	19		T267	25
auto[0]	values[4]	values[7]	584	1			T197	20		T169	28		T29	24
auto[0]	values[5]	values[0]	517	1			T273	2		T197	20		T201	6
auto[0]	values[5]	values[1]	279	1			T195	21		T205	20		T281	19
auto[0]	values[5]	values[2]	472	1			T282	18		T239	20		T206	18
auto[0]	values[5]	values[3]	349	1			T49	20		T197	47		T167	17
auto[0]	values[5]	values[4]	415	1			T48	20		T221	20		T209	22
auto[0]	values[5]	values[5]	392	1			T41	48		T45	57		T197	47
auto[0]	values[5]	values[6]	406	1			T13	19		T15	20		T41	20
auto[0]	values[5]	values[7]	548	1			T13	20		T41	19		T48	18
auto[0]	values[6]	values[0]	407	1			T194	6		T169	20		T242	16
auto[0]	values[6]	values[1]	181	1			T19	19		T283	8		T213	20
auto[0]	values[6]	values[2]	374	1			T15	19		T43	18		T167	20
auto[0]	values[6]	values[3]	558	1			T49	66		T85	61		T168	18
auto[0]	values[6]	values[4]	653	1			T250	2		T209	21		T169	26
auto[0]	values[6]	values[5]	491	1			T13	40		T45	52		T166	20
auto[0]	values[6]	values[6]	460	1			T4	22		T13	18		T168	20
auto[0]	values[6]	values[7]	520	1			T48	19		T166	27		T169	20
auto[0]	values[7]	values[0]	347	1			T166	18		T261	4		T237	18
auto[0]	values[7]	values[1]	473	1			T15	42		T45	20		T167	20
auto[0]	values[7]	values[2]	335	1			T19	19		T29	21		T268	6
auto[0]	values[7]	values[3]	385	1			T13	17		T168	18		T89	19
auto[0]	values[7]	values[4]	623	1			T7	6		T42	20		T199	115
auto[0]	values[7]	values[5]	626	1			T169	81		T199	88		T205	20
auto[0]	values[7]	values[6]	528	1			T41	22		T49	33		T255	6
auto[0]	values[7]	values[7]	497	1			T47	20		T43	20		T212	14
auto[1]	values[0]	values[0]	12	1			T209	1		T197	3		T230	3
auto[1]	values[0]	values[1]	22	1			T41	1		T29	2		T231	1
auto[1]	values[0]	values[2]	13	1			T197	1		T168	1		T241	3
auto[1]	values[0]	values[3]	23	1			T29	3		T213	3		T195	1
auto[1]	values[0]	values[4]	17	1			T220	1		T199	2		T230	4
auto[1]	values[0]	values[5]	4	1			T89	1		T195	1		T284	1
auto[1]	values[0]	values[6]	17	1			T12	2		T18	1		T285	4
auto[1]	values[0]	values[7]	9	1			T18	2		T239	1		T286	6
auto[1]	values[1]	values[0]	18	1			T168	2		T241	2		T287	2
auto[1]	values[1]	values[1]	14	1			T288	1		T289	1		T290	2
auto[1]	values[1]	values[2]	14	1			T29	1		T210	1		T91	3
auto[1]	values[1]	values[3]	9	1			T13	1		T18	1		T291	1
auto[1]	values[1]	values[4]	7	1			T292	2		T293	2		T294	3
auto[1]	values[1]	values[5]	16	1			T15	1		T89	3		T270	2
auto[1]	values[1]	values[6]	11	1			T166	2		T213	1		T295	1
auto[1]	values[1]	values[7]	15	1			T197	3		T242	1		T199	1
auto[1]	values[2]	values[0]	6	1			T196	1		T240	2		T296	1
auto[1]	values[2]	values[1]	7	1			T169	2		T213	2		T291	1
auto[1]	values[2]	values[2]	7	1			T41	1		T265	2		T292	1
auto[1]	values[2]	values[3]	9	1			T44	1		T195	1		T159	1
auto[1]	values[2]	values[4]	7	1			T297	2		T298	4		T299	1
auto[1]	values[2]	values[5]	10	1			T206	1		T291	1		T300	1
auto[1]	values[2]	values[6]	10	1			T168	2		T29	1		T230	2
auto[1]	values[2]	values[7]	29	1			T48	2		T44	1		T209	1
auto[1]	values[3]	values[0]	27	1			T199	2		T157	3		T231	3
auto[1]	values[3]	values[1]	15	1			T199	4		T301	2		T302	3
auto[1]	values[3]	values[2]	16	1			T43	1		T228	4		T303	2
auto[1]	values[3]	values[3]	9	1			T44	1		T19	1		T230	2
auto[1]	values[3]	values[4]	3	1			T278	3		-	-		-	-
auto[1]	values[3]	values[5]	11	1			T304	2		T305	2		T306	1
auto[1]	values[3]	values[6]	11	1			T18	1		T19	2		T89	1
auto[1]	values[3]	values[7]	3	1			T74	1		T206	1		T294	1
auto[1]	values[4]	values[0]	10	1			T270	4		T289	1		T307	1
auto[1]	values[4]	values[1]	10	1			T308	1		T30	1		T292	2
auto[1]	values[4]	values[2]	12	1			T166	1		T167	7		T309	2
auto[1]	values[4]	values[3]	6	1			T196	2		T310	1		T311	1
auto[1]	values[4]	values[4]	20	1			T50	2		T169	1		T199	6
auto[1]	values[4]	values[5]	10	1			T292	1		T291	1		T312	2
auto[1]	values[4]	values[6]	5	1			T166	1		T313	1		T314	1
auto[1]	values[4]	values[7]	11	1			T197	1		T210	1		T61	2
auto[1]	values[5]	values[0]	12	1			T197	1		T29	1		T196	1
auto[1]	values[5]	values[1]	6	1			T195	2		T281	1		T315	1
auto[1]	values[5]	values[2]	9	1			T206	2		T315	1		T316	4
auto[1]	values[5]	values[3]	14	1			T197	1		T167	3		T219	1
auto[1]	values[5]	values[4]	10	1			T209	1		T29	4		T199	2
auto[1]	values[5]	values[5]	14	1			T41	1		T45	2		T168	1
auto[1]	values[5]	values[6]	12	1			T13	1		T15	3		T49	1
auto[1]	values[5]	values[7]	19	1			T41	1		T48	2		T229	1
auto[1]	values[6]	values[0]	10	1			T242	4		T199	1		T53	1
auto[1]	values[6]	values[1]	5	1			T19	1		T267	1		T241	1
auto[1]	values[6]	values[2]	12	1			T15	3		T43	2		T168	2
auto[1]	values[6]	values[3]	21	1			T49	2		T168	2		T281	1
auto[1]	values[6]	values[4]	15	1			T157	1		T30	1		T196	3
auto[1]	values[6]	values[5]	15	1			T45	2		T157	5		T89	1
auto[1]	values[6]	values[6]	10	1			T13	2		T240	3		T317	2
auto[1]	values[6]	values[7]	20	1			T48	4		T89	3		T241	1
auto[1]	values[7]	values[0]	8	1			T166	2		T241	3		T53	2
auto[1]	values[7]	values[1]	8	1			T15	1		T157	1		T230	1
auto[1]	values[7]	values[2]	6	1			T19	1		T268	2		T301	1
auto[1]	values[7]	values[3]	8	1			T13	3		T168	2		T89	1
auto[1]	values[7]	values[4]	14	1			T199	2		T61	1		T303	2
auto[1]	values[7]	values[5]	14	1			T169	3		T137	1		T198	3
auto[1]	values[7]	values[6]	18	1			T18	1		T308	1		T30	2
auto[1]	values[7]	values[7]	10	1			T89	1		T61	1		T318	4