Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1664

1

T5

3

T8

8

T11

12

auto[1]

1723

1

T5

9

T8

6

T11

25

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1700

1

T5

10

T8

12

T24

6

auto[1]

1687

1

T5

2

T8

2

T11

37

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2688

1

T5

9

T8

10

T11

37

auto[1]

699

1

T5

3

T8

4

T24

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	678	1			T8	1		T11	7		T22	4
valid[1]	651	1			T5	4		T8	5		T11	11
valid[2]	680	1			T5	4		T8	2		T11	10
valid[3]	662	1			T5	2		T8	5		T11	6
valid[4]	716	1			T5	2		T8	1		T11	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	99	1			T8	1		T24	1		T15	2
auto[0]	auto[0]	valid[0]	auto[1]	182	1			T11	1		T22	1		T23	2
auto[0]	auto[0]	valid[1]	auto[0]	106	1			T5	1		T8	2		T26	1
auto[0]	auto[0]	valid[1]	auto[1]	160	1			T11	7		T22	1		T23	3
auto[0]	auto[0]	valid[2]	auto[0]	94	1			T26	1		T52	1		T333	1
auto[0]	auto[0]	valid[2]	auto[1]	150	1			T8	1		T11	2		T22	1
auto[0]	auto[0]	valid[3]	auto[0]	94	1			T8	1		T26	1		T15	1
auto[0]	auto[0]	valid[3]	auto[1]	159	1			T11	2		T22	4		T23	2
auto[0]	auto[0]	valid[4]	auto[0]	85	1			T42	1		T17	1		T36	1
auto[0]	auto[0]	valid[4]	auto[1]	178	1			T5	1		T22	1		T23	1
auto[0]	auto[1]	valid[0]	auto[0]	103	1			T26	1		T52	1		T48	1
auto[0]	auto[1]	valid[0]	auto[1]	163	1			T11	6		T22	3		T23	2
auto[0]	auto[1]	valid[1]	auto[0]	92	1			T5	1		T8	2		T330	1
auto[0]	auto[1]	valid[1]	auto[1]	151	1			T11	4		T22	1		T83	5
auto[0]	auto[1]	valid[2]	auto[0]	109	1			T5	3		T26	1		T52	1
auto[0]	auto[1]	valid[2]	auto[1]	180	1			T11	8		T23	1		T15	1
auto[0]	auto[1]	valid[3]	auto[0]	104	1			T5	2		T8	1		T26	1
auto[0]	auto[1]	valid[3]	auto[1]	175	1			T8	1		T11	4		T23	2
auto[0]	auto[1]	valid[4]	auto[0]	115	1			T8	1		T24	1		T26	1
auto[0]	auto[1]	valid[4]	auto[1]	189	1			T5	1		T11	3		T22	2
auto[1]	auto[0]	valid[0]	auto[0]	66	1			T15	1		T333	1		T43	1
auto[1]	auto[0]	valid[1]	auto[0]	70	1			T5	1		T8	1		T24	1
auto[1]	auto[0]	valid[2]	auto[0]	80	1			T8	1		T333	1		T330	1
auto[1]	auto[0]	valid[3]	auto[0]	61	1			T8	1		T48	1		T330	1
auto[1]	auto[0]	valid[4]	auto[0]	80	1			T26	2		T15	1		T36	1
auto[1]	auto[1]	valid[0]	auto[0]	65	1			T42	1		T17	2		T36	1
auto[1]	auto[1]	valid[1]	auto[0]	72	1			T5	1		T24	2		T44	1
auto[1]	auto[1]	valid[2]	auto[0]	67	1			T5	1		T26	1		T15	2
auto[1]	auto[1]	valid[3]	auto[0]	69	1			T8	1		T26	1		T17	1
auto[1]	auto[1]	valid[4]	auto[0]	69	1			T24	1		T26	2		T44	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal