Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44938

1

T1

14

T5

484

T8

288

auto[1]

17407

1

T5

78

T8

48

T11

390

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45551

1

T1

8

T5

379

T8

220

auto[1]

16794

1

T1

6

T5

183

T8

116

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32404	1			T1	6		T5	267		T8	174
others[1]	5164	1			T1	2		T5	55		T8	30
others[2]	5315	1			T1	1		T5	58		T8	32
others[3]	5889	1			T1	1		T5	61		T8	34
interest[1]	3400	1			T5	26		T8	16		T11	26
interest[4]	21283	1			T1	3		T5	181		T8	114
interest[64]	10173	1			T1	4		T5	95		T8	50

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14526	1			T1	3		T5	141		T8	92
auto[0]	auto[0]	others[1]	2334	1			T1	1		T5	35		T8	19
auto[0]	auto[0]	others[2]	2410	1			T1	1		T5	29		T8	15
auto[0]	auto[0]	others[3]	2644	1			T5	29		T8	13		T24	11
auto[0]	auto[0]	interest[1]	1585	1			T5	13		T8	12		T24	5
auto[0]	auto[0]	interest[4]	9436	1			T1	1		T5	92		T8	59
auto[0]	auto[0]	interest[64]	4645	1			T1	3		T5	54		T8	21
auto[0]	auto[1]	others[0]	9206	1			T5	38		T8	25		T11	193
auto[0]	auto[1]	others[1]	1446	1			T5	7		T8	3		T11	27
auto[0]	auto[1]	others[2]	1437	1			T5	8		T8	4		T11	45
auto[0]	auto[1]	others[3]	1640	1			T5	11		T8	7		T11	37
auto[0]	auto[1]	interest[1]	944	1			T5	4		T11	26		T23	25
auto[0]	auto[1]	interest[4]	6128	1			T5	26		T8	15		T11	135
auto[0]	auto[1]	interest[64]	2734	1			T5	10		T8	9		T11	62
auto[1]	auto[0]	others[0]	8672	1			T1	3		T5	88		T8	57
auto[1]	auto[0]	others[1]	1384	1			T1	1		T5	13		T8	8
auto[1]	auto[0]	others[2]	1468	1			T5	21		T8	13		T24	5
auto[1]	auto[0]	others[3]	1605	1			T1	1		T5	21		T8	14
auto[1]	auto[0]	interest[1]	871	1			T5	9		T8	4		T24	3
auto[1]	auto[0]	interest[4]	5719	1			T1	2		T5	63		T8	40
auto[1]	auto[0]	interest[64]	2794	1			T1	1		T5	31		T8	20

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal