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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1149
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T119 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2600111277 Aug 16 04:53:06 PM PDT 24 Aug 16 04:53:09 PM PDT 24 189449248 ps
T122 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2640725998 Aug 16 04:53:02 PM PDT 24 Aug 16 04:53:04 PM PDT 24 27194644 ps
T1049 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.897086821 Aug 16 04:53:12 PM PDT 24 Aug 16 04:53:13 PM PDT 24 54862223 ps
T1050 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3560041560 Aug 16 04:53:14 PM PDT 24 Aug 16 04:53:15 PM PDT 24 14702256 ps
T1051 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4272771174 Aug 16 04:53:14 PM PDT 24 Aug 16 04:53:15 PM PDT 24 13680433 ps
T1052 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4187263607 Aug 16 04:52:46 PM PDT 24 Aug 16 04:52:47 PM PDT 24 33255073 ps
T1053 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1938259971 Aug 16 04:52:49 PM PDT 24 Aug 16 04:52:50 PM PDT 24 62092671 ps
T110 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4226520025 Aug 16 04:52:45 PM PDT 24 Aug 16 04:52:48 PM PDT 24 784779298 ps
T1054 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2664092729 Aug 16 04:53:17 PM PDT 24 Aug 16 04:53:18 PM PDT 24 28264124 ps
T1055 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.478487203 Aug 16 04:52:56 PM PDT 24 Aug 16 04:52:57 PM PDT 24 46537402 ps
T117 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.419130954 Aug 16 04:53:05 PM PDT 24 Aug 16 04:53:08 PM PDT 24 91251840 ps
T1056 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3049365108 Aug 16 04:53:02 PM PDT 24 Aug 16 04:53:03 PM PDT 24 22894087 ps
T104 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1365346489 Aug 16 04:52:55 PM PDT 24 Aug 16 04:53:19 PM PDT 24 1906344682 ps
T120 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2175934466 Aug 16 04:52:44 PM PDT 24 Aug 16 04:52:49 PM PDT 24 70244997 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3986337266 Aug 16 04:52:53 PM PDT 24 Aug 16 04:52:57 PM PDT 24 61829856 ps
T1058 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3234090331 Aug 16 04:53:06 PM PDT 24 Aug 16 04:53:07 PM PDT 24 45067077 ps
T1059 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2696736779 Aug 16 04:52:54 PM PDT 24 Aug 16 04:52:56 PM PDT 24 518817369 ps
T176 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1772495072 Aug 16 04:52:56 PM PDT 24 Aug 16 04:53:11 PM PDT 24 807975921 ps
T123 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1140985119 Aug 16 04:53:02 PM PDT 24 Aug 16 04:53:05 PM PDT 24 40996132 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2541995259 Aug 16 04:52:46 PM PDT 24 Aug 16 04:52:48 PM PDT 24 207655056 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4277264993 Aug 16 04:52:40 PM PDT 24 Aug 16 04:52:42 PM PDT 24 101295830 ps
T111 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.445610013 Aug 16 04:52:57 PM PDT 24 Aug 16 04:53:04 PM PDT 24 781894218 ps
T150 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2746079268 Aug 16 04:52:42 PM PDT 24 Aug 16 04:52:46 PM PDT 24 1681553988 ps
T1062 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3504657565 Aug 16 04:53:15 PM PDT 24 Aug 16 04:53:16 PM PDT 24 13065782 ps
T1063 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3858236216 Aug 16 04:53:12 PM PDT 24 Aug 16 04:53:13 PM PDT 24 53879766 ps
T151 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.116687875 Aug 16 04:53:06 PM PDT 24 Aug 16 04:53:09 PM PDT 24 349472964 ps
T79 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3625243291 Aug 16 04:52:44 PM PDT 24 Aug 16 04:52:45 PM PDT 24 215075359 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1468420327 Aug 16 04:52:46 PM PDT 24 Aug 16 04:52:47 PM PDT 24 22232025 ps
T124 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2811894163 Aug 16 04:52:44 PM PDT 24 Aug 16 04:52:46 PM PDT 24 122599290 ps
T125 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4248956228 Aug 16 04:52:59 PM PDT 24 Aug 16 04:53:01 PM PDT 24 64257540 ps
T1065 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2879321153 Aug 16 04:52:56 PM PDT 24 Aug 16 04:52:57 PM PDT 24 14489020 ps
T152 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1633685905 Aug 16 04:53:03 PM PDT 24 Aug 16 04:53:05 PM PDT 24 291274650 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.156356937 Aug 16 04:52:50 PM PDT 24 Aug 16 04:52:52 PM PDT 24 50197890 ps
T126 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3944099634 Aug 16 04:52:47 PM PDT 24 Aug 16 04:52:48 PM PDT 24 67391445 ps
T1067 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3560293450 Aug 16 04:53:10 PM PDT 24 Aug 16 04:53:11 PM PDT 24 12840719 ps
T1068 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1592031427 Aug 16 04:53:12 PM PDT 24 Aug 16 04:53:12 PM PDT 24 47872755 ps
T1069 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2824793512 Aug 16 04:53:02 PM PDT 24 Aug 16 04:53:03 PM PDT 24 43961045 ps
T156 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1617951009 Aug 16 04:53:06 PM PDT 24 Aug 16 04:53:07 PM PDT 24 490041397 ps
T153 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2088741827 Aug 16 04:52:43 PM PDT 24 Aug 16 04:52:51 PM PDT 24 687328378 ps
T1070 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.626450195 Aug 16 04:53:24 PM PDT 24 Aug 16 04:53:25 PM PDT 24 15268747 ps
T1071 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2149293986 Aug 16 04:52:45 PM PDT 24 Aug 16 04:52:47 PM PDT 24 91633260 ps
T177 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3376751732 Aug 16 04:52:59 PM PDT 24 Aug 16 04:53:19 PM PDT 24 3297047028 ps
T1072 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4083926355 Aug 16 04:52:52 PM PDT 24 Aug 16 04:52:55 PM PDT 24 72098512 ps
T106 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1026506465 Aug 16 04:52:59 PM PDT 24 Aug 16 04:53:04 PM PDT 24 150445110 ps
T1073 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3906477221 Aug 16 04:52:56 PM PDT 24 Aug 16 04:52:57 PM PDT 24 11904662 ps
T112 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2592273848 Aug 16 04:52:43 PM PDT 24 Aug 16 04:52:45 PM PDT 24 25768336 ps
T154 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.281996968 Aug 16 04:52:58 PM PDT 24 Aug 16 04:53:01 PM PDT 24 362555447 ps
T155 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.181482691 Aug 16 04:52:44 PM PDT 24 Aug 16 04:52:46 PM PDT 24 82656591 ps
T1074 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3884976382 Aug 16 04:52:45 PM PDT 24 Aug 16 04:52:46 PM PDT 24 39740432 ps
T80 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.732415141 Aug 16 04:52:44 PM PDT 24 Aug 16 04:52:46 PM PDT 24 23575857 ps
T163 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4080824150 Aug 16 04:53:04 PM PDT 24 Aug 16 04:53:17 PM PDT 24 4636942134 ps
T127 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3410504671 Aug 16 04:53:02 PM PDT 24 Aug 16 04:53:04 PM PDT 24 81572573 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3455093672 Aug 16 04:52:46 PM PDT 24 Aug 16 04:52:47 PM PDT 24 40075183 ps
T1076 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.265393639 Aug 16 04:53:00 PM PDT 24 Aug 16 04:53:02 PM PDT 24 143300769 ps
T1077 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3545017559 Aug 16 04:52:49 PM PDT 24 Aug 16 04:52:53 PM PDT 24 176167919 ps
T1078 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3220272651 Aug 16 04:53:11 PM PDT 24 Aug 16 04:53:12 PM PDT 24 11443824 ps
T1079 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1335313103 Aug 16 04:52:57 PM PDT 24 Aug 16 04:52:59 PM PDT 24 431835676 ps
T81 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.392946400 Aug 16 04:52:50 PM PDT 24 Aug 16 04:52:52 PM PDT 24 53944977 ps
T1080 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3358155369 Aug 16 04:53:01 PM PDT 24 Aug 16 04:53:23 PM PDT 24 889211727 ps
T128 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3842083838 Aug 16 04:53:02 PM PDT 24 Aug 16 04:53:05 PM PDT 24 573508852 ps
T1081 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1094850851 Aug 16 04:53:05 PM PDT 24 Aug 16 04:53:08 PM PDT 24 88993609 ps
T1082 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3883989188 Aug 16 04:52:50 PM PDT 24 Aug 16 04:52:51 PM PDT 24 102285701 ps
T1083 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.944703836 Aug 16 04:53:07 PM PDT 24 Aug 16 04:53:08 PM PDT 24 58460975 ps
T1084 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2433248307 Aug 16 04:53:15 PM PDT 24 Aug 16 04:53:16 PM PDT 24 96187365 ps
T107 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2875510383 Aug 16 04:53:04 PM PDT 24 Aug 16 04:53:09 PM PDT 24 70587978 ps
T1085 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4138057103 Aug 16 04:52:47 PM PDT 24 Aug 16 04:52:48 PM PDT 24 49368254 ps
T1086 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2070768863 Aug 16 04:53:18 PM PDT 24 Aug 16 04:53:19 PM PDT 24 11991026 ps
T129 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3171907353 Aug 16 04:52:48 PM PDT 24 Aug 16 04:53:09 PM PDT 24 367556632 ps
T1087 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2287829484 Aug 16 04:53:03 PM PDT 24 Aug 16 04:53:05 PM PDT 24 238890701 ps
T115 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.470827303 Aug 16 04:52:52 PM PDT 24 Aug 16 04:52:54 PM PDT 24 84681961 ps
T1088 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3165096647 Aug 16 04:53:00 PM PDT 24 Aug 16 04:53:02 PM PDT 24 154609143 ps
T184 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1689289306 Aug 16 04:53:04 PM PDT 24 Aug 16 04:53:12 PM PDT 24 319919808 ps
T1089 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2510209931 Aug 16 04:52:55 PM PDT 24 Aug 16 04:52:56 PM PDT 24 21459055 ps
T178 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3687331271 Aug 16 04:52:57 PM PDT 24 Aug 16 04:53:15 PM PDT 24 297846362 ps
T1090 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3178888849 Aug 16 04:52:58 PM PDT 24 Aug 16 04:53:00 PM PDT 24 93108808 ps
T1091 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.620096640 Aug 16 04:52:58 PM PDT 24 Aug 16 04:53:02 PM PDT 24 492913055 ps
T116 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1891836182 Aug 16 04:53:01 PM PDT 24 Aug 16 04:53:04 PM PDT 24 75966694 ps
T1092 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4253461132 Aug 16 04:52:58 PM PDT 24 Aug 16 04:53:03 PM PDT 24 1083710061 ps
T1093 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.441357586 Aug 16 04:53:01 PM PDT 24 Aug 16 04:53:04 PM PDT 24 57920400 ps
T130 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4094013077 Aug 16 04:52:51 PM PDT 24 Aug 16 04:52:54 PM PDT 24 157327700 ps
T1094 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.439130589 Aug 16 04:53:10 PM PDT 24 Aug 16 04:53:11 PM PDT 24 46653224 ps
T180 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3971591616 Aug 16 04:53:07 PM PDT 24 Aug 16 04:53:25 PM PDT 24 283819425 ps
T1095 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3365526420 Aug 16 04:53:08 PM PDT 24 Aug 16 04:53:11 PM PDT 24 158807899 ps
T1096 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3958300983 Aug 16 04:53:00 PM PDT 24 Aug 16 04:53:02 PM PDT 24 114569101 ps
T108 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.595915728 Aug 16 04:52:59 PM PDT 24 Aug 16 04:53:04 PM PDT 24 158945189 ps
T1097 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.901684316 Aug 16 04:52:56 PM PDT 24 Aug 16 04:52:59 PM PDT 24 52481619 ps
T1098 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2720737407 Aug 16 04:53:14 PM PDT 24 Aug 16 04:53:14 PM PDT 24 23909763 ps
T1099 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1620157669 Aug 16 04:52:57 PM PDT 24 Aug 16 04:52:58 PM PDT 24 23125368 ps
T131 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3383104259 Aug 16 04:52:46 PM PDT 24 Aug 16 04:53:18 PM PDT 24 527833952 ps
T1100 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1386877672 Aug 16 04:52:59 PM PDT 24 Aug 16 04:53:02 PM PDT 24 126756169 ps
T1101 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1685147303 Aug 16 04:53:03 PM PDT 24 Aug 16 04:53:04 PM PDT 24 48142079 ps
T1102 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.433613552 Aug 16 04:53:11 PM PDT 24 Aug 16 04:53:12 PM PDT 24 15163920 ps
T132 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.175035282 Aug 16 04:52:53 PM PDT 24 Aug 16 04:52:55 PM PDT 24 62725235 ps
T113 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.202740617 Aug 16 04:52:47 PM PDT 24 Aug 16 04:52:50 PM PDT 24 46759100 ps
T1103 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.876478363 Aug 16 04:53:03 PM PDT 24 Aug 16 04:53:07 PM PDT 24 58778428 ps
T1104 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1322417346 Aug 16 04:52:53 PM PDT 24 Aug 16 04:52:54 PM PDT 24 23075030 ps
T1105 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2146476813 Aug 16 04:52:44 PM PDT 24 Aug 16 04:52:58 PM PDT 24 1289469408 ps
T1106 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2499523308 Aug 16 04:53:12 PM PDT 24 Aug 16 04:53:13 PM PDT 24 12756140 ps
T1107 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4130863355 Aug 16 04:53:01 PM PDT 24 Aug 16 04:53:02 PM PDT 24 39745889 ps
T1108 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2239456455 Aug 16 04:52:57 PM PDT 24 Aug 16 04:53:02 PM PDT 24 696586458 ps
T1109 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3159804824 Aug 16 04:52:46 PM PDT 24 Aug 16 04:52:54 PM PDT 24 1687137826 ps
T109 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1794911290 Aug 16 04:53:03 PM PDT 24 Aug 16 04:53:08 PM PDT 24 163677995 ps
T1110 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1767733492 Aug 16 04:53:04 PM PDT 24 Aug 16 04:53:06 PM PDT 24 19628723 ps
T1111 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.435497656 Aug 16 04:52:47 PM PDT 24 Aug 16 04:53:01 PM PDT 24 217727142 ps
T1112 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2220873335 Aug 16 04:52:59 PM PDT 24 Aug 16 04:53:02 PM PDT 24 182895042 ps
T1113 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.511029722 Aug 16 04:53:05 PM PDT 24 Aug 16 04:53:06 PM PDT 24 17488609 ps
T1114 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.933837083 Aug 16 04:53:05 PM PDT 24 Aug 16 04:53:08 PM PDT 24 500466043 ps
T1115 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2172759225 Aug 16 04:53:11 PM PDT 24 Aug 16 04:53:12 PM PDT 24 12806176 ps
T1116 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.833844439 Aug 16 04:52:49 PM PDT 24 Aug 16 04:53:05 PM PDT 24 3104170991 ps
T114 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.63939954 Aug 16 04:52:42 PM PDT 24 Aug 16 04:52:47 PM PDT 24 623335253 ps
T1117 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1918565449 Aug 16 04:52:46 PM PDT 24 Aug 16 04:52:48 PM PDT 24 21227700 ps
T1118 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1721039981 Aug 16 04:53:14 PM PDT 24 Aug 16 04:53:15 PM PDT 24 36699377 ps
T1119 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2071770119 Aug 16 04:52:55 PM PDT 24 Aug 16 04:53:30 PM PDT 24 9812643678 ps
T1120 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.763468566 Aug 16 04:53:04 PM PDT 24 Aug 16 04:53:07 PM PDT 24 44762252 ps
T181 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1418263684 Aug 16 04:52:46 PM PDT 24 Aug 16 04:53:08 PM PDT 24 3107409508 ps
T1121 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3484820557 Aug 16 04:52:59 PM PDT 24 Aug 16 04:53:14 PM PDT 24 640917768 ps
T1122 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2046716085 Aug 16 04:52:57 PM PDT 24 Aug 16 04:52:59 PM PDT 24 51146998 ps
T185 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.531491774 Aug 16 04:52:57 PM PDT 24 Aug 16 04:53:15 PM PDT 24 1511752775 ps
T175 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3646612344 Aug 16 04:52:58 PM PDT 24 Aug 16 04:53:01 PM PDT 24 56378180 ps
T183 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.634141873 Aug 16 04:53:00 PM PDT 24 Aug 16 04:53:15 PM PDT 24 3194791605 ps
T1123 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3307493056 Aug 16 04:52:57 PM PDT 24 Aug 16 04:53:00 PM PDT 24 405872688 ps
T1124 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2130924133 Aug 16 04:52:56 PM PDT 24 Aug 16 04:53:00 PM PDT 24 465291501 ps
T1125 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2057803209 Aug 16 04:53:01 PM PDT 24 Aug 16 04:53:01 PM PDT 24 11498107 ps
T1126 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3479777203 Aug 16 04:53:01 PM PDT 24 Aug 16 04:53:04 PM PDT 24 211370736 ps
T1127 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.373991215 Aug 16 04:52:54 PM PDT 24 Aug 16 04:52:55 PM PDT 24 18611199 ps
T1128 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3319092251 Aug 16 04:52:53 PM PDT 24 Aug 16 04:52:54 PM PDT 24 48458110 ps
T1129 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.420661151 Aug 16 04:53:06 PM PDT 24 Aug 16 04:53:11 PM PDT 24 1845351873 ps
T1130 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2563168541 Aug 16 04:53:15 PM PDT 24 Aug 16 04:53:16 PM PDT 24 31498532 ps
T1131 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.301424337 Aug 16 04:53:04 PM PDT 24 Aug 16 04:53:05 PM PDT 24 36408070 ps
T1132 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.64844652 Aug 16 04:53:06 PM PDT 24 Aug 16 04:53:09 PM PDT 24 703846275 ps
T1133 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1494521235 Aug 16 04:52:57 PM PDT 24 Aug 16 04:53:02 PM PDT 24 198164100 ps
T1134 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4192981882 Aug 16 04:53:13 PM PDT 24 Aug 16 04:53:13 PM PDT 24 16794628 ps
T182 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3043065251 Aug 16 04:52:57 PM PDT 24 Aug 16 04:53:12 PM PDT 24 824533762 ps
T1135 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3233575468 Aug 16 04:52:58 PM PDT 24 Aug 16 04:53:00 PM PDT 24 72459967 ps
T1136 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3550325390 Aug 16 04:52:50 PM PDT 24 Aug 16 04:52:52 PM PDT 24 184121488 ps
T1137 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3791758347 Aug 16 04:52:49 PM PDT 24 Aug 16 04:53:12 PM PDT 24 919846369 ps
T179 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2403415033 Aug 16 04:52:59 PM PDT 24 Aug 16 04:53:22 PM PDT 24 1680870003 ps
T1138 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1728591372 Aug 16 04:52:57 PM PDT 24 Aug 16 04:53:01 PM PDT 24 278332807 ps
T1139 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.709324172 Aug 16 04:52:53 PM PDT 24 Aug 16 04:52:57 PM PDT 24 230785473 ps
T1140 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.297619138 Aug 16 04:53:06 PM PDT 24 Aug 16 04:53:09 PM PDT 24 50531300 ps
T1141 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3137555065 Aug 16 04:53:12 PM PDT 24 Aug 16 04:53:13 PM PDT 24 41447365 ps
T1142 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1443662151 Aug 16 04:53:03 PM PDT 24 Aug 16 04:53:04 PM PDT 24 26597074 ps
T1143 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3622873322 Aug 16 04:52:55 PM PDT 24 Aug 16 04:53:17 PM PDT 24 2086171725 ps
T1144 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.778141110 Aug 16 04:53:04 PM PDT 24 Aug 16 04:53:06 PM PDT 24 84545527 ps
T1145 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.546389078 Aug 16 04:52:51 PM PDT 24 Aug 16 04:53:12 PM PDT 24 844149156 ps
T1146 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.78673183 Aug 16 04:52:59 PM PDT 24 Aug 16 04:53:00 PM PDT 24 22097091 ps
T1147 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2988893923 Aug 16 04:53:03 PM PDT 24 Aug 16 04:53:05 PM PDT 24 267784191 ps
T1148 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.377055882 Aug 16 04:52:55 PM PDT 24 Aug 16 04:53:14 PM PDT 24 1350723713 ps
T1149 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1860584807 Aug 16 04:52:50 PM PDT 24 Aug 16 04:53:13 PM PDT 24 451028605 ps

Test location /workspace/coverage/default/26.spi_device_stress_all.2058139501
Short name T5
Test name
Test status
Simulation time 115297164714 ps
CPU time 478.9 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 06:03:41 PM PDT 24
Peak memory 273180 kb
Host smart-5f066775-e09c-4202-bbfb-cd34f3fa4abe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058139501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2058139501
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2910582059
Short name T15
Test name
Test status
Simulation time 1004978875005 ps
CPU time 470.8 seconds
Started Aug 16 05:55:19 PM PDT 24
Finished Aug 16 06:03:10 PM PDT 24
Peak memory 254256 kb
Host smart-e69a90cf-392c-49e1-b304-bcb69e8a519e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910582059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2910582059
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3961620183
Short name T29
Test name
Test status
Simulation time 137861580322 ps
CPU time 331.41 seconds
Started Aug 16 05:54:37 PM PDT 24
Finished Aug 16 06:00:09 PM PDT 24
Peak memory 272636 kb
Host smart-524b965b-9708-437d-b267-0c1abcd86c59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961620183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3961620183
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3224822471
Short name T102
Test name
Test status
Simulation time 1428602102 ps
CPU time 15.74 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:53:13 PM PDT 24
Peak memory 215980 kb
Host smart-9e837703-b015-4ecb-adbe-0c105c31b816
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224822471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3224822471
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3434356329
Short name T209
Test name
Test status
Simulation time 17858330103 ps
CPU time 101 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:57:17 PM PDT 24
Peak memory 257524 kb
Host smart-539c92d0-25e3-47b5-9445-86752c095d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434356329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3434356329
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.14520049
Short name T67
Test name
Test status
Simulation time 63760945 ps
CPU time 0.74 seconds
Started Aug 16 05:54:26 PM PDT 24
Finished Aug 16 05:54:27 PM PDT 24
Peak memory 216236 kb
Host smart-4ff95efe-d320-4db3-89cc-6b5aa5e2afc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14520049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.14520049
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.40266728
Short name T19
Test name
Test status
Simulation time 12249213380 ps
CPU time 130.35 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:58:34 PM PDT 24
Peak memory 268480 kb
Host smart-4e6045e8-cdd2-4287-941a-dd9de1893b46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40266728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress
_all.40266728
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2617804171
Short name T137
Test name
Test status
Simulation time 143545755016 ps
CPU time 215.23 seconds
Started Aug 16 05:55:31 PM PDT 24
Finished Aug 16 05:59:06 PM PDT 24
Peak memory 256616 kb
Host smart-6a39657a-d91f-4b28-8fb4-607593be81e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617804171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2617804171
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.635022612
Short name T100
Test name
Test status
Simulation time 706624464 ps
CPU time 5.21 seconds
Started Aug 16 04:52:54 PM PDT 24
Finished Aug 16 04:52:59 PM PDT 24
Peak memory 216152 kb
Host smart-7831012d-13fd-4aec-ac8a-40affe2d456c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635022612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.635022612
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1742941238
Short name T13
Test name
Test status
Simulation time 34233729297 ps
CPU time 266.01 seconds
Started Aug 16 05:56:04 PM PDT 24
Finished Aug 16 06:00:30 PM PDT 24
Peak memory 261368 kb
Host smart-98400208-1094-4677-b18b-e16102627a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742941238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1742941238
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3973014435
Short name T199
Test name
Test status
Simulation time 132652537542 ps
CPU time 147.94 seconds
Started Aug 16 05:55:47 PM PDT 24
Finished Aug 16 05:58:15 PM PDT 24
Peak memory 273704 kb
Host smart-f49d38c8-948c-4147-8f3d-2f4e427030ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973014435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3973014435
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3300098518
Short name T21
Test name
Test status
Simulation time 43147881 ps
CPU time 0.91 seconds
Started Aug 16 05:54:49 PM PDT 24
Finished Aug 16 05:54:50 PM PDT 24
Peak memory 235544 kb
Host smart-01ed56b5-6679-4344-af0b-27854464c83f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300098518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3300098518
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4212675087
Short name T195
Test name
Test status
Simulation time 117555606250 ps
CPU time 469 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 06:04:17 PM PDT 24
Peak memory 257612 kb
Host smart-d1ea147d-780d-4151-a93a-261c26271825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212675087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4212675087
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1557433294
Short name T37
Test name
Test status
Simulation time 5316172585 ps
CPU time 18.15 seconds
Started Aug 16 05:56:37 PM PDT 24
Finished Aug 16 05:56:56 PM PDT 24
Peak memory 236524 kb
Host smart-caf4c9ad-42ce-45d1-9aff-ea35cb1ea2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557433294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1557433294
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3356204547
Short name T166
Test name
Test status
Simulation time 11823338412 ps
CPU time 153.14 seconds
Started Aug 16 05:55:33 PM PDT 24
Finished Aug 16 05:58:06 PM PDT 24
Peak memory 264612 kb
Host smart-60586ca0-40ea-40a7-9b3b-93a7e3c30538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356204547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3356204547
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1142056728
Short name T30
Test name
Test status
Simulation time 150333810975 ps
CPU time 342.36 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 06:00:36 PM PDT 24
Peak memory 265704 kb
Host smart-c5cf4c9a-2174-4681-8c16-322d500115e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142056728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1142056728
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2158972404
Short name T197
Test name
Test status
Simulation time 134800885828 ps
CPU time 334.72 seconds
Started Aug 16 05:55:25 PM PDT 24
Finished Aug 16 06:01:00 PM PDT 24
Peak memory 273956 kb
Host smart-09d2a2a0-6fde-476f-8ee7-199dee106657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158972404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2158972404
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.392946400
Short name T81
Test name
Test status
Simulation time 53944977 ps
CPU time 1.49 seconds
Started Aug 16 04:52:50 PM PDT 24
Finished Aug 16 04:52:52 PM PDT 24
Peak memory 216932 kb
Host smart-4fc4a607-e6c5-44c2-b848-ae43ca371ef9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392946400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.392946400
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.262502884
Short name T18
Test name
Test status
Simulation time 25155854238 ps
CPU time 105.08 seconds
Started Aug 16 05:55:48 PM PDT 24
Finished Aug 16 05:57:33 PM PDT 24
Peak memory 252276 kb
Host smart-5d80ec37-e59d-4b37-a7f9-0308958d0a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262502884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.262502884
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1448718213
Short name T157
Test name
Test status
Simulation time 15508957980 ps
CPU time 154.87 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:58:28 PM PDT 24
Peak memory 288340 kb
Host smart-55fcafbb-94ee-421a-b7f1-a4b41bf902a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448718213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1448718213
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.4146216002
Short name T428
Test name
Test status
Simulation time 114987212 ps
CPU time 1.03 seconds
Started Aug 16 05:54:20 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 217920 kb
Host smart-b4d5fdb0-caf5-439b-af66-b20f383a46fe
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146216002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.4146216002
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3428153231
Short name T292
Test name
Test status
Simulation time 121673420996 ps
CPU time 986.07 seconds
Started Aug 16 05:56:02 PM PDT 24
Finished Aug 16 06:12:28 PM PDT 24
Peak memory 290252 kb
Host smart-e6964bb5-c593-41a7-ab88-21865b4a5552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428153231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3428153231
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4082990913
Short name T17
Test name
Test status
Simulation time 16012999690 ps
CPU time 171.55 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 05:58:15 PM PDT 24
Peak memory 257276 kb
Host smart-8883e844-59d0-46da-a211-f43aa1727b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082990913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4082990913
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.184165607
Short name T89
Test name
Test status
Simulation time 14204286672 ps
CPU time 93.89 seconds
Started Aug 16 05:56:08 PM PDT 24
Finished Aug 16 05:57:42 PM PDT 24
Peak memory 265724 kb
Host smart-267138aa-0da0-4c6f-87a7-467e9e31339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184165607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.184165607
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1689320044
Short name T390
Test name
Test status
Simulation time 28070012 ps
CPU time 0.74 seconds
Started Aug 16 05:55:00 PM PDT 24
Finished Aug 16 05:55:01 PM PDT 24
Peak memory 205520 kb
Host smart-1a101784-4447-43e6-a707-a7704ce835de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689320044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1689320044
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.442459687
Short name T219
Test name
Test status
Simulation time 25749883081 ps
CPU time 109.01 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:57:42 PM PDT 24
Peak memory 253824 kb
Host smart-e5eb63a5-08e8-4aae-a60b-ff7bf8c4d8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442459687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.442459687
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4077172362
Short name T315
Test name
Test status
Simulation time 25884331411 ps
CPU time 123.67 seconds
Started Aug 16 05:55:19 PM PDT 24
Finished Aug 16 05:57:23 PM PDT 24
Peak memory 266584 kb
Host smart-b6e91eda-8e7e-4db8-9fbc-a4a799066b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077172362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4077172362
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.531268456
Short name T36
Test name
Test status
Simulation time 6114690211 ps
CPU time 110.93 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:58:16 PM PDT 24
Peak memory 255448 kb
Host smart-1773d165-8483-41b2-a2f3-2707c0623f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531268456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.531268456
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.63939954
Short name T114
Test name
Test status
Simulation time 623335253 ps
CPU time 4.97 seconds
Started Aug 16 04:52:42 PM PDT 24
Finished Aug 16 04:52:47 PM PDT 24
Peak memory 216092 kb
Host smart-907d18de-6dff-40df-bd68-d4c108f98b68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63939954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.63939954
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3971591616
Short name T180
Test name
Test status
Simulation time 283819425 ps
CPU time 18.2 seconds
Started Aug 16 04:53:07 PM PDT 24
Finished Aug 16 04:53:25 PM PDT 24
Peak memory 215900 kb
Host smart-69732687-0b6a-4fdd-b611-e87c18b8de26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971591616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3971591616
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2786975645
Short name T318
Test name
Test status
Simulation time 4444857735 ps
CPU time 54.21 seconds
Started Aug 16 05:54:58 PM PDT 24
Finished Aug 16 05:55:53 PM PDT 24
Peak memory 250460 kb
Host smart-8bf6d7aa-72f4-4553-9bbe-4226f0743a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786975645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2786975645
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.315457837
Short name T291
Test name
Test status
Simulation time 163428452217 ps
CPU time 312.29 seconds
Started Aug 16 05:54:25 PM PDT 24
Finished Aug 16 05:59:38 PM PDT 24
Peak memory 255652 kb
Host smart-17b1c94f-5bf5-4404-bfe3-d1e4e9ce68be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315457837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
315457837
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2403415033
Short name T179
Test name
Test status
Simulation time 1680870003 ps
CPU time 22.79 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:22 PM PDT 24
Peak memory 215944 kb
Host smart-c020240f-6683-4361-9560-d16e05f26721
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403415033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2403415033
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3028934604
Short name T290
Test name
Test status
Simulation time 17531030388 ps
CPU time 136.48 seconds
Started Aug 16 05:55:00 PM PDT 24
Finished Aug 16 05:57:17 PM PDT 24
Peak memory 241148 kb
Host smart-a3a78925-0225-4299-b215-72989dd59c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028934604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3028934604
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1371907233
Short name T322
Test name
Test status
Simulation time 1304018054 ps
CPU time 17.79 seconds
Started Aug 16 05:55:17 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 251720 kb
Host smart-00e2c9cf-e623-4444-a707-09b3727b7bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371907233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1371907233
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.391995308
Short name T74
Test name
Test status
Simulation time 3752748961 ps
CPU time 54.28 seconds
Started Aug 16 05:55:39 PM PDT 24
Finished Aug 16 05:56:33 PM PDT 24
Peak memory 249356 kb
Host smart-fbbcc50a-a092-499f-a465-7cf3ba27d057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391995308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.391995308
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3725411236
Short name T235
Test name
Test status
Simulation time 2557087029 ps
CPU time 32.8 seconds
Started Aug 16 05:54:25 PM PDT 24
Finished Aug 16 05:54:58 PM PDT 24
Peak memory 249352 kb
Host smart-a5bd4e54-09a6-4d9f-9286-254448c0fd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725411236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3725411236
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3718500159
Short name T196
Test name
Test status
Simulation time 101060519960 ps
CPU time 362.08 seconds
Started Aug 16 05:55:31 PM PDT 24
Finished Aug 16 06:01:34 PM PDT 24
Peak memory 265736 kb
Host smart-04227485-07ac-4586-9e06-3823fd421ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718500159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3718500159
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3014991799
Short name T198
Test name
Test status
Simulation time 64630416319 ps
CPU time 259.45 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 06:00:16 PM PDT 24
Peak memory 264204 kb
Host smart-28adec03-bb61-4a5e-be00-e830f0451345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014991799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3014991799
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2447091905
Short name T306
Test name
Test status
Simulation time 4259868612 ps
CPU time 57.61 seconds
Started Aug 16 05:56:38 PM PDT 24
Finished Aug 16 05:57:36 PM PDT 24
Peak memory 249348 kb
Host smart-71f5e5cf-e5d2-4f55-a93d-abe35fc5387e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447091905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2447091905
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1418263684
Short name T181
Test name
Test status
Simulation time 3107409508 ps
CPU time 21.99 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:53:08 PM PDT 24
Peak memory 216388 kb
Host smart-4c754fd8-891b-4afa-b8bf-7d88bc12ee2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418263684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1418263684
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1222426145
Short name T191
Test name
Test status
Simulation time 160370886411 ps
CPU time 398.11 seconds
Started Aug 16 05:54:24 PM PDT 24
Finished Aug 16 06:01:02 PM PDT 24
Peak memory 256296 kb
Host smart-93788152-86a2-405c-883f-2735ed964d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222426145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1222426145
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2767168445
Short name T285
Test name
Test status
Simulation time 15828735248 ps
CPU time 26.44 seconds
Started Aug 16 05:54:45 PM PDT 24
Finished Aug 16 05:55:11 PM PDT 24
Peak memory 249312 kb
Host smart-25e7808a-478a-4e7f-9e22-4e44265af536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767168445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2767168445
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3512399341
Short name T991
Test name
Test status
Simulation time 32406815872 ps
CPU time 280.76 seconds
Started Aug 16 05:54:28 PM PDT 24
Finished Aug 16 05:59:09 PM PDT 24
Peak memory 257648 kb
Host smart-a4aa2f81-10fc-4a77-8e19-6092d929f802
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512399341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3512399341
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2722129028
Short name T298
Test name
Test status
Simulation time 125438254842 ps
CPU time 215.82 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:59:29 PM PDT 24
Peak memory 241112 kb
Host smart-5736414c-4802-4d06-abca-f1a39dfd1cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722129028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2722129028
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.4164513484
Short name T398
Test name
Test status
Simulation time 7911018045 ps
CPU time 79.53 seconds
Started Aug 16 05:54:46 PM PDT 24
Finished Aug 16 05:56:05 PM PDT 24
Peak memory 241156 kb
Host smart-edf94e2f-d609-46fa-a932-6d5fd60c7698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164513484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4164513484
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.914406204
Short name T278
Test name
Test status
Simulation time 3992341826 ps
CPU time 72.06 seconds
Started Aug 16 05:55:38 PM PDT 24
Finished Aug 16 05:56:51 PM PDT 24
Peak memory 250532 kb
Host smart-af089ea3-ed76-4a44-ba18-49c08c68a0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914406204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.914406204
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1853775789
Short name T268
Test name
Test status
Simulation time 1875060890 ps
CPU time 7.1 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:42 PM PDT 24
Peak memory 232792 kb
Host smart-46ee9624-bf5d-4267-9d76-cc6527a6f98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853775789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1853775789
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.445610013
Short name T111
Test name
Test status
Simulation time 781894218 ps
CPU time 6.55 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:53:04 PM PDT 24
Peak memory 216036 kb
Host smart-40bde96f-7be7-4546-8dd3-b49672c94bec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445610013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.445610013
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.420661151
Short name T1129
Test name
Test status
Simulation time 1845351873 ps
CPU time 4.86 seconds
Started Aug 16 04:53:06 PM PDT 24
Finished Aug 16 04:53:11 PM PDT 24
Peak memory 216108 kb
Host smart-6fcc54f0-4365-4629-af40-d33d652aab4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420661151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.420661151
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3159804824
Short name T1109
Test name
Test status
Simulation time 1687137826 ps
CPU time 8.72 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:54 PM PDT 24
Peak memory 207684 kb
Host smart-0f81af6b-5d7f-44c7-9e53-6182368d8534
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159804824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3159804824
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.661202120
Short name T121
Test name
Test status
Simulation time 850746492 ps
CPU time 11.73 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:53:07 PM PDT 24
Peak memory 207736 kb
Host smart-bf92c102-de7c-434e-be9d-26bc3cc9d348
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661202120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.661202120
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3424238114
Short name T78
Test name
Test status
Simulation time 62951817 ps
CPU time 1.19 seconds
Started Aug 16 04:52:47 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 207812 kb
Host smart-ecdd3b8f-5995-4d67-a887-9fe72510c430
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424238114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3424238114
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2175934466
Short name T120
Test name
Test status
Simulation time 70244997 ps
CPU time 3.84 seconds
Started Aug 16 04:52:44 PM PDT 24
Finished Aug 16 04:52:49 PM PDT 24
Peak memory 217716 kb
Host smart-798d987d-0499-4cd1-bf5b-f6c6f5ccbc04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175934466 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2175934466
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4094013077
Short name T130
Test name
Test status
Simulation time 157327700 ps
CPU time 2.23 seconds
Started Aug 16 04:52:51 PM PDT 24
Finished Aug 16 04:52:54 PM PDT 24
Peak memory 207776 kb
Host smart-2d92322b-163e-428c-baed-05782a62d820
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094013077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
094013077
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.934425455
Short name T1038
Test name
Test status
Simulation time 11618830 ps
CPU time 0.71 seconds
Started Aug 16 04:52:47 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 204632 kb
Host smart-88640d58-50b4-46f1-9970-e042b7e44536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934425455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.934425455
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1918565449
Short name T1117
Test name
Test status
Simulation time 21227700 ps
CPU time 1.72 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 215956 kb
Host smart-ec540ee1-7dbf-4715-8dd8-94fa30bd5d79
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918565449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1918565449
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4118238687
Short name T1047
Test name
Test status
Simulation time 31373491 ps
CPU time 0.65 seconds
Started Aug 16 04:52:48 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 204616 kb
Host smart-028ebbc4-8538-4a96-b936-357aa8371537
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118238687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4118238687
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3594540550
Short name T1037
Test name
Test status
Simulation time 307525518 ps
CPU time 4.41 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:53:00 PM PDT 24
Peak memory 215884 kb
Host smart-d06876ce-8c2a-45c7-b94a-7610dcedb096
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594540550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3594540550
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2046716085
Short name T1122
Test name
Test status
Simulation time 51146998 ps
CPU time 1.43 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:52:59 PM PDT 24
Peak memory 216124 kb
Host smart-02bd807a-a052-4044-a575-9d95cc9f829f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046716085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
046716085
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2088741827
Short name T153
Test name
Test status
Simulation time 687328378 ps
CPU time 8.19 seconds
Started Aug 16 04:52:43 PM PDT 24
Finished Aug 16 04:52:51 PM PDT 24
Peak memory 215992 kb
Host smart-804e58c0-b058-46c8-b91d-1444f97a58e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088741827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2088741827
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3791758347
Short name T1137
Test name
Test status
Simulation time 919846369 ps
CPU time 23.79 seconds
Started Aug 16 04:52:49 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 215968 kb
Host smart-9601d917-3789-4ea5-a6d1-68f832974f95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791758347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3791758347
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2146476813
Short name T1105
Test name
Test status
Simulation time 1289469408 ps
CPU time 13.31 seconds
Started Aug 16 04:52:44 PM PDT 24
Finished Aug 16 04:52:58 PM PDT 24
Peak memory 207680 kb
Host smart-5f5159a3-a786-44af-9e98-49c7230cd0bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146476813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2146476813
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3625243291
Short name T79
Test name
Test status
Simulation time 215075359 ps
CPU time 1.13 seconds
Started Aug 16 04:52:44 PM PDT 24
Finished Aug 16 04:52:45 PM PDT 24
Peak memory 216840 kb
Host smart-fc3beb5c-3e07-4db0-aa72-142dae9c1c61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625243291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3625243291
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4083926355
Short name T1072
Test name
Test status
Simulation time 72098512 ps
CPU time 2.69 seconds
Started Aug 16 04:52:52 PM PDT 24
Finished Aug 16 04:52:55 PM PDT 24
Peak memory 219080 kb
Host smart-3bcb7846-ffdd-4957-8de9-e9ceb25603c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083926355 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4083926355
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1812820488
Short name T1044
Test name
Test status
Simulation time 272974266 ps
CPU time 1.98 seconds
Started Aug 16 04:52:45 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 207728 kb
Host smart-72893fb1-1b02-4e6a-983c-8e5f086d68bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812820488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
812820488
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3097037320
Short name T1036
Test name
Test status
Simulation time 14127905 ps
CPU time 0.72 seconds
Started Aug 16 04:53:00 PM PDT 24
Finished Aug 16 04:53:01 PM PDT 24
Peak memory 204288 kb
Host smart-8ee2d5ba-876f-40be-a4f7-5ffdb7b0bb1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097037320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
097037320
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1322417346
Short name T1104
Test name
Test status
Simulation time 23075030 ps
CPU time 1.7 seconds
Started Aug 16 04:52:53 PM PDT 24
Finished Aug 16 04:52:54 PM PDT 24
Peak memory 215984 kb
Host smart-ddc50a70-d945-418b-8f67-79bbfc435971
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322417346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1322417346
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3883989188
Short name T1082
Test name
Test status
Simulation time 102285701 ps
CPU time 0.66 seconds
Started Aug 16 04:52:50 PM PDT 24
Finished Aug 16 04:52:51 PM PDT 24
Peak memory 204292 kb
Host smart-e3c09f94-b7f0-4044-9e65-f3e982dd5440
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883989188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3883989188
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4277264993
Short name T1061
Test name
Test status
Simulation time 101295830 ps
CPU time 1.8 seconds
Started Aug 16 04:52:40 PM PDT 24
Finished Aug 16 04:52:42 PM PDT 24
Peak memory 215996 kb
Host smart-b5a71cb6-281d-484c-9b95-7dda47cc100f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277264993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4277264993
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.64844652
Short name T1132
Test name
Test status
Simulation time 703846275 ps
CPU time 2.77 seconds
Started Aug 16 04:53:06 PM PDT 24
Finished Aug 16 04:53:09 PM PDT 24
Peak memory 217000 kb
Host smart-c85319e3-8a1b-4d15-a65a-f04164c35e6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64844652 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.64844652
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4248956228
Short name T125
Test name
Test status
Simulation time 64257540 ps
CPU time 1.92 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:01 PM PDT 24
Peak memory 215920 kb
Host smart-252da9a2-099a-4efb-8cdc-7ab260c48393
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248956228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4248956228
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2130043432
Short name T1048
Test name
Test status
Simulation time 24276449 ps
CPU time 0.7 seconds
Started Aug 16 04:53:09 PM PDT 24
Finished Aug 16 04:53:09 PM PDT 24
Peak memory 204264 kb
Host smart-0aa51aa3-38ca-4773-bf60-3d4acb6e9ba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130043432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2130043432
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2287829484
Short name T1087
Test name
Test status
Simulation time 238890701 ps
CPU time 1.81 seconds
Started Aug 16 04:53:03 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 216036 kb
Host smart-4341f1af-8087-43bb-8d14-0a24595f6e57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287829484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2287829484
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.377055882
Short name T1148
Test name
Test status
Simulation time 1350723713 ps
CPU time 19.01 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:53:14 PM PDT 24
Peak memory 216316 kb
Host smart-a11f7784-a0ab-4fae-a300-05dd5eb093ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377055882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.377055882
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.901684316
Short name T1097
Test name
Test status
Simulation time 52481619 ps
CPU time 3.51 seconds
Started Aug 16 04:52:56 PM PDT 24
Finished Aug 16 04:52:59 PM PDT 24
Peak memory 218272 kb
Host smart-032595f9-ea60-4dca-9cc6-c87563d73920
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901684316 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.901684316
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3958300983
Short name T1096
Test name
Test status
Simulation time 114569101 ps
CPU time 2.09 seconds
Started Aug 16 04:53:00 PM PDT 24
Finished Aug 16 04:53:02 PM PDT 24
Peak memory 215976 kb
Host smart-9910f973-887d-4625-8bab-72e8f52de96c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958300983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3958300983
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3319092251
Short name T1128
Test name
Test status
Simulation time 48458110 ps
CPU time 0.72 seconds
Started Aug 16 04:52:53 PM PDT 24
Finished Aug 16 04:52:54 PM PDT 24
Peak memory 204264 kb
Host smart-8a489d1d-216e-48f4-85e6-822835dc8871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319092251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3319092251
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4253461132
Short name T1092
Test name
Test status
Simulation time 1083710061 ps
CPU time 4.25 seconds
Started Aug 16 04:52:58 PM PDT 24
Finished Aug 16 04:53:03 PM PDT 24
Peak memory 215852 kb
Host smart-d0ef9e3f-774d-4065-8928-7e30bad29067
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253461132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4253461132
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3484820557
Short name T1121
Test name
Test status
Simulation time 640917768 ps
CPU time 14.83 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:14 PM PDT 24
Peak memory 216348 kb
Host smart-3b2ef7c0-a27c-4215-95ac-2fa398b2d4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484820557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3484820557
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3307493056
Short name T1123
Test name
Test status
Simulation time 405872688 ps
CPU time 2.47 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:53:00 PM PDT 24
Peak memory 218556 kb
Host smart-08d2719c-a984-47a3-ad28-9a2b201312b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307493056 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3307493056
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1094850851
Short name T1081
Test name
Test status
Simulation time 88993609 ps
CPU time 2.54 seconds
Started Aug 16 04:53:05 PM PDT 24
Finished Aug 16 04:53:08 PM PDT 24
Peak memory 215912 kb
Host smart-5028671a-2335-484a-9e6a-38e22cea5b0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094850851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1094850851
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2510209931
Short name T1089
Test name
Test status
Simulation time 21459055 ps
CPU time 0.66 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:52:56 PM PDT 24
Peak memory 204240 kb
Host smart-ae5d8a34-91ba-4b73-a68e-c561e2edb311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510209931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2510209931
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.545509408
Short name T149
Test name
Test status
Simulation time 186507405 ps
CPU time 3.99 seconds
Started Aug 16 04:52:56 PM PDT 24
Finished Aug 16 04:53:00 PM PDT 24
Peak memory 215920 kb
Host smart-592b187c-e355-4c2c-a11f-6c3c222bf776
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545509408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.545509408
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.470827303
Short name T115
Test name
Test status
Simulation time 84681961 ps
CPU time 2.49 seconds
Started Aug 16 04:52:52 PM PDT 24
Finished Aug 16 04:52:54 PM PDT 24
Peak memory 216040 kb
Host smart-5bea1c63-c2bc-4aa5-8f90-74fd42cf163b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470827303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.470827303
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3376751732
Short name T177
Test name
Test status
Simulation time 3297047028 ps
CPU time 19.73 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:19 PM PDT 24
Peak memory 216452 kb
Host smart-87431108-1cb6-4fd6-b9e9-31c0028bcda4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376751732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3376751732
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.419130954
Short name T117
Test name
Test status
Simulation time 91251840 ps
CPU time 2.67 seconds
Started Aug 16 04:53:05 PM PDT 24
Finished Aug 16 04:53:08 PM PDT 24
Peak memory 217072 kb
Host smart-f48c3599-37ac-455e-9ab3-89bd5ab30dd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419130954 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.419130954
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3842083838
Short name T128
Test name
Test status
Simulation time 573508852 ps
CPU time 2.8 seconds
Started Aug 16 04:53:02 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 215964 kb
Host smart-e1bc52f5-2e1a-4107-bd5f-6fa66bd5bfc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842083838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3842083838
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2736655307
Short name T1039
Test name
Test status
Simulation time 40815601 ps
CPU time 0.76 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:00 PM PDT 24
Peak memory 204660 kb
Host smart-13553d05-778f-4c0e-adf4-32f661c3cfe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736655307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2736655307
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3550325390
Short name T1136
Test name
Test status
Simulation time 184121488 ps
CPU time 1.93 seconds
Started Aug 16 04:52:50 PM PDT 24
Finished Aug 16 04:52:52 PM PDT 24
Peak memory 215876 kb
Host smart-bb5e2700-3b44-4523-a39d-1e17c9984b4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550325390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3550325390
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1369581766
Short name T101
Test name
Test status
Simulation time 1682996037 ps
CPU time 4.96 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 216052 kb
Host smart-998e6137-ea34-4e61-935e-518a228e404e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369581766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1369581766
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.634141873
Short name T183
Test name
Test status
Simulation time 3194791605 ps
CPU time 14.55 seconds
Started Aug 16 04:53:00 PM PDT 24
Finished Aug 16 04:53:15 PM PDT 24
Peak memory 216048 kb
Host smart-0b7373a8-7acb-4350-8dde-b6812d5bda88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634141873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.634141873
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2220873335
Short name T1112
Test name
Test status
Simulation time 182895042 ps
CPU time 2.79 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:02 PM PDT 24
Peak memory 217020 kb
Host smart-2486ebf4-0462-4527-b9ef-cf3276db6015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220873335 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2220873335
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2696736779
Short name T1059
Test name
Test status
Simulation time 518817369 ps
CPU time 1.43 seconds
Started Aug 16 04:52:54 PM PDT 24
Finished Aug 16 04:52:56 PM PDT 24
Peak memory 207704 kb
Host smart-5ce16823-b6c6-46f5-a20f-f0aee1110425
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696736779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2696736779
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1685147303
Short name T1101
Test name
Test status
Simulation time 48142079 ps
CPU time 0.74 seconds
Started Aug 16 04:53:03 PM PDT 24
Finished Aug 16 04:53:04 PM PDT 24
Peak memory 204672 kb
Host smart-2305f4ec-1506-4903-97bd-2ed7e85babf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685147303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1685147303
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.707777971
Short name T142
Test name
Test status
Simulation time 394176370 ps
CPU time 4.41 seconds
Started Aug 16 04:53:00 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 215940 kb
Host smart-0e6c6bd9-9d5a-4788-a49a-46e7e2465ddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707777971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.707777971
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1160590554
Short name T97
Test name
Test status
Simulation time 37261937 ps
CPU time 2.29 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:01 PM PDT 24
Peak memory 215992 kb
Host smart-97a54e3f-466c-460b-bbf3-8ebc63efc6ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160590554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1160590554
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3358155369
Short name T1080
Test name
Test status
Simulation time 889211727 ps
CPU time 21.5 seconds
Started Aug 16 04:53:01 PM PDT 24
Finished Aug 16 04:53:23 PM PDT 24
Peak memory 216040 kb
Host smart-2362fa83-fe08-4ccc-b833-356fe00f8dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358155369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3358155369
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3234090331
Short name T1058
Test name
Test status
Simulation time 45067077 ps
CPU time 1.68 seconds
Started Aug 16 04:53:06 PM PDT 24
Finished Aug 16 04:53:07 PM PDT 24
Peak memory 216056 kb
Host smart-0ab1e39b-2e1b-415d-a700-832b657ab4b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234090331 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3234090331
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2988893923
Short name T1147
Test name
Test status
Simulation time 267784191 ps
CPU time 1.35 seconds
Started Aug 16 04:53:03 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 207860 kb
Host smart-f7d70b3a-656d-422f-b6f2-7dc5ccd7b027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988893923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2988893923
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1443662151
Short name T1142
Test name
Test status
Simulation time 26597074 ps
CPU time 0.74 seconds
Started Aug 16 04:53:03 PM PDT 24
Finished Aug 16 04:53:04 PM PDT 24
Peak memory 204696 kb
Host smart-857e1a39-bca7-4ac0-8766-68fe67ec3396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443662151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1443662151
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1633685905
Short name T152
Test name
Test status
Simulation time 291274650 ps
CPU time 1.94 seconds
Started Aug 16 04:53:03 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 215964 kb
Host smart-a1dd220b-a305-42bf-b35f-4badbe40195b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633685905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1633685905
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1794911290
Short name T109
Test name
Test status
Simulation time 163677995 ps
CPU time 3.91 seconds
Started Aug 16 04:53:03 PM PDT 24
Finished Aug 16 04:53:08 PM PDT 24
Peak memory 216060 kb
Host smart-320c50ad-d698-4518-9398-0d057a81f8eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794911290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1794911290
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3043065251
Short name T182
Test name
Test status
Simulation time 824533762 ps
CPU time 14.42 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 215896 kb
Host smart-38a118b9-1c94-448b-bee3-a70479c3dbca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043065251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3043065251
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2600111277
Short name T119
Test name
Test status
Simulation time 189449248 ps
CPU time 2.52 seconds
Started Aug 16 04:53:06 PM PDT 24
Finished Aug 16 04:53:09 PM PDT 24
Peak memory 217460 kb
Host smart-93c3089a-4280-4333-a982-32d5b16d4c25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600111277 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2600111277
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.281996968
Short name T154
Test name
Test status
Simulation time 362555447 ps
CPU time 2.05 seconds
Started Aug 16 04:52:58 PM PDT 24
Finished Aug 16 04:53:01 PM PDT 24
Peak memory 215960 kb
Host smart-5cee3396-3bfe-47f1-b948-eb143d7cccc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281996968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.281996968
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2879321153
Short name T1065
Test name
Test status
Simulation time 14489020 ps
CPU time 0.75 seconds
Started Aug 16 04:52:56 PM PDT 24
Finished Aug 16 04:52:57 PM PDT 24
Peak memory 204668 kb
Host smart-5c8677ba-1757-43bd-b740-db15972edbb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879321153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2879321153
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3467307987
Short name T143
Test name
Test status
Simulation time 142280526 ps
CPU time 4.07 seconds
Started Aug 16 04:52:58 PM PDT 24
Finished Aug 16 04:53:03 PM PDT 24
Peak memory 215960 kb
Host smart-9b5f1336-4ec0-4e0c-96dc-9f80f8b1a1d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467307987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3467307987
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1026506465
Short name T106
Test name
Test status
Simulation time 150445110 ps
CPU time 4.03 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:04 PM PDT 24
Peak memory 216216 kb
Host smart-56ce7052-1eb2-49c4-833f-1f3a2636c7e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026506465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1026506465
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1689289306
Short name T184
Test name
Test status
Simulation time 319919808 ps
CPU time 7.74 seconds
Started Aug 16 04:53:04 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 215980 kb
Host smart-ba2f5c1b-e291-465d-bc81-c94ce1e226a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689289306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1689289306
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.595915728
Short name T108
Test name
Test status
Simulation time 158945189 ps
CPU time 4.16 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:04 PM PDT 24
Peak memory 217652 kb
Host smart-24f1dd6a-6615-46b8-88d0-bdf1f89d1d34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595915728 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.595915728
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2640725998
Short name T122
Test name
Test status
Simulation time 27194644 ps
CPU time 2 seconds
Started Aug 16 04:53:02 PM PDT 24
Finished Aug 16 04:53:04 PM PDT 24
Peak memory 215976 kb
Host smart-7bd11892-da5f-4d30-9fd8-e73460a01c70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640725998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2640725998
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4130863355
Short name T1107
Test name
Test status
Simulation time 39745889 ps
CPU time 0.75 seconds
Started Aug 16 04:53:01 PM PDT 24
Finished Aug 16 04:53:02 PM PDT 24
Peak memory 204364 kb
Host smart-224d4ca6-0c9a-489b-9e8f-4c2ed6ec8853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130863355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4130863355
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3479777203
Short name T1126
Test name
Test status
Simulation time 211370736 ps
CPU time 2.89 seconds
Started Aug 16 04:53:01 PM PDT 24
Finished Aug 16 04:53:04 PM PDT 24
Peak memory 215936 kb
Host smart-6b7295f2-7399-4f6b-a0d2-b2c1f3a1f150
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479777203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3479777203
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3801365456
Short name T98
Test name
Test status
Simulation time 483200239 ps
CPU time 3.65 seconds
Started Aug 16 04:53:08 PM PDT 24
Finished Aug 16 04:53:11 PM PDT 24
Peak memory 216040 kb
Host smart-3f6c0467-6844-43eb-9785-0222acd3a7b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801365456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3801365456
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3872365909
Short name T118
Test name
Test status
Simulation time 407893047 ps
CPU time 2.52 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:52:57 PM PDT 24
Peak memory 217040 kb
Host smart-8949e863-f216-4823-8254-0995340d784b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872365909 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3872365909
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1140985119
Short name T123
Test name
Test status
Simulation time 40996132 ps
CPU time 2.63 seconds
Started Aug 16 04:53:02 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 215940 kb
Host smart-5e6119e7-983c-4161-8c4f-5b252c368596
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140985119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1140985119
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1794819230
Short name T1041
Test name
Test status
Simulation time 17792055 ps
CPU time 0.79 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:00 PM PDT 24
Peak memory 204380 kb
Host smart-fe734cc5-a0d6-42c2-bc81-bee5f83a2f25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794819230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1794819230
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.933837083
Short name T1114
Test name
Test status
Simulation time 500466043 ps
CPU time 2.94 seconds
Started Aug 16 04:53:05 PM PDT 24
Finished Aug 16 04:53:08 PM PDT 24
Peak memory 215980 kb
Host smart-89bad4f7-d6a1-4266-86b6-eedec4875a81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933837083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.933837083
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1891836182
Short name T116
Test name
Test status
Simulation time 75966694 ps
CPU time 2.16 seconds
Started Aug 16 04:53:01 PM PDT 24
Finished Aug 16 04:53:04 PM PDT 24
Peak memory 217204 kb
Host smart-a49170e9-f8fd-4964-9e16-883457db6244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891836182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1891836182
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1400130656
Short name T103
Test name
Test status
Simulation time 1177613622 ps
CPU time 7.62 seconds
Started Aug 16 04:53:03 PM PDT 24
Finished Aug 16 04:53:11 PM PDT 24
Peak memory 222936 kb
Host smart-1650895e-0892-43a4-8de0-ff28d6d8740a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400130656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1400130656
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1335313103
Short name T1079
Test name
Test status
Simulation time 431835676 ps
CPU time 1.7 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:52:59 PM PDT 24
Peak memory 216064 kb
Host smart-a88568da-325e-4f66-a7e7-bd2f58c6c6f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335313103 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1335313103
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3410504671
Short name T127
Test name
Test status
Simulation time 81572573 ps
CPU time 1.92 seconds
Started Aug 16 04:53:02 PM PDT 24
Finished Aug 16 04:53:04 PM PDT 24
Peak memory 207824 kb
Host smart-7f32ac27-4ab2-4d6b-943c-0aa953a67db6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410504671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3410504671
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2824793512
Short name T1069
Test name
Test status
Simulation time 43961045 ps
CPU time 0.84 seconds
Started Aug 16 04:53:02 PM PDT 24
Finished Aug 16 04:53:03 PM PDT 24
Peak memory 204332 kb
Host smart-88401f66-aa7d-41a6-a3fb-40d073b8e9d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824793512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2824793512
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.876478363
Short name T1103
Test name
Test status
Simulation time 58778428 ps
CPU time 3.74 seconds
Started Aug 16 04:53:03 PM PDT 24
Finished Aug 16 04:53:07 PM PDT 24
Peak memory 216024 kb
Host smart-7bc303c3-c0b2-4cca-a53b-3bef25e037ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876478363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.876478363
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3165096647
Short name T1088
Test name
Test status
Simulation time 154609143 ps
CPU time 2.23 seconds
Started Aug 16 04:53:00 PM PDT 24
Finished Aug 16 04:53:02 PM PDT 24
Peak memory 216020 kb
Host smart-6c417ea7-e8d7-47b0-b8a2-39861066a3e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165096647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3165096647
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.833844439
Short name T1116
Test name
Test status
Simulation time 3104170991 ps
CPU time 16.1 seconds
Started Aug 16 04:52:49 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 215956 kb
Host smart-692412cc-26be-4b52-8346-97bb76818219
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833844439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.833844439
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3383104259
Short name T131
Test name
Test status
Simulation time 527833952 ps
CPU time 32.03 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 215848 kb
Host smart-5920a93d-4654-4819-87bb-598a913ca009
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383104259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3383104259
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.156356937
Short name T1066
Test name
Test status
Simulation time 50197890 ps
CPU time 2.1 seconds
Started Aug 16 04:52:50 PM PDT 24
Finished Aug 16 04:52:52 PM PDT 24
Peak memory 217084 kb
Host smart-12bcb3f1-61c0-4eb8-9079-ee0fee63f173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156356937 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.156356937
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.181482691
Short name T155
Test name
Test status
Simulation time 82656591 ps
CPU time 2.24 seconds
Started Aug 16 04:52:44 PM PDT 24
Finished Aug 16 04:52:46 PM PDT 24
Peak memory 215916 kb
Host smart-593611cb-05c6-4f01-b9d7-c254ddfc4f93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181482691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.181482691
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3884976382
Short name T1074
Test name
Test status
Simulation time 39740432 ps
CPU time 0.69 seconds
Started Aug 16 04:52:45 PM PDT 24
Finished Aug 16 04:52:46 PM PDT 24
Peak memory 204632 kb
Host smart-b50b6878-e4e3-4c72-a0fb-b2966025f231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884976382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
884976382
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2811894163
Short name T124
Test name
Test status
Simulation time 122599290 ps
CPU time 2 seconds
Started Aug 16 04:52:44 PM PDT 24
Finished Aug 16 04:52:46 PM PDT 24
Peak memory 215960 kb
Host smart-bf124041-9708-4f8c-a758-efd4c7bd4347
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811894163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2811894163
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4138057103
Short name T1085
Test name
Test status
Simulation time 49368254 ps
CPU time 0.68 seconds
Started Aug 16 04:52:47 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 204276 kb
Host smart-f754ffc2-6245-4725-94b8-07b1d20b1373
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138057103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4138057103
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3545017559
Short name T1077
Test name
Test status
Simulation time 176167919 ps
CPU time 3.88 seconds
Started Aug 16 04:52:49 PM PDT 24
Finished Aug 16 04:52:53 PM PDT 24
Peak memory 215892 kb
Host smart-83039914-7d87-43b5-b199-d7221c071303
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545017559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3545017559
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4226520025
Short name T110
Test name
Test status
Simulation time 784779298 ps
CPU time 2.48 seconds
Started Aug 16 04:52:45 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 216092 kb
Host smart-29770579-9e28-4c27-acff-890d50d8edf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226520025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
226520025
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1365346489
Short name T104
Test name
Test status
Simulation time 1906344682 ps
CPU time 22.98 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:53:19 PM PDT 24
Peak memory 215988 kb
Host smart-9034a661-5705-4878-ab08-c8d57bf348aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365346489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1365346489
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1620157669
Short name T1099
Test name
Test status
Simulation time 23125368 ps
CPU time 0.73 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:52:58 PM PDT 24
Peak memory 204336 kb
Host smart-19ef5756-d1a2-442f-9cb1-5c786bb127c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620157669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1620157669
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2057803209
Short name T1125
Test name
Test status
Simulation time 11498107 ps
CPU time 0.75 seconds
Started Aug 16 04:53:01 PM PDT 24
Finished Aug 16 04:53:01 PM PDT 24
Peak memory 204336 kb
Host smart-806218af-d4ec-464b-9490-da16e5814546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057803209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2057803209
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1767733492
Short name T1110
Test name
Test status
Simulation time 19628723 ps
CPU time 0.71 seconds
Started Aug 16 04:53:04 PM PDT 24
Finished Aug 16 04:53:06 PM PDT 24
Peak memory 204300 kb
Host smart-d109f6de-4bd7-4681-8442-6f9d8d13d0ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767733492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1767733492
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2563168541
Short name T1130
Test name
Test status
Simulation time 31498532 ps
CPU time 0.72 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:16 PM PDT 24
Peak memory 204644 kb
Host smart-6b971b39-535a-42b0-8436-1bdf8cd86550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563168541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2563168541
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.439130589
Short name T1094
Test name
Test status
Simulation time 46653224 ps
CPU time 0.7 seconds
Started Aug 16 04:53:10 PM PDT 24
Finished Aug 16 04:53:11 PM PDT 24
Peak memory 204620 kb
Host smart-d67332eb-f4c9-4825-ab01-8e38adbe8b1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439130589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.439130589
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.626450195
Short name T1070
Test name
Test status
Simulation time 15268747 ps
CPU time 0.78 seconds
Started Aug 16 04:53:24 PM PDT 24
Finished Aug 16 04:53:25 PM PDT 24
Peak memory 204640 kb
Host smart-7d336453-87f2-4672-9d83-9a08d9b2cdbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626450195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.626450195
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2499523308
Short name T1106
Test name
Test status
Simulation time 12756140 ps
CPU time 0.7 seconds
Started Aug 16 04:53:12 PM PDT 24
Finished Aug 16 04:53:13 PM PDT 24
Peak memory 204664 kb
Host smart-782e423b-3672-4643-b436-45b74a22b224
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499523308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2499523308
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4192981882
Short name T1134
Test name
Test status
Simulation time 16794628 ps
CPU time 0.75 seconds
Started Aug 16 04:53:13 PM PDT 24
Finished Aug 16 04:53:13 PM PDT 24
Peak memory 204336 kb
Host smart-44862dce-cc7b-470b-8089-82a1096301f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192981882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4192981882
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2720737407
Short name T1098
Test name
Test status
Simulation time 23909763 ps
CPU time 0.68 seconds
Started Aug 16 04:53:14 PM PDT 24
Finished Aug 16 04:53:14 PM PDT 24
Peak memory 204340 kb
Host smart-6581c6c9-605c-46fb-bc93-70b5b2f3ec63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720737407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2720737407
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.897086821
Short name T1049
Test name
Test status
Simulation time 54862223 ps
CPU time 0.7 seconds
Started Aug 16 04:53:12 PM PDT 24
Finished Aug 16 04:53:13 PM PDT 24
Peak memory 204288 kb
Host smart-4e57d1b9-5e8f-4237-8767-349563863c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897086821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.897086821
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3622873322
Short name T1143
Test name
Test status
Simulation time 2086171725 ps
CPU time 21.98 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:53:17 PM PDT 24
Peak memory 215968 kb
Host smart-7975b189-c104-4a54-97c9-12268d8d3f66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622873322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3622873322
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2071770119
Short name T1119
Test name
Test status
Simulation time 9812643678 ps
CPU time 34.47 seconds
Started Aug 16 04:52:55 PM PDT 24
Finished Aug 16 04:53:30 PM PDT 24
Peak memory 207780 kb
Host smart-54d02c99-5d59-4d2b-a9ad-5416a4722280
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071770119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2071770119
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.732415141
Short name T80
Test name
Test status
Simulation time 23575857 ps
CPU time 1.42 seconds
Started Aug 16 04:52:44 PM PDT 24
Finished Aug 16 04:52:46 PM PDT 24
Peak memory 216884 kb
Host smart-c96be75d-15ee-4863-a60b-c3e3ff21845b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732415141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.732415141
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2746079268
Short name T150
Test name
Test status
Simulation time 1681553988 ps
CPU time 3.9 seconds
Started Aug 16 04:52:42 PM PDT 24
Finished Aug 16 04:52:46 PM PDT 24
Peak memory 218600 kb
Host smart-54156e82-5d58-4966-b12e-43cee715e1c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746079268 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2746079268
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2541995259
Short name T1060
Test name
Test status
Simulation time 207655056 ps
CPU time 1.35 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 207672 kb
Host smart-6e243f67-515f-4c00-ade7-5f3770d7082f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541995259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
541995259
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1468420327
Short name T1064
Test name
Test status
Simulation time 22232025 ps
CPU time 0.71 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:47 PM PDT 24
Peak memory 204628 kb
Host smart-18957d2e-f83c-4728-83d5-2e886e338392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468420327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
468420327
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.441357586
Short name T1093
Test name
Test status
Simulation time 57920400 ps
CPU time 2.34 seconds
Started Aug 16 04:53:01 PM PDT 24
Finished Aug 16 04:53:04 PM PDT 24
Peak memory 216000 kb
Host smart-ded4ac8d-0568-478c-99e9-fc5e29ac8acb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441357586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.441357586
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4187263607
Short name T1052
Test name
Test status
Simulation time 33255073 ps
CPU time 0.67 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:47 PM PDT 24
Peak memory 204624 kb
Host smart-5f3ed400-9e8c-4fa6-9dbc-a99ca286ae22
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187263607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4187263607
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3986337266
Short name T1057
Test name
Test status
Simulation time 61829856 ps
CPU time 3.75 seconds
Started Aug 16 04:52:53 PM PDT 24
Finished Aug 16 04:52:57 PM PDT 24
Peak memory 215976 kb
Host smart-387386ea-4828-4280-a5e9-682ad1587cde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986337266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3986337266
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2592273848
Short name T112
Test name
Test status
Simulation time 25768336 ps
CPU time 1.75 seconds
Started Aug 16 04:52:43 PM PDT 24
Finished Aug 16 04:52:45 PM PDT 24
Peak memory 216200 kb
Host smart-c08a651d-1f08-47ff-a246-90aaa4dd05b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592273848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
592273848
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1772495072
Short name T176
Test name
Test status
Simulation time 807975921 ps
CPU time 14.08 seconds
Started Aug 16 04:52:56 PM PDT 24
Finished Aug 16 04:53:11 PM PDT 24
Peak memory 216144 kb
Host smart-3fa4c3ff-3545-48d9-bb73-5392dc4e16c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772495072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1772495072
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4272771174
Short name T1051
Test name
Test status
Simulation time 13680433 ps
CPU time 0.75 seconds
Started Aug 16 04:53:14 PM PDT 24
Finished Aug 16 04:53:15 PM PDT 24
Peak memory 204332 kb
Host smart-c35919b0-280d-4315-9454-390149bdc023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272771174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4272771174
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2070768863
Short name T1086
Test name
Test status
Simulation time 11991026 ps
CPU time 0.7 seconds
Started Aug 16 04:53:18 PM PDT 24
Finished Aug 16 04:53:19 PM PDT 24
Peak memory 204652 kb
Host smart-18b41ee5-91f7-4e0a-984f-549546f0bb98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070768863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2070768863
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.301424337
Short name T1131
Test name
Test status
Simulation time 36408070 ps
CPU time 0.75 seconds
Started Aug 16 04:53:04 PM PDT 24
Finished Aug 16 04:53:05 PM PDT 24
Peak memory 204340 kb
Host smart-adc75a40-b303-4ce2-98bb-e5c69a5cd419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301424337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.301424337
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3858236216
Short name T1063
Test name
Test status
Simulation time 53879766 ps
CPU time 0.75 seconds
Started Aug 16 04:53:12 PM PDT 24
Finished Aug 16 04:53:13 PM PDT 24
Peak memory 204388 kb
Host smart-fe754663-a344-4f2d-a0d9-f254ee128ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858236216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3858236216
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4221903273
Short name T1046
Test name
Test status
Simulation time 26544262 ps
CPU time 0.75 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:16 PM PDT 24
Peak memory 204340 kb
Host smart-4930e660-f02a-48e2-90ae-512528f43e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221903273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4221903273
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1592031427
Short name T1068
Test name
Test status
Simulation time 47872755 ps
CPU time 0.74 seconds
Started Aug 16 04:53:12 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 204652 kb
Host smart-5ebb30fc-7291-4af8-9eca-6192d16825d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592031427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1592031427
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2237665159
Short name T1045
Test name
Test status
Simulation time 71794526 ps
CPU time 0.7 seconds
Started Aug 16 04:53:08 PM PDT 24
Finished Aug 16 04:53:09 PM PDT 24
Peak memory 204672 kb
Host smart-5be4444c-3331-480c-ab40-2562200f16a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237665159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2237665159
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.643433955
Short name T1043
Test name
Test status
Simulation time 36035084 ps
CPU time 0.73 seconds
Started Aug 16 04:53:07 PM PDT 24
Finished Aug 16 04:53:08 PM PDT 24
Peak memory 204400 kb
Host smart-b7f6fc8c-0e5c-49a3-a997-05892a8a3b81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643433955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.643433955
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.944703836
Short name T1083
Test name
Test status
Simulation time 58460975 ps
CPU time 0.77 seconds
Started Aug 16 04:53:07 PM PDT 24
Finished Aug 16 04:53:08 PM PDT 24
Peak memory 204260 kb
Host smart-6e32fb01-37df-4695-a468-3e370ce8529c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944703836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.944703836
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2664092729
Short name T1054
Test name
Test status
Simulation time 28264124 ps
CPU time 0.74 seconds
Started Aug 16 04:53:17 PM PDT 24
Finished Aug 16 04:53:18 PM PDT 24
Peak memory 204628 kb
Host smart-f1b11f75-cf8a-4ec3-a347-ae926c76376b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664092729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2664092729
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1860584807
Short name T1149
Test name
Test status
Simulation time 451028605 ps
CPU time 22.46 seconds
Started Aug 16 04:52:50 PM PDT 24
Finished Aug 16 04:53:13 PM PDT 24
Peak memory 207788 kb
Host smart-59cc1d7c-64fd-44ba-89b7-dcb52da6f166
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860584807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1860584807
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3171907353
Short name T129
Test name
Test status
Simulation time 367556632 ps
CPU time 20.77 seconds
Started Aug 16 04:52:48 PM PDT 24
Finished Aug 16 04:53:09 PM PDT 24
Peak memory 207716 kb
Host smart-ff1a1a80-79a8-400f-a22f-d164bf7869d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171907353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3171907353
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3944099634
Short name T126
Test name
Test status
Simulation time 67391445 ps
CPU time 0.96 seconds
Started Aug 16 04:52:47 PM PDT 24
Finished Aug 16 04:52:48 PM PDT 24
Peak memory 207336 kb
Host smart-278e0c5b-20a8-4960-802c-b866bb758fde
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944099634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3944099634
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1728591372
Short name T1138
Test name
Test status
Simulation time 278332807 ps
CPU time 3.4 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:53:01 PM PDT 24
Peak memory 217220 kb
Host smart-a0d5bf87-a1e9-49cf-bab8-d8b5e2b3bfb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728591372 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1728591372
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1938259971
Short name T1053
Test name
Test status
Simulation time 62092671 ps
CPU time 1.27 seconds
Started Aug 16 04:52:49 PM PDT 24
Finished Aug 16 04:52:50 PM PDT 24
Peak memory 207756 kb
Host smart-0fe04579-408e-416c-8eee-a1083aa31714
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938259971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
938259971
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3455093672
Short name T1075
Test name
Test status
Simulation time 40075183 ps
CPU time 0.74 seconds
Started Aug 16 04:52:46 PM PDT 24
Finished Aug 16 04:52:47 PM PDT 24
Peak memory 204660 kb
Host smart-02ca2370-078f-4409-9843-481ead1728eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455093672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
455093672
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.175035282
Short name T132
Test name
Test status
Simulation time 62725235 ps
CPU time 2.22 seconds
Started Aug 16 04:52:53 PM PDT 24
Finished Aug 16 04:52:55 PM PDT 24
Peak memory 215948 kb
Host smart-481c2c3d-6926-49dd-9aca-c5bcbcfaa4dd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175035282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.175035282
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.78673183
Short name T1146
Test name
Test status
Simulation time 22097091 ps
CPU time 0.69 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:00 PM PDT 24
Peak memory 204284 kb
Host smart-43ce1e0c-9b10-4755-a7e6-0bd749dbd77b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78673183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_
walk.78673183
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2149293986
Short name T1071
Test name
Test status
Simulation time 91633260 ps
CPU time 1.71 seconds
Started Aug 16 04:52:45 PM PDT 24
Finished Aug 16 04:52:47 PM PDT 24
Peak memory 215900 kb
Host smart-325e6034-f422-44e5-b4ed-2884aaa3da27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149293986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2149293986
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.202740617
Short name T113
Test name
Test status
Simulation time 46759100 ps
CPU time 2.77 seconds
Started Aug 16 04:52:47 PM PDT 24
Finished Aug 16 04:52:50 PM PDT 24
Peak memory 216208 kb
Host smart-a0e9953a-2b16-4397-82fb-428f22e626d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202740617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.202740617
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.435497656
Short name T1111
Test name
Test status
Simulation time 217727142 ps
CPU time 13.92 seconds
Started Aug 16 04:52:47 PM PDT 24
Finished Aug 16 04:53:01 PM PDT 24
Peak memory 216096 kb
Host smart-610803bd-5c64-439b-82af-86d34e160a99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435497656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.435497656
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.433613552
Short name T1102
Test name
Test status
Simulation time 15163920 ps
CPU time 0.76 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 204320 kb
Host smart-553025dc-38ce-4dd1-9446-676212172841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433613552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.433613552
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2433248307
Short name T1084
Test name
Test status
Simulation time 96187365 ps
CPU time 0.76 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:16 PM PDT 24
Peak memory 204304 kb
Host smart-fe85381f-efec-495a-84fc-9fe4d2230669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433248307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2433248307
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1721039981
Short name T1118
Test name
Test status
Simulation time 36699377 ps
CPU time 0.76 seconds
Started Aug 16 04:53:14 PM PDT 24
Finished Aug 16 04:53:15 PM PDT 24
Peak memory 204340 kb
Host smart-8c2229ed-69ce-49c1-94fa-bb0013711cae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721039981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1721039981
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3504657565
Short name T1062
Test name
Test status
Simulation time 13065782 ps
CPU time 0.7 seconds
Started Aug 16 04:53:15 PM PDT 24
Finished Aug 16 04:53:16 PM PDT 24
Peak memory 204348 kb
Host smart-92edbd47-007b-499e-b497-686056ed8830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504657565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3504657565
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3560041560
Short name T1050
Test name
Test status
Simulation time 14702256 ps
CPU time 0.68 seconds
Started Aug 16 04:53:14 PM PDT 24
Finished Aug 16 04:53:15 PM PDT 24
Peak memory 204700 kb
Host smart-a11ca5c5-f81b-4b48-925b-b889468582d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560041560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3560041560
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3220272651
Short name T1078
Test name
Test status
Simulation time 11443824 ps
CPU time 0.76 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 204332 kb
Host smart-f7bd5cda-4f0e-4e84-b5f6-45e509ce0811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220272651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3220272651
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2172759225
Short name T1115
Test name
Test status
Simulation time 12806176 ps
CPU time 0.7 seconds
Started Aug 16 04:53:11 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 204364 kb
Host smart-b51ebdc5-6d8e-41a0-ac54-2455753373df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172759225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2172759225
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3560293450
Short name T1067
Test name
Test status
Simulation time 12840719 ps
CPU time 0.8 seconds
Started Aug 16 04:53:10 PM PDT 24
Finished Aug 16 04:53:11 PM PDT 24
Peak memory 204484 kb
Host smart-3425c4ac-7bff-4a20-ac93-c445db677763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560293450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3560293450
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3137555065
Short name T1141
Test name
Test status
Simulation time 41447365 ps
CPU time 0.71 seconds
Started Aug 16 04:53:12 PM PDT 24
Finished Aug 16 04:53:13 PM PDT 24
Peak memory 204316 kb
Host smart-f114788d-8c24-4480-ad4e-bd85b3171eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137555065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3137555065
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1185467446
Short name T1042
Test name
Test status
Simulation time 48918303 ps
CPU time 0.84 seconds
Started Aug 16 04:53:09 PM PDT 24
Finished Aug 16 04:53:10 PM PDT 24
Peak memory 204340 kb
Host smart-96b7fe9e-b01b-4604-8e6b-84756f596276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185467446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1185467446
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.116687875
Short name T151
Test name
Test status
Simulation time 349472964 ps
CPU time 2.68 seconds
Started Aug 16 04:53:06 PM PDT 24
Finished Aug 16 04:53:09 PM PDT 24
Peak memory 218468 kb
Host smart-4b7e4bee-4ce3-4242-912e-b8fafd47d633
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116687875 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.116687875
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.373991215
Short name T1127
Test name
Test status
Simulation time 18611199 ps
CPU time 1.25 seconds
Started Aug 16 04:52:54 PM PDT 24
Finished Aug 16 04:52:55 PM PDT 24
Peak memory 207808 kb
Host smart-9ee7a64f-e561-4fdd-941f-44c4eb03be11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373991215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.373991215
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.511029722
Short name T1113
Test name
Test status
Simulation time 17488609 ps
CPU time 0.79 seconds
Started Aug 16 04:53:05 PM PDT 24
Finished Aug 16 04:53:06 PM PDT 24
Peak memory 204308 kb
Host smart-60c0761b-31cd-47e6-8430-83f419c08505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511029722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.511029722
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3178888849
Short name T1090
Test name
Test status
Simulation time 93108808 ps
CPU time 1.83 seconds
Started Aug 16 04:52:58 PM PDT 24
Finished Aug 16 04:53:00 PM PDT 24
Peak memory 215952 kb
Host smart-d4314820-6b7b-47f4-ae7c-9b2190f92dd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178888849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3178888849
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1726912171
Short name T99
Test name
Test status
Simulation time 69744043 ps
CPU time 1.92 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:02 PM PDT 24
Peak memory 216100 kb
Host smart-96f43689-426a-4719-89a5-c8cb8e0b5630
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726912171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
726912171
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2130924133
Short name T1124
Test name
Test status
Simulation time 465291501 ps
CPU time 3.6 seconds
Started Aug 16 04:52:56 PM PDT 24
Finished Aug 16 04:53:00 PM PDT 24
Peak memory 218280 kb
Host smart-b242a157-14e1-4acc-ade3-6d3e8f8e50e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130924133 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2130924133
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.778141110
Short name T1144
Test name
Test status
Simulation time 84545527 ps
CPU time 2.21 seconds
Started Aug 16 04:53:04 PM PDT 24
Finished Aug 16 04:53:06 PM PDT 24
Peak memory 215904 kb
Host smart-ea1a0258-683c-4c9e-8a4d-3172ff8426ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778141110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.778141110
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3234002977
Short name T1040
Test name
Test status
Simulation time 19736002 ps
CPU time 0.75 seconds
Started Aug 16 04:53:00 PM PDT 24
Finished Aug 16 04:53:01 PM PDT 24
Peak memory 204644 kb
Host smart-c6cd15e9-70fd-4bcc-9e03-3a4e3a2d082b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234002977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
234002977
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2239456455
Short name T1108
Test name
Test status
Simulation time 696586458 ps
CPU time 4.35 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:53:02 PM PDT 24
Peak memory 215956 kb
Host smart-368c38d1-3dbb-4347-9173-c79165c0f15a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239456455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2239456455
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.546389078
Short name T1145
Test name
Test status
Simulation time 844149156 ps
CPU time 20.91 seconds
Started Aug 16 04:52:51 PM PDT 24
Finished Aug 16 04:53:12 PM PDT 24
Peak memory 215992 kb
Host smart-1c97ec40-6809-48a1-b215-9c7c561326f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546389078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.546389078
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.297619138
Short name T1140
Test name
Test status
Simulation time 50531300 ps
CPU time 3.46 seconds
Started Aug 16 04:53:06 PM PDT 24
Finished Aug 16 04:53:09 PM PDT 24
Peak memory 218888 kb
Host smart-1a2f846b-66ae-488d-8912-6f12b22e0e92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297619138 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.297619138
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3233575468
Short name T1135
Test name
Test status
Simulation time 72459967 ps
CPU time 2.17 seconds
Started Aug 16 04:52:58 PM PDT 24
Finished Aug 16 04:53:00 PM PDT 24
Peak memory 215948 kb
Host smart-ccd96ee0-716d-482a-ab88-d4a7d83b45f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233575468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
233575468
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.478487203
Short name T1055
Test name
Test status
Simulation time 46537402 ps
CPU time 0.72 seconds
Started Aug 16 04:52:56 PM PDT 24
Finished Aug 16 04:52:57 PM PDT 24
Peak memory 204620 kb
Host smart-d941ddc5-a9f1-4aef-ba16-01e546f9df41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478487203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.478487203
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3365526420
Short name T1095
Test name
Test status
Simulation time 158807899 ps
CPU time 3.56 seconds
Started Aug 16 04:53:08 PM PDT 24
Finished Aug 16 04:53:11 PM PDT 24
Peak memory 215804 kb
Host smart-44d5b432-3e7c-4256-a2bc-c4ce0ac8101e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365526420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3365526420
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3646612344
Short name T175
Test name
Test status
Simulation time 56378180 ps
CPU time 3.23 seconds
Started Aug 16 04:52:58 PM PDT 24
Finished Aug 16 04:53:01 PM PDT 24
Peak memory 216136 kb
Host smart-c5610b5f-51ac-4652-a55c-7e5ca6b6839b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646612344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
646612344
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.531491774
Short name T185
Test name
Test status
Simulation time 1511752775 ps
CPU time 18.16 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:53:15 PM PDT 24
Peak memory 216140 kb
Host smart-46e9b33a-560d-41aa-9d87-50bfe084a506
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531491774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.531491774
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.763468566
Short name T1120
Test name
Test status
Simulation time 44762252 ps
CPU time 3.35 seconds
Started Aug 16 04:53:04 PM PDT 24
Finished Aug 16 04:53:07 PM PDT 24
Peak memory 217096 kb
Host smart-80a88fd6-a25e-4438-ad4f-7894bae1f6b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763468566 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.763468566
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.265393639
Short name T1076
Test name
Test status
Simulation time 143300769 ps
CPU time 1.43 seconds
Started Aug 16 04:53:00 PM PDT 24
Finished Aug 16 04:53:02 PM PDT 24
Peak memory 215884 kb
Host smart-fc82a44b-c77c-4ee9-ad2d-e979541056db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265393639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.265393639
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3049365108
Short name T1056
Test name
Test status
Simulation time 22894087 ps
CPU time 0.76 seconds
Started Aug 16 04:53:02 PM PDT 24
Finished Aug 16 04:53:03 PM PDT 24
Peak memory 204260 kb
Host smart-23c0deca-6517-42d4-a14a-3950190acca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049365108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
049365108
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.709324172
Short name T1139
Test name
Test status
Simulation time 230785473 ps
CPU time 3.22 seconds
Started Aug 16 04:52:53 PM PDT 24
Finished Aug 16 04:52:57 PM PDT 24
Peak memory 215992 kb
Host smart-454417c4-01fe-44bd-9462-d837c7eb2cd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709324172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.709324172
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2875510383
Short name T107
Test name
Test status
Simulation time 70587978 ps
CPU time 4.93 seconds
Started Aug 16 04:53:04 PM PDT 24
Finished Aug 16 04:53:09 PM PDT 24
Peak memory 216140 kb
Host smart-2ddd3282-6f73-47b2-98ef-5deb04161c12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875510383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
875510383
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4080824150
Short name T163
Test name
Test status
Simulation time 4636942134 ps
CPU time 12.99 seconds
Started Aug 16 04:53:04 PM PDT 24
Finished Aug 16 04:53:17 PM PDT 24
Peak memory 215968 kb
Host smart-61cfc422-d86b-4088-b004-e1c1eb241968
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080824150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4080824150
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1386877672
Short name T1100
Test name
Test status
Simulation time 126756169 ps
CPU time 3.05 seconds
Started Aug 16 04:52:59 PM PDT 24
Finished Aug 16 04:53:02 PM PDT 24
Peak memory 217472 kb
Host smart-9f14d816-a85f-4e45-9ec7-3bfc5f2aaa83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386877672 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1386877672
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1617951009
Short name T156
Test name
Test status
Simulation time 490041397 ps
CPU time 1.44 seconds
Started Aug 16 04:53:06 PM PDT 24
Finished Aug 16 04:53:07 PM PDT 24
Peak memory 207764 kb
Host smart-eb1b222a-5c43-4ddd-b5cd-5f189c95b64e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617951009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
617951009
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3906477221
Short name T1073
Test name
Test status
Simulation time 11904662 ps
CPU time 0.74 seconds
Started Aug 16 04:52:56 PM PDT 24
Finished Aug 16 04:52:57 PM PDT 24
Peak memory 204260 kb
Host smart-d651b1ea-1bc0-4b36-9cda-bf846b20e520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906477221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
906477221
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.620096640
Short name T1091
Test name
Test status
Simulation time 492913055 ps
CPU time 4.13 seconds
Started Aug 16 04:52:58 PM PDT 24
Finished Aug 16 04:53:02 PM PDT 24
Peak memory 215932 kb
Host smart-c58c60a5-ca5b-46d5-a57a-4c4a5517b617
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620096640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.620096640
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1494521235
Short name T1133
Test name
Test status
Simulation time 198164100 ps
CPU time 4.77 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:53:02 PM PDT 24
Peak memory 216208 kb
Host smart-3fd6ab5c-1af4-4469-8494-64232af59951
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494521235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
494521235
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3687331271
Short name T178
Test name
Test status
Simulation time 297846362 ps
CPU time 18.06 seconds
Started Aug 16 04:52:57 PM PDT 24
Finished Aug 16 04:53:15 PM PDT 24
Peak memory 215968 kb
Host smart-e12adf29-cde6-4d47-bf15-c6465c9aa94b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687331271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3687331271
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1442130373
Short name T420
Test name
Test status
Simulation time 13090206 ps
CPU time 0.72 seconds
Started Aug 16 05:54:23 PM PDT 24
Finished Aug 16 05:54:24 PM PDT 24
Peak memory 205528 kb
Host smart-5bde715b-74d4-4492-894b-4aeca8626db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442130373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
442130373
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2480600989
Short name T916
Test name
Test status
Simulation time 113245779 ps
CPU time 2.11 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:54:49 PM PDT 24
Peak memory 224228 kb
Host smart-a6086ccf-94d0-40cf-a1d5-c3c28eb31d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480600989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2480600989
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2619264739
Short name T25
Test name
Test status
Simulation time 66704224 ps
CPU time 0.75 seconds
Started Aug 16 05:54:52 PM PDT 24
Finished Aug 16 05:54:53 PM PDT 24
Peak memory 206952 kb
Host smart-fc4a2431-b57c-4f6b-ad91-7b3d17ec32bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619264739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2619264739
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.551339973
Short name T239
Test name
Test status
Simulation time 139078445648 ps
CPU time 58.29 seconds
Started Aug 16 05:55:14 PM PDT 24
Finished Aug 16 05:56:17 PM PDT 24
Peak memory 232848 kb
Host smart-88c96bbc-5bd2-4f42-9a0b-055ab45577cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551339973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.551339973
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3052113434
Short name T853
Test name
Test status
Simulation time 7646580627 ps
CPU time 93.77 seconds
Started Aug 16 05:54:20 PM PDT 24
Finished Aug 16 05:55:54 PM PDT 24
Peak memory 257576 kb
Host smart-8454f93e-4247-487b-a80e-80bf8336b2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052113434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3052113434
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3886689341
Short name T333
Test name
Test status
Simulation time 8591836585 ps
CPU time 12.09 seconds
Started Aug 16 05:54:24 PM PDT 24
Finished Aug 16 05:54:36 PM PDT 24
Peak memory 217880 kb
Host smart-3c52de9f-0f66-4ae5-afbb-261691f84e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886689341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3886689341
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1123506746
Short name T399
Test name
Test status
Simulation time 2065566780 ps
CPU time 25.07 seconds
Started Aug 16 05:55:05 PM PDT 24
Finished Aug 16 05:55:30 PM PDT 24
Peak memory 232884 kb
Host smart-d4f32484-89ab-4d60-b61c-1bb31a77f8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123506746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1123506746
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4085858487
Short name T671
Test name
Test status
Simulation time 784344404 ps
CPU time 3.26 seconds
Started Aug 16 05:54:19 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 232868 kb
Host smart-2a52aabc-c8c9-4d96-af10-6c64b40c632a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085858487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4085858487
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3022762707
Short name T914
Test name
Test status
Simulation time 18364162167 ps
CPU time 41.35 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:55:29 PM PDT 24
Peak memory 232876 kb
Host smart-2e9b2c67-8c20-4ccd-beee-81c829094664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022762707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3022762707
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.178360153
Short name T514
Test name
Test status
Simulation time 16465705 ps
CPU time 1.12 seconds
Started Aug 16 05:54:19 PM PDT 24
Finished Aug 16 05:54:21 PM PDT 24
Peak memory 216740 kb
Host smart-c863e4dc-1a06-4223-b44f-f04224c2994d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178360153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.178360153
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1793590158
Short name T777
Test name
Test status
Simulation time 12503742769 ps
CPU time 18.79 seconds
Started Aug 16 05:54:22 PM PDT 24
Finished Aug 16 05:54:41 PM PDT 24
Peak memory 232880 kb
Host smart-be724206-2563-49ba-ad8a-0d1ec99f759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793590158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1793590158
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3068823332
Short name T859
Test name
Test status
Simulation time 3758779017 ps
CPU time 11.19 seconds
Started Aug 16 05:54:26 PM PDT 24
Finished Aug 16 05:54:37 PM PDT 24
Peak memory 218900 kb
Host smart-c7011b2f-de18-414b-b464-3134721e6673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068823332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3068823332
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1800478182
Short name T971
Test name
Test status
Simulation time 454634946 ps
CPU time 6.79 seconds
Started Aug 16 05:54:20 PM PDT 24
Finished Aug 16 05:54:27 PM PDT 24
Peak memory 222608 kb
Host smart-c3e7d037-64cf-492f-bbeb-1ac4e633bee1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1800478182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1800478182
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3643014759
Short name T68
Test name
Test status
Simulation time 68223441 ps
CPU time 0.95 seconds
Started Aug 16 05:54:24 PM PDT 24
Finished Aug 16 05:54:30 PM PDT 24
Peak memory 235184 kb
Host smart-afd51c1c-5809-4a62-a46a-c46b6e7da92d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643014759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3643014759
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.335454814
Short name T649
Test name
Test status
Simulation time 155377707 ps
CPU time 0.95 seconds
Started Aug 16 05:54:48 PM PDT 24
Finished Aug 16 05:54:49 PM PDT 24
Peak memory 207528 kb
Host smart-130caa06-3ade-4fc0-bd8b-e2c8c1f5632d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335454814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.335454814
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2598956639
Short name T570
Test name
Test status
Simulation time 38708910 ps
CPU time 0.7 seconds
Started Aug 16 05:54:51 PM PDT 24
Finished Aug 16 05:54:57 PM PDT 24
Peak memory 205680 kb
Host smart-2208a080-9848-49a4-8d23-3a9a004aac80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598956639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2598956639
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3472437335
Short name T939
Test name
Test status
Simulation time 5291875241 ps
CPU time 16.32 seconds
Started Aug 16 05:54:19 PM PDT 24
Finished Aug 16 05:54:36 PM PDT 24
Peak memory 216588 kb
Host smart-589c71cf-c389-4ea2-b938-a4dd518c2967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472437335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3472437335
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1922103303
Short name T797
Test name
Test status
Simulation time 24331163 ps
CPU time 1.4 seconds
Started Aug 16 05:54:51 PM PDT 24
Finished Aug 16 05:54:53 PM PDT 24
Peak memory 216344 kb
Host smart-03d730af-f2bc-43f0-b5bf-960c8389edc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922103303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1922103303
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2142423079
Short name T348
Test name
Test status
Simulation time 64098380 ps
CPU time 0.83 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:55:06 PM PDT 24
Peak memory 206132 kb
Host smart-0cb2320c-694b-4626-8980-a68cfecd87b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142423079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2142423079
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2961617048
Short name T282
Test name
Test status
Simulation time 1033664464 ps
CPU time 8.06 seconds
Started Aug 16 05:54:23 PM PDT 24
Finished Aug 16 05:54:31 PM PDT 24
Peak memory 241020 kb
Host smart-fe619389-0b7a-4028-aead-523837cbe40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961617048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2961617048
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4034372665
Short name T894
Test name
Test status
Simulation time 16302083 ps
CPU time 0.71 seconds
Started Aug 16 05:54:32 PM PDT 24
Finished Aug 16 05:54:32 PM PDT 24
Peak memory 205520 kb
Host smart-cb581bf7-1730-40d0-b193-00d2958e241b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034372665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
034372665
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3385485041
Short name T652
Test name
Test status
Simulation time 75421764 ps
CPU time 2.22 seconds
Started Aug 16 05:54:26 PM PDT 24
Finished Aug 16 05:54:28 PM PDT 24
Peak memory 223676 kb
Host smart-7be9c9a4-ec2f-4cd1-8f5d-9aedfc428751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385485041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3385485041
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3521064183
Short name T692
Test name
Test status
Simulation time 15216931 ps
CPU time 0.75 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:54:54 PM PDT 24
Peak memory 206504 kb
Host smart-53f4be35-4d11-4ec3-a69b-3b0e8fc64c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521064183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3521064183
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3145737571
Short name T689
Test name
Test status
Simulation time 30423821387 ps
CPU time 206.3 seconds
Started Aug 16 05:54:23 PM PDT 24
Finished Aug 16 05:57:50 PM PDT 24
Peak memory 249720 kb
Host smart-d1968e37-a177-4605-babd-87984533f1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145737571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3145737571
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2822180699
Short name T42
Test name
Test status
Simulation time 3007914090 ps
CPU time 44.77 seconds
Started Aug 16 05:54:24 PM PDT 24
Finished Aug 16 05:55:09 PM PDT 24
Peak memory 252672 kb
Host smart-bb685d2f-8551-450c-bf9d-56bfdf64c0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822180699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2822180699
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1172386932
Short name T915
Test name
Test status
Simulation time 247268417 ps
CPU time 4.52 seconds
Started Aug 16 05:54:24 PM PDT 24
Finished Aug 16 05:54:28 PM PDT 24
Peak memory 224700 kb
Host smart-6390c540-806d-4152-b0d3-65847a3f75eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172386932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1172386932
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.4061676412
Short name T767
Test name
Test status
Simulation time 3860421373 ps
CPU time 47.21 seconds
Started Aug 16 05:54:23 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 253752 kb
Host smart-7cf899e5-ad74-493b-b72c-2dbbda9bd7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061676412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.4061676412
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2441079096
Short name T927
Test name
Test status
Simulation time 2339073774 ps
CPU time 24.05 seconds
Started Aug 16 05:54:23 PM PDT 24
Finished Aug 16 05:54:47 PM PDT 24
Peak memory 232976 kb
Host smart-692babc5-15b6-4424-847b-13de1f35d3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441079096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2441079096
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3723541777
Short name T612
Test name
Test status
Simulation time 10977537510 ps
CPU time 94.66 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:56:39 PM PDT 24
Peak memory 240596 kb
Host smart-9e298e5a-5ee5-43b8-b339-3dc7510931bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723541777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3723541777
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1222037251
Short name T789
Test name
Test status
Simulation time 37620061 ps
CPU time 2.66 seconds
Started Aug 16 05:54:20 PM PDT 24
Finished Aug 16 05:54:22 PM PDT 24
Peak memory 232876 kb
Host smart-f37595b1-f20a-436a-8679-e51e758e8a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222037251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1222037251
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2610012256
Short name T553
Test name
Test status
Simulation time 533106767 ps
CPU time 4.52 seconds
Started Aug 16 05:54:58 PM PDT 24
Finished Aug 16 05:55:03 PM PDT 24
Peak memory 218828 kb
Host smart-c668950c-c03c-4fc6-b933-0c3086d2a2ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2610012256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2610012256
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.636429361
Short name T70
Test name
Test status
Simulation time 90717804 ps
CPU time 1.16 seconds
Started Aug 16 05:54:51 PM PDT 24
Finished Aug 16 05:54:52 PM PDT 24
Peak memory 235456 kb
Host smart-359a8e55-6117-4930-9bf7-b31ba722f947
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636429361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.636429361
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.728106988
Short name T82
Test name
Test status
Simulation time 6686318214 ps
CPU time 8.84 seconds
Started Aug 16 05:54:24 PM PDT 24
Finished Aug 16 05:54:38 PM PDT 24
Peak memory 216828 kb
Host smart-87e99bf6-518f-452d-88ce-3069765c8256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728106988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.728106988
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2882603941
Short name T340
Test name
Test status
Simulation time 1574846486 ps
CPU time 6.71 seconds
Started Aug 16 05:54:23 PM PDT 24
Finished Aug 16 05:54:30 PM PDT 24
Peak memory 216428 kb
Host smart-f906d97b-19ad-42d1-a060-929d582862d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882603941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2882603941
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1291105287
Short name T642
Test name
Test status
Simulation time 122841310 ps
CPU time 1.77 seconds
Started Aug 16 05:54:25 PM PDT 24
Finished Aug 16 05:54:27 PM PDT 24
Peak memory 216448 kb
Host smart-d35d8675-9ab6-4bfc-8bc3-2224b4296ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291105287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1291105287
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1736052375
Short name T681
Test name
Test status
Simulation time 119931041 ps
CPU time 0.73 seconds
Started Aug 16 05:54:23 PM PDT 24
Finished Aug 16 05:54:24 PM PDT 24
Peak memory 206160 kb
Host smart-fada8ca0-7d2f-4081-bd83-2bd762b21ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736052375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1736052375
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2677761679
Short name T563
Test name
Test status
Simulation time 1917135298 ps
CPU time 7.23 seconds
Started Aug 16 05:54:22 PM PDT 24
Finished Aug 16 05:54:30 PM PDT 24
Peak memory 232912 kb
Host smart-e4bb95e9-c2c3-49e1-ba30-a4990e2fa6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677761679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2677761679
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1339262
Short name T407
Test name
Test status
Simulation time 27474483 ps
CPU time 0.71 seconds
Started Aug 16 05:54:56 PM PDT 24
Finished Aug 16 05:54:57 PM PDT 24
Peak memory 205688 kb
Host smart-f045c6e4-eb64-4503-ae09-93ccfaf73ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.1339262
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2444541474
Short name T1016
Test name
Test status
Simulation time 791209301 ps
CPU time 6.08 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:16 PM PDT 24
Peak memory 232860 kb
Host smart-3af6990d-3f7e-4056-bc26-96e7676409cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444541474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2444541474
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.104240122
Short name T842
Test name
Test status
Simulation time 12355474 ps
CPU time 0.74 seconds
Started Aug 16 05:55:17 PM PDT 24
Finished Aug 16 05:55:18 PM PDT 24
Peak memory 205592 kb
Host smart-8f1e7d83-9b99-404f-9ae8-bea4d0a804bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104240122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.104240122
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3294729100
Short name T40
Test name
Test status
Simulation time 1692927695 ps
CPU time 17.91 seconds
Started Aug 16 05:55:12 PM PDT 24
Finished Aug 16 05:55:30 PM PDT 24
Peak memory 241172 kb
Host smart-d354ce90-32e2-448f-9e25-0af08a94ec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294729100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3294729100
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1769739919
Short name T53
Test name
Test status
Simulation time 1557797339 ps
CPU time 47.09 seconds
Started Aug 16 05:54:52 PM PDT 24
Finished Aug 16 05:55:39 PM PDT 24
Peak memory 254732 kb
Host smart-f321953a-fedd-45ab-b52c-efb943b47634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769739919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1769739919
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3708658043
Short name T631
Test name
Test status
Simulation time 44646020589 ps
CPU time 36 seconds
Started Aug 16 05:54:56 PM PDT 24
Finished Aug 16 05:55:33 PM PDT 24
Peak memory 232872 kb
Host smart-0e4c602a-d79b-45e8-b636-0d09f8aad098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708658043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3708658043
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2227220380
Short name T556
Test name
Test status
Simulation time 36720421027 ps
CPU time 249.21 seconds
Started Aug 16 05:55:21 PM PDT 24
Finished Aug 16 05:59:30 PM PDT 24
Peak memory 256292 kb
Host smart-34135c9b-47cc-421d-8441-5a1b9033300a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227220380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2227220380
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1293385707
Short name T247
Test name
Test status
Simulation time 7705036771 ps
CPU time 19.57 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:55:56 PM PDT 24
Peak memory 232932 kb
Host smart-c5d0e2c7-1201-470b-afe8-ec762d6391da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293385707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1293385707
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1751114885
Short name T277
Test name
Test status
Simulation time 152808514 ps
CPU time 4.97 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:55:41 PM PDT 24
Peak memory 232896 kb
Host smart-95863ebd-ba37-45d3-86f1-f18d5565fe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751114885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1751114885
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3673819667
Short name T33
Test name
Test status
Simulation time 186347830 ps
CPU time 1.06 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 216720 kb
Host smart-402c1f5e-c358-4402-a25f-392e0377993b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673819667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3673819667
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3911657729
Short name T764
Test name
Test status
Simulation time 74174096 ps
CPU time 3.36 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 05:55:27 PM PDT 24
Peak memory 224640 kb
Host smart-1c0fa811-4c8a-49ad-9f68-ab641559091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911657729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3911657729
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2876716301
Short name T659
Test name
Test status
Simulation time 5359886321 ps
CPU time 14 seconds
Started Aug 16 05:55:37 PM PDT 24
Finished Aug 16 05:55:51 PM PDT 24
Peak memory 232908 kb
Host smart-9a2ef68b-52c6-4a10-a62e-b424f326d220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876716301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2876716301
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3988520569
Short name T736
Test name
Test status
Simulation time 360151563 ps
CPU time 4.09 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:54:57 PM PDT 24
Peak memory 223268 kb
Host smart-be50743a-93fe-42fc-9bb2-6e4813a4981b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3988520569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3988520569
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.804253401
Short name T996
Test name
Test status
Simulation time 15894648750 ps
CPU time 22.1 seconds
Started Aug 16 05:55:29 PM PDT 24
Finished Aug 16 05:55:51 PM PDT 24
Peak memory 216556 kb
Host smart-2c69dd1b-42a4-4f78-89af-84702fb89226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804253401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.804253401
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1987550173
Short name T737
Test name
Test status
Simulation time 2001143485 ps
CPU time 5.03 seconds
Started Aug 16 05:54:56 PM PDT 24
Finished Aug 16 05:55:01 PM PDT 24
Peak memory 216448 kb
Host smart-cf94edc3-b52f-47d3-941d-e9474e1af0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987550173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1987550173
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3719729121
Short name T907
Test name
Test status
Simulation time 397533491 ps
CPU time 4.67 seconds
Started Aug 16 05:54:59 PM PDT 24
Finished Aug 16 05:55:03 PM PDT 24
Peak memory 216484 kb
Host smart-f449bd1d-140b-40dc-b517-88982c53eafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719729121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3719729121
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1313855075
Short name T432
Test name
Test status
Simulation time 140297697 ps
CPU time 0.93 seconds
Started Aug 16 05:54:52 PM PDT 24
Finished Aug 16 05:54:53 PM PDT 24
Peak memory 207156 kb
Host smart-bcb723dd-6ed3-4554-8c9f-be62895bc5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313855075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1313855075
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3236518332
Short name T476
Test name
Test status
Simulation time 11654842073 ps
CPU time 22.4 seconds
Started Aug 16 05:54:51 PM PDT 24
Finished Aug 16 05:55:14 PM PDT 24
Peak memory 232932 kb
Host smart-a6b32109-8760-4563-bdaa-df24661321b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236518332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3236518332
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1019652361
Short name T530
Test name
Test status
Simulation time 14428161 ps
CPU time 0.79 seconds
Started Aug 16 05:55:01 PM PDT 24
Finished Aug 16 05:55:02 PM PDT 24
Peak memory 205892 kb
Host smart-3c226162-cfff-481f-be71-358633ee6e99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019652361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1019652361
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.587794563
Short name T384
Test name
Test status
Simulation time 206707684 ps
CPU time 2.45 seconds
Started Aug 16 05:55:03 PM PDT 24
Finished Aug 16 05:55:06 PM PDT 24
Peak memory 224628 kb
Host smart-7519ca8f-40dc-4136-b421-8b818723bfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587794563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.587794563
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.854521322
Short name T616
Test name
Test status
Simulation time 35119621 ps
CPU time 0.73 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 205496 kb
Host smart-68dbb268-36eb-4da6-9dd9-64e2fc15979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854521322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.854521322
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.100649871
Short name T460
Test name
Test status
Simulation time 20138046 ps
CPU time 0.8 seconds
Started Aug 16 05:55:01 PM PDT 24
Finished Aug 16 05:55:02 PM PDT 24
Peak memory 215888 kb
Host smart-c4fdff98-8c5e-4d7b-a0bd-3e126e291b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100649871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.100649871
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3959763197
Short name T44
Test name
Test status
Simulation time 89355347724 ps
CPU time 456.62 seconds
Started Aug 16 05:54:56 PM PDT 24
Finished Aug 16 06:02:33 PM PDT 24
Peak memory 253856 kb
Host smart-4b053028-83ea-4c80-9491-1277607bfa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959763197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3959763197
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1943356282
Short name T321
Test name
Test status
Simulation time 453747055 ps
CPU time 9.72 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:45 PM PDT 24
Peak memory 241004 kb
Host smart-ed94e2ee-6e8f-4601-a3d2-79401ada7ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943356282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1943356282
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2481971769
Short name T893
Test name
Test status
Simulation time 23182760620 ps
CPU time 46.13 seconds
Started Aug 16 05:55:06 PM PDT 24
Finished Aug 16 05:55:52 PM PDT 24
Peak memory 249380 kb
Host smart-c2e8b114-9da4-410f-8598-19b142898df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481971769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2481971769
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2216508492
Short name T216
Test name
Test status
Simulation time 17310182581 ps
CPU time 27.33 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:56:07 PM PDT 24
Peak memory 230092 kb
Host smart-1e30bbf9-0815-4ee6-903a-d6b62ba3edd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216508492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2216508492
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.181808647
Short name T957
Test name
Test status
Simulation time 20689436521 ps
CPU time 86.87 seconds
Started Aug 16 05:54:57 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 249296 kb
Host smart-87e26ba1-ca66-482c-b297-13bffb7bdd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181808647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.181808647
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2449034378
Short name T362
Test name
Test status
Simulation time 233155128 ps
CPU time 1.02 seconds
Started Aug 16 05:54:54 PM PDT 24
Finished Aug 16 05:54:56 PM PDT 24
Peak memory 218048 kb
Host smart-c3804ace-76cf-46f1-b7c1-92fd9a6835af
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449034378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2449034378
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3726251651
Short name T816
Test name
Test status
Simulation time 419560852 ps
CPU time 6.19 seconds
Started Aug 16 05:55:29 PM PDT 24
Finished Aug 16 05:55:36 PM PDT 24
Peak memory 224564 kb
Host smart-12b5a4db-7627-456c-9455-6989b9a6ba73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726251651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3726251651
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3610390646
Short name T260
Test name
Test status
Simulation time 86995872 ps
CPU time 2.66 seconds
Started Aug 16 05:55:12 PM PDT 24
Finished Aug 16 05:55:15 PM PDT 24
Peak memory 232904 kb
Host smart-0dd0b67f-f576-4de4-99d7-edb696fa3de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610390646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3610390646
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.4288357941
Short name T913
Test name
Test status
Simulation time 140232539 ps
CPU time 3.69 seconds
Started Aug 16 05:55:02 PM PDT 24
Finished Aug 16 05:55:06 PM PDT 24
Peak memory 220820 kb
Host smart-17c8272d-58a9-4f9d-a541-c896424f545f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4288357941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.4288357941
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.626896492
Short name T757
Test name
Test status
Simulation time 124039044240 ps
CPU time 329.96 seconds
Started Aug 16 05:55:30 PM PDT 24
Finished Aug 16 06:01:00 PM PDT 24
Peak memory 257644 kb
Host smart-90c4da96-c7f8-4b90-8d30-cdc6dd8414dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626896492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.626896492
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1119001487
Short name T843
Test name
Test status
Simulation time 5974630570 ps
CPU time 12.35 seconds
Started Aug 16 05:54:57 PM PDT 24
Finished Aug 16 05:55:09 PM PDT 24
Peak memory 216740 kb
Host smart-2e3c6b7e-e6b3-4cc3-b46a-c119a678b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119001487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1119001487
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3128869405
Short name T582
Test name
Test status
Simulation time 5018938628 ps
CPU time 10.53 seconds
Started Aug 16 05:55:00 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 216712 kb
Host smart-dc7baad3-f01f-4202-820c-72bbb9af9a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128869405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3128869405
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2251336240
Short name T336
Test name
Test status
Simulation time 98810461 ps
CPU time 0.93 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:25 PM PDT 24
Peak memory 207212 kb
Host smart-fdd311cf-e393-422e-bf57-ec4fb14786c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251336240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2251336240
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3427130751
Short name T361
Test name
Test status
Simulation time 39828029 ps
CPU time 0.78 seconds
Started Aug 16 05:54:52 PM PDT 24
Finished Aug 16 05:54:53 PM PDT 24
Peak memory 206104 kb
Host smart-d026be19-ec7c-4ce7-a1bc-30f75c7da9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427130751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3427130751
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4270544854
Short name T858
Test name
Test status
Simulation time 2055032611 ps
CPU time 10.09 seconds
Started Aug 16 05:54:59 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 233828 kb
Host smart-0d08ceca-9d51-4bf2-a663-ff1e6296850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270544854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4270544854
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3340350955
Short name T807
Test name
Test status
Simulation time 816102296 ps
CPU time 4.33 seconds
Started Aug 16 05:55:41 PM PDT 24
Finished Aug 16 05:55:46 PM PDT 24
Peak memory 224616 kb
Host smart-9884f1e6-952c-4434-9139-3362e434af76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340350955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3340350955
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2757785728
Short name T624
Test name
Test status
Simulation time 14302220 ps
CPU time 0.76 seconds
Started Aug 16 05:54:55 PM PDT 24
Finished Aug 16 05:54:55 PM PDT 24
Peak memory 206608 kb
Host smart-cb190fe2-8ec9-4d1a-a472-003bd5571ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757785728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2757785728
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.355587743
Short name T469
Test name
Test status
Simulation time 1543028476 ps
CPU time 5.25 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:55:42 PM PDT 24
Peak memory 224600 kb
Host smart-a3a3ce10-281e-44fb-81e8-82a62adc8af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355587743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.355587743
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2976254910
Short name T513
Test name
Test status
Simulation time 84492837580 ps
CPU time 163.78 seconds
Started Aug 16 05:55:41 PM PDT 24
Finished Aug 16 05:58:25 PM PDT 24
Peak memory 241136 kb
Host smart-b0b88c89-6b2a-4b61-bcdd-8b4e3807d031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976254910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2976254910
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1048915997
Short name T337
Test name
Test status
Simulation time 33107773904 ps
CPU time 29.37 seconds
Started Aug 16 05:55:29 PM PDT 24
Finished Aug 16 05:55:58 PM PDT 24
Peak memory 217784 kb
Host smart-c3b35a21-6057-4e69-93b5-bbb828ddc8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048915997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1048915997
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2207811736
Short name T324
Test name
Test status
Simulation time 9577760015 ps
CPU time 26.66 seconds
Started Aug 16 05:55:31 PM PDT 24
Finished Aug 16 05:55:58 PM PDT 24
Peak memory 239472 kb
Host smart-e7d49a6e-1170-4815-8c33-62011e920eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207811736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2207811736
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.143847498
Short name T954
Test name
Test status
Simulation time 65409064752 ps
CPU time 124.8 seconds
Started Aug 16 05:55:31 PM PDT 24
Finished Aug 16 05:57:36 PM PDT 24
Peak memory 257480 kb
Host smart-c13a9ba7-b10f-4aab-ae0e-0e210e02efda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143847498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.143847498
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.754135024
Short name T846
Test name
Test status
Simulation time 882997448 ps
CPU time 4.49 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:55:39 PM PDT 24
Peak memory 232800 kb
Host smart-2d8d6896-64f8-4b03-b607-d0785560db09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754135024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.754135024
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1673107516
Short name T545
Test name
Test status
Simulation time 8075713362 ps
CPU time 71.81 seconds
Started Aug 16 05:55:01 PM PDT 24
Finished Aug 16 05:56:13 PM PDT 24
Peak memory 249332 kb
Host smart-fa5c4ec4-41b2-4596-9ea1-60ed138efbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673107516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1673107516
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.217995110
Short name T831
Test name
Test status
Simulation time 95616897 ps
CPU time 1 seconds
Started Aug 16 05:55:13 PM PDT 24
Finished Aug 16 05:55:14 PM PDT 24
Peak memory 217936 kb
Host smart-90cb0792-e665-4398-bac9-6b9a744c2678
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217995110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.217995110
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2305130697
Short name T264
Test name
Test status
Simulation time 14224886718 ps
CPU time 11.35 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:47 PM PDT 24
Peak memory 224768 kb
Host smart-c72fbd42-2497-490c-8a0d-cccf6d19b12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305130697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2305130697
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4136412890
Short name T769
Test name
Test status
Simulation time 9962539959 ps
CPU time 17.9 seconds
Started Aug 16 05:55:19 PM PDT 24
Finished Aug 16 05:55:37 PM PDT 24
Peak memory 220688 kb
Host smart-86dd6079-18d9-4495-a255-8ec649d2073d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4136412890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4136412890
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2303513155
Short name T645
Test name
Test status
Simulation time 7799349241 ps
CPU time 56.54 seconds
Started Aug 16 05:55:38 PM PDT 24
Finished Aug 16 05:56:35 PM PDT 24
Peak memory 233048 kb
Host smart-998b6389-9652-4e84-b734-a1a6e9834aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303513155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2303513155
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.40932115
Short name T959
Test name
Test status
Simulation time 6208960320 ps
CPU time 45.59 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:55:39 PM PDT 24
Peak memory 216512 kb
Host smart-2e1d391d-c039-4c72-8f27-229ee2d3e3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40932115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.40932115
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3652379785
Short name T1027
Test name
Test status
Simulation time 6838488662 ps
CPU time 20.74 seconds
Started Aug 16 05:55:05 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 216528 kb
Host smart-a10ece51-91ca-4284-9fc9-7e8855cbd675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652379785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3652379785
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4211904309
Short name T1017
Test name
Test status
Simulation time 3217125127 ps
CPU time 11.53 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:55:48 PM PDT 24
Peak memory 216496 kb
Host smart-8c8c6fb9-cc1b-458e-84ee-8bd8489bf0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211904309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4211904309
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2141946308
Short name T902
Test name
Test status
Simulation time 262048571 ps
CPU time 0.85 seconds
Started Aug 16 05:55:28 PM PDT 24
Finished Aug 16 05:55:29 PM PDT 24
Peak memory 206040 kb
Host smart-1d8f2152-7850-408d-b10c-69b10f1112da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141946308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2141946308
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1620076416
Short name T598
Test name
Test status
Simulation time 67232723 ps
CPU time 2.34 seconds
Started Aug 16 05:55:02 PM PDT 24
Finished Aug 16 05:55:05 PM PDT 24
Peak memory 224272 kb
Host smart-860b816b-7348-4809-96e3-3cc7bbfd16dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620076416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1620076416
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1970287376
Short name T506
Test name
Test status
Simulation time 56782239 ps
CPU time 0.71 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:36 PM PDT 24
Peak memory 205808 kb
Host smart-9797ba4d-daca-4c0a-8433-b4a4f5cf7954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970287376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1970287376
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4079661741
Short name T440
Test name
Test status
Simulation time 124212040 ps
CPU time 2.58 seconds
Started Aug 16 05:55:06 PM PDT 24
Finished Aug 16 05:55:08 PM PDT 24
Peak memory 232824 kb
Host smart-39a944d5-d28c-4a9b-98cd-9cf655a83184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079661741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4079661741
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2841983229
Short name T817
Test name
Test status
Simulation time 84957063 ps
CPU time 0.75 seconds
Started Aug 16 05:55:33 PM PDT 24
Finished Aug 16 05:55:34 PM PDT 24
Peak memory 206512 kb
Host smart-547c3e10-49bd-40d1-8ef1-bb61163ab8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841983229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2841983229
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2098389089
Short name T49
Test name
Test status
Simulation time 16325624819 ps
CPU time 85.3 seconds
Started Aug 16 05:54:56 PM PDT 24
Finished Aug 16 05:56:22 PM PDT 24
Peak memory 249328 kb
Host smart-6f7f1f81-871b-43bc-b5b0-a987406a8912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098389089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2098389089
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.159978354
Short name T587
Test name
Test status
Simulation time 26666659748 ps
CPU time 188.25 seconds
Started Aug 16 05:54:58 PM PDT 24
Finished Aug 16 05:58:07 PM PDT 24
Peak memory 249720 kb
Host smart-21377f00-a338-4294-9e19-e49e3be8df12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159978354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.159978354
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3330315740
Short name T525
Test name
Test status
Simulation time 26207462041 ps
CPU time 28.23 seconds
Started Aug 16 05:55:05 PM PDT 24
Finished Aug 16 05:55:34 PM PDT 24
Peak memory 241172 kb
Host smart-b321c9a5-97b7-4f35-8a03-f9d5d155905d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330315740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3330315740
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.840372017
Short name T224
Test name
Test status
Simulation time 3829399104 ps
CPU time 26.84 seconds
Started Aug 16 05:54:52 PM PDT 24
Finished Aug 16 05:55:19 PM PDT 24
Peak memory 254768 kb
Host smart-86792a45-2582-4e59-9c7d-0fa7dedfbe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840372017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.840372017
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3840480942
Short name T1006
Test name
Test status
Simulation time 2100422115 ps
CPU time 7.83 seconds
Started Aug 16 05:55:30 PM PDT 24
Finished Aug 16 05:55:38 PM PDT 24
Peak memory 232820 kb
Host smart-df5892eb-3c21-49c2-9bd9-fef3f3b4fe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840480942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3840480942
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2289517529
Short name T462
Test name
Test status
Simulation time 47410986474 ps
CPU time 75.83 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:56:51 PM PDT 24
Peak memory 224684 kb
Host smart-3d84ff9d-5629-42d9-8077-30a7b3931b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289517529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2289517529
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2186087994
Short name T345
Test name
Test status
Simulation time 397307656 ps
CPU time 1.01 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:36 PM PDT 24
Peak memory 216644 kb
Host smart-8a9ef502-15e4-4781-ab89-08263be961e5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186087994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2186087994
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2375698262
Short name T687
Test name
Test status
Simulation time 143889240159 ps
CPU time 27.81 seconds
Started Aug 16 05:54:58 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 232936 kb
Host smart-ac8e868a-631e-411f-9335-ef5709bc651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375698262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2375698262
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1025983113
Short name T217
Test name
Test status
Simulation time 162590350 ps
CPU time 4.35 seconds
Started Aug 16 05:55:03 PM PDT 24
Finished Aug 16 05:55:08 PM PDT 24
Peak memory 232848 kb
Host smart-2cfa6edf-1f47-45e5-a384-7b59cc80d333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025983113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1025983113
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1092147059
Short name T144
Test name
Test status
Simulation time 83923341 ps
CPU time 3.47 seconds
Started Aug 16 05:54:54 PM PDT 24
Finished Aug 16 05:54:57 PM PDT 24
Peak memory 220596 kb
Host smart-c1ea0c29-c30d-465f-8947-d01338daab06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1092147059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1092147059
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1036518993
Short name T284
Test name
Test status
Simulation time 38617182481 ps
CPU time 117.5 seconds
Started Aug 16 05:55:47 PM PDT 24
Finished Aug 16 05:57:44 PM PDT 24
Peak memory 264800 kb
Host smart-2ece04ee-4bb3-409c-9aca-0fe80e2ba135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036518993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1036518993
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1972160212
Short name T644
Test name
Test status
Simulation time 505492584 ps
CPU time 4 seconds
Started Aug 16 05:55:05 PM PDT 24
Finished Aug 16 05:55:09 PM PDT 24
Peak memory 218300 kb
Host smart-b28a4562-2a31-4519-a21c-6a723a28ce02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972160212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1972160212
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.744677140
Short name T999
Test name
Test status
Simulation time 125760949 ps
CPU time 0.69 seconds
Started Aug 16 05:55:33 PM PDT 24
Finished Aug 16 05:55:34 PM PDT 24
Peak memory 205648 kb
Host smart-33a8c301-7d39-4d3d-8051-5945c51cb2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744677140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.744677140
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3448266931
Short name T397
Test name
Test status
Simulation time 356104833 ps
CPU time 1.58 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 216492 kb
Host smart-b44a24f8-55ff-4456-aa3f-e99284519944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448266931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3448266931
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3567714257
Short name T1012
Test name
Test status
Simulation time 82586097 ps
CPU time 0.95 seconds
Started Aug 16 05:54:54 PM PDT 24
Finished Aug 16 05:54:56 PM PDT 24
Peak memory 206144 kb
Host smart-f84c501f-2b07-4749-9ae4-54e521d6ae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567714257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3567714257
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.4004692807
Short name T569
Test name
Test status
Simulation time 425707695 ps
CPU time 3.69 seconds
Started Aug 16 05:55:39 PM PDT 24
Finished Aug 16 05:55:43 PM PDT 24
Peak memory 224568 kb
Host smart-9c60187f-eccc-4b36-8302-b4cdf42d2242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004692807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.4004692807
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2057463626
Short name T751
Test name
Test status
Simulation time 53725553 ps
CPU time 0.73 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:25 PM PDT 24
Peak memory 205552 kb
Host smart-d415a76a-aee6-4f83-ab76-d7edda0e752e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057463626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2057463626
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.409193377
Short name T676
Test name
Test status
Simulation time 31992168 ps
CPU time 2.3 seconds
Started Aug 16 05:55:41 PM PDT 24
Finished Aug 16 05:55:43 PM PDT 24
Peak memory 232364 kb
Host smart-bddf4baa-d80c-4b59-a604-e73d0b06211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409193377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.409193377
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2125287316
Short name T416
Test name
Test status
Simulation time 53784041 ps
CPU time 0.76 seconds
Started Aug 16 05:55:38 PM PDT 24
Finished Aug 16 05:55:39 PM PDT 24
Peak memory 206520 kb
Host smart-6f7ea8d2-503e-49c8-80e2-9e57e8e4ee34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125287316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2125287316
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.226929740
Short name T873
Test name
Test status
Simulation time 35192530199 ps
CPU time 120.67 seconds
Started Aug 16 05:55:02 PM PDT 24
Finished Aug 16 05:57:03 PM PDT 24
Peak memory 239972 kb
Host smart-5461d571-5be3-44bf-b3d0-2d94d22101e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226929740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.226929740
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1445730840
Short name T205
Test name
Test status
Simulation time 5749112835 ps
CPU time 115.72 seconds
Started Aug 16 05:55:03 PM PDT 24
Finished Aug 16 05:56:59 PM PDT 24
Peak memory 272168 kb
Host smart-eabd80bd-a35a-4d92-9d0f-f56d608efce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445730840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1445730840
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.876590024
Short name T725
Test name
Test status
Simulation time 19355096188 ps
CPU time 72.69 seconds
Started Aug 16 05:55:02 PM PDT 24
Finished Aug 16 05:56:15 PM PDT 24
Peak memory 251040 kb
Host smart-7145dc51-7768-44cb-b969-64a406a104a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876590024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.876590024
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2319030072
Short name T374
Test name
Test status
Simulation time 555794283 ps
CPU time 8.66 seconds
Started Aug 16 05:55:38 PM PDT 24
Finished Aug 16 05:55:47 PM PDT 24
Peak memory 236320 kb
Host smart-ba760d20-bb52-49d3-826e-2310902349a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319030072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2319030072
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.284517829
Short name T826
Test name
Test status
Simulation time 18513610942 ps
CPU time 147.24 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:57:32 PM PDT 24
Peak memory 257556 kb
Host smart-8e5ab61d-e445-4c73-9398-5e76a1a16671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284517829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.284517829
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.559716306
Short name T662
Test name
Test status
Simulation time 412966776 ps
CPU time 3.32 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:55:08 PM PDT 24
Peak memory 232916 kb
Host smart-e5ff6899-9899-4a67-bdb3-079bc0a1ff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559716306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.559716306
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1015988674
Short name T480
Test name
Test status
Simulation time 1576154432 ps
CPU time 6.25 seconds
Started Aug 16 05:55:40 PM PDT 24
Finished Aug 16 05:55:46 PM PDT 24
Peak memory 224616 kb
Host smart-07353309-6d16-418f-b606-020d5126e648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015988674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1015988674
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.379539889
Short name T380
Test name
Test status
Simulation time 105323520 ps
CPU time 1.01 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:55:58 PM PDT 24
Peak memory 217876 kb
Host smart-13fd473a-18cd-4886-b454-bf075638fe93
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379539889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.379539889
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.519937476
Short name T875
Test name
Test status
Simulation time 185747520 ps
CPU time 2.36 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:55:07 PM PDT 24
Peak memory 224652 kb
Host smart-cf5ff1f8-bc83-4896-9c5a-1780df4ac588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519937476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.519937476
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3321645953
Short name T542
Test name
Test status
Simulation time 21241099518 ps
CPU time 14.93 seconds
Started Aug 16 05:54:59 PM PDT 24
Finished Aug 16 05:55:14 PM PDT 24
Peak memory 232944 kb
Host smart-afb4789e-9a86-441b-8f33-9f0d0c271438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321645953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3321645953
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3128315355
Short name T382
Test name
Test status
Simulation time 899620806 ps
CPU time 7.26 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:42 PM PDT 24
Peak memory 223472 kb
Host smart-63fcde08-becd-45f8-8652-ae82410c55b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3128315355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3128315355
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3452120609
Short name T464
Test name
Test status
Simulation time 178928625 ps
CPU time 0.98 seconds
Started Aug 16 05:55:01 PM PDT 24
Finished Aug 16 05:55:03 PM PDT 24
Peak memory 206940 kb
Host smart-ef005d93-28a4-477c-aa34-9be1386e22b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452120609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3452120609
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3490230380
Short name T833
Test name
Test status
Simulation time 1909299682 ps
CPU time 6.35 seconds
Started Aug 16 05:55:14 PM PDT 24
Finished Aug 16 05:55:21 PM PDT 24
Peak memory 216244 kb
Host smart-2eba06ed-f102-46bf-8cb1-75fa84abfa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490230380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3490230380
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.164142429
Short name T820
Test name
Test status
Simulation time 880937685 ps
CPU time 5.46 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 216492 kb
Host smart-823908d6-c993-4841-a018-0cf1f63a8c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164142429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.164142429
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3717889758
Short name T922
Test name
Test status
Simulation time 54461415 ps
CPU time 1.18 seconds
Started Aug 16 05:55:39 PM PDT 24
Finished Aug 16 05:55:40 PM PDT 24
Peak memory 216380 kb
Host smart-737e304c-cbaf-40c8-bc14-40e079cdf48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717889758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3717889758
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2276944984
Short name T494
Test name
Test status
Simulation time 385405105 ps
CPU time 0.99 seconds
Started Aug 16 05:55:29 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 207140 kb
Host smart-e2f18cd3-e69b-4666-afc2-be28daf1db41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276944984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2276944984
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.24796992
Short name T526
Test name
Test status
Simulation time 1066025910 ps
CPU time 5.49 seconds
Started Aug 16 05:55:13 PM PDT 24
Finished Aug 16 05:55:19 PM PDT 24
Peak memory 224584 kb
Host smart-e886f8a3-2b1a-4852-b6af-49b6a1bb6f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24796992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.24796992
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3996239792
Short name T58
Test name
Test status
Simulation time 40121403 ps
CPU time 0.72 seconds
Started Aug 16 05:55:05 PM PDT 24
Finished Aug 16 05:55:06 PM PDT 24
Peak memory 204940 kb
Host smart-2eb4d571-6a40-4d5a-b0a2-9a51dc797f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996239792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3996239792
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3662675685
Short name T811
Test name
Test status
Simulation time 2522680576 ps
CPU time 28.93 seconds
Started Aug 16 05:55:30 PM PDT 24
Finished Aug 16 05:55:59 PM PDT 24
Peak memory 224760 kb
Host smart-7a958907-381a-4bd1-ad72-b096cdb318dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662675685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3662675685
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1268467375
Short name T863
Test name
Test status
Simulation time 25689062 ps
CPU time 0.87 seconds
Started Aug 16 05:55:03 PM PDT 24
Finished Aug 16 05:55:04 PM PDT 24
Peak memory 206552 kb
Host smart-7467a092-c935-49b8-b6eb-a147cd5833c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268467375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1268467375
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3512911418
Short name T878
Test name
Test status
Simulation time 1303564199 ps
CPU time 28.11 seconds
Started Aug 16 05:55:05 PM PDT 24
Finished Aug 16 05:55:33 PM PDT 24
Peak memory 232980 kb
Host smart-b9f14d81-1179-42d4-a962-0b18d16354b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512911418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3512911418
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2549570962
Short name T241
Test name
Test status
Simulation time 6213956660 ps
CPU time 145.24 seconds
Started Aug 16 05:55:59 PM PDT 24
Finished Aug 16 05:58:25 PM PDT 24
Peak memory 265828 kb
Host smart-aed6b48e-79eb-4c90-97ae-3bdad7d2ec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549570962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2549570962
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.142901855
Short name T56
Test name
Test status
Simulation time 289134997 ps
CPU time 3.76 seconds
Started Aug 16 05:55:00 PM PDT 24
Finished Aug 16 05:55:04 PM PDT 24
Peak memory 224644 kb
Host smart-038a0d42-2c65-4d4d-8cc4-50ea6eeb10d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142901855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.142901855
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1021648606
Short name T256
Test name
Test status
Simulation time 4229607458 ps
CPU time 37.98 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:56:23 PM PDT 24
Peak memory 224760 kb
Host smart-2346a338-605a-4d7f-824b-e12b0a36b08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021648606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1021648606
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2607249602
Short name T955
Test name
Test status
Simulation time 1213611098 ps
CPU time 14.09 seconds
Started Aug 16 05:55:03 PM PDT 24
Finished Aug 16 05:55:18 PM PDT 24
Peak memory 232888 kb
Host smart-e94051c5-da48-43ee-b816-f5cf5efb7d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607249602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2607249602
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4031105652
Short name T534
Test name
Test status
Simulation time 6875663882 ps
CPU time 62.45 seconds
Started Aug 16 05:55:06 PM PDT 24
Finished Aug 16 05:56:08 PM PDT 24
Peak memory 232940 kb
Host smart-89637128-38a2-4c3a-852d-5b39acdd9a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031105652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4031105652
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1664275230
Short name T801
Test name
Test status
Simulation time 27025896 ps
CPU time 1.13 seconds
Started Aug 16 05:54:55 PM PDT 24
Finished Aug 16 05:54:56 PM PDT 24
Peak memory 216684 kb
Host smart-6c40156d-4cb1-46a8-8b69-94c6c93d138f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664275230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1664275230
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.552558394
Short name T779
Test name
Test status
Simulation time 7274536494 ps
CPU time 19.27 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:55:56 PM PDT 24
Peak memory 224720 kb
Host smart-48efc426-875a-47f9-9f0a-d2969fe2f118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552558394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.552558394
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2194581215
Short name T96
Test name
Test status
Simulation time 19735200531 ps
CPU time 30.12 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 249068 kb
Host smart-244e66a9-eee0-4f01-b1af-c9949a457fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194581215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2194581215
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3184151834
Short name T147
Test name
Test status
Simulation time 5677435863 ps
CPU time 9.63 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:55:14 PM PDT 24
Peak memory 221132 kb
Host smart-d1f1c817-c45c-4166-82e8-03908efd58ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3184151834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3184151834
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1800285578
Short name T823
Test name
Test status
Simulation time 282251577 ps
CPU time 1.18 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:55:38 PM PDT 24
Peak memory 207144 kb
Host smart-f77825f8-b4ab-4ee8-b9d1-b979daa01268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800285578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1800285578
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3125361770
Short name T574
Test name
Test status
Simulation time 8137052070 ps
CPU time 20.78 seconds
Started Aug 16 05:55:31 PM PDT 24
Finished Aug 16 05:55:52 PM PDT 24
Peak memory 216528 kb
Host smart-0ab31ca6-2d23-41b1-a8d8-2da31f0b68c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125361770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3125361770
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3012370128
Short name T1021
Test name
Test status
Simulation time 30303543666 ps
CPU time 18.63 seconds
Started Aug 16 05:55:01 PM PDT 24
Finished Aug 16 05:55:20 PM PDT 24
Peak memory 217640 kb
Host smart-26f2db0f-d1eb-4531-aa1a-ff83877ae104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012370128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3012370128
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.158406322
Short name T1001
Test name
Test status
Simulation time 275167487 ps
CPU time 3.8 seconds
Started Aug 16 05:55:01 PM PDT 24
Finished Aug 16 05:55:05 PM PDT 24
Peak memory 216536 kb
Host smart-815e6d06-eefa-4d7b-9727-8677738ac5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158406322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.158406322
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.810376208
Short name T410
Test name
Test status
Simulation time 89606408 ps
CPU time 0.93 seconds
Started Aug 16 05:55:38 PM PDT 24
Finished Aug 16 05:55:39 PM PDT 24
Peak memory 206080 kb
Host smart-3c0f1a79-3a84-44ce-9fb3-6463e45fe08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810376208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.810376208
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.647705940
Short name T262
Test name
Test status
Simulation time 995085049 ps
CPU time 5.09 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:55:09 PM PDT 24
Peak memory 224660 kb
Host smart-2f4b9196-328a-4f4f-a4be-4f61242b30e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647705940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.647705940
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1365163076
Short name T134
Test name
Test status
Simulation time 15606292 ps
CPU time 0.77 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:11 PM PDT 24
Peak memory 205896 kb
Host smart-8f960428-f8c0-45cc-b756-12335d889932
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365163076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1365163076
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3311151763
Short name T852
Test name
Test status
Simulation time 111342895 ps
CPU time 2.09 seconds
Started Aug 16 05:55:05 PM PDT 24
Finished Aug 16 05:55:07 PM PDT 24
Peak memory 224692 kb
Host smart-c17aa076-acc1-4c18-820e-7c2f7e021ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311151763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3311151763
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3475409403
Short name T788
Test name
Test status
Simulation time 12732161 ps
CPU time 0.73 seconds
Started Aug 16 05:55:43 PM PDT 24
Finished Aug 16 05:55:44 PM PDT 24
Peak memory 205536 kb
Host smart-6b0db615-2e78-4027-8a60-12cf3abdfa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475409403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3475409403
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2934474763
Short name T614
Test name
Test status
Simulation time 8722494463 ps
CPU time 85.71 seconds
Started Aug 16 05:55:03 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 249344 kb
Host smart-8d7e602b-ba82-444f-9dfc-99b4f24f83f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934474763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2934474763
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2371090699
Short name T739
Test name
Test status
Simulation time 11089092406 ps
CPU time 49.23 seconds
Started Aug 16 05:55:14 PM PDT 24
Finished Aug 16 05:56:03 PM PDT 24
Peak memory 249560 kb
Host smart-d32b01e1-9dcb-4da9-bc35-f5d1ce5753a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371090699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2371090699
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4003756985
Short name T229
Test name
Test status
Simulation time 38805015889 ps
CPU time 99.36 seconds
Started Aug 16 05:55:03 PM PDT 24
Finished Aug 16 05:56:43 PM PDT 24
Peak memory 238356 kb
Host smart-0e501ae3-d614-4e47-aeb9-098b25650acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003756985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4003756985
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.15923546
Short name T636
Test name
Test status
Simulation time 611717005 ps
CPU time 4.63 seconds
Started Aug 16 05:55:03 PM PDT 24
Finished Aug 16 05:55:08 PM PDT 24
Peak memory 232896 kb
Host smart-e12843b4-2f01-4535-9aff-b298570a517d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15923546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.15923546
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3592096697
Short name T577
Test name
Test status
Simulation time 1514770230 ps
CPU time 10.64 seconds
Started Aug 16 05:55:20 PM PDT 24
Finished Aug 16 05:55:31 PM PDT 24
Peak memory 228540 kb
Host smart-c64aed20-4fd7-4dbf-a030-44e360bec025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592096697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3592096697
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1383544447
Short name T498
Test name
Test status
Simulation time 28433678 ps
CPU time 2.34 seconds
Started Aug 16 05:55:33 PM PDT 24
Finished Aug 16 05:55:36 PM PDT 24
Peak memory 232520 kb
Host smart-3a8caf72-a2a0-40c7-9a1f-889bf8f7eb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383544447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1383544447
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.667726196
Short name T962
Test name
Test status
Simulation time 31419669 ps
CPU time 1.05 seconds
Started Aug 16 05:55:02 PM PDT 24
Finished Aug 16 05:55:04 PM PDT 24
Peak memory 217992 kb
Host smart-1444d10d-afc5-44ad-b8bf-7d64de03fcaf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667726196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.667726196
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4004288678
Short name T273
Test name
Test status
Simulation time 1054651070 ps
CPU time 2.3 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:55:36 PM PDT 24
Peak memory 224388 kb
Host smart-e76ab2e0-1f39-484b-a548-03da4e8b80eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004288678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4004288678
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1156017706
Short name T719
Test name
Test status
Simulation time 456805177 ps
CPU time 3.48 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:14 PM PDT 24
Peak memory 224640 kb
Host smart-f6b6f087-f9fc-4c73-aecb-e4ef3c8bb70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156017706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1156017706
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2385146688
Short name T730
Test name
Test status
Simulation time 3505667997 ps
CPU time 9.43 seconds
Started Aug 16 05:55:12 PM PDT 24
Finished Aug 16 05:55:22 PM PDT 24
Peak memory 222216 kb
Host smart-4bfaba1e-2db5-4b46-ba05-6c5767d4ccb0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2385146688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2385146688
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1805945728
Short name T165
Test name
Test status
Simulation time 27580263417 ps
CPU time 226.39 seconds
Started Aug 16 05:55:20 PM PDT 24
Finished Aug 16 05:59:07 PM PDT 24
Peak memory 251372 kb
Host smart-21cfb98d-8e18-4d3e-ac26-c4d08ca087e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805945728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1805945728
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3907588367
Short name T474
Test name
Test status
Simulation time 1554690826 ps
CPU time 6.83 seconds
Started Aug 16 05:55:32 PM PDT 24
Finished Aug 16 05:55:39 PM PDT 24
Peak memory 219584 kb
Host smart-aa88783f-2f7a-46ea-8da3-e3d74ab92120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907588367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3907588367
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1508236080
Short name T994
Test name
Test status
Simulation time 2881278385 ps
CPU time 5.81 seconds
Started Aug 16 05:55:06 PM PDT 24
Finished Aug 16 05:55:12 PM PDT 24
Peak memory 216580 kb
Host smart-96ffce37-e041-45fc-a34a-5360ebca971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508236080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1508236080
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2641880392
Short name T370
Test name
Test status
Simulation time 147105619 ps
CPU time 1.07 seconds
Started Aug 16 05:55:03 PM PDT 24
Finished Aug 16 05:55:05 PM PDT 24
Peak memory 207480 kb
Host smart-af28e5fa-59c9-4607-b07f-c22a5975acad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641880392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2641880392
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1621381201
Short name T1011
Test name
Test status
Simulation time 56952167 ps
CPU time 0.75 seconds
Started Aug 16 05:55:33 PM PDT 24
Finished Aug 16 05:55:34 PM PDT 24
Peak memory 206128 kb
Host smart-6e650b43-3e38-4207-9b6c-7d47dae19e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621381201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1621381201
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2194872811
Short name T227
Test name
Test status
Simulation time 1264290049 ps
CPU time 6.24 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:55:11 PM PDT 24
Peak memory 232872 kb
Host smart-10896e3b-e81e-4c42-939d-6713636ff5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194872811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2194872811
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2309974897
Short name T419
Test name
Test status
Simulation time 22443301 ps
CPU time 0.71 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 205520 kb
Host smart-f32b4919-7eb1-47c7-bf4f-c869c4ab262f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309974897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2309974897
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1996981138
Short name T597
Test name
Test status
Simulation time 137070748 ps
CPU time 3.57 seconds
Started Aug 16 05:55:14 PM PDT 24
Finished Aug 16 05:55:18 PM PDT 24
Peak memory 232756 kb
Host smart-beab126a-1067-4198-a0f7-e51b6004ab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996981138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1996981138
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3022443840
Short name T576
Test name
Test status
Simulation time 17556746 ps
CPU time 0.83 seconds
Started Aug 16 05:55:38 PM PDT 24
Finished Aug 16 05:55:39 PM PDT 24
Peak memory 205500 kb
Host smart-1f652b07-ef33-4323-8a30-818e62417fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022443840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3022443840
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3603087012
Short name T472
Test name
Test status
Simulation time 38456248 ps
CPU time 0.79 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 216084 kb
Host smart-cc1fbc73-7ad0-401d-a969-a6a2fec2809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603087012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3603087012
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1526013989
Short name T308
Test name
Test status
Simulation time 13092462137 ps
CPU time 128.89 seconds
Started Aug 16 05:55:14 PM PDT 24
Finished Aug 16 05:57:23 PM PDT 24
Peak memory 243256 kb
Host smart-514423d7-0255-4b4a-b995-a79a7454e8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526013989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1526013989
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3554878284
Short name T803
Test name
Test status
Simulation time 102578597545 ps
CPU time 505.45 seconds
Started Aug 16 05:55:37 PM PDT 24
Finished Aug 16 06:04:03 PM PDT 24
Peak memory 251420 kb
Host smart-3561a1f6-82a7-46e0-9b63-1561a24e5856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554878284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3554878284
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3110761276
Short name T1028
Test name
Test status
Simulation time 668438722 ps
CPU time 6.77 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:42 PM PDT 24
Peak memory 241032 kb
Host smart-923edc92-f04d-4e50-865b-0ed119a0f9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110761276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3110761276
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2923416187
Short name T868
Test name
Test status
Simulation time 104939945944 ps
CPU time 109.03 seconds
Started Aug 16 05:55:14 PM PDT 24
Finished Aug 16 05:57:03 PM PDT 24
Peak memory 249300 kb
Host smart-3e2140af-9786-41e8-9819-a6c741849195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923416187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2923416187
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.940304347
Short name T593
Test name
Test status
Simulation time 205859242 ps
CPU time 2.79 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:13 PM PDT 24
Peak memory 224576 kb
Host smart-612489ac-3b8e-4361-9f51-8a6a1427a5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940304347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.940304347
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3412592700
Short name T947
Test name
Test status
Simulation time 4219785567 ps
CPU time 23.02 seconds
Started Aug 16 05:55:32 PM PDT 24
Finished Aug 16 05:55:56 PM PDT 24
Peak memory 241088 kb
Host smart-c0f9e93a-2e50-456e-ae3a-ec958a3c8953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412592700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3412592700
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1691316980
Short name T32
Test name
Test status
Simulation time 27052326 ps
CPU time 0.96 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 217988 kb
Host smart-7135e461-69f6-4afb-840c-d1076aca0844
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691316980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1691316980
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2833750065
Short name T776
Test name
Test status
Simulation time 417846787 ps
CPU time 2.6 seconds
Started Aug 16 05:55:15 PM PDT 24
Finished Aug 16 05:55:18 PM PDT 24
Peak memory 224600 kb
Host smart-1859a421-0e98-46be-a4ea-b268d8d9f881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833750065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2833750065
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1421993004
Short name T447
Test name
Test status
Simulation time 8776598319 ps
CPU time 20.72 seconds
Started Aug 16 05:55:38 PM PDT 24
Finished Aug 16 05:55:58 PM PDT 24
Peak memory 232948 kb
Host smart-aa6e0725-3d28-428e-b9a9-52b8e9090e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421993004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1421993004
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.327104475
Short name T690
Test name
Test status
Simulation time 2343844086 ps
CPU time 10.75 seconds
Started Aug 16 05:55:14 PM PDT 24
Finished Aug 16 05:55:25 PM PDT 24
Peak memory 222536 kb
Host smart-4d680fa9-c3c6-47ac-be81-ce3085f67bbb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=327104475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.327104475
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3448703884
Short name T289
Test name
Test status
Simulation time 100683778725 ps
CPU time 279.92 seconds
Started Aug 16 05:55:27 PM PDT 24
Finished Aug 16 06:00:07 PM PDT 24
Peak memory 257604 kb
Host smart-571b31ef-dbbd-4e9e-9a18-dd646e9c9f93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448703884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3448703884
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3185102053
Short name T948
Test name
Test status
Simulation time 8048570435 ps
CPU time 46.36 seconds
Started Aug 16 05:55:49 PM PDT 24
Finished Aug 16 05:56:35 PM PDT 24
Peak memory 216540 kb
Host smart-37f2dc56-ecb9-4272-b9cd-b35958e50dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185102053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3185102053
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2942902406
Short name T627
Test name
Test status
Simulation time 27913629 ps
CPU time 0.73 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:11 PM PDT 24
Peak memory 205684 kb
Host smart-8e7bc25e-f4f1-4d76-a1e1-fb9b0b603562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942902406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2942902406
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.341761396
Short name T824
Test name
Test status
Simulation time 18919113 ps
CPU time 1.07 seconds
Started Aug 16 05:55:12 PM PDT 24
Finished Aug 16 05:55:13 PM PDT 24
Peak memory 207440 kb
Host smart-34131866-dd5d-44d5-b644-cce434617773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341761396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.341761396
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.337921012
Short name T604
Test name
Test status
Simulation time 81807748 ps
CPU time 1 seconds
Started Aug 16 05:55:06 PM PDT 24
Finished Aug 16 05:55:08 PM PDT 24
Peak memory 206084 kb
Host smart-914d2572-3b33-41d5-b274-885169150531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337921012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.337921012
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3157862943
Short name T202
Test name
Test status
Simulation time 2403769264 ps
CPU time 6.03 seconds
Started Aug 16 05:55:14 PM PDT 24
Finished Aug 16 05:55:20 PM PDT 24
Peak memory 232920 kb
Host smart-b0343040-f0d5-4158-b16a-ea585c9a120c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157862943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3157862943
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4184552634
Short name T768
Test name
Test status
Simulation time 15155385 ps
CPU time 0.73 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:25 PM PDT 24
Peak memory 204884 kb
Host smart-164fbdbd-3299-467d-a088-349e2d0588cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184552634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4184552634
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1463929456
Short name T629
Test name
Test status
Simulation time 426668149 ps
CPU time 4.05 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:55:40 PM PDT 24
Peak memory 232788 kb
Host smart-f56741c3-4195-47f5-afc8-88979664b2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463929456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1463929456
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.364577301
Short name T523
Test name
Test status
Simulation time 29571103 ps
CPU time 0.73 seconds
Started Aug 16 05:55:22 PM PDT 24
Finished Aug 16 05:55:22 PM PDT 24
Peak memory 205552 kb
Host smart-733f0681-3643-4706-84c2-81914cce2f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364577301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.364577301
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3404125871
Short name T654
Test name
Test status
Simulation time 15606003202 ps
CPU time 144.28 seconds
Started Aug 16 05:55:40 PM PDT 24
Finished Aug 16 05:58:04 PM PDT 24
Peak memory 252328 kb
Host smart-fc2b7e53-d719-42db-90cb-dab86d988e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404125871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3404125871
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.326009523
Short name T946
Test name
Test status
Simulation time 12286586388 ps
CPU time 121.3 seconds
Started Aug 16 05:55:30 PM PDT 24
Finished Aug 16 05:57:31 PM PDT 24
Peak memory 252736 kb
Host smart-7de1b4e3-9ba1-402f-bbbd-ed17be38c377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326009523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.326009523
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3764066858
Short name T76
Test name
Test status
Simulation time 3591874394 ps
CPU time 8.68 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:19 PM PDT 24
Peak memory 252288 kb
Host smart-c1cecd32-5803-4805-ad95-adb1273390f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764066858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3764066858
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.930779245
Short name T313
Test name
Test status
Simulation time 21074675677 ps
CPU time 176.8 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:58:01 PM PDT 24
Peak memory 251948 kb
Host smart-a230a45a-b47d-4989-992c-ce9cf2402b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930779245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.930779245
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2464124203
Short name T279
Test name
Test status
Simulation time 150415288 ps
CPU time 3.74 seconds
Started Aug 16 05:55:21 PM PDT 24
Finished Aug 16 05:55:25 PM PDT 24
Peak memory 224664 kb
Host smart-f52730f4-dfa1-480c-8895-bf3049f31d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464124203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2464124203
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.884243802
Short name T796
Test name
Test status
Simulation time 103953496 ps
CPU time 2.14 seconds
Started Aug 16 05:55:11 PM PDT 24
Finished Aug 16 05:55:13 PM PDT 24
Peak memory 232532 kb
Host smart-01889b94-f01a-4009-a414-df4a786c7714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884243802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.884243802
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.109534219
Short name T34
Test name
Test status
Simulation time 105541845 ps
CPU time 1.11 seconds
Started Aug 16 05:55:09 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 216728 kb
Host smart-2c30da6a-bd96-4404-b47e-e77996d61ad3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109534219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.109534219
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.473415273
Short name T304
Test name
Test status
Simulation time 18728563499 ps
CPU time 12.71 seconds
Started Aug 16 05:55:09 PM PDT 24
Finished Aug 16 05:55:22 PM PDT 24
Peak memory 224704 kb
Host smart-7ad7be74-f42a-4740-bdde-113bf2ea88f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473415273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.473415273
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2562388402
Short name T417
Test name
Test status
Simulation time 407357965 ps
CPU time 4.22 seconds
Started Aug 16 05:54:58 PM PDT 24
Finished Aug 16 05:55:03 PM PDT 24
Peak memory 224672 kb
Host smart-fa63bc33-55c6-4458-b94c-b1180a6cdca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562388402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2562388402
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.404618307
Short name T531
Test name
Test status
Simulation time 7775045966 ps
CPU time 11.26 seconds
Started Aug 16 05:55:51 PM PDT 24
Finished Aug 16 05:56:04 PM PDT 24
Peak memory 222164 kb
Host smart-173ad79c-ac29-4fae-8d2d-fdf72f13e1b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=404618307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.404618307
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.799404168
Short name T885
Test name
Test status
Simulation time 546005787 ps
CPU time 1.2 seconds
Started Aug 16 05:55:08 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 206956 kb
Host smart-c11d9f6f-ab72-42be-bc5c-9f10df57ae37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799404168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.799404168
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3630893037
Short name T24
Test name
Test status
Simulation time 18588740055 ps
CPU time 23.31 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:56:00 PM PDT 24
Peak memory 216508 kb
Host smart-21326be7-4455-4b0c-95c2-f18aa4c47186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630893037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3630893037
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2236775029
Short name T650
Test name
Test status
Simulation time 5572658746 ps
CPU time 15.79 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 216316 kb
Host smart-c09632ff-5c95-418f-bfd4-cecd44c4092e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236775029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2236775029
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3021713219
Short name T1
Test name
Test status
Simulation time 106467604 ps
CPU time 2.45 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 216448 kb
Host smart-a3486153-abc6-492a-a1f3-e1dc35876957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021713219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3021713219
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2698940829
Short name T344
Test name
Test status
Simulation time 210951347 ps
CPU time 0.92 seconds
Started Aug 16 05:55:32 PM PDT 24
Finished Aug 16 05:55:33 PM PDT 24
Peak memory 207148 kb
Host smart-7aa12463-2493-411b-a65d-27b025630a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698940829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2698940829
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3866436778
Short name T258
Test name
Test status
Simulation time 323531189 ps
CPU time 4.63 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:15 PM PDT 24
Peak memory 232676 kb
Host smart-72656912-e98e-4662-95f0-ba179394c890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866436778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3866436778
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.635502722
Short name T358
Test name
Test status
Simulation time 15407463 ps
CPU time 0.71 seconds
Started Aug 16 05:55:09 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 205488 kb
Host smart-01078ee8-4ce6-48bf-9457-8b6ac1f13edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635502722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.635502722
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.924121346
Short name T980
Test name
Test status
Simulation time 31548774 ps
CPU time 2.13 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 224564 kb
Host smart-ff22c921-a013-48f3-a61f-50099061b716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924121346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.924121346
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3100793483
Short name T351
Test name
Test status
Simulation time 82649485 ps
CPU time 0.76 seconds
Started Aug 16 05:55:39 PM PDT 24
Finished Aug 16 05:55:40 PM PDT 24
Peak memory 205892 kb
Host smart-b5e1b230-a565-42f7-abff-13c625193cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100793483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3100793483
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2293066254
Short name T299
Test name
Test status
Simulation time 3837919399 ps
CPU time 67.61 seconds
Started Aug 16 05:55:44 PM PDT 24
Finished Aug 16 05:56:51 PM PDT 24
Peak memory 265512 kb
Host smart-c33ed573-d10d-4f2c-96ee-422cf9279fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293066254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2293066254
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2756063191
Short name T966
Test name
Test status
Simulation time 10954113161 ps
CPU time 71.4 seconds
Started Aug 16 05:55:40 PM PDT 24
Finished Aug 16 05:56:52 PM PDT 24
Peak memory 241264 kb
Host smart-0c10f130-c5f9-4202-b765-da1d1a065611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756063191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2756063191
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2553081100
Short name T485
Test name
Test status
Simulation time 27345267827 ps
CPU time 228.31 seconds
Started Aug 16 05:55:44 PM PDT 24
Finished Aug 16 05:59:32 PM PDT 24
Peak memory 250752 kb
Host smart-0df47faf-6a91-47dd-8c94-5f1430c601b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553081100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2553081100
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3432905342
Short name T583
Test name
Test status
Simulation time 497068274 ps
CPU time 4.33 seconds
Started Aug 16 05:55:54 PM PDT 24
Finished Aug 16 05:56:03 PM PDT 24
Peak memory 232864 kb
Host smart-cf444644-7ccb-4288-a587-5a7ba3e54bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432905342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3432905342
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.7274078
Short name T187
Test name
Test status
Simulation time 47146000177 ps
CPU time 171.71 seconds
Started Aug 16 05:55:50 PM PDT 24
Finished Aug 16 05:58:42 PM PDT 24
Peak memory 249344 kb
Host smart-20520ef6-8777-40c9-b448-4a399e069a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7274078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.7274078
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1463869747
Short name T883
Test name
Test status
Simulation time 1221225626 ps
CPU time 10.81 seconds
Started Aug 16 05:55:52 PM PDT 24
Finished Aug 16 05:56:03 PM PDT 24
Peak memory 224640 kb
Host smart-0ad469de-e4ae-46e3-bb5c-87cb1379fc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463869747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1463869747
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2835177700
Short name T1015
Test name
Test status
Simulation time 22258104116 ps
CPU time 18.4 seconds
Started Aug 16 05:55:43 PM PDT 24
Finished Aug 16 05:56:02 PM PDT 24
Peak memory 224792 kb
Host smart-3dd3f639-c13e-4593-8046-c1a0f8b3291d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835177700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2835177700
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1091556182
Short name T1007
Test name
Test status
Simulation time 14717739 ps
CPU time 0.98 seconds
Started Aug 16 05:56:00 PM PDT 24
Finished Aug 16 05:56:02 PM PDT 24
Peak memory 216680 kb
Host smart-9446a026-7abc-46c4-9c13-64f6cbb020ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091556182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1091556182
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.797033770
Short name T389
Test name
Test status
Simulation time 1684281219 ps
CPU time 8.44 seconds
Started Aug 16 05:55:18 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 232844 kb
Host smart-881de836-e290-4690-9c97-525839dc7516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797033770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.797033770
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1601807561
Short name T892
Test name
Test status
Simulation time 211006189 ps
CPU time 2.35 seconds
Started Aug 16 05:55:49 PM PDT 24
Finished Aug 16 05:55:52 PM PDT 24
Peak memory 223972 kb
Host smart-c7960d53-b39e-4aa7-8426-18ca07738fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601807561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1601807561
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2447144357
Short name T586
Test name
Test status
Simulation time 2698191579 ps
CPU time 12.39 seconds
Started Aug 16 05:55:39 PM PDT 24
Finished Aug 16 05:55:52 PM PDT 24
Peak memory 222320 kb
Host smart-abce3d26-3ce9-4e06-8e60-1eae3dc74291
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2447144357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2447144357
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3105242713
Short name T1013
Test name
Test status
Simulation time 16304128144 ps
CPU time 42.35 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:53 PM PDT 24
Peak memory 216568 kb
Host smart-b63e6ce2-6e63-4b06-b901-9e0d9a247477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105242713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3105242713
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2985745129
Short name T527
Test name
Test status
Simulation time 9918343230 ps
CPU time 10.25 seconds
Started Aug 16 05:55:28 PM PDT 24
Finished Aug 16 05:55:39 PM PDT 24
Peak memory 216548 kb
Host smart-74a60270-9078-402d-bdcd-92fd7482bd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985745129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2985745129
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3607654135
Short name T394
Test name
Test status
Simulation time 35397981 ps
CPU time 0.78 seconds
Started Aug 16 05:55:16 PM PDT 24
Finished Aug 16 05:55:17 PM PDT 24
Peak memory 206120 kb
Host smart-2eec835b-4519-4c03-9788-ea619e62f465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607654135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3607654135
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2369265393
Short name T623
Test name
Test status
Simulation time 32589165 ps
CPU time 0.79 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 206100 kb
Host smart-fcf19305-16f4-4cb9-9536-0e14e8e2848a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369265393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2369265393
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1292542265
Short name T637
Test name
Test status
Simulation time 8752731908 ps
CPU time 9.49 seconds
Started Aug 16 05:56:02 PM PDT 24
Finished Aug 16 05:56:12 PM PDT 24
Peak memory 232764 kb
Host smart-68a782a1-2e21-4312-9ad5-8cdb592e0925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292542265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1292542265
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2398576531
Short name T422
Test name
Test status
Simulation time 12587198 ps
CPU time 0.7 seconds
Started Aug 16 05:55:06 PM PDT 24
Finished Aug 16 05:55:07 PM PDT 24
Peak memory 205544 kb
Host smart-89a489ad-0332-4c98-b511-80fd128f8e23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398576531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
398576531
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2499876605
Short name T609
Test name
Test status
Simulation time 1030997809 ps
CPU time 3.98 seconds
Started Aug 16 05:55:01 PM PDT 24
Finished Aug 16 05:55:05 PM PDT 24
Peak memory 232864 kb
Host smart-508ed15d-eb45-4154-8f14-dfb0c4fb7829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499876605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2499876605
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1259421662
Short name T901
Test name
Test status
Simulation time 71964505 ps
CPU time 0.73 seconds
Started Aug 16 05:55:07 PM PDT 24
Finished Aug 16 05:55:08 PM PDT 24
Peak memory 206504 kb
Host smart-2d3dbbc9-e965-4dd1-8420-f94223a1d9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259421662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1259421662
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1108451277
Short name T169
Test name
Test status
Simulation time 21034855717 ps
CPU time 151.05 seconds
Started Aug 16 05:54:57 PM PDT 24
Finished Aug 16 05:57:28 PM PDT 24
Peak memory 255956 kb
Host smart-4ca39d18-2577-4ca4-9354-6998d3420e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108451277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1108451277
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2285473420
Short name T305
Test name
Test status
Simulation time 12782259035 ps
CPU time 119.53 seconds
Started Aug 16 05:55:32 PM PDT 24
Finished Aug 16 05:57:32 PM PDT 24
Peak memory 250436 kb
Host smart-b469e7f7-44bd-499a-81e4-dfbdbcd9d7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285473420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2285473420
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.617491367
Short name T421
Test name
Test status
Simulation time 1705789891 ps
CPU time 20.57 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:31 PM PDT 24
Peak memory 224728 kb
Host smart-9a36061b-d1b5-42fe-a92d-f767616f6e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617491367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.617491367
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.457436488
Short name T35
Test name
Test status
Simulation time 25139414265 ps
CPU time 47.36 seconds
Started Aug 16 05:54:24 PM PDT 24
Finished Aug 16 05:55:12 PM PDT 24
Peak memory 253248 kb
Host smart-6d702e87-dabd-40f7-9c33-487c3bda4693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457436488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
457436488
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3011907314
Short name T436
Test name
Test status
Simulation time 291477715 ps
CPU time 2.99 seconds
Started Aug 16 05:55:07 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 232804 kb
Host smart-843beb99-7ce4-41b1-816f-c7097b339306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011907314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3011907314
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2830091457
Short name T244
Test name
Test status
Simulation time 9437821363 ps
CPU time 22.32 seconds
Started Aug 16 05:54:28 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 227948 kb
Host smart-1a3737d1-9fc4-44ea-a6ac-3ad82fb9d198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830091457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2830091457
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1703186112
Short name T918
Test name
Test status
Simulation time 83521866 ps
CPU time 1.01 seconds
Started Aug 16 05:54:28 PM PDT 24
Finished Aug 16 05:54:29 PM PDT 24
Peak memory 216668 kb
Host smart-92afd4fe-edee-4e21-afe1-2f73ef24c514
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703186112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1703186112
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.963057926
Short name T272
Test name
Test status
Simulation time 1194037853 ps
CPU time 4.25 seconds
Started Aug 16 05:54:31 PM PDT 24
Finished Aug 16 05:54:36 PM PDT 24
Peak memory 232880 kb
Host smart-94074b3e-4ea2-435d-805b-483fded49a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963057926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
963057926
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4031886059
Short name T452
Test name
Test status
Simulation time 3173019392 ps
CPU time 11.33 seconds
Started Aug 16 05:54:29 PM PDT 24
Finished Aug 16 05:54:41 PM PDT 24
Peak memory 232968 kb
Host smart-aa87dff7-bf0d-4913-a407-da03422eef7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031886059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4031886059
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.66784310
Short name T625
Test name
Test status
Simulation time 1286695049 ps
CPU time 8.92 seconds
Started Aug 16 05:55:01 PM PDT 24
Finished Aug 16 05:55:11 PM PDT 24
Peak memory 222644 kb
Host smart-c554a9f9-350e-4a9a-b798-1eda5c18463c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=66784310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct
.66784310
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.828714904
Short name T69
Test name
Test status
Simulation time 62528806 ps
CPU time 1.09 seconds
Started Aug 16 05:54:24 PM PDT 24
Finished Aug 16 05:54:25 PM PDT 24
Peak memory 235616 kb
Host smart-d42085c9-0302-46ff-a82e-e8462f6ff210
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828714904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.828714904
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.563337516
Short name T300
Test name
Test status
Simulation time 63490271719 ps
CPU time 179.51 seconds
Started Aug 16 05:54:32 PM PDT 24
Finished Aug 16 05:57:31 PM PDT 24
Peak memory 249388 kb
Host smart-1374eeae-e555-4e47-b9a9-af47d30a4eda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563337516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.563337516
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2407943834
Short name T529
Test name
Test status
Simulation time 1064562779 ps
CPU time 4.82 seconds
Started Aug 16 05:55:01 PM PDT 24
Finished Aug 16 05:55:06 PM PDT 24
Peak memory 216600 kb
Host smart-2e6095b7-cd4e-4ba5-9357-d9bc68a56f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407943834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2407943834
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2464115898
Short name T405
Test name
Test status
Simulation time 13373055 ps
CPU time 0.7 seconds
Started Aug 16 05:55:13 PM PDT 24
Finished Aug 16 05:55:14 PM PDT 24
Peak memory 205700 kb
Host smart-8cd94c89-050c-410b-8618-bafdce5e34b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464115898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2464115898
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1967435555
Short name T793
Test name
Test status
Simulation time 74829652 ps
CPU time 0.81 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:55:05 PM PDT 24
Peak memory 206676 kb
Host smart-6d78ace8-0e76-4ce3-9f0f-4ae3035fa193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967435555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1967435555
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.491749941
Short name T561
Test name
Test status
Simulation time 47838804 ps
CPU time 0.78 seconds
Started Aug 16 05:55:00 PM PDT 24
Finished Aug 16 05:55:01 PM PDT 24
Peak memory 205976 kb
Host smart-87e3f9d6-9545-4819-88c1-ee84a80bb004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491749941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.491749941
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.598788939
Short name T592
Test name
Test status
Simulation time 410162354 ps
CPU time 2.07 seconds
Started Aug 16 05:54:46 PM PDT 24
Finished Aug 16 05:54:48 PM PDT 24
Peak memory 224256 kb
Host smart-d67fc0ba-21ac-4860-8c26-0942ddd3f6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598788939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.598788939
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.4130009980
Short name T973
Test name
Test status
Simulation time 19613234 ps
CPU time 0.68 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:55:54 PM PDT 24
Peak memory 205504 kb
Host smart-e6acc444-81d4-4b03-910f-2fddcd379961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130009980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
4130009980
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3533464640
Short name T274
Test name
Test status
Simulation time 33816892 ps
CPU time 2.49 seconds
Started Aug 16 05:55:29 PM PDT 24
Finished Aug 16 05:55:31 PM PDT 24
Peak memory 232852 kb
Host smart-ccf490db-e9c3-4e57-b16b-08e927eb3392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533464640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3533464640
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.709669132
Short name T443
Test name
Test status
Simulation time 149965384 ps
CPU time 0.72 seconds
Started Aug 16 05:55:21 PM PDT 24
Finished Aug 16 05:55:22 PM PDT 24
Peak memory 205900 kb
Host smart-cf81d682-3161-477d-921f-2ae690083baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709669132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.709669132
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3556334251
Short name T310
Test name
Test status
Simulation time 51829172343 ps
CPU time 82.63 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:56:32 PM PDT 24
Peak memory 236600 kb
Host smart-bf9f49c7-05d7-4af4-8f14-da1a8af519a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556334251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3556334251
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_intercept.692838691
Short name T870
Test name
Test status
Simulation time 672607936 ps
CPU time 7.69 seconds
Started Aug 16 05:55:20 PM PDT 24
Finished Aug 16 05:55:27 PM PDT 24
Peak memory 232928 kb
Host smart-7d1b6a63-3365-407d-940f-706e87f6fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692838691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.692838691
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1644391541
Short name T544
Test name
Test status
Simulation time 1296536989 ps
CPU time 6.64 seconds
Started Aug 16 05:55:49 PM PDT 24
Finished Aug 16 05:56:01 PM PDT 24
Peak memory 224648 kb
Host smart-c48a0f37-1cfd-4828-aede-fb324d2c0020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644391541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1644391541
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.184704084
Short name T266
Test name
Test status
Simulation time 15686096279 ps
CPU time 11.45 seconds
Started Aug 16 05:55:21 PM PDT 24
Finished Aug 16 05:55:33 PM PDT 24
Peak memory 224680 kb
Host smart-c42b0e48-898b-4297-b361-35d42dd25742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184704084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.184704084
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3979354893
Short name T596
Test name
Test status
Simulation time 479072501 ps
CPU time 4.23 seconds
Started Aug 16 05:55:20 PM PDT 24
Finished Aug 16 05:55:25 PM PDT 24
Peak memory 232892 kb
Host smart-bd726c90-d7ef-41a2-8cf0-4dc44e3aa1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979354893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3979354893
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1149363155
Short name T538
Test name
Test status
Simulation time 436595524 ps
CPU time 6.93 seconds
Started Aug 16 05:55:21 PM PDT 24
Finished Aug 16 05:55:28 PM PDT 24
Peak memory 219352 kb
Host smart-1b354c38-dba1-4f67-bfbd-90b3db0b84aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1149363155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1149363155
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2239499920
Short name T140
Test name
Test status
Simulation time 172829731509 ps
CPU time 330.73 seconds
Started Aug 16 05:55:19 PM PDT 24
Finished Aug 16 06:00:50 PM PDT 24
Peak memory 265780 kb
Host smart-179315ed-c1c7-476d-b562-5bc3a8dc8cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239499920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2239499920
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.18831738
Short name T740
Test name
Test status
Simulation time 26568990708 ps
CPU time 34.1 seconds
Started Aug 16 05:56:00 PM PDT 24
Finished Aug 16 05:56:35 PM PDT 24
Peak memory 216524 kb
Host smart-d6b84230-d7e2-4e44-9756-c4115bdf739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18831738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.18831738
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1753235860
Short name T633
Test name
Test status
Simulation time 12444415128 ps
CPU time 7.19 seconds
Started Aug 16 05:55:21 PM PDT 24
Finished Aug 16 05:55:28 PM PDT 24
Peak memory 217584 kb
Host smart-88171fec-119f-43a0-9d64-5de1dd6aa2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753235860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1753235860
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2516470036
Short name T135
Test name
Test status
Simulation time 163071219 ps
CPU time 0.8 seconds
Started Aug 16 05:55:47 PM PDT 24
Finished Aug 16 05:55:48 PM PDT 24
Peak memory 206080 kb
Host smart-2e31f71b-ebaf-4241-b723-5f3defa82b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516470036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2516470036
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3415271701
Short name T562
Test name
Test status
Simulation time 918086428 ps
CPU time 0.94 seconds
Started Aug 16 05:55:37 PM PDT 24
Finished Aug 16 05:55:38 PM PDT 24
Peak memory 207152 kb
Host smart-8995d3d2-b24f-4343-827e-011b924f98f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415271701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3415271701
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1114375735
Short name T723
Test name
Test status
Simulation time 4621390852 ps
CPU time 11.3 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:36 PM PDT 24
Peak memory 241088 kb
Host smart-5ae0844a-21d7-4c23-aefc-93fb0b3c042c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114375735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1114375735
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.109299172
Short name T943
Test name
Test status
Simulation time 12778506 ps
CPU time 0.7 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:25 PM PDT 24
Peak memory 205528 kb
Host smart-ffa81012-e7e4-44f7-a7f9-dcc07d701bae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109299172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.109299172
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1711651794
Short name T357
Test name
Test status
Simulation time 72174244 ps
CPU time 2.27 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 05:55:25 PM PDT 24
Peak memory 224252 kb
Host smart-a52d25f5-1959-43ac-b7ce-968918287bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711651794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1711651794
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1094491428
Short name T341
Test name
Test status
Simulation time 28927568 ps
CPU time 0.78 seconds
Started Aug 16 05:55:21 PM PDT 24
Finished Aug 16 05:55:22 PM PDT 24
Peak memory 206592 kb
Host smart-da71dc13-ddef-4287-9bb4-8c3a1e9d4395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094491428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1094491428
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.768804518
Short name T170
Test name
Test status
Simulation time 32530267524 ps
CPU time 87.01 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:57:24 PM PDT 24
Peak memory 251588 kb
Host smart-557d55d7-d48f-4ef6-a76b-317e4423ce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768804518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.768804518
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.249072597
Short name T693
Test name
Test status
Simulation time 4197315918 ps
CPU time 57.58 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:56:32 PM PDT 24
Peak memory 252760 kb
Host smart-19a4da78-145c-407e-aab0-5ba769d4c40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249072597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.249072597
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.4009077890
Short name T791
Test name
Test status
Simulation time 4909856427 ps
CPU time 15.15 seconds
Started Aug 16 05:55:43 PM PDT 24
Finished Aug 16 05:55:59 PM PDT 24
Peak memory 240872 kb
Host smart-59107b6f-e49d-44da-b070-66518ea0d930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009077890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.4009077890
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2173518923
Short name T236
Test name
Test status
Simulation time 15903396632 ps
CPU time 85.26 seconds
Started Aug 16 05:55:20 PM PDT 24
Finished Aug 16 05:56:46 PM PDT 24
Peak memory 253916 kb
Host smart-ed27bf25-8527-4a07-be59-f7caa5dffead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173518923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2173518923
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1365186710
Short name T200
Test name
Test status
Simulation time 1138369150 ps
CPU time 5.55 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:55:59 PM PDT 24
Peak memory 232856 kb
Host smart-63011f39-6135-45ab-9e1a-288080381b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365186710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1365186710
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3664340196
Short name T855
Test name
Test status
Simulation time 773226372 ps
CPU time 7.78 seconds
Started Aug 16 05:55:52 PM PDT 24
Finished Aug 16 05:56:00 PM PDT 24
Peak memory 232892 kb
Host smart-fbdb4253-80a0-48c4-a6a3-a2f624ebbd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664340196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3664340196
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2833875672
Short name T578
Test name
Test status
Simulation time 153269626 ps
CPU time 2.56 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:55:49 PM PDT 24
Peak memory 232440 kb
Host smart-bd9beebd-b128-4258-a013-1279573438b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833875672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2833875672
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4277564687
Short name T605
Test name
Test status
Simulation time 26638451978 ps
CPU time 16.37 seconds
Started Aug 16 05:55:21 PM PDT 24
Finished Aug 16 05:55:37 PM PDT 24
Peak memory 224708 kb
Host smart-16aec3fd-c6ad-47c4-8a9f-65f897bd29bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277564687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4277564687
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.284235544
Short name T884
Test name
Test status
Simulation time 1957378341 ps
CPU time 3.1 seconds
Started Aug 16 05:55:22 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 218984 kb
Host smart-71b2fa72-7612-46eb-adab-dbf87fda4090
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=284235544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.284235544
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4225119514
Short name T743
Test name
Test status
Simulation time 2116008212 ps
CPU time 15.36 seconds
Started Aug 16 05:55:20 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 216528 kb
Host smart-af264721-97d6-49ea-903d-84136d4e6c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225119514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4225119514
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.138452648
Short name T756
Test name
Test status
Simulation time 2266000445 ps
CPU time 12.01 seconds
Started Aug 16 05:55:56 PM PDT 24
Finished Aug 16 05:56:08 PM PDT 24
Peak memory 216564 kb
Host smart-43082e42-a88f-4c8f-bec9-d76f65e388a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138452648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.138452648
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2546794784
Short name T497
Test name
Test status
Simulation time 228438303 ps
CPU time 1.58 seconds
Started Aug 16 05:55:21 PM PDT 24
Finished Aug 16 05:55:23 PM PDT 24
Peak memory 216496 kb
Host smart-4be0c413-960c-42b5-8e91-fa253ccde423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546794784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2546794784
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.30134455
Short name T709
Test name
Test status
Simulation time 48031899 ps
CPU time 0.72 seconds
Started Aug 16 05:55:50 PM PDT 24
Finished Aug 16 05:55:51 PM PDT 24
Peak memory 206124 kb
Host smart-dc3d6b13-7cb4-4193-9a25-a136e3eb49e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30134455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.30134455
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1383704092
Short name T830
Test name
Test status
Simulation time 11217118855 ps
CPU time 35.11 seconds
Started Aug 16 05:55:20 PM PDT 24
Finished Aug 16 05:55:56 PM PDT 24
Peak memory 234288 kb
Host smart-e2cff5c4-5c15-4cca-a86f-1f803e6ecd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383704092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1383704092
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3823802700
Short name T548
Test name
Test status
Simulation time 300747330 ps
CPU time 0.75 seconds
Started Aug 16 05:55:52 PM PDT 24
Finished Aug 16 05:55:53 PM PDT 24
Peak memory 205532 kb
Host smart-3e850f24-eda0-471b-aa5f-4a14dfea27c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823802700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3823802700
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2565349443
Short name T903
Test name
Test status
Simulation time 408075762 ps
CPU time 3.55 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:55:40 PM PDT 24
Peak memory 224712 kb
Host smart-f83491fc-0e92-46a2-928a-72cc443286a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565349443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2565349443
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3064023680
Short name T867
Test name
Test status
Simulation time 17255462 ps
CPU time 0.76 seconds
Started Aug 16 05:55:48 PM PDT 24
Finished Aug 16 05:55:49 PM PDT 24
Peak memory 206896 kb
Host smart-c269ffcd-a6dd-44af-986a-edf398d5a477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064023680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3064023680
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1552115782
Short name T891
Test name
Test status
Simulation time 1329594717 ps
CPU time 16.4 seconds
Started Aug 16 05:56:21 PM PDT 24
Finished Aug 16 05:56:47 PM PDT 24
Peak memory 249296 kb
Host smart-f9e535e3-f4fb-4dda-bbaf-94f3f1a8115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552115782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1552115782
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.304625146
Short name T139
Test name
Test status
Simulation time 63545461026 ps
CPU time 188.33 seconds
Started Aug 16 05:56:11 PM PDT 24
Finished Aug 16 05:59:20 PM PDT 24
Peak memory 266524 kb
Host smart-a5bed548-5ad5-4ef3-a3a3-d06b41f0d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304625146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.304625146
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3939151788
Short name T773
Test name
Test status
Simulation time 58853558799 ps
CPU time 167.81 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:58:24 PM PDT 24
Peak memory 253776 kb
Host smart-0268b497-66b2-4234-9177-f1fce342f91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939151788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3939151788
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2061779810
Short name T325
Test name
Test status
Simulation time 302566992 ps
CPU time 4.86 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:40 PM PDT 24
Peak memory 232900 kb
Host smart-d8abb043-89ca-4ac6-ba32-4bdbe939ab88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061779810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2061779810
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3471270325
Short name T360
Test name
Test status
Simulation time 293491323 ps
CPU time 3.1 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 232872 kb
Host smart-86f114d4-0485-4145-8077-0a97a54731c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471270325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3471270325
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1822393282
Short name T481
Test name
Test status
Simulation time 5346125930 ps
CPU time 49.05 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 05:56:12 PM PDT 24
Peak memory 257500 kb
Host smart-5829f18d-ef2d-41be-9f39-491057973694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822393282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1822393282
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1167186971
Short name T237
Test name
Test status
Simulation time 5174836550 ps
CPU time 11.15 seconds
Started Aug 16 05:56:05 PM PDT 24
Finished Aug 16 05:56:17 PM PDT 24
Peak memory 224660 kb
Host smart-140e1ad6-6321-4f0d-a81f-39fd43668b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167186971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1167186971
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4125987027
Short name T818
Test name
Test status
Simulation time 1148842178 ps
CPU time 5.11 seconds
Started Aug 16 05:56:01 PM PDT 24
Finished Aug 16 05:56:07 PM PDT 24
Peak memory 232856 kb
Host smart-001e3e05-d9c5-40eb-a5b5-acce64381188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125987027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4125987027
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.281771360
Short name T634
Test name
Test status
Simulation time 8953359505 ps
CPU time 23.32 seconds
Started Aug 16 05:55:59 PM PDT 24
Finished Aug 16 05:56:22 PM PDT 24
Peak memory 222768 kb
Host smart-68f5cfc9-59bb-46fe-964e-d96eb16c6800
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=281771360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.281771360
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4260154100
Short name T190
Test name
Test status
Simulation time 374597745209 ps
CPU time 898.85 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 06:10:22 PM PDT 24
Peak memory 289400 kb
Host smart-d8a353fd-70e3-4f07-8359-bbed2f3a4103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260154100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4260154100
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1854159802
Short name T648
Test name
Test status
Simulation time 259376693 ps
CPU time 4.03 seconds
Started Aug 16 05:56:02 PM PDT 24
Finished Aug 16 05:56:06 PM PDT 24
Peak memory 216508 kb
Host smart-57e629d7-11c2-493c-a3c6-d590b2a61fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854159802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1854159802
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2564262101
Short name T508
Test name
Test status
Simulation time 354848643 ps
CPU time 1.63 seconds
Started Aug 16 05:55:37 PM PDT 24
Finished Aug 16 05:55:39 PM PDT 24
Peak memory 208096 kb
Host smart-f9fc7ebc-1238-479f-ba67-85c7915c6d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564262101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2564262101
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.4193246046
Short name T953
Test name
Test status
Simulation time 97799669 ps
CPU time 1.52 seconds
Started Aug 16 05:55:25 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 216484 kb
Host smart-9e125da1-89e5-41b7-a325-d0c8813c8261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193246046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.4193246046
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2429751282
Short name T806
Test name
Test status
Simulation time 24050007 ps
CPU time 0.79 seconds
Started Aug 16 05:55:48 PM PDT 24
Finished Aug 16 05:55:49 PM PDT 24
Peak memory 206124 kb
Host smart-ceabae61-0ff9-4d84-b534-d581f3e418ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429751282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2429751282
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2923465409
Short name T2
Test name
Test status
Simulation time 4792107373 ps
CPU time 8.03 seconds
Started Aug 16 05:55:47 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 240180 kb
Host smart-1f882a05-0ad9-4d54-a3b6-677cc9429d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923465409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2923465409
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3704287036
Short name T412
Test name
Test status
Simulation time 13083015 ps
CPU time 0.72 seconds
Started Aug 16 05:56:13 PM PDT 24
Finished Aug 16 05:56:14 PM PDT 24
Peak memory 205816 kb
Host smart-841ecbeb-b22f-43c8-ae80-20139f76d9ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704287036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3704287036
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2605586348
Short name T718
Test name
Test status
Simulation time 2455209077 ps
CPU time 4.1 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:56:02 PM PDT 24
Peak memory 224596 kb
Host smart-c4fdac26-8a4b-464d-8eb2-245c6214f444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605586348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2605586348
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2948307868
Short name T431
Test name
Test status
Simulation time 13913385 ps
CPU time 0.72 seconds
Started Aug 16 05:56:11 PM PDT 24
Finished Aug 16 05:56:12 PM PDT 24
Peak memory 205580 kb
Host smart-a339a091-a884-4581-bf58-3667995c41ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948307868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2948307868
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2156306190
Short name T297
Test name
Test status
Simulation time 5680842544 ps
CPU time 38.42 seconds
Started Aug 16 05:55:39 PM PDT 24
Finished Aug 16 05:56:18 PM PDT 24
Peak memory 237300 kb
Host smart-005021c7-915e-45a5-a22e-dfade9fb7ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156306190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2156306190
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1567587330
Short name T302
Test name
Test status
Simulation time 6615594771 ps
CPU time 59.93 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 05:56:23 PM PDT 24
Peak memory 249384 kb
Host smart-32b57d75-f9b1-4b43-8b15-3d64ddbc2fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567587330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1567587330
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1386444921
Short name T615
Test name
Test status
Simulation time 1714226011 ps
CPU time 34.92 seconds
Started Aug 16 05:55:26 PM PDT 24
Finished Aug 16 05:56:01 PM PDT 24
Peak memory 233976 kb
Host smart-60aa63df-f06f-42dc-8122-db711a5e476b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386444921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1386444921
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1844191380
Short name T979
Test name
Test status
Simulation time 9945439871 ps
CPU time 12.77 seconds
Started Aug 16 05:55:39 PM PDT 24
Finished Aug 16 05:55:52 PM PDT 24
Peak memory 232936 kb
Host smart-217e6d6d-635d-4cdc-9c37-dd85126f7908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844191380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1844191380
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1761126839
Short name T243
Test name
Test status
Simulation time 340672690 ps
CPU time 3.35 seconds
Started Aug 16 05:55:25 PM PDT 24
Finished Aug 16 05:55:29 PM PDT 24
Peak memory 224644 kb
Host smart-41056654-9067-4778-b4ae-6acd09c4200d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761126839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1761126839
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2628731812
Short name T222
Test name
Test status
Simulation time 7883981402 ps
CPU time 11.66 seconds
Started Aug 16 05:55:49 PM PDT 24
Finished Aug 16 05:56:01 PM PDT 24
Peak memory 232996 kb
Host smart-23898fc0-b254-4b49-a13d-3d6e3a1cb275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628731812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2628731812
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3672473759
Short name T484
Test name
Test status
Simulation time 327210352 ps
CPU time 4.54 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:29 PM PDT 24
Peak memory 224552 kb
Host smart-ea42b9ab-f47a-4010-88c5-9501ea6c381e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672473759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3672473759
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3230217150
Short name T866
Test name
Test status
Simulation time 2196281775 ps
CPU time 9.35 seconds
Started Aug 16 05:55:25 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 232916 kb
Host smart-45286fdb-ebf8-4f83-94df-2722547f373d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230217150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3230217150
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3857319184
Short name T425
Test name
Test status
Simulation time 443645516 ps
CPU time 8.15 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:55:44 PM PDT 24
Peak memory 222388 kb
Host smart-e1cd8367-ef23-4e62-bf16-9eddb4d85009
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3857319184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3857319184
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4217971232
Short name T663
Test name
Test status
Simulation time 203348677839 ps
CPU time 576.24 seconds
Started Aug 16 05:56:09 PM PDT 24
Finished Aug 16 06:05:46 PM PDT 24
Peak memory 289036 kb
Host smart-7b05e640-eda8-4630-b18e-5880d0ce89ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217971232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4217971232
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1616920798
Short name T349
Test name
Test status
Simulation time 40434793 ps
CPU time 0.71 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 206100 kb
Host smart-bbb876c3-47b3-4efc-8db6-a41ced2cd6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616920798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1616920798
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3476046542
Short name T628
Test name
Test status
Simulation time 334314208 ps
CPU time 1.57 seconds
Started Aug 16 05:55:49 PM PDT 24
Finished Aug 16 05:55:58 PM PDT 24
Peak memory 207520 kb
Host smart-f10bbe4c-7ca9-4d33-b074-450f6d9e7c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476046542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3476046542
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1884712619
Short name T27
Test name
Test status
Simulation time 123555429 ps
CPU time 1.24 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 05:56:10 PM PDT 24
Peak memory 216456 kb
Host smart-6b7b087c-6189-4f26-b289-3ec77ebdf375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884712619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1884712619
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.432762100
Short name T986
Test name
Test status
Simulation time 76954910 ps
CPU time 0.91 seconds
Started Aug 16 05:55:41 PM PDT 24
Finished Aug 16 05:55:42 PM PDT 24
Peak memory 206104 kb
Host smart-469ed100-a7f7-4dca-bcbf-851ea6e5c1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432762100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.432762100
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2502227902
Short name T985
Test name
Test status
Simulation time 4043168925 ps
CPU time 6.3 seconds
Started Aug 16 05:55:41 PM PDT 24
Finished Aug 16 05:55:47 PM PDT 24
Peak memory 224712 kb
Host smart-0d49d4b0-fc21-489c-90a1-d3dbc53e1feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502227902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2502227902
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4067339371
Short name T733
Test name
Test status
Simulation time 36822998 ps
CPU time 0.72 seconds
Started Aug 16 05:55:54 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 205852 kb
Host smart-6e170c83-cf31-4d09-9195-cdfca4171686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067339371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4067339371
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1124379425
Short name T931
Test name
Test status
Simulation time 245403849 ps
CPU time 5.28 seconds
Started Aug 16 05:55:41 PM PDT 24
Finished Aug 16 05:55:47 PM PDT 24
Peak memory 224712 kb
Host smart-93e20a8b-cf12-4abf-a804-a413cff26d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124379425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1124379425
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.391019230
Short name T543
Test name
Test status
Simulation time 251025357 ps
CPU time 0.81 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 05:55:24 PM PDT 24
Peak memory 206576 kb
Host smart-43d4fef8-bf0e-45bc-995f-fcf0cc6b1dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391019230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.391019230
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.109719271
Short name T45
Test name
Test status
Simulation time 42507082954 ps
CPU time 79.71 seconds
Started Aug 16 05:55:39 PM PDT 24
Finished Aug 16 05:56:59 PM PDT 24
Peak memory 254668 kb
Host smart-7064c650-0e33-4410-84a2-b91191440ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109719271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.109719271
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.910643963
Short name T295
Test name
Test status
Simulation time 105479468181 ps
CPU time 222.65 seconds
Started Aug 16 05:56:03 PM PDT 24
Finished Aug 16 05:59:46 PM PDT 24
Peak memory 256904 kb
Host smart-c35ad162-11cd-4a67-9524-6c02d12801f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910643963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.910643963
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1288595998
Short name T1005
Test name
Test status
Simulation time 2759056907 ps
CPU time 26.08 seconds
Started Aug 16 05:55:41 PM PDT 24
Finished Aug 16 05:56:07 PM PDT 24
Peak memory 224460 kb
Host smart-f13145cf-45fd-49ba-af33-45d7daec2c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288595998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1288595998
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2563634765
Short name T319
Test name
Test status
Simulation time 204039193 ps
CPU time 6.67 seconds
Started Aug 16 05:56:13 PM PDT 24
Finished Aug 16 05:56:20 PM PDT 24
Peak memory 224696 kb
Host smart-da52ab03-cc3d-4659-992a-283eaa246295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563634765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2563634765
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2491058886
Short name T845
Test name
Test status
Simulation time 238748123 ps
CPU time 3.44 seconds
Started Aug 16 05:56:01 PM PDT 24
Finished Aug 16 05:56:04 PM PDT 24
Peak memory 232852 kb
Host smart-87596b7d-9c25-427e-ac87-1cb9eb1e76ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491058886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2491058886
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1223928645
Short name T677
Test name
Test status
Simulation time 3579977259 ps
CPU time 48.56 seconds
Started Aug 16 05:55:39 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 232936 kb
Host smart-e56f75b3-6488-416d-9353-3f26e7eec9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223928645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1223928645
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1940781030
Short name T835
Test name
Test status
Simulation time 18111581828 ps
CPU time 17.45 seconds
Started Aug 16 05:56:08 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 224788 kb
Host smart-6f319fcc-dc96-45a4-8e64-940ab566d4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940781030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1940781030
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1212429928
Short name T706
Test name
Test status
Simulation time 683161754 ps
CPU time 6.87 seconds
Started Aug 16 05:55:22 PM PDT 24
Finished Aug 16 05:55:30 PM PDT 24
Peak memory 232896 kb
Host smart-acfafc2f-a11b-45b5-a50b-2dda0434a8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212429928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1212429928
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2893845796
Short name T391
Test name
Test status
Simulation time 338061367 ps
CPU time 5.69 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:55:40 PM PDT 24
Peak memory 220184 kb
Host smart-1eba2a76-2da6-429f-82c3-8a6f819bff01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2893845796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2893845796
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1106892260
Short name T515
Test name
Test status
Simulation time 46091464 ps
CPU time 1.02 seconds
Started Aug 16 05:55:25 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 206756 kb
Host smart-b6f48321-3bd0-49a6-9d29-4ada69aca697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106892260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1106892260
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.482391128
Short name T899
Test name
Test status
Simulation time 11027621762 ps
CPU time 18.89 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 05:55:42 PM PDT 24
Peak memory 216556 kb
Host smart-b071a05d-d00e-40d5-8588-5071f885fd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482391128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.482391128
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.969720067
Short name T684
Test name
Test status
Simulation time 871694271 ps
CPU time 5.39 seconds
Started Aug 16 05:55:37 PM PDT 24
Finished Aug 16 05:55:43 PM PDT 24
Peak memory 216468 kb
Host smart-8980d0b0-5e20-428c-803c-d3bf68ec64bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969720067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.969720067
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2555710353
Short name T409
Test name
Test status
Simulation time 415298582 ps
CPU time 1.92 seconds
Started Aug 16 05:55:26 PM PDT 24
Finished Aug 16 05:55:28 PM PDT 24
Peak memory 216540 kb
Host smart-52f120ba-5e8a-40db-90b7-0bc955f6c956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555710353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2555710353
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.357568873
Short name T493
Test name
Test status
Simulation time 24777650 ps
CPU time 0.75 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 206036 kb
Host smart-7853a79c-1e99-4668-b2ca-ad10de3d8bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357568873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.357568873
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2689033896
Short name T857
Test name
Test status
Simulation time 24820998169 ps
CPU time 16.79 seconds
Started Aug 16 05:56:15 PM PDT 24
Finished Aug 16 05:56:32 PM PDT 24
Peak memory 224680 kb
Host smart-5b348e82-a01e-4194-8703-edc5b7bdbf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689033896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2689033896
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1884896003
Short name T346
Test name
Test status
Simulation time 13208297 ps
CPU time 0.67 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:55:42 PM PDT 24
Peak memory 205540 kb
Host smart-456e108b-3f2f-4df1-bbf8-3f05c114d907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884896003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1884896003
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.4019615448
Short name T638
Test name
Test status
Simulation time 349730841 ps
CPU time 5.08 seconds
Started Aug 16 05:56:12 PM PDT 24
Finished Aug 16 05:56:17 PM PDT 24
Peak memory 224628 kb
Host smart-41c1d055-555d-4672-9c42-8afdce678ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019615448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4019615448
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.835217738
Short name T568
Test name
Test status
Simulation time 28188047 ps
CPU time 0.74 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:25 PM PDT 24
Peak memory 205516 kb
Host smart-d153b9c9-2a4a-451a-8ebe-e9e68417a12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835217738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.835217738
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2812307184
Short name T657
Test name
Test status
Simulation time 12895974173 ps
CPU time 57.79 seconds
Started Aug 16 05:55:40 PM PDT 24
Finished Aug 16 05:56:38 PM PDT 24
Peak memory 249440 kb
Host smart-5ca345b1-fd15-406d-8916-988a1eefeac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812307184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2812307184
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.135449105
Short name T327
Test name
Test status
Simulation time 1313465871 ps
CPU time 8.37 seconds
Started Aug 16 05:55:51 PM PDT 24
Finished Aug 16 05:56:00 PM PDT 24
Peak memory 217644 kb
Host smart-28156d95-cbbf-449c-a305-bb3a97b54a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135449105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.135449105
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1868910155
Short name T910
Test name
Test status
Simulation time 1643299259 ps
CPU time 17.7 seconds
Started Aug 16 05:55:46 PM PDT 24
Finished Aug 16 05:56:04 PM PDT 24
Peak memory 240160 kb
Host smart-2cab3fd6-5136-4e6e-b565-5632aff302b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868910155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1868910155
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.431711297
Short name T91
Test name
Test status
Simulation time 11568973004 ps
CPU time 80.03 seconds
Started Aug 16 05:56:19 PM PDT 24
Finished Aug 16 05:57:40 PM PDT 24
Peak memory 250616 kb
Host smart-3a574006-5617-4730-8c0b-aae69b9e7543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431711297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.431711297
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.146219475
Short name T841
Test name
Test status
Simulation time 891944542 ps
CPU time 10.62 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:55:53 PM PDT 24
Peak memory 232840 kb
Host smart-2285d1b2-a6ed-44a9-bc25-de26c5b469f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146219475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.146219475
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1855206703
Short name T651
Test name
Test status
Simulation time 74889231911 ps
CPU time 128.4 seconds
Started Aug 16 05:55:40 PM PDT 24
Finished Aug 16 05:57:48 PM PDT 24
Peak memory 249308 kb
Host smart-b53debe0-ed8d-4e74-a9a8-f640fc60be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855206703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1855206703
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.911610434
Short name T660
Test name
Test status
Simulation time 9365800825 ps
CPU time 7.51 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:55:53 PM PDT 24
Peak memory 224668 kb
Host smart-221fc27f-d3d1-4fce-bb46-f9030d4899f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911610434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.911610434
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.206058077
Short name T869
Test name
Test status
Simulation time 1515702507 ps
CPU time 2.6 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:55:59 PM PDT 24
Peak memory 224628 kb
Host smart-de312195-f39d-445b-9445-7aaf8649839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206058077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.206058077
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1211876777
Short name T519
Test name
Test status
Simulation time 1398555501 ps
CPU time 7.05 seconds
Started Aug 16 05:55:41 PM PDT 24
Finished Aug 16 05:55:48 PM PDT 24
Peak memory 219068 kb
Host smart-160f48a5-6b0c-41f6-94df-6a4d408800c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1211876777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1211876777
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3108219185
Short name T919
Test name
Test status
Simulation time 1355946914 ps
CPU time 19.62 seconds
Started Aug 16 05:56:03 PM PDT 24
Finished Aug 16 05:56:23 PM PDT 24
Peak memory 216724 kb
Host smart-0155f5a2-5fa9-4d9d-85de-90a86e4696f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108219185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3108219185
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1692366044
Short name T487
Test name
Test status
Simulation time 3793114142 ps
CPU time 13.63 seconds
Started Aug 16 05:56:11 PM PDT 24
Finished Aug 16 05:56:25 PM PDT 24
Peak memory 216576 kb
Host smart-60138244-0951-4c03-a649-3b0447d8549e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692366044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1692366044
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3832682672
Short name T825
Test name
Test status
Simulation time 166416140 ps
CPU time 2.02 seconds
Started Aug 16 05:55:47 PM PDT 24
Finished Aug 16 05:55:49 PM PDT 24
Peak memory 216504 kb
Host smart-3d83d906-44c4-4a54-b6e5-ac0f05515965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832682672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3832682672
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3023611503
Short name T715
Test name
Test status
Simulation time 23465561 ps
CPU time 0.72 seconds
Started Aug 16 05:55:56 PM PDT 24
Finished Aug 16 05:55:56 PM PDT 24
Peak memory 206080 kb
Host smart-a708f7c9-caf4-4d5f-a6c5-f70e4374fc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023611503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3023611503
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.934960050
Short name T847
Test name
Test status
Simulation time 4483776599 ps
CPU time 14.14 seconds
Started Aug 16 05:56:19 PM PDT 24
Finished Aug 16 05:56:33 PM PDT 24
Peak memory 224756 kb
Host smart-960f3fe8-1479-43ac-99ef-8333ff0a8840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934960050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.934960050
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3265957121
Short name T726
Test name
Test status
Simulation time 15817719 ps
CPU time 0.74 seconds
Started Aug 16 05:55:46 PM PDT 24
Finished Aug 16 05:55:46 PM PDT 24
Peak memory 205732 kb
Host smart-6cff1612-10c3-45fd-81c6-890a7318af35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265957121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3265957121
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1840675446
Short name T189
Test name
Test status
Simulation time 145391532 ps
CPU time 3.37 seconds
Started Aug 16 05:55:37 PM PDT 24
Finished Aug 16 05:55:41 PM PDT 24
Peak memory 224724 kb
Host smart-c5966e9b-3a94-46b3-946c-dcb0748a3bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840675446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1840675446
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3794935611
Short name T810
Test name
Test status
Simulation time 40908609 ps
CPU time 0.73 seconds
Started Aug 16 05:55:26 PM PDT 24
Finished Aug 16 05:55:27 PM PDT 24
Peak memory 205588 kb
Host smart-6b7b17ee-38cf-4881-b419-12eb0338c4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794935611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3794935611
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3577450365
Short name T551
Test name
Test status
Simulation time 27122621319 ps
CPU time 108.64 seconds
Started Aug 16 05:56:04 PM PDT 24
Finished Aug 16 05:57:53 PM PDT 24
Peak memory 249376 kb
Host smart-d118b136-72de-48da-a8b0-8318d4bf9e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577450365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3577450365
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2208546991
Short name T242
Test name
Test status
Simulation time 8486378324 ps
CPU time 86.99 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:57:12 PM PDT 24
Peak memory 254444 kb
Host smart-02a114e5-a5ea-4404-9fe4-0dd7dfdf6acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208546991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2208546991
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1612062163
Short name T882
Test name
Test status
Simulation time 3186179832 ps
CPU time 79.8 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 05:57:18 PM PDT 24
Peak memory 256176 kb
Host smart-4b5a2657-3ff0-440c-9ef6-6bfbdca991f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612062163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1612062163
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2455157653
Short name T38
Test name
Test status
Simulation time 480911707 ps
CPU time 9.28 seconds
Started Aug 16 05:55:49 PM PDT 24
Finished Aug 16 05:56:04 PM PDT 24
Peak memory 224008 kb
Host smart-5041e1a8-d934-4e5a-a654-12bf9d7a2904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455157653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2455157653
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3455254098
Short name T296
Test name
Test status
Simulation time 71635195295 ps
CPU time 463.14 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 06:03:28 PM PDT 24
Peak memory 267792 kb
Host smart-7c7c5b97-940e-4e44-bda1-7c6cebed4bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455254098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3455254098
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3659860691
Short name T695
Test name
Test status
Simulation time 34522141 ps
CPU time 2.37 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 232868 kb
Host smart-ca9f5ede-50eb-48b8-a1c0-8b430fa72ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659860691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3659860691
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1016723013
Short name T850
Test name
Test status
Simulation time 47911882265 ps
CPU time 97.62 seconds
Started Aug 16 05:56:37 PM PDT 24
Finished Aug 16 05:58:14 PM PDT 24
Peak memory 234740 kb
Host smart-2a0c69e3-d39f-4e5b-afe7-e2c0e830ea32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016723013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1016723013
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1136963080
Short name T742
Test name
Test status
Simulation time 1728880537 ps
CPU time 3.19 seconds
Started Aug 16 05:56:15 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 224476 kb
Host smart-4ee0b76a-0e22-4589-a6a1-8998b473e620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136963080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1136963080
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1647540175
Short name T849
Test name
Test status
Simulation time 1422074812 ps
CPU time 8.25 seconds
Started Aug 16 05:55:25 PM PDT 24
Finished Aug 16 05:55:34 PM PDT 24
Peak memory 232872 kb
Host smart-eb671e9f-e38a-4d8f-ac2f-ac149c282076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647540175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1647540175
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3001168710
Short name T618
Test name
Test status
Simulation time 523656078 ps
CPU time 9.3 seconds
Started Aug 16 05:55:30 PM PDT 24
Finished Aug 16 05:55:40 PM PDT 24
Peak memory 222152 kb
Host smart-1f4cdc19-4626-4f58-938a-b1294c26983d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3001168710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3001168710
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2460801209
Short name T975
Test name
Test status
Simulation time 2437932304 ps
CPU time 28.88 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:56:04 PM PDT 24
Peak memory 216780 kb
Host smart-e5fe3e1a-dc7e-473f-a1b1-5bc997d8243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460801209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2460801209
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3546908194
Short name T478
Test name
Test status
Simulation time 1784224852 ps
CPU time 5.29 seconds
Started Aug 16 05:55:26 PM PDT 24
Finished Aug 16 05:55:31 PM PDT 24
Peak memory 216500 kb
Host smart-c5b471f9-1f51-4c91-bfca-0de4fcf6d389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546908194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3546908194
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1398073194
Short name T840
Test name
Test status
Simulation time 63038148 ps
CPU time 0.98 seconds
Started Aug 16 05:55:38 PM PDT 24
Finished Aug 16 05:55:40 PM PDT 24
Peak memory 207276 kb
Host smart-2b6b2b6d-2d3f-4303-9392-ed6ff4f75b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398073194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1398073194
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.693951418
Short name T871
Test name
Test status
Simulation time 525523697 ps
CPU time 0.86 seconds
Started Aug 16 05:55:43 PM PDT 24
Finished Aug 16 05:55:44 PM PDT 24
Peak memory 206116 kb
Host smart-236d29f0-2a20-4263-a47e-f049af00f7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693951418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.693951418
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2698353882
Short name T7
Test name
Test status
Simulation time 8756796472 ps
CPU time 10.64 seconds
Started Aug 16 05:55:31 PM PDT 24
Finished Aug 16 05:55:42 PM PDT 24
Peak memory 232968 kb
Host smart-95d865f4-231e-42f1-9726-d93f98756b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698353882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2698353882
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3136491184
Short name T401
Test name
Test status
Simulation time 22275444 ps
CPU time 0.73 seconds
Started Aug 16 05:55:46 PM PDT 24
Finished Aug 16 05:55:47 PM PDT 24
Peak memory 204944 kb
Host smart-0ffe78b3-40f6-41cf-bffe-14b82f484d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136491184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3136491184
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1561674510
Short name T383
Test name
Test status
Simulation time 2129141817 ps
CPU time 24.68 seconds
Started Aug 16 05:56:08 PM PDT 24
Finished Aug 16 05:56:33 PM PDT 24
Peak memory 224708 kb
Host smart-71656d57-e164-456f-ba35-1a9aa3fda3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561674510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1561674510
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3834273198
Short name T371
Test name
Test status
Simulation time 15064060 ps
CPU time 0.76 seconds
Started Aug 16 05:56:02 PM PDT 24
Finished Aug 16 05:56:02 PM PDT 24
Peak memory 206616 kb
Host smart-354cc667-19b2-4fb2-b0a5-41b7bccddc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834273198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3834273198
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2001918772
Short name T269
Test name
Test status
Simulation time 11263115621 ps
CPU time 82.08 seconds
Started Aug 16 05:56:04 PM PDT 24
Finished Aug 16 05:57:26 PM PDT 24
Peak memory 241112 kb
Host smart-cc666609-9812-414e-bb60-de2ba70eb009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001918772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2001918772
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2765594730
Short name T772
Test name
Test status
Simulation time 43196482431 ps
CPU time 235.27 seconds
Started Aug 16 05:55:48 PM PDT 24
Finished Aug 16 05:59:44 PM PDT 24
Peak memory 255104 kb
Host smart-7830b943-7c64-4b67-b97e-ccf0d4c08382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765594730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2765594730
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.799846955
Short name T667
Test name
Test status
Simulation time 6315572448 ps
CPU time 32.9 seconds
Started Aug 16 05:55:51 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 224772 kb
Host smart-bf57ad5b-8ca2-447e-9037-56595ef069bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799846955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.799846955
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1962227151
Short name T923
Test name
Test status
Simulation time 3856426901 ps
CPU time 51.17 seconds
Started Aug 16 05:56:13 PM PDT 24
Finished Aug 16 05:57:05 PM PDT 24
Peak memory 249368 kb
Host smart-3e9d1771-f4f1-454b-986a-20800e470c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962227151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1962227151
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3785593201
Short name T73
Test name
Test status
Simulation time 6696120840 ps
CPU time 86.49 seconds
Started Aug 16 05:56:12 PM PDT 24
Finished Aug 16 05:57:39 PM PDT 24
Peak memory 250800 kb
Host smart-04112fd2-317f-48c1-9207-7fd02f000c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785593201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3785593201
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3840476229
Short name T775
Test name
Test status
Simulation time 510725621 ps
CPU time 8.42 seconds
Started Aug 16 05:56:17 PM PDT 24
Finished Aug 16 05:56:25 PM PDT 24
Peak memory 224644 kb
Host smart-f59b9cfe-1e6f-43b7-9a2e-d834d0e06fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840476229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3840476229
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2830236990
Short name T505
Test name
Test status
Simulation time 101283172 ps
CPU time 2.44 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:56:00 PM PDT 24
Peak memory 232920 kb
Host smart-d934da0f-e1ae-4d59-80b8-064919ab576a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830236990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2830236990
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3846299452
Short name T271
Test name
Test status
Simulation time 1084372937 ps
CPU time 4.85 seconds
Started Aug 16 05:56:02 PM PDT 24
Finished Aug 16 05:56:07 PM PDT 24
Peak memory 224660 kb
Host smart-d34d3971-f1fc-4883-acbc-1cc2b196e85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846299452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3846299452
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1681916307
Short name T608
Test name
Test status
Simulation time 16809785391 ps
CPU time 26.74 seconds
Started Aug 16 05:55:46 PM PDT 24
Finished Aug 16 05:56:12 PM PDT 24
Peak memory 250016 kb
Host smart-7688ead5-fb7d-41dd-8937-b83fa5b84c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681916307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1681916307
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4175040864
Short name T675
Test name
Test status
Simulation time 1018676718 ps
CPU time 9.79 seconds
Started Aug 16 05:56:14 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 222380 kb
Host smart-164ee05e-c02d-4a62-9f42-53e76312e501
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4175040864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4175040864
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2942682381
Short name T161
Test name
Test status
Simulation time 108544564205 ps
CPU time 228.6 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:59:34 PM PDT 24
Peak memory 249564 kb
Host smart-ca313889-021b-4978-bb56-ae43b9c32561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942682381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2942682381
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1679063910
Short name T520
Test name
Test status
Simulation time 38383920299 ps
CPU time 22.75 seconds
Started Aug 16 05:55:39 PM PDT 24
Finished Aug 16 05:56:02 PM PDT 24
Peak memory 216600 kb
Host smart-8b115a47-7b01-4d27-8912-674bd3f8f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679063910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1679063910
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3296115044
Short name T964
Test name
Test status
Simulation time 144443983 ps
CPU time 1.75 seconds
Started Aug 16 05:56:31 PM PDT 24
Finished Aug 16 05:56:33 PM PDT 24
Peak memory 208112 kb
Host smart-5bc6399c-c49f-49fe-8a1e-98f91cb3135f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296115044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3296115044
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3971682993
Short name T557
Test name
Test status
Simulation time 149903011 ps
CPU time 2.13 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:27 PM PDT 24
Peak memory 216452 kb
Host smart-75783abd-39d8-4993-bdd9-379ae9b901bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971682993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3971682993
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2577990092
Short name T678
Test name
Test status
Simulation time 54652267 ps
CPU time 0.88 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:25 PM PDT 24
Peak memory 206084 kb
Host smart-ba561e76-9649-47a7-8235-04c9f9cadc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577990092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2577990092
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.852263082
Short name T872
Test name
Test status
Simulation time 9676768020 ps
CPU time 20.67 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:45 PM PDT 24
Peak memory 233944 kb
Host smart-48029d13-b1ee-4b3a-9b06-f8ed2e639dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852263082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.852263082
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2577108641
Short name T635
Test name
Test status
Simulation time 17358953 ps
CPU time 0.72 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:55:46 PM PDT 24
Peak memory 204948 kb
Host smart-d5a5c676-0e6c-481b-a4bf-a0222ba559b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577108641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2577108641
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3802458403
Short name T188
Test name
Test status
Simulation time 549468532 ps
CPU time 4.29 seconds
Started Aug 16 05:56:22 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 232700 kb
Host smart-ef2cc593-44cd-4c80-97c6-1ecb1dd04453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802458403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3802458403
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4022794747
Short name T488
Test name
Test status
Simulation time 16164056 ps
CPU time 0.76 seconds
Started Aug 16 05:56:21 PM PDT 24
Finished Aug 16 05:56:27 PM PDT 24
Peak memory 205592 kb
Host smart-5bd8ac95-3684-462d-a323-e8d51c309f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022794747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4022794747
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2646701534
Short name T168
Test name
Test status
Simulation time 44141397602 ps
CPU time 160.53 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:58:23 PM PDT 24
Peak memory 264048 kb
Host smart-de8c3591-c1ab-4473-8eba-d8a81abc234c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646701534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2646701534
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1121363504
Short name T752
Test name
Test status
Simulation time 17350633513 ps
CPU time 96.26 seconds
Started Aug 16 05:56:14 PM PDT 24
Finished Aug 16 05:57:50 PM PDT 24
Peak memory 253704 kb
Host smart-f73e82b3-f867-4af8-8a4e-3bf804f34047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121363504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1121363504
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2927086616
Short name T441
Test name
Test status
Simulation time 93663388346 ps
CPU time 183.27 seconds
Started Aug 16 05:55:37 PM PDT 24
Finished Aug 16 05:58:41 PM PDT 24
Peak memory 249416 kb
Host smart-c8f11f9f-3d07-4c6f-b5b8-35fe7b400921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927086616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2927086616
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3303781135
Short name T75
Test name
Test status
Simulation time 8532695564 ps
CPU time 124.87 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:57:50 PM PDT 24
Peak memory 251564 kb
Host smart-d48494a0-0ce6-465b-aa47-3bc1c7e2fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303781135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3303781135
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1636754637
Short name T573
Test name
Test status
Simulation time 23373213900 ps
CPU time 157.48 seconds
Started Aug 16 05:55:44 PM PDT 24
Finished Aug 16 05:58:21 PM PDT 24
Peak memory 249644 kb
Host smart-ff21c1db-cdb1-46b8-a71a-917d9e92e5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636754637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1636754637
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.521207881
Short name T254
Test name
Test status
Simulation time 2171537559 ps
CPU time 12.26 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:55:57 PM PDT 24
Peak memory 224712 kb
Host smart-e3150c35-78f2-4481-a7da-33e8a03acb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521207881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.521207881
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3443502712
Short name T704
Test name
Test status
Simulation time 9204815443 ps
CPU time 58.35 seconds
Started Aug 16 05:56:26 PM PDT 24
Finished Aug 16 05:57:25 PM PDT 24
Peak memory 232820 kb
Host smart-2b930ead-f790-4ce7-bf8f-86dc18b8044a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443502712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3443502712
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3053046641
Short name T745
Test name
Test status
Simulation time 559378514 ps
CPU time 3.97 seconds
Started Aug 16 05:55:44 PM PDT 24
Finished Aug 16 05:55:48 PM PDT 24
Peak memory 232912 kb
Host smart-47d71e8f-35bf-462c-962d-8236e8dcdb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053046641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3053046641
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2955443154
Short name T411
Test name
Test status
Simulation time 1148757933 ps
CPU time 4.43 seconds
Started Aug 16 05:56:25 PM PDT 24
Finished Aug 16 05:56:29 PM PDT 24
Peak memory 232860 kb
Host smart-69ab7df0-42cd-4c02-bab0-3f6a548f6af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955443154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2955443154
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3423806051
Short name T865
Test name
Test status
Simulation time 344597661 ps
CPU time 3.99 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:55:46 PM PDT 24
Peak memory 219420 kb
Host smart-127378da-b174-4b76-9e1f-55158a8cc524
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3423806051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3423806051
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1550041479
Short name T707
Test name
Test status
Simulation time 25067173405 ps
CPU time 207.7 seconds
Started Aug 16 05:56:19 PM PDT 24
Finished Aug 16 05:59:47 PM PDT 24
Peak memory 267956 kb
Host smart-ec07fdcd-f322-4831-ba08-a3a27dd6eff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550041479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1550041479
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2855449413
Short name T8
Test name
Test status
Simulation time 13287715882 ps
CPU time 31.83 seconds
Started Aug 16 05:56:18 PM PDT 24
Finished Aug 16 05:56:50 PM PDT 24
Peak memory 216628 kb
Host smart-740b1b87-6e14-4f56-9aef-50045ee19d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855449413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2855449413
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3269323702
Short name T1022
Test name
Test status
Simulation time 1051395650 ps
CPU time 2.83 seconds
Started Aug 16 05:56:14 PM PDT 24
Finished Aug 16 05:56:17 PM PDT 24
Peak memory 216344 kb
Host smart-77e628cd-fc24-428c-9d81-5d1a52f38197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269323702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3269323702
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.981577355
Short name T876
Test name
Test status
Simulation time 65884830 ps
CPU time 0.87 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:55:46 PM PDT 24
Peak memory 206552 kb
Host smart-9dce41bd-fc9e-44ab-b1c2-0728fdb6af0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981577355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.981577355
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1952571453
Short name T694
Test name
Test status
Simulation time 57048552 ps
CPU time 0.91 seconds
Started Aug 16 05:56:16 PM PDT 24
Finished Aug 16 05:56:17 PM PDT 24
Peak memory 207160 kb
Host smart-09f18755-9211-45dd-90b4-2c537de9fa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952571453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1952571453
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2939511100
Short name T537
Test name
Test status
Simulation time 6503357322 ps
CPU time 16.57 seconds
Started Aug 16 05:55:48 PM PDT 24
Finished Aug 16 05:56:05 PM PDT 24
Peak memory 224708 kb
Host smart-1acb3fc9-e261-4da4-95cd-62d8987443ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939511100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2939511100
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.534431046
Short name T450
Test name
Test status
Simulation time 16423427 ps
CPU time 0.68 seconds
Started Aug 16 05:56:27 PM PDT 24
Finished Aug 16 05:56:33 PM PDT 24
Peak memory 205472 kb
Host smart-71238af6-063a-4da9-8420-622bb6c0f5d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534431046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.534431046
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2359259054
Short name T1031
Test name
Test status
Simulation time 541561619 ps
CPU time 7.23 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:55:50 PM PDT 24
Peak memory 224700 kb
Host smart-a3495e47-1360-4c21-aaee-20deb9a5e246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359259054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2359259054
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1756480675
Short name T702
Test name
Test status
Simulation time 21274983 ps
CPU time 0.77 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:55:46 PM PDT 24
Peak memory 206604 kb
Host smart-8b642237-0ea6-4296-b4c4-83ee42acc889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756480675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1756480675
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2981148896
Short name T972
Test name
Test status
Simulation time 31209552162 ps
CPU time 53.59 seconds
Started Aug 16 05:56:19 PM PDT 24
Finished Aug 16 05:57:12 PM PDT 24
Peak memory 249360 kb
Host smart-58b2ba7b-71f4-4650-92ab-38938c73e346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981148896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2981148896
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2779162594
Short name T373
Test name
Test status
Simulation time 1432233075 ps
CPU time 21.49 seconds
Started Aug 16 05:55:46 PM PDT 24
Finished Aug 16 05:56:08 PM PDT 24
Peak memory 238904 kb
Host smart-5e5c2967-7c4a-45f7-8d94-c1362093c26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779162594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2779162594
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1707574688
Short name T363
Test name
Test status
Simulation time 977165954 ps
CPU time 2.77 seconds
Started Aug 16 05:56:12 PM PDT 24
Finished Aug 16 05:56:15 PM PDT 24
Peak memory 217784 kb
Host smart-c5df2ab3-8d1a-46c7-b558-c89e07e58663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707574688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1707574688
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.436181587
Short name T323
Test name
Test status
Simulation time 558576117 ps
CPU time 6.93 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:55:52 PM PDT 24
Peak memory 224732 kb
Host smart-d406fe6b-d407-44a0-9258-5afe020baf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436181587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.436181587
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3664500434
Short name T206
Test name
Test status
Simulation time 5159778077 ps
CPU time 91.71 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:57:17 PM PDT 24
Peak memory 254540 kb
Host smart-9dbe0859-4156-43c4-b7e8-d1ef0baeeaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664500434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3664500434
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.391030239
Short name T512
Test name
Test status
Simulation time 102599707 ps
CPU time 2.5 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:55:48 PM PDT 24
Peak memory 232428 kb
Host smart-b52e70b9-b8ba-42b9-9f5d-081e022acb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391030239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.391030239
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3619448228
Short name T251
Test name
Test status
Simulation time 989142041 ps
CPU time 14.69 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:56:00 PM PDT 24
Peak memory 249204 kb
Host smart-35bfe95d-1c06-4bbd-b44b-4b99aaaa640f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619448228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3619448228
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.495085729
Short name T228
Test name
Test status
Simulation time 3056957868 ps
CPU time 14.47 seconds
Started Aug 16 05:56:21 PM PDT 24
Finished Aug 16 05:56:36 PM PDT 24
Peak memory 241144 kb
Host smart-8f240da4-553d-4c34-8fa7-d59ec6a1f9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495085729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.495085729
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4275946342
Short name T482
Test name
Test status
Simulation time 5969876903 ps
CPU time 6.3 seconds
Started Aug 16 05:55:41 PM PDT 24
Finished Aug 16 05:55:47 PM PDT 24
Peak memory 224688 kb
Host smart-706e462b-1117-43c0-adc9-70c86623a31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275946342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4275946342
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3992245517
Short name T639
Test name
Test status
Simulation time 861508517 ps
CPU time 8.53 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:55:51 PM PDT 24
Peak memory 222392 kb
Host smart-57d0f2e0-a1a0-4dad-a709-8e39862ad60c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3992245517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3992245517
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1869107761
Short name T16
Test name
Test status
Simulation time 170440967 ps
CPU time 0.98 seconds
Started Aug 16 05:56:03 PM PDT 24
Finished Aug 16 05:56:04 PM PDT 24
Peak memory 207000 kb
Host smart-27a180c6-efaf-4914-9601-048c02c1cd9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869107761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1869107761
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3747200461
Short name T438
Test name
Test status
Simulation time 2664706913 ps
CPU time 18.74 seconds
Started Aug 16 05:55:52 PM PDT 24
Finished Aug 16 05:56:11 PM PDT 24
Peak memory 216496 kb
Host smart-d0378bed-fe52-49fb-8c0f-6c8c79c519d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747200461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3747200461
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2835880892
Short name T555
Test name
Test status
Simulation time 24359620728 ps
CPU time 19.65 seconds
Started Aug 16 05:56:04 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 216444 kb
Host smart-28f926ae-dd26-4284-ad24-cb0a560e9f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835880892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2835880892
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3736789309
Short name T722
Test name
Test status
Simulation time 171732920 ps
CPU time 1.52 seconds
Started Aug 16 05:55:40 PM PDT 24
Finished Aug 16 05:55:41 PM PDT 24
Peak memory 216320 kb
Host smart-2a718d6c-a175-4ef2-97dc-783a13d826e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736789309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3736789309
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.4111058086
Short name T22
Test name
Test status
Simulation time 318784348 ps
CPU time 1 seconds
Started Aug 16 05:56:09 PM PDT 24
Finished Aug 16 05:56:10 PM PDT 24
Peak memory 207064 kb
Host smart-2e00dd71-92b7-49d6-9de5-c24fd20d3fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111058086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.4111058086
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1948539097
Short name T226
Test name
Test status
Simulation time 2399649394 ps
CPU time 14.23 seconds
Started Aug 16 05:55:50 PM PDT 24
Finished Aug 16 05:56:04 PM PDT 24
Peak memory 240984 kb
Host smart-7adc5682-d371-47a0-bbf0-877b3d671c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948539097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1948539097
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1249058812
Short name T603
Test name
Test status
Simulation time 41435585 ps
CPU time 0.7 seconds
Started Aug 16 05:55:05 PM PDT 24
Finished Aug 16 05:55:06 PM PDT 24
Peak memory 205532 kb
Host smart-f76f3b5c-2afd-4f9c-8f1d-08c2be0bfb91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249058812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
249058812
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2221735650
Short name T691
Test name
Test status
Simulation time 6533585334 ps
CPU time 17.8 seconds
Started Aug 16 05:55:21 PM PDT 24
Finished Aug 16 05:55:39 PM PDT 24
Peak memory 224676 kb
Host smart-c38942fa-e4cb-433c-9159-4ca38bee55eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221735650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2221735650
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1855064847
Short name T990
Test name
Test status
Simulation time 25151401 ps
CPU time 0.74 seconds
Started Aug 16 05:54:57 PM PDT 24
Finished Aug 16 05:54:57 PM PDT 24
Peak memory 205544 kb
Host smart-c4a625a8-40d0-4dd3-b22e-aa042c2fdf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855064847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1855064847
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3916738009
Short name T248
Test name
Test status
Simulation time 151537644978 ps
CPU time 201.7 seconds
Started Aug 16 05:54:29 PM PDT 24
Finished Aug 16 05:57:51 PM PDT 24
Peak memory 256872 kb
Host smart-f902c7ea-971b-4c6d-9176-f043609a10e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916738009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3916738009
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.4282409033
Short name T741
Test name
Test status
Simulation time 1881841947 ps
CPU time 27.23 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:55:32 PM PDT 24
Peak memory 239956 kb
Host smart-3b8c9e69-2675-4d76-8caf-302661210912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282409033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.4282409033
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3029576946
Short name T936
Test name
Test status
Simulation time 3913904929 ps
CPU time 25.8 seconds
Started Aug 16 05:54:57 PM PDT 24
Finished Aug 16 05:55:23 PM PDT 24
Peak memory 224756 kb
Host smart-86465806-a6d5-45f0-bb03-6e3d64e34c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029576946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3029576946
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3883906926
Short name T541
Test name
Test status
Simulation time 180874309 ps
CPU time 4.78 seconds
Started Aug 16 05:54:27 PM PDT 24
Finished Aug 16 05:54:32 PM PDT 24
Peak memory 234164 kb
Host smart-e18acda1-00e5-4e0d-b424-a0672e2be9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883906926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3883906926
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2852917140
Short name T233
Test name
Test status
Simulation time 7504072682 ps
CPU time 22.77 seconds
Started Aug 16 05:54:32 PM PDT 24
Finished Aug 16 05:54:55 PM PDT 24
Peak memory 232940 kb
Host smart-c0431fa9-0259-4ffc-8536-4a3fdfac9baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852917140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2852917140
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3959164188
Short name T461
Test name
Test status
Simulation time 4317295780 ps
CPU time 15.48 seconds
Started Aug 16 05:54:32 PM PDT 24
Finished Aug 16 05:54:52 PM PDT 24
Peak memory 224708 kb
Host smart-546e4598-f656-46a8-be42-bc4991b5dbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959164188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3959164188
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3627061926
Short name T724
Test name
Test status
Simulation time 32433227 ps
CPU time 1.04 seconds
Started Aug 16 05:54:45 PM PDT 24
Finished Aug 16 05:54:47 PM PDT 24
Peak memory 216696 kb
Host smart-82f9878c-dc45-449a-adbb-20141614b6ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627061926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3627061926
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2912751259
Short name T287
Test name
Test status
Simulation time 1523037413 ps
CPU time 4.39 seconds
Started Aug 16 05:54:50 PM PDT 24
Finished Aug 16 05:54:55 PM PDT 24
Peak memory 224656 kb
Host smart-b7574b6e-e14c-4504-a33e-64ed26a8b638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912751259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2912751259
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1465584194
Short name T539
Test name
Test status
Simulation time 828986687 ps
CPU time 5.47 seconds
Started Aug 16 05:55:05 PM PDT 24
Finished Aug 16 05:55:11 PM PDT 24
Peak memory 227036 kb
Host smart-6e575851-153a-4eaa-97a8-2da876521c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465584194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1465584194
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.198390005
Short name T1026
Test name
Test status
Simulation time 1123391050 ps
CPU time 10.44 seconds
Started Aug 16 05:55:12 PM PDT 24
Finished Aug 16 05:55:23 PM PDT 24
Peak memory 220336 kb
Host smart-eefbf29e-d855-4c54-9ea2-1a83bc4eea0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=198390005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.198390005
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.981945387
Short name T968
Test name
Test status
Simulation time 28447171983 ps
CPU time 97.49 seconds
Started Aug 16 05:54:54 PM PDT 24
Finished Aug 16 05:56:31 PM PDT 24
Peak memory 257508 kb
Host smart-99076e41-cb9b-472b-8212-6f4ebebdce97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981945387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.981945387
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.4192215640
Short name T790
Test name
Test status
Simulation time 9542389573 ps
CPU time 29.65 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:40 PM PDT 24
Peak memory 216768 kb
Host smart-ff438a85-dcd7-426d-8c10-b7d0d31c518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192215640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.4192215640
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1981326565
Short name T459
Test name
Test status
Simulation time 1919040287 ps
CPU time 9.74 seconds
Started Aug 16 05:54:32 PM PDT 24
Finished Aug 16 05:54:41 PM PDT 24
Peak memory 216468 kb
Host smart-ac301968-ccb7-4b87-9428-13314425e9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981326565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1981326565
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3714790384
Short name T900
Test name
Test status
Simulation time 66128999 ps
CPU time 1.51 seconds
Started Aug 16 05:55:02 PM PDT 24
Finished Aug 16 05:55:04 PM PDT 24
Peak memory 216480 kb
Host smart-90806eb7-c4d2-402e-bc29-e4bbc65c8e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714790384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3714790384
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1168224309
Short name T499
Test name
Test status
Simulation time 123324791 ps
CPU time 0.83 seconds
Started Aug 16 05:54:58 PM PDT 24
Finished Aug 16 05:54:59 PM PDT 24
Peak memory 206112 kb
Host smart-1ee409a7-671e-48a7-9eba-24361e5de4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168224309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1168224309
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2078461648
Short name T917
Test name
Test status
Simulation time 1933241221 ps
CPU time 4.3 seconds
Started Aug 16 05:54:51 PM PDT 24
Finished Aug 16 05:54:56 PM PDT 24
Peak memory 224556 kb
Host smart-4afa1dc3-969a-4397-98b9-d011f6a03d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078461648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2078461648
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1402989605
Short name T602
Test name
Test status
Simulation time 13014325 ps
CPU time 0.72 seconds
Started Aug 16 05:55:47 PM PDT 24
Finished Aug 16 05:55:48 PM PDT 24
Peak memory 204940 kb
Host smart-a1b87539-f679-4216-bfae-73674a53c981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402989605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1402989605
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3367817321
Short name T854
Test name
Test status
Simulation time 124431059 ps
CPU time 2.26 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:55:48 PM PDT 24
Peak memory 224596 kb
Host smart-1e9acaac-fe6e-47f5-827c-fb96e3d2d61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367817321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3367817321
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3796427853
Short name T912
Test name
Test status
Simulation time 30244178 ps
CPU time 0.83 seconds
Started Aug 16 05:55:44 PM PDT 24
Finished Aug 16 05:55:45 PM PDT 24
Peak memory 206744 kb
Host smart-1f3ab25d-d9a2-4ab9-8aa2-a2cba71f2052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796427853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3796427853
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.372552355
Short name T921
Test name
Test status
Simulation time 55112734251 ps
CPU time 99.74 seconds
Started Aug 16 05:56:17 PM PDT 24
Finished Aug 16 05:57:57 PM PDT 24
Peak memory 249476 kb
Host smart-551a93fb-e3f5-4e7e-8e33-110a8e780ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372552355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.372552355
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.784400348
Short name T454
Test name
Test status
Simulation time 14835118465 ps
CPU time 16.1 seconds
Started Aug 16 05:56:00 PM PDT 24
Finished Aug 16 05:56:17 PM PDT 24
Peak memory 224716 kb
Host smart-1257c649-9d70-4de2-a142-0818dceb6537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784400348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.784400348
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.498829136
Short name T423
Test name
Test status
Simulation time 2898604349 ps
CPU time 46.2 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:56:32 PM PDT 24
Peak memory 240468 kb
Host smart-1e8114f4-33f7-4e2d-9c9f-96c6d59f5ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498829136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.498829136
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3316369871
Short name T146
Test name
Test status
Simulation time 872514970 ps
CPU time 8.34 seconds
Started Aug 16 05:55:47 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 234796 kb
Host smart-ab1878ed-d63e-439b-83ab-8c9822d3eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316369871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3316369871
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3327309200
Short name T728
Test name
Test status
Simulation time 578935235 ps
CPU time 8.62 seconds
Started Aug 16 05:56:14 PM PDT 24
Finished Aug 16 05:56:22 PM PDT 24
Peak memory 249176 kb
Host smart-6f4d7d0f-b066-460b-9653-8532b7219db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327309200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3327309200
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.994783774
Short name T207
Test name
Test status
Simulation time 20146604658 ps
CPU time 20.27 seconds
Started Aug 16 05:56:18 PM PDT 24
Finished Aug 16 05:56:38 PM PDT 24
Peak memory 224696 kb
Host smart-a14e13e9-f6f4-4cf8-bc52-926ce3f19e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994783774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.994783774
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1984319763
Short name T500
Test name
Test status
Simulation time 3558786323 ps
CPU time 35.29 seconds
Started Aug 16 05:56:16 PM PDT 24
Finished Aug 16 05:56:51 PM PDT 24
Peak memory 224716 kb
Host smart-14575ec1-b636-4315-be86-12c57982e8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984319763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1984319763
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3340492091
Short name T911
Test name
Test status
Simulation time 172464577 ps
CPU time 3.04 seconds
Started Aug 16 05:55:43 PM PDT 24
Finished Aug 16 05:55:46 PM PDT 24
Peak memory 224680 kb
Host smart-26571c23-af89-45e8-8c80-6a0558452dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340492091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3340492091
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1493382573
Short name T554
Test name
Test status
Simulation time 3778873252 ps
CPU time 5.91 seconds
Started Aug 16 05:56:27 PM PDT 24
Finished Aug 16 05:56:33 PM PDT 24
Peak memory 232952 kb
Host smart-a3984d1a-635e-4b0e-a5ae-c4071e3a2dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493382573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1493382573
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.798794502
Short name T10
Test name
Test status
Simulation time 175241991 ps
CPU time 3.58 seconds
Started Aug 16 05:56:25 PM PDT 24
Finished Aug 16 05:56:29 PM PDT 24
Peak memory 220268 kb
Host smart-ad559557-919b-4113-812a-0ccbd3a79fb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=798794502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.798794502
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.339557656
Short name T162
Test name
Test status
Simulation time 193972466 ps
CPU time 0.99 seconds
Started Aug 16 05:56:25 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 207628 kb
Host smart-dee41a31-25c2-4327-b79d-aff26fd25988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339557656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.339557656
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1718019193
Short name T509
Test name
Test status
Simulation time 1173317020 ps
CPU time 8.32 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:55:50 PM PDT 24
Peak memory 216468 kb
Host smart-b8cbf6ab-3207-4e03-bf42-0f922ec479f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718019193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1718019193
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.72996022
Short name T23
Test name
Test status
Simulation time 14038113856 ps
CPU time 13.53 seconds
Started Aug 16 05:56:06 PM PDT 24
Finished Aug 16 05:56:20 PM PDT 24
Peak memory 216596 kb
Host smart-9892bb13-a026-42b3-924f-79cbc546c079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72996022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.72996022
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.507520745
Short name T334
Test name
Test status
Simulation time 372815223 ps
CPU time 6.23 seconds
Started Aug 16 05:55:44 PM PDT 24
Finished Aug 16 05:55:50 PM PDT 24
Peak memory 216448 kb
Host smart-b056f150-7f3c-4b93-9291-b6d6c53b3413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507520745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.507520745
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2023143738
Short name T376
Test name
Test status
Simulation time 108150745 ps
CPU time 0.88 seconds
Started Aug 16 05:56:09 PM PDT 24
Finished Aug 16 05:56:10 PM PDT 24
Peak memory 207048 kb
Host smart-a1f1337d-90e2-42d4-b34c-5a7bfc0ae148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023143738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2023143738
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1316861633
Short name T388
Test name
Test status
Simulation time 1558123987 ps
CPU time 6.87 seconds
Started Aug 16 05:56:12 PM PDT 24
Finished Aug 16 05:56:19 PM PDT 24
Peak memory 224656 kb
Host smart-2b1001ab-2d35-444f-911b-af18090f46b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316861633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1316861633
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3939982568
Short name T64
Test name
Test status
Simulation time 37069296 ps
CPU time 0.71 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:55:43 PM PDT 24
Peak memory 205460 kb
Host smart-25b99622-0358-4419-8d3e-b8687d5dac76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939982568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3939982568
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.831992457
Short name T1004
Test name
Test status
Simulation time 33667981 ps
CPU time 2.5 seconds
Started Aug 16 05:55:47 PM PDT 24
Finished Aug 16 05:55:50 PM PDT 24
Peak memory 232892 kb
Host smart-8f281fa3-26e3-47b6-a8b6-da2518be8959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831992457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.831992457
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3713027043
Short name T434
Test name
Test status
Simulation time 18538416 ps
CPU time 0.79 seconds
Started Aug 16 05:56:20 PM PDT 24
Finished Aug 16 05:56:21 PM PDT 24
Peak memory 205584 kb
Host smart-f47eded8-5dfa-46e5-998b-8f0fda9ff874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713027043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3713027043
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3419956051
Short name T758
Test name
Test status
Simulation time 302167720167 ps
CPU time 168.76 seconds
Started Aug 16 05:56:22 PM PDT 24
Finished Aug 16 05:59:11 PM PDT 24
Peak memory 254232 kb
Host smart-0ba0cc9b-05fd-4849-aed9-bf0318060435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419956051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3419956051
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4290008594
Short name T989
Test name
Test status
Simulation time 28335882177 ps
CPU time 41.46 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 217820 kb
Host smart-87d67b4c-5355-48d8-828a-9df91a0e5b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290008594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4290008594
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3563335227
Short name T643
Test name
Test status
Simulation time 416249185 ps
CPU time 3.15 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 232844 kb
Host smart-1264619b-1fa8-41c0-ac5c-cf5ece8233b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563335227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3563335227
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2192941681
Short name T281
Test name
Test status
Simulation time 19124328479 ps
CPU time 141.84 seconds
Started Aug 16 05:56:27 PM PDT 24
Finished Aug 16 05:58:50 PM PDT 24
Peak memory 252864 kb
Host smart-1986166d-c3e6-4697-ab8b-3a7bf631669c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192941681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2192941681
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1476575770
Short name T958
Test name
Test status
Simulation time 911180798 ps
CPU time 4.24 seconds
Started Aug 16 05:56:19 PM PDT 24
Finished Aug 16 05:56:23 PM PDT 24
Peak memory 224608 kb
Host smart-a09773b1-e771-4aa7-a7fd-24951e7f142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476575770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1476575770
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2942613059
Short name T765
Test name
Test status
Simulation time 8171632643 ps
CPU time 62.7 seconds
Started Aug 16 05:56:15 PM PDT 24
Finished Aug 16 05:57:17 PM PDT 24
Peak memory 241148 kb
Host smart-9ea06136-5a6c-4b30-9ed3-69747c92532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942613059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2942613059
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2054674538
Short name T795
Test name
Test status
Simulation time 2527658925 ps
CPU time 3.07 seconds
Started Aug 16 05:56:49 PM PDT 24
Finished Aug 16 05:56:52 PM PDT 24
Peak memory 224776 kb
Host smart-608f9e26-e8ee-45d5-94fd-e5106a001792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054674538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2054674538
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3519692496
Short name T393
Test name
Test status
Simulation time 296371856 ps
CPU time 5.15 seconds
Started Aug 16 05:55:41 PM PDT 24
Finished Aug 16 05:55:47 PM PDT 24
Peak memory 224704 kb
Host smart-8cee05bb-bfce-4405-872d-0aa68bf05d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519692496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3519692496
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3314437315
Short name T585
Test name
Test status
Simulation time 166788531 ps
CPU time 4.13 seconds
Started Aug 16 05:56:21 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 219308 kb
Host smart-e1b1e1b4-34a7-46cd-a105-4e094564de2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3314437315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3314437315
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1007994813
Short name T293
Test name
Test status
Simulation time 14938471236 ps
CPU time 153.42 seconds
Started Aug 16 05:55:47 PM PDT 24
Finished Aug 16 05:58:21 PM PDT 24
Peak memory 268900 kb
Host smart-fe4871de-4b21-4316-ae11-e21e4906116e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007994813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1007994813
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3227263637
Short name T904
Test name
Test status
Simulation time 592353852 ps
CPU time 6.18 seconds
Started Aug 16 05:56:18 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 216488 kb
Host smart-a5ac9089-20e9-4aa7-a470-a34bd643d85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227263637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3227263637
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3792803518
Short name T564
Test name
Test status
Simulation time 30619469 ps
CPU time 0.98 seconds
Started Aug 16 05:56:22 PM PDT 24
Finished Aug 16 05:56:23 PM PDT 24
Peak memory 207220 kb
Host smart-0decc341-9e59-4fb3-bfed-bdc5f0430c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792803518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3792803518
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.150952705
Short name T880
Test name
Test status
Simulation time 42575539 ps
CPU time 1.2 seconds
Started Aug 16 05:55:41 PM PDT 24
Finished Aug 16 05:55:42 PM PDT 24
Peak memory 216468 kb
Host smart-981d9080-5f90-4516-a108-55583aa5b470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150952705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.150952705
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2799564070
Short name T572
Test name
Test status
Simulation time 18619331 ps
CPU time 0.79 seconds
Started Aug 16 05:55:39 PM PDT 24
Finished Aug 16 05:55:40 PM PDT 24
Peak memory 205684 kb
Host smart-b1894d7b-b1c0-4973-8435-22eec743e308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799564070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2799564070
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3166709207
Short name T674
Test name
Test status
Simulation time 668852820 ps
CPU time 3.25 seconds
Started Aug 16 05:56:22 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 224648 kb
Host smart-bec69a4b-fd0f-443d-bd58-5cb86f7bb9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166709207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3166709207
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3224006626
Short name T392
Test name
Test status
Simulation time 34393691 ps
CPU time 0.67 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:55:43 PM PDT 24
Peak memory 204868 kb
Host smart-8dad4a08-063d-46c2-81a8-09d4efb49e91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224006626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3224006626
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3108153955
Short name T822
Test name
Test status
Simulation time 33441228 ps
CPU time 2.33 seconds
Started Aug 16 05:56:32 PM PDT 24
Finished Aug 16 05:56:35 PM PDT 24
Peak memory 232360 kb
Host smart-c51efdbd-ef7c-4e3c-9cde-61a338ed8d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108153955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3108153955
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2379974182
Short name T819
Test name
Test status
Simulation time 13817444 ps
CPU time 0.76 seconds
Started Aug 16 05:55:46 PM PDT 24
Finished Aug 16 05:55:47 PM PDT 24
Peak memory 205912 kb
Host smart-d949b37e-1993-4632-933b-d37aa461e1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379974182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2379974182
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3647198932
Short name T77
Test name
Test status
Simulation time 21714742816 ps
CPU time 55.58 seconds
Started Aug 16 05:55:47 PM PDT 24
Finished Aug 16 05:56:43 PM PDT 24
Peak memory 250528 kb
Host smart-8657bb9b-0e70-4185-8e99-a9ce88375a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647198932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3647198932
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2266129259
Short name T969
Test name
Test status
Simulation time 3928326132 ps
CPU time 96.96 seconds
Started Aug 16 05:55:44 PM PDT 24
Finished Aug 16 05:57:21 PM PDT 24
Peak memory 264344 kb
Host smart-3632dc4b-526e-4c79-938f-93cea2ed2cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266129259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2266129259
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4258971031
Short name T240
Test name
Test status
Simulation time 51497863484 ps
CPU time 184.29 seconds
Started Aug 16 05:56:16 PM PDT 24
Finished Aug 16 05:59:20 PM PDT 24
Peak memory 263292 kb
Host smart-9188e837-16a8-4fd7-9e26-962a0fe3f2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258971031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4258971031
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1343535149
Short name T414
Test name
Test status
Simulation time 3610920910 ps
CPU time 52.19 seconds
Started Aug 16 05:56:26 PM PDT 24
Finished Aug 16 05:57:18 PM PDT 24
Peak memory 238132 kb
Host smart-3b69da27-69a9-4b16-ba70-0d30cc4b7f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343535149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1343535149
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1648837002
Short name T59
Test name
Test status
Simulation time 25862126932 ps
CPU time 106.64 seconds
Started Aug 16 05:56:32 PM PDT 24
Finished Aug 16 05:58:19 PM PDT 24
Peak memory 257500 kb
Host smart-a15a9cc2-7216-4cb2-a0cc-676a3186d6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648837002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1648837002
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2776997066
Short name T744
Test name
Test status
Simulation time 194080491 ps
CPU time 3.72 seconds
Started Aug 16 05:55:43 PM PDT 24
Finished Aug 16 05:55:47 PM PDT 24
Peak memory 224572 kb
Host smart-78ac943a-2b23-43dc-8e6d-0d9cac9c7bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776997066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2776997066
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.118011014
Short name T533
Test name
Test status
Simulation time 591803020 ps
CPU time 7.77 seconds
Started Aug 16 05:55:42 PM PDT 24
Finished Aug 16 05:55:49 PM PDT 24
Peak memory 232856 kb
Host smart-604e1f61-d0d8-4b27-8c44-db57f46321fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118011014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.118011014
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.366627866
Short name T50
Test name
Test status
Simulation time 1324854423 ps
CPU time 3.19 seconds
Started Aug 16 05:56:33 PM PDT 24
Finished Aug 16 05:56:36 PM PDT 24
Peak memory 224592 kb
Host smart-2c956b98-76fd-4267-becf-cbb2e4a276cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366627866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.366627866
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.116523440
Short name T794
Test name
Test status
Simulation time 6074387457 ps
CPU time 20.02 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:43 PM PDT 24
Peak memory 232840 kb
Host smart-ba2af6e5-456c-4f0f-a037-ae6b2eb1cd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116523440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.116523440
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.376278912
Short name T926
Test name
Test status
Simulation time 1139089106 ps
CPU time 3.79 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 218996 kb
Host smart-602b7379-c13b-4cf5-bb94-af181287c65f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=376278912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.376278912
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.40408725
Short name T294
Test name
Test status
Simulation time 51951660679 ps
CPU time 439.87 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 06:03:43 PM PDT 24
Peak memory 265748 kb
Host smart-ba13d714-cdca-437a-a05a-91e200df78db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40408725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress
_all.40408725
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1827920104
Short name T565
Test name
Test status
Simulation time 13775182750 ps
CPU time 20.95 seconds
Started Aug 16 05:56:21 PM PDT 24
Finished Aug 16 05:56:43 PM PDT 24
Peak memory 216480 kb
Host smart-4b970d3c-3db2-4d5a-9176-28be9ffed046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827920104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1827920104
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1246999585
Short name T11
Test name
Test status
Simulation time 7880337436 ps
CPU time 12.61 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:37 PM PDT 24
Peak memory 216592 kb
Host smart-db05d7f9-429c-4955-b58b-801e8e4b3334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246999585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1246999585
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3059636684
Short name T698
Test name
Test status
Simulation time 413088934 ps
CPU time 2.12 seconds
Started Aug 16 05:56:09 PM PDT 24
Finished Aug 16 05:56:11 PM PDT 24
Peak memory 216488 kb
Host smart-667d76a5-4f15-42e0-994b-db9336e06669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059636684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3059636684
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2598771813
Short name T828
Test name
Test status
Simulation time 260002710 ps
CPU time 0.82 seconds
Started Aug 16 05:55:43 PM PDT 24
Finished Aug 16 05:55:43 PM PDT 24
Peak memory 206128 kb
Host smart-e5b99325-d82f-4569-b935-6528f210f8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598771813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2598771813
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.484448055
Short name T85
Test name
Test status
Simulation time 6314912920 ps
CPU time 25.39 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:48 PM PDT 24
Peak memory 250344 kb
Host smart-c646f106-3017-45c5-a35c-9c4d3f7c6822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484448055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.484448055
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1468099711
Short name T1014
Test name
Test status
Simulation time 16529297 ps
CPU time 0.78 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:55:58 PM PDT 24
Peak memory 204960 kb
Host smart-bf7d1f38-450a-4c73-826c-790c9971d423
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468099711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1468099711
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1039122415
Short name T782
Test name
Test status
Simulation time 35231461 ps
CPU time 2.11 seconds
Started Aug 16 05:55:47 PM PDT 24
Finished Aug 16 05:55:50 PM PDT 24
Peak memory 224764 kb
Host smart-c9cbb512-67dc-4e57-9679-7b9355519fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039122415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1039122415
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1591698607
Short name T672
Test name
Test status
Simulation time 23156112 ps
CPU time 0.82 seconds
Started Aug 16 05:56:08 PM PDT 24
Finished Aug 16 05:56:09 PM PDT 24
Peak memory 206640 kb
Host smart-95a72341-a967-4e82-ad46-46b67809652b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591698607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1591698607
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.4095001225
Short name T630
Test name
Test status
Simulation time 4101093145 ps
CPU time 23.41 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:48 PM PDT 24
Peak memory 249356 kb
Host smart-75418932-c2b3-437a-8817-006feb16544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095001225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4095001225
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3105775657
Short name T839
Test name
Test status
Simulation time 9996625031 ps
CPU time 13.45 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:37 PM PDT 24
Peak memory 219652 kb
Host smart-b9a89c2c-c0d8-4af7-a4ec-3f8a5540f65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105775657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3105775657
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1426175618
Short name T1008
Test name
Test status
Simulation time 26525428895 ps
CPU time 94.21 seconds
Started Aug 16 05:55:46 PM PDT 24
Finished Aug 16 05:57:21 PM PDT 24
Peak memory 267540 kb
Host smart-30174afe-4e81-4d90-b38e-fdd4fffc4c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426175618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1426175618
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3677564738
Short name T646
Test name
Test status
Simulation time 596684169 ps
CPU time 3.19 seconds
Started Aug 16 05:55:46 PM PDT 24
Finished Aug 16 05:55:49 PM PDT 24
Peak memory 224636 kb
Host smart-c4bf8b01-6607-44ef-87f5-66c4f3d42bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677564738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3677564738
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.269812318
Short name T213
Test name
Test status
Simulation time 27510350589 ps
CPU time 225.93 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 05:59:44 PM PDT 24
Peak memory 256436 kb
Host smart-4878c971-05b8-49af-91db-6870fcd68c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269812318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.269812318
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1331551397
Short name T755
Test name
Test status
Simulation time 474678854 ps
CPU time 7.67 seconds
Started Aug 16 05:56:07 PM PDT 24
Finished Aug 16 05:56:15 PM PDT 24
Peak memory 232928 kb
Host smart-2ec6ad3f-a3e0-402d-95ae-9670bfdfd41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331551397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1331551397
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1286365776
Short name T95
Test name
Test status
Simulation time 10045351171 ps
CPU time 27.21 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:51 PM PDT 24
Peak memory 224668 kb
Host smart-c9c4ff73-0ce4-452e-9ecc-e9b0415a485a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286365776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1286365776
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2954403261
Short name T571
Test name
Test status
Simulation time 4168884420 ps
CPU time 7.89 seconds
Started Aug 16 05:56:05 PM PDT 24
Finished Aug 16 05:56:13 PM PDT 24
Peak memory 232868 kb
Host smart-6c2c83ac-8abc-4793-a09c-0a886cbbf25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954403261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2954403261
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3340472390
Short name T844
Test name
Test status
Simulation time 4645818975 ps
CPU time 6.51 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:31 PM PDT 24
Peak memory 232952 kb
Host smart-cef55528-cc9c-40f4-9066-f74e70058459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340472390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3340472390
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1804309049
Short name T381
Test name
Test status
Simulation time 179518062 ps
CPU time 3.8 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:56:01 PM PDT 24
Peak memory 222588 kb
Host smart-f11a8e98-ca6c-486c-b438-4835cb582e1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1804309049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1804309049
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1796299312
Short name T528
Test name
Test status
Simulation time 1484119780 ps
CPU time 2.93 seconds
Started Aug 16 05:55:46 PM PDT 24
Finished Aug 16 05:55:49 PM PDT 24
Peak memory 216516 kb
Host smart-060fa1cf-19e4-47b1-9bc6-6ac7ed92159a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796299312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1796299312
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4261810970
Short name T368
Test name
Test status
Simulation time 1157185459 ps
CPU time 3.59 seconds
Started Aug 16 05:56:00 PM PDT 24
Finished Aug 16 05:56:04 PM PDT 24
Peak memory 216488 kb
Host smart-e343328d-576d-483a-b811-8a497f03238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261810970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4261810970
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2586357614
Short name T717
Test name
Test status
Simulation time 257411528 ps
CPU time 1.19 seconds
Started Aug 16 05:55:45 PM PDT 24
Finished Aug 16 05:55:47 PM PDT 24
Peak memory 208116 kb
Host smart-4fac1e20-dffa-4c79-ac7a-ee7b49c26df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586357614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2586357614
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1868374400
Short name T479
Test name
Test status
Simulation time 84271434 ps
CPU time 0.76 seconds
Started Aug 16 05:56:20 PM PDT 24
Finished Aug 16 05:56:21 PM PDT 24
Peak memory 206040 kb
Host smart-b164bd58-bf99-4b66-9721-3485bbd6395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868374400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1868374400
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1574214544
Short name T665
Test name
Test status
Simulation time 5605144359 ps
CPU time 19.11 seconds
Started Aug 16 05:55:43 PM PDT 24
Finished Aug 16 05:56:02 PM PDT 24
Peak memory 240988 kb
Host smart-6314c879-89a2-45c3-a86b-4cb266525710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574214544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1574214544
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2661495483
Short name T771
Test name
Test status
Simulation time 22512719 ps
CPU time 0.67 seconds
Started Aug 16 05:56:14 PM PDT 24
Finished Aug 16 05:56:15 PM PDT 24
Peak memory 204928 kb
Host smart-cc6d3176-9503-440b-a3c4-f087457cf2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661495483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2661495483
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1333506770
Short name T784
Test name
Test status
Simulation time 2154794398 ps
CPU time 13.02 seconds
Started Aug 16 05:55:51 PM PDT 24
Finished Aug 16 05:56:05 PM PDT 24
Peak memory 232928 kb
Host smart-ed5d2615-2cd8-4438-983b-786943c255b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333506770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1333506770
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4161356646
Short name T774
Test name
Test status
Simulation time 30064721 ps
CPU time 0.76 seconds
Started Aug 16 05:56:12 PM PDT 24
Finished Aug 16 05:56:12 PM PDT 24
Peak memory 205540 kb
Host smart-1649a8f6-80b2-4ec1-809e-4a3ee25e86fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161356646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4161356646
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3129445310
Short name T949
Test name
Test status
Simulation time 9866519386 ps
CPU time 97.43 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:58:01 PM PDT 24
Peak memory 251224 kb
Host smart-af615b1c-6642-44b1-95e8-1ad60fae1e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129445310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3129445310
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2079870415
Short name T978
Test name
Test status
Simulation time 40079625658 ps
CPU time 361.21 seconds
Started Aug 16 05:55:52 PM PDT 24
Finished Aug 16 06:01:53 PM PDT 24
Peak memory 257616 kb
Host smart-fab54855-f310-4e18-a99b-b8e1e40aabd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079870415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2079870415
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2628066140
Short name T329
Test name
Test status
Simulation time 15779262863 ps
CPU time 8.82 seconds
Started Aug 16 05:55:46 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 217696 kb
Host smart-81aef74b-96f3-4d60-8512-0e67bff81322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628066140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2628066140
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.726236234
Short name T490
Test name
Test status
Simulation time 2390231130 ps
CPU time 15.59 seconds
Started Aug 16 05:55:51 PM PDT 24
Finished Aug 16 05:56:07 PM PDT 24
Peak memory 234124 kb
Host smart-433c0e68-9150-4604-9975-7455b633a409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726236234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.726236234
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3188154868
Short name T317
Test name
Test status
Simulation time 16554552056 ps
CPU time 59.28 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:56:56 PM PDT 24
Peak memory 254980 kb
Host smart-436570e4-9183-475e-ad6e-8d887f5b5085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188154868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3188154868
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.714016990
Short name T455
Test name
Test status
Simulation time 268724012 ps
CPU time 4.48 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 218988 kb
Host smart-a59fb3bf-1fa8-44df-93a0-3d7c407ce675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714016990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.714016990
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3010559922
Short name T558
Test name
Test status
Simulation time 72207289 ps
CPU time 2.07 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 224208 kb
Host smart-40fef7b6-55dc-4434-97fe-88144d570960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010559922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3010559922
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.736701427
Short name T12
Test name
Test status
Simulation time 2139683254 ps
CPU time 5.51 seconds
Started Aug 16 05:55:52 PM PDT 24
Finished Aug 16 05:55:57 PM PDT 24
Peak memory 224436 kb
Host smart-6a47c7e8-c355-490a-8d0a-4b6abd57dae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736701427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.736701427
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2996888850
Short name T280
Test name
Test status
Simulation time 40057424 ps
CPU time 2.26 seconds
Started Aug 16 05:55:48 PM PDT 24
Finished Aug 16 05:55:51 PM PDT 24
Peak memory 232796 kb
Host smart-81fec4a0-a465-4488-97c1-366d03b48ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996888850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2996888850
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2303000225
Short name T448
Test name
Test status
Simulation time 226073879 ps
CPU time 5.73 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:30 PM PDT 24
Peak memory 218880 kb
Host smart-324aa759-aa01-4165-82ee-68fb698e3b37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2303000225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2303000225
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3744647673
Short name T141
Test name
Test status
Simulation time 48055862907 ps
CPU time 499.99 seconds
Started Aug 16 05:55:56 PM PDT 24
Finished Aug 16 06:04:16 PM PDT 24
Peak memory 253184 kb
Host smart-f51f01d2-76fe-4710-9600-2f2215967ca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744647673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3744647673
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3598179646
Short name T52
Test name
Test status
Simulation time 35814040776 ps
CPU time 20.6 seconds
Started Aug 16 05:56:20 PM PDT 24
Finished Aug 16 05:56:41 PM PDT 24
Peak memory 216468 kb
Host smart-544e2b55-48ab-47d8-8cb9-a6a1978f907f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598179646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3598179646
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2312090360
Short name T83
Test name
Test status
Simulation time 4615779732 ps
CPU time 13.36 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:38 PM PDT 24
Peak memory 216576 kb
Host smart-b11c35a7-195a-41e4-a7a0-0917481ed17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312090360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2312090360
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1583225665
Short name T928
Test name
Test status
Simulation time 68777296 ps
CPU time 0.88 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:55:54 PM PDT 24
Peak memory 207352 kb
Host smart-71f80b85-a4c9-4379-9f6f-dca7e4b00ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583225665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1583225665
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3855708877
Short name T895
Test name
Test status
Simulation time 27467418 ps
CPU time 0.82 seconds
Started Aug 16 05:55:48 PM PDT 24
Finished Aug 16 05:55:49 PM PDT 24
Peak memory 206192 kb
Host smart-f9ca386e-6bbe-431c-b03e-48ef86f93a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855708877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3855708877
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2403132318
Short name T945
Test name
Test status
Simulation time 11069744787 ps
CPU time 18.1 seconds
Started Aug 16 05:56:16 PM PDT 24
Finished Aug 16 05:56:34 PM PDT 24
Peak memory 232912 kb
Host smart-dd7208d8-b5d1-4b58-9020-f9c3bb678cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403132318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2403132318
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3252340395
Short name T906
Test name
Test status
Simulation time 30531530 ps
CPU time 0.74 seconds
Started Aug 16 05:55:52 PM PDT 24
Finished Aug 16 05:55:53 PM PDT 24
Peak memory 205712 kb
Host smart-cda1b70e-c65f-441f-9490-48eeb3c834fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252340395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3252340395
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.856432321
Short name T815
Test name
Test status
Simulation time 165518968 ps
CPU time 3.83 seconds
Started Aug 16 05:56:21 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 232828 kb
Host smart-0907901f-016c-42c5-9aa3-ac560f6e00a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856432321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.856432321
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.556587026
Short name T664
Test name
Test status
Simulation time 38809458 ps
CPU time 0.82 seconds
Started Aug 16 05:55:52 PM PDT 24
Finished Aug 16 05:55:53 PM PDT 24
Peak memory 206864 kb
Host smart-6a9151f8-7fc7-4002-b48a-7bfac2c51cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556587026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.556587026
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3577744011
Short name T41
Test name
Test status
Simulation time 77904829586 ps
CPU time 166.88 seconds
Started Aug 16 05:56:00 PM PDT 24
Finished Aug 16 05:58:47 PM PDT 24
Peak memory 249368 kb
Host smart-486c766e-580e-4c14-8af9-2d2303d210e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577744011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3577744011
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.709223299
Short name T43
Test name
Test status
Simulation time 53141030295 ps
CPU time 134.31 seconds
Started Aug 16 05:56:11 PM PDT 24
Finished Aug 16 05:58:26 PM PDT 24
Peak memory 253680 kb
Host smart-eb18d848-80c4-41b0-be32-ac1191e575e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709223299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.709223299
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2863144837
Short name T312
Test name
Test status
Simulation time 16762365072 ps
CPU time 222.62 seconds
Started Aug 16 05:55:56 PM PDT 24
Finished Aug 16 05:59:39 PM PDT 24
Peak memory 256112 kb
Host smart-e1663d8b-6705-45fe-93ec-17e6b5958cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863144837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2863144837
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.378665825
Short name T445
Test name
Test status
Simulation time 77258637 ps
CPU time 3.19 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:32 PM PDT 24
Peak memory 232848 kb
Host smart-b5be770b-a645-49c9-952e-819576ea2536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378665825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.378665825
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2872195020
Short name T94
Test name
Test status
Simulation time 9191320601 ps
CPU time 55.24 seconds
Started Aug 16 05:55:56 PM PDT 24
Finished Aug 16 05:56:51 PM PDT 24
Peak memory 253596 kb
Host smart-3f18329b-3420-4866-8f7d-f5760fd09132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872195020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2872195020
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2019903943
Short name T802
Test name
Test status
Simulation time 179300051 ps
CPU time 3.68 seconds
Started Aug 16 05:56:25 PM PDT 24
Finished Aug 16 05:56:29 PM PDT 24
Peak memory 232804 kb
Host smart-4091ff9b-2ed8-4174-8551-710cbf79efd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019903943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2019903943
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3961607934
Short name T813
Test name
Test status
Simulation time 12185672092 ps
CPU time 41.5 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:56:39 PM PDT 24
Peak memory 239440 kb
Host smart-e94ab049-df8b-4b04-b9cf-1c5afd224f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961607934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3961607934
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.380145032
Short name T4
Test name
Test status
Simulation time 1827143473 ps
CPU time 11.44 seconds
Started Aug 16 05:56:15 PM PDT 24
Finished Aug 16 05:56:27 PM PDT 24
Peak memory 224700 kb
Host smart-44d6697b-1de8-4364-bbcb-65756a4b1e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380145032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.380145032
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2863730816
Short name T489
Test name
Test status
Simulation time 8753881765 ps
CPU time 18.52 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:42 PM PDT 24
Peak memory 232924 kb
Host smart-eedb7067-68d0-4a16-bc56-cfe184799104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863730816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2863730816
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3854191658
Short name T87
Test name
Test status
Simulation time 7117222759 ps
CPU time 21.66 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:56:19 PM PDT 24
Peak memory 220380 kb
Host smart-70edf85d-7e88-4e42-adb4-451248a5bc38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3854191658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3854191658
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2167492234
Short name T976
Test name
Test status
Simulation time 27623796251 ps
CPU time 153.16 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:58:57 PM PDT 24
Peak memory 273596 kb
Host smart-b30107ca-799a-457a-80b5-7036f8abbd7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167492234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2167492234
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2319140594
Short name T729
Test name
Test status
Simulation time 14057134 ps
CPU time 0.71 seconds
Started Aug 16 05:55:51 PM PDT 24
Finished Aug 16 05:55:52 PM PDT 24
Peak memory 205772 kb
Host smart-59208faf-9685-4b2b-a60e-de0e26176096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319140594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2319140594
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2136915408
Short name T369
Test name
Test status
Simulation time 987993049 ps
CPU time 1.99 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 207996 kb
Host smart-b073da07-4a68-4da2-af83-f91a7bb1f690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136915408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2136915408
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.530128707
Short name T403
Test name
Test status
Simulation time 110062093 ps
CPU time 1.29 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:25 PM PDT 24
Peak memory 208328 kb
Host smart-4d3f4d80-c190-49b8-aeca-318c5da81fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530128707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.530128707
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1643713347
Short name T713
Test name
Test status
Simulation time 83114901 ps
CPU time 0.85 seconds
Started Aug 16 05:55:54 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 207156 kb
Host smart-e40bfe40-36e8-446f-aff9-4de2d7bf190f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643713347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1643713347
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1235869000
Short name T595
Test name
Test status
Simulation time 24561462264 ps
CPU time 24.67 seconds
Started Aug 16 05:56:20 PM PDT 24
Finished Aug 16 05:56:45 PM PDT 24
Peak memory 232852 kb
Host smart-f41f9f2e-f67e-4dbb-bd83-a1a14de8692b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235869000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1235869000
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.510365706
Short name T685
Test name
Test status
Simulation time 29407152 ps
CPU time 0.67 seconds
Started Aug 16 05:55:51 PM PDT 24
Finished Aug 16 05:55:52 PM PDT 24
Peak memory 205516 kb
Host smart-846bdf96-49a9-4436-a434-7a43070acb0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510365706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.510365706
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.86837297
Short name T522
Test name
Test status
Simulation time 847359266 ps
CPU time 4.49 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 232904 kb
Host smart-bf792e1d-28f2-46b3-af5a-ebbd3728e04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86837297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.86837297
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3280427487
Short name T566
Test name
Test status
Simulation time 67736269 ps
CPU time 0.77 seconds
Started Aug 16 05:55:49 PM PDT 24
Finished Aug 16 05:55:49 PM PDT 24
Peak memory 206640 kb
Host smart-3227d33d-87bf-4887-aed4-d86f073d90f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280427487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3280427487
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4010919653
Short name T732
Test name
Test status
Simulation time 20091991534 ps
CPU time 130.36 seconds
Started Aug 16 05:56:20 PM PDT 24
Finished Aug 16 05:58:31 PM PDT 24
Peak memory 257496 kb
Host smart-d9af9cb8-bd27-475f-9750-6ca96da1500b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010919653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4010919653
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1008091766
Short name T192
Test name
Test status
Simulation time 18822278375 ps
CPU time 43.4 seconds
Started Aug 16 05:56:25 PM PDT 24
Finished Aug 16 05:57:08 PM PDT 24
Peak memory 234048 kb
Host smart-f9aacf81-afe0-4b5b-a04e-e21528006f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008091766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1008091766
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3645341579
Short name T220
Test name
Test status
Simulation time 36530328729 ps
CPU time 79.51 seconds
Started Aug 16 05:55:59 PM PDT 24
Finished Aug 16 05:57:19 PM PDT 24
Peak memory 224924 kb
Host smart-f06e5d0c-c345-4c14-b3f2-3fd31313827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645341579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3645341579
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1800506906
Short name T1010
Test name
Test status
Simulation time 22053929706 ps
CPU time 67.62 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:57:31 PM PDT 24
Peak memory 233876 kb
Host smart-c07c25a7-0452-4a92-9d48-8e78fb9f38f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800506906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1800506906
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1705348855
Short name T619
Test name
Test status
Simulation time 131326493483 ps
CPU time 152.87 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:58:26 PM PDT 24
Peak memory 252280 kb
Host smart-79b439a8-05ef-4810-ac0b-d94e4f4530b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705348855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1705348855
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2786774586
Short name T276
Test name
Test status
Simulation time 8765715678 ps
CPU time 37.48 seconds
Started Aug 16 05:56:22 PM PDT 24
Finished Aug 16 05:56:59 PM PDT 24
Peak memory 230324 kb
Host smart-919466dd-bc57-4ee2-9082-839f263c2b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786774586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2786774586
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.723022998
Short name T747
Test name
Test status
Simulation time 2503070335 ps
CPU time 14.26 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:56:08 PM PDT 24
Peak memory 241112 kb
Host smart-31d1e186-0552-43ca-a367-d8306dfb2810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723022998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.723022998
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3032346320
Short name T286
Test name
Test status
Simulation time 890640976 ps
CPU time 5 seconds
Started Aug 16 05:56:36 PM PDT 24
Finished Aug 16 05:56:41 PM PDT 24
Peak memory 240528 kb
Host smart-bdd1e1b4-7339-4d7e-80cf-f8d59d98b1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032346320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3032346320
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2691183392
Short name T970
Test name
Test status
Simulation time 5281400216 ps
CPU time 17.96 seconds
Started Aug 16 05:55:52 PM PDT 24
Finished Aug 16 05:56:10 PM PDT 24
Peak memory 256988 kb
Host smart-33130def-73b9-4c55-baf1-613b3c4959ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691183392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2691183392
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1643115324
Short name T749
Test name
Test status
Simulation time 5195981946 ps
CPU time 11.35 seconds
Started Aug 16 05:56:21 PM PDT 24
Finished Aug 16 05:56:32 PM PDT 24
Peak memory 220780 kb
Host smart-45040430-e0b4-4c76-8e60-7b983ba6282c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1643115324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1643115324
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3221994726
Short name T444
Test name
Test status
Simulation time 10846614065 ps
CPU time 109.7 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:58:14 PM PDT 24
Peak memory 257220 kb
Host smart-b15e7288-3a80-480c-85c4-b3d312cefed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221994726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3221994726
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3503029143
Short name T606
Test name
Test status
Simulation time 2911908256 ps
CPU time 16.3 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:39 PM PDT 24
Peak memory 216508 kb
Host smart-38a54091-7093-4cfb-8141-820023329236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503029143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3503029143
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.189010376
Short name T890
Test name
Test status
Simulation time 35387248 ps
CPU time 0.69 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 205748 kb
Host smart-fa5f4d1a-57fe-4108-ac82-a4999be7f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189010376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.189010376
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3449406206
Short name T856
Test name
Test status
Simulation time 129886697 ps
CPU time 1.68 seconds
Started Aug 16 05:56:21 PM PDT 24
Finished Aug 16 05:56:23 PM PDT 24
Peak memory 216412 kb
Host smart-2ba82cb1-ad93-4efb-8622-78a62319afac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449406206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3449406206
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2066130837
Short name T435
Test name
Test status
Simulation time 35499492 ps
CPU time 0.83 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:55:54 PM PDT 24
Peak memory 206148 kb
Host smart-6da3473a-43b2-4851-8578-2d01df52c97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066130837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2066130837
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3028256529
Short name T433
Test name
Test status
Simulation time 97152451 ps
CPU time 2.88 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 232876 kb
Host smart-85dd96de-03a4-45d1-84af-ca59d69ea0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028256529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3028256529
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.910591162
Short name T761
Test name
Test status
Simulation time 12226165 ps
CPU time 0.71 seconds
Started Aug 16 05:56:17 PM PDT 24
Finished Aug 16 05:56:18 PM PDT 24
Peak memory 205548 kb
Host smart-0b2b0792-51a7-4954-b190-78500a041abf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910591162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.910591162
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2414527692
Short name T834
Test name
Test status
Simulation time 314428434 ps
CPU time 4.73 seconds
Started Aug 16 05:56:27 PM PDT 24
Finished Aug 16 05:56:32 PM PDT 24
Peak memory 224544 kb
Host smart-ec589c56-744f-4bd8-b3b6-be57bef5a1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414527692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2414527692
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1407909061
Short name T984
Test name
Test status
Simulation time 25020947 ps
CPU time 0.81 seconds
Started Aug 16 05:55:56 PM PDT 24
Finished Aug 16 05:55:57 PM PDT 24
Peak memory 206628 kb
Host smart-653ee004-048b-4065-883f-d81aa56e297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407909061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1407909061
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.4146345901
Short name T993
Test name
Test status
Simulation time 16242375475 ps
CPU time 71.86 seconds
Started Aug 16 05:56:33 PM PDT 24
Finished Aug 16 05:57:45 PM PDT 24
Peak memory 253904 kb
Host smart-88108337-9c75-4e62-9662-90bc9431f420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146345901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4146345901
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2200074709
Short name T215
Test name
Test status
Simulation time 3503515488 ps
CPU time 83.28 seconds
Started Aug 16 05:56:22 PM PDT 24
Finished Aug 16 05:57:45 PM PDT 24
Peak memory 256388 kb
Host smart-e24735b1-a25d-421d-ab06-13b8bb522591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200074709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2200074709
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.487578000
Short name T1024
Test name
Test status
Simulation time 1627670610 ps
CPU time 22.24 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:45 PM PDT 24
Peak memory 232908 kb
Host smart-301dece1-311c-45d7-9e92-f5425bc8b22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487578000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.487578000
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3608886440
Short name T783
Test name
Test status
Simulation time 2781498010 ps
CPU time 11.78 seconds
Started Aug 16 05:56:25 PM PDT 24
Finished Aug 16 05:56:37 PM PDT 24
Peak memory 235184 kb
Host smart-0b0420d4-abdb-4bd9-9445-df57d448cbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608886440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3608886440
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.881387546
Short name T225
Test name
Test status
Simulation time 2299073421 ps
CPU time 9.18 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 05:56:08 PM PDT 24
Peak memory 232932 kb
Host smart-4d02f5b7-7393-4b0f-aac4-b585f5182b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881387546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.881387546
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3104066494
Short name T714
Test name
Test status
Simulation time 88695329683 ps
CPU time 49.15 seconds
Started Aug 16 05:55:54 PM PDT 24
Finished Aug 16 05:56:44 PM PDT 24
Peak memory 240708 kb
Host smart-4bcf2cb9-6d8a-4925-be94-618b651cbeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104066494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3104066494
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2166915458
Short name T960
Test name
Test status
Simulation time 344349480 ps
CPU time 2.87 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 05:56:01 PM PDT 24
Peak memory 224624 kb
Host smart-f2c378c4-fc07-479f-8283-94de23735442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166915458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2166915458
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1194469568
Short name T516
Test name
Test status
Simulation time 3522189544 ps
CPU time 5.89 seconds
Started Aug 16 05:56:32 PM PDT 24
Finished Aug 16 05:56:38 PM PDT 24
Peak memory 224760 kb
Host smart-b6021c42-209c-42ec-886d-ef399e473cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194469568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1194469568
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3738821192
Short name T442
Test name
Test status
Simulation time 890813400 ps
CPU time 6.22 seconds
Started Aug 16 05:55:53 PM PDT 24
Finished Aug 16 05:56:00 PM PDT 24
Peak memory 222608 kb
Host smart-aa0e4007-e9c2-4f92-9b29-d453ec30cd97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3738821192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3738821192
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.852797515
Short name T647
Test name
Test status
Simulation time 126636857052 ps
CPU time 268.05 seconds
Started Aug 16 05:56:35 PM PDT 24
Finished Aug 16 06:01:03 PM PDT 24
Peak memory 239644 kb
Host smart-27e87491-3d14-4775-ab66-1b501066a840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852797515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.852797515
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2722298587
Short name T711
Test name
Test status
Simulation time 2607091593 ps
CPU time 5.44 seconds
Started Aug 16 05:55:52 PM PDT 24
Finished Aug 16 05:55:57 PM PDT 24
Peak memory 216496 kb
Host smart-8a79d497-e680-4e4b-9672-f2b24a91e21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722298587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2722298587
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2471240435
Short name T366
Test name
Test status
Simulation time 2232357819 ps
CPU time 3.14 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:56:00 PM PDT 24
Peak memory 216540 kb
Host smart-15be7729-a11c-437c-aec5-f28a8ce241db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471240435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2471240435
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.58003976
Short name T666
Test name
Test status
Simulation time 29171181 ps
CPU time 0.79 seconds
Started Aug 16 05:55:56 PM PDT 24
Finished Aug 16 05:55:57 PM PDT 24
Peak memory 206132 kb
Host smart-6f6fc3cf-ea63-4d67-9545-62d9aa57fa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58003976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.58003976
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3248735127
Short name T404
Test name
Test status
Simulation time 103149783 ps
CPU time 0.84 seconds
Started Aug 16 05:55:54 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 206156 kb
Host smart-21f191f3-d950-45e5-978c-b4147ffa67a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248735127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3248735127
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1436550369
Short name T133
Test name
Test status
Simulation time 6682855744 ps
CPU time 24.94 seconds
Started Aug 16 05:55:54 PM PDT 24
Finished Aug 16 05:56:19 PM PDT 24
Peak memory 224792 kb
Host smart-f83e35a3-00fb-4729-9491-ea55b6cd4d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436550369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1436550369
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2609272039
Short name T792
Test name
Test status
Simulation time 38107372 ps
CPU time 0.69 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:25 PM PDT 24
Peak memory 204876 kb
Host smart-ecb93289-1a95-47ca-9a77-e0aa5d6b65d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609272039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2609272039
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.790617182
Short name T275
Test name
Test status
Simulation time 1749916368 ps
CPU time 4.96 seconds
Started Aug 16 05:56:01 PM PDT 24
Finished Aug 16 05:56:06 PM PDT 24
Peak memory 232844 kb
Host smart-44f5ef72-48ea-4586-a432-9a69c4ed3d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790617182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.790617182
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2590831265
Short name T503
Test name
Test status
Simulation time 19125195 ps
CPU time 0.77 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 05:55:59 PM PDT 24
Peak memory 206080 kb
Host smart-7bee7315-d0e0-4e9b-bf18-3e4569c66334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590831265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2590831265
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2703876510
Short name T944
Test name
Test status
Simulation time 12248558 ps
CPU time 0.73 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 215784 kb
Host smart-2fa02ef1-a568-4187-af11-40b162ae661c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703876510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2703876510
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2360358430
Short name T259
Test name
Test status
Simulation time 30603863220 ps
CPU time 315.63 seconds
Started Aug 16 05:56:29 PM PDT 24
Finished Aug 16 06:01:45 PM PDT 24
Peak memory 256964 kb
Host smart-0de2d009-a828-4716-b791-fe3847e9141c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360358430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2360358430
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1513612972
Short name T210
Test name
Test status
Simulation time 181448703486 ps
CPU time 351.55 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 06:01:49 PM PDT 24
Peak memory 256544 kb
Host smart-9efb682c-449a-4fcb-ba64-8aa460390773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513612972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1513612972
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1419945918
Short name T473
Test name
Test status
Simulation time 5566760283 ps
CPU time 14.69 seconds
Started Aug 16 05:55:55 PM PDT 24
Finished Aug 16 05:56:10 PM PDT 24
Peak memory 241156 kb
Host smart-9957a08c-d09a-4042-bc4f-fd617a2998b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419945918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1419945918
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1567264966
Short name T798
Test name
Test status
Simulation time 22041260727 ps
CPU time 52.55 seconds
Started Aug 16 05:56:37 PM PDT 24
Finished Aug 16 05:57:29 PM PDT 24
Peak memory 251032 kb
Host smart-880247fc-1749-4da7-8f90-84b67df610a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567264966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1567264966
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2305980346
Short name T194
Test name
Test status
Simulation time 547692394 ps
CPU time 7.64 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 05:56:06 PM PDT 24
Peak memory 224600 kb
Host smart-60be4bef-78b7-4fa5-9a87-e2cce67760e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305980346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2305980346
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2115523059
Short name T579
Test name
Test status
Simulation time 3654580094 ps
CPU time 12.54 seconds
Started Aug 16 05:56:01 PM PDT 24
Finished Aug 16 05:56:14 PM PDT 24
Peak memory 232852 kb
Host smart-cf06a353-9881-4921-ab56-36e6e6e51bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115523059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2115523059
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2447885923
Short name T886
Test name
Test status
Simulation time 517418223 ps
CPU time 5.43 seconds
Started Aug 16 05:56:30 PM PDT 24
Finished Aug 16 05:56:40 PM PDT 24
Peak memory 224680 kb
Host smart-d3d829ff-8298-473f-955d-fa0a69556532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447885923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2447885923
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1645279
Short name T408
Test name
Test status
Simulation time 1070197161 ps
CPU time 3.77 seconds
Started Aug 16 05:56:20 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 232904 kb
Host smart-de3e25e8-81a0-4991-b6b1-2fffcbc23d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1645279
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1832800660
Short name T821
Test name
Test status
Simulation time 1346696248 ps
CPU time 11.87 seconds
Started Aug 16 05:55:56 PM PDT 24
Finished Aug 16 05:56:08 PM PDT 24
Peak memory 219444 kb
Host smart-1dd784b1-da68-4c2a-bf6b-ceade68d4e8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1832800660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1832800660
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.4029128351
Short name T762
Test name
Test status
Simulation time 1978487826 ps
CPU time 38.74 seconds
Started Aug 16 05:56:21 PM PDT 24
Finished Aug 16 05:57:00 PM PDT 24
Peak memory 251324 kb
Host smart-95a5d258-3bef-4fcb-8a24-4e5651d0f83a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029128351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.4029128351
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3342043315
Short name T502
Test name
Test status
Simulation time 21166683166 ps
CPU time 26.68 seconds
Started Aug 16 05:56:40 PM PDT 24
Finished Aug 16 05:57:07 PM PDT 24
Peak memory 216612 kb
Host smart-676a2210-2929-41ed-8026-ca1705743acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342043315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3342043315
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4232739376
Short name T466
Test name
Test status
Simulation time 29800972634 ps
CPU time 19.63 seconds
Started Aug 16 05:55:56 PM PDT 24
Finished Aug 16 05:56:16 PM PDT 24
Peak memory 216604 kb
Host smart-7e3c109b-43a4-4ed4-81b6-7c55496a6e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232739376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4232739376
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1632080504
Short name T925
Test name
Test status
Simulation time 248461395 ps
CPU time 1.41 seconds
Started Aug 16 05:55:54 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 216536 kb
Host smart-6b406f6f-ac84-4fb9-ac32-8fda7fbaf2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632080504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1632080504
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1644306355
Short name T699
Test name
Test status
Simulation time 132170287 ps
CPU time 0.8 seconds
Started Aug 16 05:56:25 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 206036 kb
Host smart-e408cd15-a60d-4d29-89a8-5d6b82f21562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644306355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1644306355
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2381852618
Short name T879
Test name
Test status
Simulation time 160059947 ps
CPU time 2.61 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:56:00 PM PDT 24
Peak memory 224700 kb
Host smart-b940eda3-6d3c-4872-9cea-fd816fcd2fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381852618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2381852618
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.87018055
Short name T1009
Test name
Test status
Simulation time 35054145 ps
CPU time 0.72 seconds
Started Aug 16 05:56:44 PM PDT 24
Finished Aug 16 05:56:45 PM PDT 24
Peak memory 204988 kb
Host smart-a5c75926-e6f6-47a5-a63a-487ab269dd55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87018055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.87018055
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3564250020
Short name T780
Test name
Test status
Simulation time 419674050 ps
CPU time 2.87 seconds
Started Aug 16 05:56:28 PM PDT 24
Finished Aug 16 05:56:31 PM PDT 24
Peak memory 232872 kb
Host smart-78ea1e2b-7064-4e15-87b3-8ad89d42d9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564250020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3564250020
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3040581390
Short name T716
Test name
Test status
Simulation time 36502550 ps
CPU time 0.85 seconds
Started Aug 16 05:55:54 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 206608 kb
Host smart-ae3384cd-a228-451b-bc48-24e938bf2037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040581390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3040581390
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4288837483
Short name T952
Test name
Test status
Simulation time 33902716284 ps
CPU time 260.61 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 06:00:19 PM PDT 24
Peak memory 252388 kb
Host smart-1bafa575-fccd-44a0-a431-291347a5ec77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288837483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4288837483
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1954646075
Short name T57
Test name
Test status
Simulation time 42476491456 ps
CPU time 309.08 seconds
Started Aug 16 05:56:48 PM PDT 24
Finished Aug 16 06:01:57 PM PDT 24
Peak memory 257532 kb
Host smart-e4f78679-7ded-46d0-83b4-0c9079a69a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954646075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1954646075
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2033657125
Short name T31
Test name
Test status
Simulation time 6422870969 ps
CPU time 99.85 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:58:05 PM PDT 24
Peak memory 265836 kb
Host smart-2ca4f602-433d-46a2-868e-627a86c6d2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033657125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2033657125
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.165077667
Short name T238
Test name
Test status
Simulation time 1233028327 ps
CPU time 3.77 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 224640 kb
Host smart-646cc8a0-7c1f-4a32-826e-8ae530e40103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165077667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.165077667
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2009075923
Short name T167
Test name
Test status
Simulation time 116193827314 ps
CPU time 150.21 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 05:58:28 PM PDT 24
Peak memory 256240 kb
Host smart-96434c71-9baa-468e-b47b-6ae9d8217651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009075923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2009075923
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2792379681
Short name T621
Test name
Test status
Simulation time 35902881645 ps
CPU time 20.05 seconds
Started Aug 16 05:57:09 PM PDT 24
Finished Aug 16 05:57:29 PM PDT 24
Peak memory 224700 kb
Host smart-2f60bfb9-6e63-45bf-aad0-6671a39300b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792379681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2792379681
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3707449603
Short name T451
Test name
Test status
Simulation time 1390976006 ps
CPU time 16.12 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:40 PM PDT 24
Peak memory 235016 kb
Host smart-587ec281-12f9-4f95-962d-eb8cff799713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707449603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3707449603
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.971976049
Short name T679
Test name
Test status
Simulation time 2658658038 ps
CPU time 3.9 seconds
Started Aug 16 05:55:54 PM PDT 24
Finished Aug 16 05:55:58 PM PDT 24
Peak memory 224712 kb
Host smart-21fe52c8-a2cb-4290-9343-bc8f8fb65b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971976049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.971976049
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1850027267
Short name T283
Test name
Test status
Simulation time 743186758 ps
CPU time 3.95 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:27 PM PDT 24
Peak memory 232824 kb
Host smart-8fa83d97-e3b6-434c-9543-48a7db599e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850027267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1850027267
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.242512838
Short name T950
Test name
Test status
Simulation time 611759015 ps
CPU time 3.45 seconds
Started Aug 16 05:56:26 PM PDT 24
Finished Aug 16 05:56:30 PM PDT 24
Peak memory 219420 kb
Host smart-dacbd32d-0153-4014-a849-1f596eca8079
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=242512838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.242512838
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1724457470
Short name T686
Test name
Test status
Simulation time 5567567855 ps
CPU time 26.67 seconds
Started Aug 16 05:56:40 PM PDT 24
Finished Aug 16 05:57:07 PM PDT 24
Peak memory 216424 kb
Host smart-dae8c48c-9876-4714-b3d2-51a03b5d4fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724457470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1724457470
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4072190195
Short name T613
Test name
Test status
Simulation time 653079386 ps
CPU time 2.9 seconds
Started Aug 16 05:56:25 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 216308 kb
Host smart-ee595742-f721-42ad-b8a8-7aed187a4af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072190195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4072190195
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3216368668
Short name T470
Test name
Test status
Simulation time 24421377 ps
CPU time 0.91 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:55:58 PM PDT 24
Peak memory 207264 kb
Host smart-66c58642-7b97-4844-96ba-cf1f3b6b3b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216368668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3216368668
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2912614475
Short name T720
Test name
Test status
Simulation time 28464246 ps
CPU time 0.73 seconds
Started Aug 16 05:56:16 PM PDT 24
Finished Aug 16 05:56:17 PM PDT 24
Peak memory 206068 kb
Host smart-2195329b-5740-4a76-af68-45c124db9371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912614475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2912614475
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3748077136
Short name T367
Test name
Test status
Simulation time 27924450848 ps
CPU time 24.12 seconds
Started Aug 16 05:56:34 PM PDT 24
Finished Aug 16 05:56:58 PM PDT 24
Peak memory 232820 kb
Host smart-50b71856-d114-4508-8ea7-e24c1c3fce00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748077136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3748077136
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3942001147
Short name T439
Test name
Test status
Simulation time 42695995 ps
CPU time 0.69 seconds
Started Aug 16 05:55:14 PM PDT 24
Finished Aug 16 05:55:15 PM PDT 24
Peak memory 205584 kb
Host smart-a9cfef90-dae0-4eab-9948-dde5f3476443
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942001147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
942001147
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1591722123
Short name T688
Test name
Test status
Simulation time 134792659 ps
CPU time 2.61 seconds
Started Aug 16 05:54:38 PM PDT 24
Finished Aug 16 05:54:41 PM PDT 24
Peak memory 232876 kb
Host smart-d7953ff7-697e-406f-a082-55ba161efab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591722123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1591722123
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1802007518
Short name T800
Test name
Test status
Simulation time 30151757 ps
CPU time 0.78 seconds
Started Aug 16 05:55:09 PM PDT 24
Finished Aug 16 05:55:10 PM PDT 24
Peak memory 206508 kb
Host smart-46bd79bc-32e5-41e7-9bdc-f3bf680fe782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802007518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1802007518
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.349214573
Short name T249
Test name
Test status
Simulation time 13015299444 ps
CPU time 86.68 seconds
Started Aug 16 05:54:52 PM PDT 24
Finished Aug 16 05:56:19 PM PDT 24
Peak memory 252624 kb
Host smart-8c8691a9-253b-4445-9cca-301c17da19f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349214573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.349214573
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1096643540
Short name T172
Test name
Test status
Simulation time 8350995482 ps
CPU time 82.92 seconds
Started Aug 16 05:55:18 PM PDT 24
Finished Aug 16 05:56:41 PM PDT 24
Peak memory 253908 kb
Host smart-6ccbe192-193a-44e9-8df2-bb5123d56499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096643540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1096643540
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.926980704
Short name T138
Test name
Test status
Simulation time 7547667517 ps
CPU time 21.76 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 05:55:45 PM PDT 24
Peak memory 238428 kb
Host smart-4d40a9eb-f1d7-4b1c-a950-3b27bc7848c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926980704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
926980704
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.476502111
Short name T396
Test name
Test status
Simulation time 5709291669 ps
CPU time 7.71 seconds
Started Aug 16 05:54:38 PM PDT 24
Finished Aug 16 05:54:46 PM PDT 24
Peak memory 232948 kb
Host smart-c901ab98-d0f7-4cae-a55f-35b8474198e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476502111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.476502111
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3959887204
Short name T930
Test name
Test status
Simulation time 11126333497 ps
CPU time 43.54 seconds
Started Aug 16 05:55:04 PM PDT 24
Finished Aug 16 05:55:48 PM PDT 24
Peak memory 239988 kb
Host smart-c14b8236-4dc8-4b39-90df-8705b25d2369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959887204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3959887204
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2748969569
Short name T377
Test name
Test status
Simulation time 36718037 ps
CPU time 2.92 seconds
Started Aug 16 05:54:29 PM PDT 24
Finished Aug 16 05:54:32 PM PDT 24
Peak memory 232892 kb
Host smart-95ec9ef9-b671-42c8-8609-a985fee3c721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748969569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2748969569
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1070002468
Short name T468
Test name
Test status
Simulation time 5027560577 ps
CPU time 39.42 seconds
Started Aug 16 05:54:37 PM PDT 24
Finished Aug 16 05:55:17 PM PDT 24
Peak memory 224756 kb
Host smart-e2c07d42-705b-4a56-9df5-7a4c7cdaf0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070002468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1070002468
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3777940576
Short name T495
Test name
Test status
Simulation time 52082734 ps
CPU time 1.04 seconds
Started Aug 16 05:54:27 PM PDT 24
Finished Aug 16 05:54:28 PM PDT 24
Peak memory 216752 kb
Host smart-723cae1a-a2e1-4e03-96f8-120ea4c0480d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777940576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3777940576
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2438756032
Short name T680
Test name
Test status
Simulation time 1180734663 ps
CPU time 9.59 seconds
Started Aug 16 05:54:26 PM PDT 24
Finished Aug 16 05:54:40 PM PDT 24
Peak memory 240896 kb
Host smart-eb2a993d-80a3-4ddc-abf0-326284b02024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438756032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2438756032
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3610150543
Short name T908
Test name
Test status
Simulation time 8429756141 ps
CPU time 9.36 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:44 PM PDT 24
Peak memory 232896 kb
Host smart-c79ea76b-319d-48e6-b3c7-c9384de647e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610150543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3610150543
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3267885057
Short name T998
Test name
Test status
Simulation time 1893005214 ps
CPU time 14.43 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:55:02 PM PDT 24
Peak memory 220308 kb
Host smart-2b4f538d-25ae-446a-88b4-2d2cb9edf3f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3267885057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3267885057
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1669474475
Short name T28
Test name
Test status
Simulation time 289888317 ps
CPU time 1.11 seconds
Started Aug 16 05:54:33 PM PDT 24
Finished Aug 16 05:54:34 PM PDT 24
Peak memory 235640 kb
Host smart-52fc441e-b9db-40de-b1f9-5898b87e0a9e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669474475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1669474475
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1390599329
Short name T316
Test name
Test status
Simulation time 94541970127 ps
CPU time 221.72 seconds
Started Aug 16 05:55:51 PM PDT 24
Finished Aug 16 05:59:33 PM PDT 24
Peak memory 273980 kb
Host smart-4fd814dc-012d-4153-90b5-c26d249b7d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390599329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1390599329
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3498339606
Short name T766
Test name
Test status
Simulation time 1799188722 ps
CPU time 26.54 seconds
Started Aug 16 05:54:27 PM PDT 24
Finished Aug 16 05:54:53 PM PDT 24
Peak memory 216728 kb
Host smart-aebf08ef-dff1-4298-ac27-2e2a618a48ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498339606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3498339606
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3368433590
Short name T71
Test name
Test status
Simulation time 528675733 ps
CPU time 1.18 seconds
Started Aug 16 05:54:29 PM PDT 24
Finished Aug 16 05:54:35 PM PDT 24
Peak memory 207148 kb
Host smart-1d935176-c722-4dbb-89b2-b9be0aeef727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368433590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3368433590
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3811813456
Short name T332
Test name
Test status
Simulation time 250486812 ps
CPU time 1.48 seconds
Started Aug 16 05:54:29 PM PDT 24
Finished Aug 16 05:54:31 PM PDT 24
Peak memory 216460 kb
Host smart-0afa1d85-5915-49e3-971d-29efdc740adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811813456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3811813456
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3887505252
Short name T981
Test name
Test status
Simulation time 265949540 ps
CPU time 0.89 seconds
Started Aug 16 05:54:25 PM PDT 24
Finished Aug 16 05:54:26 PM PDT 24
Peak memory 206076 kb
Host smart-d6c6463a-d793-4a88-9ce2-62c8499a1064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887505252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3887505252
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3816772670
Short name T1002
Test name
Test status
Simulation time 1283193864 ps
CPU time 9.16 seconds
Started Aug 16 05:54:41 PM PDT 24
Finished Aug 16 05:54:50 PM PDT 24
Peak memory 232904 kb
Host smart-da8bb0f2-6e00-4b9c-ae1f-c5bca1698a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816772670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3816772670
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1411537144
Short name T496
Test name
Test status
Simulation time 54322306 ps
CPU time 0.7 seconds
Started Aug 16 05:56:35 PM PDT 24
Finished Aug 16 05:56:36 PM PDT 24
Peak memory 204976 kb
Host smart-41ef6b55-e0f3-41b4-94ad-0cec4f2937e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411537144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1411537144
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1099404716
Short name T90
Test name
Test status
Simulation time 308472013 ps
CPU time 4.46 seconds
Started Aug 16 05:56:36 PM PDT 24
Finished Aug 16 05:56:41 PM PDT 24
Peak memory 232784 kb
Host smart-8190e073-74a1-4a18-8b2f-31966426a350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099404716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1099404716
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2695060831
Short name T463
Test name
Test status
Simulation time 44410621 ps
CPU time 0.77 seconds
Started Aug 16 05:56:01 PM PDT 24
Finished Aug 16 05:56:01 PM PDT 24
Peak memory 205856 kb
Host smart-36791dfd-813c-4e5a-9628-91a32d1e818a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695060831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2695060831
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2776928722
Short name T193
Test name
Test status
Simulation time 14781539053 ps
CPU time 25.48 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:49 PM PDT 24
Peak memory 241172 kb
Host smart-8fea4eb9-40f8-4300-8840-9344a282dfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776928722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2776928722
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1193870952
Short name T48
Test name
Test status
Simulation time 35066111285 ps
CPU time 327.63 seconds
Started Aug 16 05:55:56 PM PDT 24
Finished Aug 16 06:01:23 PM PDT 24
Peak memory 267636 kb
Host smart-e2e5afc6-c8e4-4a81-83a0-8c9a0c765211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193870952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1193870952
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.828790604
Short name T909
Test name
Test status
Simulation time 19955713260 ps
CPU time 209.48 seconds
Started Aug 16 05:56:40 PM PDT 24
Finished Aug 16 06:00:10 PM PDT 24
Peak memory 256860 kb
Host smart-ca669719-9ecb-4a99-b9cd-dbb6f4dc1c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828790604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.828790604
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4122210771
Short name T701
Test name
Test status
Simulation time 1960860325 ps
CPU time 17.58 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:42 PM PDT 24
Peak memory 240904 kb
Host smart-07daee97-828a-4a5a-b8ba-4479e190c525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122210771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4122210771
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2208505301
Short name T934
Test name
Test status
Simulation time 13922536 ps
CPU time 0.75 seconds
Started Aug 16 05:56:46 PM PDT 24
Finished Aug 16 05:56:47 PM PDT 24
Peak memory 215784 kb
Host smart-1b724cf0-f22f-412a-aad0-a7251d0550a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208505301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2208505301
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1250933035
Short name T250
Test name
Test status
Simulation time 156009417 ps
CPU time 2.87 seconds
Started Aug 16 05:55:59 PM PDT 24
Finished Aug 16 05:56:02 PM PDT 24
Peak memory 232864 kb
Host smart-8856f9ce-799c-4ff6-8c4b-f0c16d4f4856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250933035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1250933035
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3581340565
Short name T721
Test name
Test status
Simulation time 22123055422 ps
CPU time 50.17 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:57:14 PM PDT 24
Peak memory 235684 kb
Host smart-429a779d-3c6a-42e1-aa02-d414641929e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581340565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3581340565
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.861041805
Short name T661
Test name
Test status
Simulation time 34858082460 ps
CPU time 18.23 seconds
Started Aug 16 05:56:38 PM PDT 24
Finished Aug 16 05:56:57 PM PDT 24
Peak memory 232916 kb
Host smart-8e1edbb7-4f14-4cdd-ba3a-d341d0cb9349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861041805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.861041805
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2590854691
Short name T14
Test name
Test status
Simulation time 1169476170 ps
CPU time 6.31 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 05:56:05 PM PDT 24
Peak memory 232876 kb
Host smart-e9a7db92-7f8a-4e62-ac7f-09091fe3ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590854691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2590854691
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2510215653
Short name T837
Test name
Test status
Simulation time 959854644 ps
CPU time 11.79 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 05:56:10 PM PDT 24
Peak memory 221656 kb
Host smart-6edd30ab-6bba-4df6-996f-03430a341fe6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2510215653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2510215653
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.653458241
Short name T804
Test name
Test status
Simulation time 81775280836 ps
CPU time 210.11 seconds
Started Aug 16 05:56:52 PM PDT 24
Finished Aug 16 06:00:22 PM PDT 24
Peak memory 266360 kb
Host smart-47d2fe5c-a0ab-4408-b73f-0ae76c477c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653458241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.653458241
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3010424688
Short name T546
Test name
Test status
Simulation time 603954714 ps
CPU time 4.47 seconds
Started Aug 16 05:56:48 PM PDT 24
Finished Aug 16 05:56:52 PM PDT 24
Peak memory 217756 kb
Host smart-d9d9495b-f325-4acd-a462-c55579955d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010424688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3010424688
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3498950675
Short name T589
Test name
Test status
Simulation time 4016799989 ps
CPU time 11.87 seconds
Started Aug 16 05:56:35 PM PDT 24
Finished Aug 16 05:56:47 PM PDT 24
Peak memory 216524 kb
Host smart-5d1b4acf-0a70-4bac-ab23-cfcf5e150df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498950675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3498950675
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3011132451
Short name T402
Test name
Test status
Simulation time 265600049 ps
CPU time 3.12 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:56:01 PM PDT 24
Peak memory 216476 kb
Host smart-649d8457-1910-40ae-be7f-5d396b79f301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011132451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3011132451
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1039694191
Short name T1018
Test name
Test status
Simulation time 52996003 ps
CPU time 0.7 seconds
Started Aug 16 05:56:26 PM PDT 24
Finished Aug 16 05:56:27 PM PDT 24
Peak memory 206068 kb
Host smart-e14a239c-4797-49d9-ac19-980eab53ab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039694191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1039694191
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3840086606
Short name T93
Test name
Test status
Simulation time 3100434943 ps
CPU time 10.83 seconds
Started Aug 16 05:56:27 PM PDT 24
Finished Aug 16 05:56:37 PM PDT 24
Peak memory 232892 kb
Host smart-687a897a-2ad3-4a53-87ec-688ef27ab292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840086606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3840086606
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1662859283
Short name T343
Test name
Test status
Simulation time 20510940 ps
CPU time 0.71 seconds
Started Aug 16 05:56:36 PM PDT 24
Finished Aug 16 05:56:37 PM PDT 24
Peak memory 205572 kb
Host smart-0efcd8bc-50bd-41a2-a866-fe99896d5e01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662859283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1662859283
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.88804579
Short name T982
Test name
Test status
Simulation time 1371664377 ps
CPU time 6.23 seconds
Started Aug 16 05:55:58 PM PDT 24
Finished Aug 16 05:56:04 PM PDT 24
Peak memory 224624 kb
Host smart-99896118-bd72-4cbb-8177-68b89add4525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88804579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.88804579
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1377394298
Short name T937
Test name
Test status
Simulation time 13409895 ps
CPU time 0.75 seconds
Started Aug 16 05:56:26 PM PDT 24
Finished Aug 16 05:56:32 PM PDT 24
Peak memory 206508 kb
Host smart-5b86a951-514f-4d71-a7a0-1f4afe6beaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377394298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1377394298
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3391105215
Short name T786
Test name
Test status
Simulation time 1981866523 ps
CPU time 41.15 seconds
Started Aug 16 05:56:07 PM PDT 24
Finished Aug 16 05:56:49 PM PDT 24
Peak memory 254392 kb
Host smart-d5afdff6-2cb5-4d17-93b6-9dcabd38ae4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391105215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3391105215
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1230246938
Short name T920
Test name
Test status
Simulation time 1560350836 ps
CPU time 28.19 seconds
Started Aug 16 05:56:07 PM PDT 24
Finished Aug 16 05:56:35 PM PDT 24
Peak memory 249868 kb
Host smart-c3e34204-712a-4f95-ab5d-24e16f81265e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230246938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1230246938
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2767029312
Short name T54
Test name
Test status
Simulation time 24851416005 ps
CPU time 183.24 seconds
Started Aug 16 05:56:08 PM PDT 24
Finished Aug 16 05:59:12 PM PDT 24
Peak memory 254464 kb
Host smart-839ed5bb-ede6-4772-9759-a27659e8844a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767029312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2767029312
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3614603239
Short name T862
Test name
Test status
Simulation time 323176472 ps
CPU time 2.31 seconds
Started Aug 16 05:56:20 PM PDT 24
Finished Aug 16 05:56:23 PM PDT 24
Peak memory 224688 kb
Host smart-8ad5c6c0-6a51-41b0-a8cf-3613da62eaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614603239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3614603239
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2502002382
Short name T669
Test name
Test status
Simulation time 4717764275 ps
CPU time 17.18 seconds
Started Aug 16 05:56:44 PM PDT 24
Finished Aug 16 05:57:02 PM PDT 24
Peak memory 232764 kb
Host smart-e44e0c68-02c9-4c1e-bb64-8d363e76bef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502002382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2502002382
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4051190516
Short name T712
Test name
Test status
Simulation time 286689073 ps
CPU time 5.3 seconds
Started Aug 16 05:56:01 PM PDT 24
Finished Aug 16 05:56:06 PM PDT 24
Peak memory 224648 kb
Host smart-20226447-b009-4c35-9dec-ff9a7d6c4698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051190516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4051190516
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2033307310
Short name T889
Test name
Test status
Simulation time 3396786443 ps
CPU time 15.08 seconds
Started Aug 16 05:55:59 PM PDT 24
Finished Aug 16 05:56:14 PM PDT 24
Peak memory 232924 kb
Host smart-c79c4c90-7706-4a74-89c7-f020226bc3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033307310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2033307310
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2230593588
Short name T1029
Test name
Test status
Simulation time 153256636 ps
CPU time 2.12 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:55:59 PM PDT 24
Peak memory 224540 kb
Host smart-b76f8a31-f209-4a37-b67a-cc2b6c1cc50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230593588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2230593588
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.129421285
Short name T559
Test name
Test status
Simulation time 44607023071 ps
CPU time 25.92 seconds
Started Aug 16 05:55:59 PM PDT 24
Finished Aug 16 05:56:25 PM PDT 24
Peak memory 232976 kb
Host smart-a1cf4fb3-866c-4847-982e-64c19bfe61ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129421285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.129421285
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.6979311
Short name T385
Test name
Test status
Simulation time 4669003488 ps
CPU time 12.83 seconds
Started Aug 16 05:56:09 PM PDT 24
Finished Aug 16 05:56:22 PM PDT 24
Peak memory 223236 kb
Host smart-783cba00-4b6a-4937-9e76-cfc2733efbb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=6979311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.6979311
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.900719459
Short name T159
Test name
Test status
Simulation time 18329992825 ps
CPU time 131.02 seconds
Started Aug 16 05:56:35 PM PDT 24
Finished Aug 16 05:58:46 PM PDT 24
Peak memory 234748 kb
Host smart-3c8aa2de-f7c9-433e-b6a2-8ed2a3f578d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900719459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.900719459
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.34930106
Short name T353
Test name
Test status
Simulation time 3736623223 ps
CPU time 8.03 seconds
Started Aug 16 05:56:29 PM PDT 24
Finished Aug 16 05:56:37 PM PDT 24
Peak memory 216848 kb
Host smart-a85009bb-d039-4184-a3bd-f4c11c9069d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34930106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.34930106
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4141786588
Short name T977
Test name
Test status
Simulation time 8462746320 ps
CPU time 22.96 seconds
Started Aug 16 05:56:47 PM PDT 24
Finished Aug 16 05:57:10 PM PDT 24
Peak memory 216548 kb
Host smart-b7e897b5-ad74-4cf2-bbaf-27a80d7a3132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141786588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4141786588
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1058936166
Short name T812
Test name
Test status
Simulation time 184302691 ps
CPU time 2.29 seconds
Started Aug 16 05:56:33 PM PDT 24
Finished Aug 16 05:56:35 PM PDT 24
Peak memory 216516 kb
Host smart-67f387b2-61b6-4797-a8f3-34fd6fe4c952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058936166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1058936166
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1107275975
Short name T727
Test name
Test status
Simulation time 210803716 ps
CPU time 0.8 seconds
Started Aug 16 05:55:57 PM PDT 24
Finished Aug 16 05:55:58 PM PDT 24
Peak memory 206116 kb
Host smart-4a24af6a-545e-45e4-b3a6-fa8520cf220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107275975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1107275975
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1126817658
Short name T507
Test name
Test status
Simulation time 2426461238 ps
CPU time 5.45 seconds
Started Aug 16 05:56:30 PM PDT 24
Finished Aug 16 05:56:35 PM PDT 24
Peak memory 232976 kb
Host smart-6bae0166-6018-4a00-bbfc-ee6008a1b6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126817658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1126817658
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3536334839
Short name T1032
Test name
Test status
Simulation time 42677804 ps
CPU time 0.75 seconds
Started Aug 16 05:56:28 PM PDT 24
Finished Aug 16 05:56:29 PM PDT 24
Peak memory 204936 kb
Host smart-65ab744c-8062-417b-b82b-ed81c755ce8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536334839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3536334839
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.687659618
Short name T88
Test name
Test status
Simulation time 6803464609 ps
CPU time 13.07 seconds
Started Aug 16 05:56:26 PM PDT 24
Finished Aug 16 05:56:39 PM PDT 24
Peak memory 232936 kb
Host smart-c5bd725c-2ea2-4da8-8690-702f9bcb1999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687659618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.687659618
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.665702078
Short name T504
Test name
Test status
Simulation time 36074794 ps
CPU time 0.81 seconds
Started Aug 16 05:56:30 PM PDT 24
Finished Aug 16 05:56:31 PM PDT 24
Peak memory 206608 kb
Host smart-2ac61f52-0a68-464f-970c-ee52ee8ad721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665702078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.665702078
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4168032590
Short name T992
Test name
Test status
Simulation time 20769793286 ps
CPU time 26.95 seconds
Started Aug 16 05:56:55 PM PDT 24
Finished Aug 16 05:57:22 PM PDT 24
Peak memory 217796 kb
Host smart-7367ae9e-94e3-428f-97a1-1a2265d45c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168032590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4168032590
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3744897008
Short name T832
Test name
Test status
Simulation time 4832544592 ps
CPU time 21.42 seconds
Started Aug 16 05:56:07 PM PDT 24
Finished Aug 16 05:56:29 PM PDT 24
Peak memory 233024 kb
Host smart-efcb5f15-f7bf-429e-a7a9-f4dad65997db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744897008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3744897008
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.567799686
Short name T607
Test name
Test status
Simulation time 11220329647 ps
CPU time 38.23 seconds
Started Aug 16 05:56:48 PM PDT 24
Finished Aug 16 05:57:27 PM PDT 24
Peak memory 252844 kb
Host smart-fd402e4d-cd9f-45fa-903e-450984d44e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567799686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.567799686
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1336107298
Short name T375
Test name
Test status
Simulation time 1428150931 ps
CPU time 3.61 seconds
Started Aug 16 05:56:06 PM PDT 24
Finished Aug 16 05:56:09 PM PDT 24
Peak memory 232888 kb
Host smart-54d96767-f349-4fd4-b267-5a5742a56a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336107298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1336107298
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1077182300
Short name T983
Test name
Test status
Simulation time 8167207885 ps
CPU time 27.24 seconds
Started Aug 16 05:56:09 PM PDT 24
Finished Aug 16 05:56:36 PM PDT 24
Peak memory 249388 kb
Host smart-d2a6fe92-6790-461f-9a17-19d9dc22c5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077182300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1077182300
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3399690063
Short name T760
Test name
Test status
Simulation time 1841522784 ps
CPU time 7.17 seconds
Started Aug 16 05:56:06 PM PDT 24
Finished Aug 16 05:56:14 PM PDT 24
Peak memory 224684 kb
Host smart-37bd0736-0f7e-4e8a-b9ce-87d31a92cfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399690063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3399690063
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.627869354
Short name T356
Test name
Test status
Simulation time 78832831 ps
CPU time 2.26 seconds
Started Aug 16 05:56:25 PM PDT 24
Finished Aug 16 05:56:27 PM PDT 24
Peak memory 223864 kb
Host smart-b0e5d363-7929-4d0c-9d8c-43f46c180385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627869354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.627869354
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2495704088
Short name T524
Test name
Test status
Simulation time 3796065511 ps
CPU time 6.49 seconds
Started Aug 16 05:57:04 PM PDT 24
Finished Aug 16 05:57:11 PM PDT 24
Peak memory 223308 kb
Host smart-a3173cb3-4fbb-4df9-89e1-faa8b77112a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2495704088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2495704088
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2841692753
Short name T20
Test name
Test status
Simulation time 57537522 ps
CPU time 1.03 seconds
Started Aug 16 05:56:10 PM PDT 24
Finished Aug 16 05:56:11 PM PDT 24
Peak memory 206964 kb
Host smart-69000648-ee90-4da0-8d0f-862538f9a777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841692753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2841692753
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1115696268
Short name T547
Test name
Test status
Simulation time 374519147 ps
CPU time 2.82 seconds
Started Aug 16 05:56:11 PM PDT 24
Finished Aug 16 05:56:14 PM PDT 24
Peak memory 216644 kb
Host smart-202472fb-2170-464d-925a-d0c2737653ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115696268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1115696268
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.246708997
Short name T580
Test name
Test status
Simulation time 1089958606 ps
CPU time 4.46 seconds
Started Aug 16 05:56:08 PM PDT 24
Finished Aug 16 05:56:13 PM PDT 24
Peak memory 216416 kb
Host smart-49b8763f-4814-4fc8-a664-d1f18ef0d312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246708997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.246708997
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2040651169
Short name T517
Test name
Test status
Simulation time 76097636 ps
CPU time 1.65 seconds
Started Aug 16 05:56:34 PM PDT 24
Finished Aug 16 05:56:36 PM PDT 24
Peak memory 216464 kb
Host smart-9c153223-e522-427e-bb68-1bf0a652f566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040651169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2040651169
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3473867725
Short name T753
Test name
Test status
Simulation time 136468214 ps
CPU time 0.87 seconds
Started Aug 16 05:56:08 PM PDT 24
Finished Aug 16 05:56:09 PM PDT 24
Peak memory 206036 kb
Host smart-9fa65272-8244-4a15-82ec-17afda88c504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473867725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3473867725
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2440024365
Short name T610
Test name
Test status
Simulation time 331896883 ps
CPU time 5.12 seconds
Started Aug 16 05:56:55 PM PDT 24
Finished Aug 16 05:57:00 PM PDT 24
Peak memory 239784 kb
Host smart-028fed63-d684-4d71-919f-279e7546aa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440024365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2440024365
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.207075096
Short name T877
Test name
Test status
Simulation time 29764539 ps
CPU time 0.72 seconds
Started Aug 16 05:56:11 PM PDT 24
Finished Aug 16 05:56:12 PM PDT 24
Peak memory 205892 kb
Host smart-583cbb2c-e2a9-4dc3-877d-1c7622a9a5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207075096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.207075096
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1475235562
Short name T471
Test name
Test status
Simulation time 902903347 ps
CPU time 10.59 seconds
Started Aug 16 05:56:07 PM PDT 24
Finished Aug 16 05:56:18 PM PDT 24
Peak memory 224708 kb
Host smart-9126c7e0-d729-4dd1-b16f-12a77abfbe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475235562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1475235562
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.734970060
Short name T60
Test name
Test status
Simulation time 17677156 ps
CPU time 0.75 seconds
Started Aug 16 05:56:08 PM PDT 24
Finished Aug 16 05:56:08 PM PDT 24
Peak memory 205932 kb
Host smart-c77b541b-1ec8-41ed-a598-002749952e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734970060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.734970060
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.132615317
Short name T486
Test name
Test status
Simulation time 9564596674 ps
CPU time 96.4 seconds
Started Aug 16 05:56:32 PM PDT 24
Finished Aug 16 05:58:08 PM PDT 24
Peak memory 249264 kb
Host smart-59063183-279f-4134-ac2e-a9d3ef1454da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132615317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.132615317
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4059784728
Short name T311
Test name
Test status
Simulation time 35251265123 ps
CPU time 410.32 seconds
Started Aug 16 05:56:08 PM PDT 24
Finished Aug 16 06:02:58 PM PDT 24
Peak memory 266912 kb
Host smart-6757ec76-f7c7-4f38-b78a-2e227cc7d9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059784728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4059784728
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2892289902
Short name T601
Test name
Test status
Simulation time 53376417395 ps
CPU time 280.38 seconds
Started Aug 16 05:56:26 PM PDT 24
Finished Aug 16 06:01:07 PM PDT 24
Peak memory 241004 kb
Host smart-0246c200-d29d-4f89-989f-cbe1c99ed70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892289902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2892289902
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.879762763
Short name T72
Test name
Test status
Simulation time 9556186478 ps
CPU time 62.77 seconds
Started Aug 16 05:56:45 PM PDT 24
Finished Aug 16 05:57:48 PM PDT 24
Peak memory 250280 kb
Host smart-0436292e-ee84-4597-af13-1d00b946d443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879762763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.879762763
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2529361333
Short name T223
Test name
Test status
Simulation time 328502563 ps
CPU time 6.59 seconds
Started Aug 16 05:56:31 PM PDT 24
Finished Aug 16 05:56:38 PM PDT 24
Peak memory 232936 kb
Host smart-c3cdc010-4f98-4ecd-a885-a47b6974aa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529361333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2529361333
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2840772715
Short name T261
Test name
Test status
Simulation time 838328182 ps
CPU time 7.14 seconds
Started Aug 16 05:56:11 PM PDT 24
Finished Aug 16 05:56:18 PM PDT 24
Peak memory 235124 kb
Host smart-4209c574-421d-4dea-90b9-634226ccec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840772715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2840772715
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.137409564
Short name T246
Test name
Test status
Simulation time 26291552451 ps
CPU time 18.91 seconds
Started Aug 16 05:56:09 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 224756 kb
Host smart-bd12e54a-3002-4603-bf6a-cde3c8f62d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137409564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.137409564
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3530273797
Short name T735
Test name
Test status
Simulation time 962170065 ps
CPU time 4.86 seconds
Started Aug 16 05:56:08 PM PDT 24
Finished Aug 16 05:56:13 PM PDT 24
Peak memory 224688 kb
Host smart-c4090efe-aefc-46b3-8dc3-737c4da28888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530273797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3530273797
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2863977938
Short name T705
Test name
Test status
Simulation time 632376728 ps
CPU time 4.67 seconds
Started Aug 16 05:56:11 PM PDT 24
Finished Aug 16 05:56:16 PM PDT 24
Peak memory 223264 kb
Host smart-de551b5e-51e9-49b2-93c7-9b8521229118
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2863977938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2863977938
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3464311427
Short name T164
Test name
Test status
Simulation time 30082412677 ps
CPU time 33.13 seconds
Started Aug 16 05:56:11 PM PDT 24
Finished Aug 16 05:56:44 PM PDT 24
Peak memory 232968 kb
Host smart-a59942df-c8e5-4037-8a08-e3eb46ef319d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464311427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3464311427
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3153644114
Short name T406
Test name
Test status
Simulation time 7345151541 ps
CPU time 22.32 seconds
Started Aug 16 05:56:07 PM PDT 24
Finished Aug 16 05:56:34 PM PDT 24
Peak memory 220352 kb
Host smart-00369b03-429b-4f73-b0e1-48be78e6b413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153644114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3153644114
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4291460873
Short name T1025
Test name
Test status
Simulation time 3774868607 ps
CPU time 5.68 seconds
Started Aug 16 05:56:06 PM PDT 24
Finished Aug 16 05:56:12 PM PDT 24
Peak memory 216532 kb
Host smart-515c6145-5d97-4ed9-ac65-1061ad6685b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291460873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4291460873
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3164894359
Short name T754
Test name
Test status
Simulation time 35843332 ps
CPU time 1.64 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 216472 kb
Host smart-9a5ce6ad-6a32-4728-a8ca-7498c3c6aeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164894359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3164894359
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3595000559
Short name T864
Test name
Test status
Simulation time 126378466 ps
CPU time 0.9 seconds
Started Aug 16 05:56:08 PM PDT 24
Finished Aug 16 05:56:09 PM PDT 24
Peak memory 206056 kb
Host smart-b495d8b8-6a67-461f-aee9-29aeb69d3f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595000559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3595000559
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.418438632
Short name T252
Test name
Test status
Simulation time 755658424 ps
CPU time 4.01 seconds
Started Aug 16 05:56:56 PM PDT 24
Finished Aug 16 05:57:00 PM PDT 24
Peak memory 232812 kb
Host smart-d71bffff-e8d1-46aa-b3ff-cadfcf8f78d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418438632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.418438632
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3063540490
Short name T465
Test name
Test status
Simulation time 39123454 ps
CPU time 0.73 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 205476 kb
Host smart-edadbd40-5681-4be6-a3af-fd94a7a4db1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063540490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3063540490
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3471415514
Short name T881
Test name
Test status
Simulation time 117956412 ps
CPU time 2.45 seconds
Started Aug 16 05:56:57 PM PDT 24
Finished Aug 16 05:57:00 PM PDT 24
Peak memory 232732 kb
Host smart-0991da19-18ce-4836-8731-16449528370b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471415514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3471415514
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.628740367
Short name T347
Test name
Test status
Simulation time 16268724 ps
CPU time 0.76 seconds
Started Aug 16 05:56:09 PM PDT 24
Finished Aug 16 05:56:10 PM PDT 24
Peak memory 205588 kb
Host smart-3980ea39-88dc-4d54-a908-9d806e25bbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628740367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.628740367
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2425146345
Short name T997
Test name
Test status
Simulation time 9577074552 ps
CPU time 41.67 seconds
Started Aug 16 05:57:11 PM PDT 24
Finished Aug 16 05:57:52 PM PDT 24
Peak memory 241100 kb
Host smart-7542b15f-b221-4491-9a1a-e71df4b6b330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425146345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2425146345
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2843773299
Short name T511
Test name
Test status
Simulation time 2324702084 ps
CPU time 33.1 seconds
Started Aug 16 05:56:57 PM PDT 24
Finished Aug 16 05:57:30 PM PDT 24
Peak memory 224812 kb
Host smart-4e2b00f2-38b6-4ceb-8751-b2f0d4d145ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843773299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2843773299
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2424345188
Short name T328
Test name
Test status
Simulation time 3534242945 ps
CPU time 30.8 seconds
Started Aug 16 05:57:04 PM PDT 24
Finished Aug 16 05:57:35 PM PDT 24
Peak memory 249360 kb
Host smart-8741b7ad-1aad-494c-b638-e797a8e7530e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424345188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2424345188
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.797009157
Short name T457
Test name
Test status
Simulation time 1768054952 ps
CPU time 27.35 seconds
Started Aug 16 05:56:16 PM PDT 24
Finished Aug 16 05:56:43 PM PDT 24
Peak memory 232912 kb
Host smart-8b1c57b9-46b5-4474-b44e-1465151a5df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797009157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.797009157
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.176113095
Short name T518
Test name
Test status
Simulation time 2295155776 ps
CPU time 22.65 seconds
Started Aug 16 05:56:14 PM PDT 24
Finished Aug 16 05:56:37 PM PDT 24
Peak memory 238540 kb
Host smart-208dcb4f-5c12-451a-a9aa-997777f9d5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176113095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.176113095
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3699247346
Short name T212
Test name
Test status
Simulation time 1226836062 ps
CPU time 14.3 seconds
Started Aug 16 05:56:22 PM PDT 24
Finished Aug 16 05:56:36 PM PDT 24
Peak memory 232912 kb
Host smart-b145c17c-a57c-4a0d-9591-e040f895fbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699247346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3699247346
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2111295318
Short name T437
Test name
Test status
Simulation time 27591585148 ps
CPU time 61.82 seconds
Started Aug 16 05:56:59 PM PDT 24
Finished Aug 16 05:58:01 PM PDT 24
Peak memory 249112 kb
Host smart-e9e76e79-7b0f-490a-aabb-d8eb86a108bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111295318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2111295318
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.397978902
Short name T584
Test name
Test status
Simulation time 3455948090 ps
CPU time 13.26 seconds
Started Aug 16 05:57:01 PM PDT 24
Finished Aug 16 05:57:14 PM PDT 24
Peak memory 240828 kb
Host smart-b4579d6f-05d3-42dd-bf45-d5903bd6ee62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397978902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.397978902
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2720565872
Short name T535
Test name
Test status
Simulation time 153226504 ps
CPU time 3.94 seconds
Started Aug 16 05:56:14 PM PDT 24
Finished Aug 16 05:56:18 PM PDT 24
Peak memory 232868 kb
Host smart-4b512d1f-05f6-495a-8134-898d0ebf8e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720565872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2720565872
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1781044687
Short name T145
Test name
Test status
Simulation time 2345486619 ps
CPU time 4.72 seconds
Started Aug 16 05:57:04 PM PDT 24
Finished Aug 16 05:57:08 PM PDT 24
Peak memory 223116 kb
Host smart-97690185-7989-4a42-babe-efea3c040b3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1781044687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1781044687
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1940090529
Short name T160
Test name
Test status
Simulation time 551658653 ps
CPU time 13.85 seconds
Started Aug 16 05:56:52 PM PDT 24
Finished Aug 16 05:57:06 PM PDT 24
Peak memory 232952 kb
Host smart-79979c07-dad0-4397-9beb-59ceca271252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940090529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1940090529
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3834797272
Short name T331
Test name
Test status
Simulation time 3871391826 ps
CPU time 20.74 seconds
Started Aug 16 05:56:09 PM PDT 24
Finished Aug 16 05:56:30 PM PDT 24
Peak memory 216588 kb
Host smart-db9b051e-727c-4209-b3ed-b1e914605600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834797272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3834797272
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1377635459
Short name T501
Test name
Test status
Simulation time 64563445 ps
CPU time 0.71 seconds
Started Aug 16 05:56:07 PM PDT 24
Finished Aug 16 05:56:08 PM PDT 24
Peak memory 205736 kb
Host smart-83f6a481-ed7a-4b15-b53f-375c13569f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377635459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1377635459
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.646720692
Short name T746
Test name
Test status
Simulation time 79237053 ps
CPU time 1.25 seconds
Started Aug 16 05:56:18 PM PDT 24
Finished Aug 16 05:56:19 PM PDT 24
Peak memory 208100 kb
Host smart-917cdc8b-5aa1-4b70-b597-b65109156c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646720692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.646720692
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3196665361
Short name T446
Test name
Test status
Simulation time 224731764 ps
CPU time 0.85 seconds
Started Aug 16 05:56:17 PM PDT 24
Finished Aug 16 05:56:18 PM PDT 24
Peak memory 206152 kb
Host smart-f7c70e48-f5e8-491c-9804-c753f8cf5953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196665361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3196665361
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2024237429
Short name T549
Test name
Test status
Simulation time 781677048 ps
CPU time 5.88 seconds
Started Aug 16 05:56:22 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 224692 kb
Host smart-c0d77b38-f80d-446f-b451-5d6f01762cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024237429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2024237429
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1349646048
Short name T65
Test name
Test status
Simulation time 16986930 ps
CPU time 0.75 seconds
Started Aug 16 05:56:15 PM PDT 24
Finished Aug 16 05:56:16 PM PDT 24
Peak memory 204892 kb
Host smart-d6950a53-3bb1-40bd-a367-74fcc9df1fcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349646048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1349646048
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3852830273
Short name T255
Test name
Test status
Simulation time 2818976573 ps
CPU time 31.28 seconds
Started Aug 16 05:56:31 PM PDT 24
Finished Aug 16 05:57:08 PM PDT 24
Peak memory 224572 kb
Host smart-69f315fd-b582-4a01-b4d3-b9f8c702dcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852830273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3852830273
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1995006752
Short name T386
Test name
Test status
Simulation time 75675096 ps
CPU time 0.78 seconds
Started Aug 16 05:56:21 PM PDT 24
Finished Aug 16 05:56:21 PM PDT 24
Peak memory 206752 kb
Host smart-8699e4fb-8928-48d9-8378-112cd35c0a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995006752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1995006752
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2737883524
Short name T956
Test name
Test status
Simulation time 1756702131 ps
CPU time 39.21 seconds
Started Aug 16 05:56:16 PM PDT 24
Finished Aug 16 05:56:55 PM PDT 24
Peak memory 251364 kb
Host smart-86ef6f83-d2d5-49dc-b7b3-23e2882ec897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737883524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2737883524
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4255879022
Short name T449
Test name
Test status
Simulation time 30427575264 ps
CPU time 243.63 seconds
Started Aug 16 05:56:15 PM PDT 24
Finished Aug 16 06:00:18 PM PDT 24
Peak memory 252012 kb
Host smart-404629b3-8fcc-4555-8afe-05ad98ca3a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255879022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4255879022
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2843964302
Short name T888
Test name
Test status
Simulation time 192626277 ps
CPU time 0.93 seconds
Started Aug 16 05:57:02 PM PDT 24
Finished Aug 16 05:57:03 PM PDT 24
Peak memory 217120 kb
Host smart-f413369c-04e4-4e91-bc9b-cdf2c4d4d3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843964302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2843964302
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1020796871
Short name T456
Test name
Test status
Simulation time 1643954757 ps
CPU time 26.47 seconds
Started Aug 16 05:56:46 PM PDT 24
Finished Aug 16 05:57:12 PM PDT 24
Peak memory 234684 kb
Host smart-4ede1ee3-4091-4407-ad4e-197ac651acba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020796871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1020796871
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2594472347
Short name T750
Test name
Test status
Simulation time 288027543 ps
CPU time 5.1 seconds
Started Aug 16 05:56:20 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 234312 kb
Host smart-0c305de1-b0ab-41ad-903f-a7c2ab93b8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594472347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2594472347
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2405959759
Short name T848
Test name
Test status
Simulation time 2744337133 ps
CPU time 5.73 seconds
Started Aug 16 05:56:50 PM PDT 24
Finished Aug 16 05:56:55 PM PDT 24
Peak memory 224696 kb
Host smart-9865bdf4-5b3f-4930-99e6-14cecf0dbfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405959759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2405959759
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.573628463
Short name T668
Test name
Test status
Simulation time 267147918 ps
CPU time 5.9 seconds
Started Aug 16 05:56:17 PM PDT 24
Finished Aug 16 05:56:23 PM PDT 24
Peak memory 237560 kb
Host smart-d87b5cf8-1ae8-4257-afbf-08278078407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573628463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.573628463
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.867936315
Short name T588
Test name
Test status
Simulation time 1362202791 ps
CPU time 4.21 seconds
Started Aug 16 05:56:38 PM PDT 24
Finished Aug 16 05:56:42 PM PDT 24
Peak memory 232816 kb
Host smart-e63f00e2-7dc4-4160-807b-dddfd3c46167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867936315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.867936315
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.347995501
Short name T987
Test name
Test status
Simulation time 4010702508 ps
CPU time 13.21 seconds
Started Aug 16 05:56:14 PM PDT 24
Finished Aug 16 05:56:27 PM PDT 24
Peak memory 241132 kb
Host smart-8ca3661a-265f-4bcd-b574-ae22021644ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347995501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.347995501
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2330935778
Short name T491
Test name
Test status
Simulation time 1243243624 ps
CPU time 14.26 seconds
Started Aug 16 05:56:16 PM PDT 24
Finished Aug 16 05:56:31 PM PDT 24
Peak memory 223204 kb
Host smart-ed5b8721-0bae-43dd-8049-4b0cd080696e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2330935778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2330935778
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2199460081
Short name T158
Test name
Test status
Simulation time 4458986065 ps
CPU time 48.47 seconds
Started Aug 16 05:56:35 PM PDT 24
Finished Aug 16 05:57:24 PM PDT 24
Peak memory 252912 kb
Host smart-d24fd404-8ae8-4610-a0be-6e84ea5b3ce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199460081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2199460081
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.58450560
Short name T365
Test name
Test status
Simulation time 52412041 ps
CPU time 0.73 seconds
Started Aug 16 05:56:15 PM PDT 24
Finished Aug 16 05:56:16 PM PDT 24
Peak memory 205768 kb
Host smart-b5af6994-2e5f-4411-8b3a-c639d4406f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58450560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.58450560
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3214830274
Short name T963
Test name
Test status
Simulation time 8205057697 ps
CPU time 10.54 seconds
Started Aug 16 05:56:45 PM PDT 24
Finished Aug 16 05:56:56 PM PDT 24
Peak memory 216568 kb
Host smart-c656f0cb-e1fa-473c-b2ef-57cf8f4a17ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214830274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3214830274
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1880368432
Short name T400
Test name
Test status
Simulation time 14991880 ps
CPU time 0.86 seconds
Started Aug 16 05:56:14 PM PDT 24
Finished Aug 16 05:56:15 PM PDT 24
Peak memory 207172 kb
Host smart-216ae7a8-010e-4219-8c02-4e60aa95df99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880368432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1880368432
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2926474734
Short name T415
Test name
Test status
Simulation time 80436879 ps
CPU time 0.78 seconds
Started Aug 16 05:56:27 PM PDT 24
Finished Aug 16 05:56:28 PM PDT 24
Peak memory 206068 kb
Host smart-c6efde16-3ff2-4ebd-b8d3-5fcc7f046e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926474734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2926474734
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3863790683
Short name T808
Test name
Test status
Simulation time 387845112 ps
CPU time 6.99 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:31 PM PDT 24
Peak memory 224588 kb
Host smart-64aff51d-7260-4adb-9998-d82acf9fb1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863790683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3863790683
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1796933799
Short name T55
Test name
Test status
Simulation time 16778560 ps
CPU time 0.66 seconds
Started Aug 16 05:56:29 PM PDT 24
Finished Aug 16 05:56:29 PM PDT 24
Peak memory 205508 kb
Host smart-3f8152ef-a745-4d1b-8c18-b8d60c96d5d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796933799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1796933799
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2829560840
Short name T924
Test name
Test status
Simulation time 170691179 ps
CPU time 2.74 seconds
Started Aug 16 05:56:15 PM PDT 24
Finished Aug 16 05:56:18 PM PDT 24
Peak memory 232824 kb
Host smart-4fe552b1-57e4-4827-b3ee-e65c3417ae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829560840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2829560840
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2052194515
Short name T6
Test name
Test status
Simulation time 65433842 ps
CPU time 0.78 seconds
Started Aug 16 05:57:12 PM PDT 24
Finished Aug 16 05:57:13 PM PDT 24
Peak memory 206600 kb
Host smart-e53aee3e-9f24-46a1-8287-7df72bbbb966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052194515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2052194515
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1059848621
Short name T532
Test name
Test status
Simulation time 2027128543 ps
CPU time 7.54 seconds
Started Aug 16 05:56:18 PM PDT 24
Finished Aug 16 05:56:25 PM PDT 24
Peak memory 234348 kb
Host smart-4d132b90-2d81-453f-a45f-5a34ca9b9809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059848621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1059848621
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3344108225
Short name T1033
Test name
Test status
Simulation time 45246128391 ps
CPU time 227.77 seconds
Started Aug 16 05:56:17 PM PDT 24
Finished Aug 16 06:00:05 PM PDT 24
Peak memory 262060 kb
Host smart-f22ce809-b570-4da2-8c98-d83ad7c9daf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344108225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3344108225
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4044003757
Short name T61
Test name
Test status
Simulation time 21281872555 ps
CPU time 125.7 seconds
Started Aug 16 05:56:48 PM PDT 24
Finished Aug 16 05:58:54 PM PDT 24
Peak memory 268888 kb
Host smart-0653440d-8b4b-40b4-9919-3c3e39a53475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044003757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4044003757
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2241177719
Short name T173
Test name
Test status
Simulation time 434286716 ps
CPU time 8.79 seconds
Started Aug 16 05:56:45 PM PDT 24
Finished Aug 16 05:56:54 PM PDT 24
Peak memory 232908 kb
Host smart-e5565abf-1aef-4e52-845f-f87a91b1ac8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241177719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2241177719
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3469828467
Short name T827
Test name
Test status
Simulation time 14648977098 ps
CPU time 142.05 seconds
Started Aug 16 05:57:08 PM PDT 24
Finished Aug 16 05:59:30 PM PDT 24
Peak memory 254192 kb
Host smart-63735610-86b3-4c8b-845d-b8c166863f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469828467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3469828467
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3889561455
Short name T590
Test name
Test status
Simulation time 186497995 ps
CPU time 2.25 seconds
Started Aug 16 05:56:53 PM PDT 24
Finished Aug 16 05:56:56 PM PDT 24
Peak memory 223224 kb
Host smart-2ce0c173-7b51-4c4a-83a2-ae13af1c20fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889561455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3889561455
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3648093489
Short name T453
Test name
Test status
Simulation time 73264697 ps
CPU time 2.14 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 223936 kb
Host smart-e21a89e7-561d-4ae6-9c13-78ec1298f210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648093489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3648093489
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3625671733
Short name T339
Test name
Test status
Simulation time 130999864 ps
CPU time 2.24 seconds
Started Aug 16 05:56:21 PM PDT 24
Finished Aug 16 05:56:24 PM PDT 24
Peak memory 223012 kb
Host smart-4e801380-446c-4abd-af1d-0e709554484f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625671733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3625671733
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4126274678
Short name T611
Test name
Test status
Simulation time 528680871 ps
CPU time 4.48 seconds
Started Aug 16 05:56:16 PM PDT 24
Finished Aug 16 05:56:20 PM PDT 24
Peak memory 224824 kb
Host smart-44c2b8b6-cb0b-4826-b099-1e18432b76e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126274678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4126274678
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3229917812
Short name T838
Test name
Test status
Simulation time 1142415527 ps
CPU time 7.56 seconds
Started Aug 16 05:56:27 PM PDT 24
Finished Aug 16 05:56:34 PM PDT 24
Peak memory 222224 kb
Host smart-51afd815-2dc4-4c40-9420-ea62da9d79f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3229917812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3229917812
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1835793865
Short name T938
Test name
Test status
Simulation time 3224682221 ps
CPU time 66.17 seconds
Started Aug 16 05:56:35 PM PDT 24
Finished Aug 16 05:57:42 PM PDT 24
Peak memory 265032 kb
Host smart-4a7d4d43-7022-4c2c-b229-ac71bb1517bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835793865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1835793865
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2096962175
Short name T799
Test name
Test status
Simulation time 37451245590 ps
CPU time 37.77 seconds
Started Aug 16 05:56:55 PM PDT 24
Finished Aug 16 05:57:33 PM PDT 24
Peak memory 216444 kb
Host smart-4a46cd3c-619c-4dd9-bccf-bbeac070bfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096962175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2096962175
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.851240699
Short name T379
Test name
Test status
Simulation time 3198546521 ps
CPU time 9.93 seconds
Started Aug 16 05:56:45 PM PDT 24
Finished Aug 16 05:56:55 PM PDT 24
Peak memory 216532 kb
Host smart-7b1766c9-ae95-48ad-9388-a1c3213ce5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851240699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.851240699
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1374817930
Short name T860
Test name
Test status
Simulation time 1176516589 ps
CPU time 9 seconds
Started Aug 16 05:56:33 PM PDT 24
Finished Aug 16 05:56:42 PM PDT 24
Peak memory 216392 kb
Host smart-6e468e2f-e371-4fa0-847f-55700537668b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374817930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1374817930
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1388353080
Short name T552
Test name
Test status
Simulation time 37980643 ps
CPU time 0.81 seconds
Started Aug 16 05:57:11 PM PDT 24
Finished Aug 16 05:57:12 PM PDT 24
Peak memory 206040 kb
Host smart-8782daa6-c90d-4963-9f89-32371269bbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388353080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1388353080
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2380550433
Short name T567
Test name
Test status
Simulation time 4032601435 ps
CPU time 10.23 seconds
Started Aug 16 05:56:46 PM PDT 24
Finished Aug 16 05:56:57 PM PDT 24
Peak memory 232992 kb
Host smart-9df333af-273d-4d8b-8958-7f1dddc432f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380550433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2380550433
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1647171713
Short name T851
Test name
Test status
Simulation time 13201527 ps
CPU time 0.73 seconds
Started Aug 16 05:57:10 PM PDT 24
Finished Aug 16 05:57:11 PM PDT 24
Peak memory 204964 kb
Host smart-fa0b5d69-f3ca-4b58-bf9f-e1096a1237b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647171713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1647171713
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2295294362
Short name T430
Test name
Test status
Simulation time 77729413 ps
CPU time 3.14 seconds
Started Aug 16 05:56:31 PM PDT 24
Finished Aug 16 05:56:35 PM PDT 24
Peak memory 232808 kb
Host smart-d6f3797a-3ac7-4532-a28d-e9121d93d62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295294362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2295294362
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1629201772
Short name T781
Test name
Test status
Simulation time 25139742 ps
CPU time 0.78 seconds
Started Aug 16 05:57:13 PM PDT 24
Finished Aug 16 05:57:14 PM PDT 24
Peak memory 206612 kb
Host smart-4b1e92ea-1c10-414b-9eb0-3a50e624eaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629201772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1629201772
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1715399861
Short name T1019
Test name
Test status
Simulation time 8901596724 ps
CPU time 64.1 seconds
Started Aug 16 05:57:02 PM PDT 24
Finished Aug 16 05:58:07 PM PDT 24
Peak memory 249360 kb
Host smart-a0907ef3-33da-45dc-80e4-ce3f38537397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715399861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1715399861
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.74615426
Short name T208
Test name
Test status
Simulation time 28548313627 ps
CPU time 137.24 seconds
Started Aug 16 05:56:30 PM PDT 24
Finished Aug 16 05:58:47 PM PDT 24
Peak memory 250496 kb
Host smart-ef593e7c-950a-481d-b78d-4f3a5c3d01fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74615426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.74615426
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.858205143
Short name T785
Test name
Test status
Simulation time 8210111805 ps
CPU time 92.18 seconds
Started Aug 16 05:56:55 PM PDT 24
Finished Aug 16 05:58:33 PM PDT 24
Peak memory 265552 kb
Host smart-f95a659a-e4e7-49be-8834-faa24e0a4c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858205143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.858205143
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3400921864
Short name T778
Test name
Test status
Simulation time 6663297293 ps
CPU time 16.42 seconds
Started Aug 16 05:56:53 PM PDT 24
Finished Aug 16 05:57:09 PM PDT 24
Peak memory 232940 kb
Host smart-5f5c4dd1-ab00-4501-970e-6655132e7e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400921864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3400921864
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3087565674
Short name T898
Test name
Test status
Simulation time 13064649409 ps
CPU time 96.01 seconds
Started Aug 16 05:56:17 PM PDT 24
Finished Aug 16 05:57:53 PM PDT 24
Peak memory 249304 kb
Host smart-30199446-6220-422c-9a14-e7527bde2ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087565674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3087565674
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.204115002
Short name T46
Test name
Test status
Simulation time 284389221 ps
CPU time 2.74 seconds
Started Aug 16 05:56:45 PM PDT 24
Finished Aug 16 05:56:47 PM PDT 24
Peak memory 232912 kb
Host smart-cb5686a5-2819-429d-881b-b356375207a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204115002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.204115002
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.939761031
Short name T682
Test name
Test status
Simulation time 12513471165 ps
CPU time 117.45 seconds
Started Aug 16 05:56:25 PM PDT 24
Finished Aug 16 05:58:23 PM PDT 24
Peak memory 241148 kb
Host smart-2293debb-0630-4ed1-b407-5e6473966ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939761031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.939761031
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3430831802
Short name T429
Test name
Test status
Simulation time 201430411 ps
CPU time 2.68 seconds
Started Aug 16 05:56:23 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 224604 kb
Host smart-17982fa7-5ed2-44d4-b394-8e64c3408a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430831802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3430831802
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3182805695
Short name T940
Test name
Test status
Simulation time 162426096 ps
CPU time 2.64 seconds
Started Aug 16 05:56:28 PM PDT 24
Finished Aug 16 05:56:31 PM PDT 24
Peak memory 232488 kb
Host smart-ceddba16-1686-402b-825f-d05a46586b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182805695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3182805695
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4157571942
Short name T887
Test name
Test status
Simulation time 247614187 ps
CPU time 4.53 seconds
Started Aug 16 05:56:33 PM PDT 24
Finished Aug 16 05:56:37 PM PDT 24
Peak memory 222556 kb
Host smart-1fb97a64-b362-4b6a-a505-61c87a1cfc97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4157571942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4157571942
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2258420058
Short name T288
Test name
Test status
Simulation time 181526650393 ps
CPU time 426.89 seconds
Started Aug 16 05:56:35 PM PDT 24
Finished Aug 16 06:03:42 PM PDT 24
Peak memory 265116 kb
Host smart-b390ba1d-3b9a-4174-8038-bba3d9be0684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258420058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2258420058
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2088385605
Short name T995
Test name
Test status
Simulation time 871411301 ps
CPU time 13.53 seconds
Started Aug 16 05:56:36 PM PDT 24
Finished Aug 16 05:56:50 PM PDT 24
Peak memory 216460 kb
Host smart-b600b067-bf36-44ac-90e7-94dbab949196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088385605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2088385605
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3790624373
Short name T759
Test name
Test status
Simulation time 5300153749 ps
CPU time 13.88 seconds
Started Aug 16 05:57:10 PM PDT 24
Finished Aug 16 05:57:24 PM PDT 24
Peak memory 216528 kb
Host smart-c45fa055-dcbc-4409-9481-57eb01698642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790624373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3790624373
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.834392768
Short name T540
Test name
Test status
Simulation time 49646637 ps
CPU time 1.18 seconds
Started Aug 16 05:56:44 PM PDT 24
Finished Aug 16 05:56:45 PM PDT 24
Peak memory 208164 kb
Host smart-389bf28f-024b-4467-8ca8-63283f376f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834392768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.834392768
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2499956429
Short name T1035
Test name
Test status
Simulation time 58125596 ps
CPU time 0.84 seconds
Started Aug 16 05:57:08 PM PDT 24
Finished Aug 16 05:57:09 PM PDT 24
Peak memory 206032 kb
Host smart-f0dd0681-7372-43a8-892d-d43796bcdfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499956429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2499956429
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2963523420
Short name T214
Test name
Test status
Simulation time 33931964000 ps
CPU time 21.9 seconds
Started Aug 16 05:57:12 PM PDT 24
Finished Aug 16 05:57:34 PM PDT 24
Peak memory 227064 kb
Host smart-9ce7c0e5-bbfc-44aa-9178-cbcf0d0918af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963523420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2963523420
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2821405828
Short name T591
Test name
Test status
Simulation time 30326666 ps
CPU time 0.73 seconds
Started Aug 16 05:56:28 PM PDT 24
Finished Aug 16 05:56:29 PM PDT 24
Peak memory 205468 kb
Host smart-7efd6e33-252f-498a-85de-925a27251c91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821405828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2821405828
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3524430961
Short name T640
Test name
Test status
Simulation time 140675257 ps
CPU time 2.39 seconds
Started Aug 16 05:56:35 PM PDT 24
Finished Aug 16 05:56:37 PM PDT 24
Peak memory 232828 kb
Host smart-ad3881ec-33db-478f-ade8-904d339d53c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524430961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3524430961
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2743662779
Short name T787
Test name
Test status
Simulation time 16862154 ps
CPU time 0.82 seconds
Started Aug 16 05:56:29 PM PDT 24
Finished Aug 16 05:56:30 PM PDT 24
Peak memory 206584 kb
Host smart-7da67422-625a-40f0-9420-f80e543ca069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743662779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2743662779
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2290008607
Short name T961
Test name
Test status
Simulation time 22620228614 ps
CPU time 56.47 seconds
Started Aug 16 05:56:51 PM PDT 24
Finished Aug 16 05:57:47 PM PDT 24
Peak memory 235968 kb
Host smart-011bc3fd-62d3-490e-904d-288c2920faf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290008607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2290008607
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3990513575
Short name T335
Test name
Test status
Simulation time 8113713023 ps
CPU time 43.74 seconds
Started Aug 16 05:57:07 PM PDT 24
Finished Aug 16 05:57:51 PM PDT 24
Peak memory 249772 kb
Host smart-27ae97e0-75cc-46cc-b53c-1a8e7db5830e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990513575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3990513575
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1639811065
Short name T203
Test name
Test status
Simulation time 3800190417 ps
CPU time 46.03 seconds
Started Aug 16 05:57:09 PM PDT 24
Finished Aug 16 05:57:55 PM PDT 24
Peak memory 249336 kb
Host smart-adc01014-1003-4953-9734-675f8c9d0307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639811065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1639811065
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3455068690
Short name T320
Test name
Test status
Simulation time 288265650 ps
CPU time 4.9 seconds
Started Aug 16 05:56:53 PM PDT 24
Finished Aug 16 05:56:58 PM PDT 24
Peak memory 232796 kb
Host smart-57fb37cc-c7b8-4332-b77e-8b1a475104b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455068690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3455068690
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3374986815
Short name T467
Test name
Test status
Simulation time 161470290 ps
CPU time 0.92 seconds
Started Aug 16 05:56:24 PM PDT 24
Finished Aug 16 05:56:26 PM PDT 24
Peak memory 216128 kb
Host smart-50080321-5465-4f2b-83d0-f4b5a6d9e598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374986815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3374986815
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2930207331
Short name T622
Test name
Test status
Simulation time 315319272 ps
CPU time 5.34 seconds
Started Aug 16 05:56:59 PM PDT 24
Finished Aug 16 05:57:05 PM PDT 24
Peak memory 232856 kb
Host smart-d6428983-d6b9-405a-9a0a-06c67b12a1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930207331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2930207331
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1985506505
Short name T655
Test name
Test status
Simulation time 957870139 ps
CPU time 20.47 seconds
Started Aug 16 05:56:34 PM PDT 24
Finished Aug 16 05:56:55 PM PDT 24
Peak memory 251700 kb
Host smart-83d9bcb8-1fde-437d-8653-b7e6fe773264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985506505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1985506505
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2196609609
Short name T483
Test name
Test status
Simulation time 430360060 ps
CPU time 7.46 seconds
Started Aug 16 05:57:05 PM PDT 24
Finished Aug 16 05:57:13 PM PDT 24
Peak memory 238492 kb
Host smart-1b7b5f3c-8c07-4d7a-9853-401ea3a19ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196609609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2196609609
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.643698877
Short name T263
Test name
Test status
Simulation time 446101374 ps
CPU time 5.78 seconds
Started Aug 16 05:56:44 PM PDT 24
Finished Aug 16 05:56:50 PM PDT 24
Peak memory 232912 kb
Host smart-24c27fff-16f9-4f56-bddf-2ee9c647fa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643698877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.643698877
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4124942811
Short name T148
Test name
Test status
Simulation time 860051905 ps
CPU time 6.15 seconds
Started Aug 16 05:57:06 PM PDT 24
Finished Aug 16 05:57:13 PM PDT 24
Peak memory 220280 kb
Host smart-7af8de87-52c6-499d-a8b3-52243a83cc69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4124942811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4124942811
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1364891761
Short name T314
Test name
Test status
Simulation time 25483796085 ps
CPU time 246.23 seconds
Started Aug 16 05:57:03 PM PDT 24
Finished Aug 16 06:01:09 PM PDT 24
Peak memory 257532 kb
Host smart-26eedb46-862a-4a0d-93d5-96a56865c04f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364891761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1364891761
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3472880225
Short name T521
Test name
Test status
Simulation time 2777697448 ps
CPU time 15.18 seconds
Started Aug 16 05:57:00 PM PDT 24
Finished Aug 16 05:57:16 PM PDT 24
Peak memory 216520 kb
Host smart-b0c3243a-a2f8-4b7b-b78d-4293c3aeb7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472880225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3472880225
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1477971456
Short name T395
Test name
Test status
Simulation time 1506201354 ps
CPU time 4.84 seconds
Started Aug 16 05:56:53 PM PDT 24
Finished Aug 16 05:56:58 PM PDT 24
Peak memory 216460 kb
Host smart-5153aee4-a041-4089-b1a3-aa5fb4ecce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477971456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1477971456
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3326774529
Short name T829
Test name
Test status
Simulation time 39971101 ps
CPU time 1.31 seconds
Started Aug 16 05:56:33 PM PDT 24
Finished Aug 16 05:56:35 PM PDT 24
Peak memory 216420 kb
Host smart-8e9b7d41-b160-4d9c-8d89-71c5b2929dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326774529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3326774529
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1213973717
Short name T951
Test name
Test status
Simulation time 38943140 ps
CPU time 0.83 seconds
Started Aug 16 05:57:12 PM PDT 24
Finished Aug 16 05:57:13 PM PDT 24
Peak memory 207064 kb
Host smart-82cf8f3e-7dc7-4d14-b357-5aece820cfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213973717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1213973717
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.4031727023
Short name T232
Test name
Test status
Simulation time 6261672847 ps
CPU time 9.41 seconds
Started Aug 16 05:56:34 PM PDT 24
Finished Aug 16 05:56:44 PM PDT 24
Peak memory 232856 kb
Host smart-b3f45808-9dac-4933-ae36-a798fe433c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031727023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4031727023
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.33893227
Short name T66
Test name
Test status
Simulation time 95815175 ps
CPU time 0.72 seconds
Started Aug 16 05:57:07 PM PDT 24
Finished Aug 16 05:57:07 PM PDT 24
Peak memory 205536 kb
Host smart-3696f567-679c-4a1d-ba2c-05cff10622c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33893227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.33893227
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2249628024
Short name T3
Test name
Test status
Simulation time 651601964 ps
CPU time 6.93 seconds
Started Aug 16 05:56:35 PM PDT 24
Finished Aug 16 05:56:42 PM PDT 24
Peak memory 224688 kb
Host smart-b0d9ea86-d509-49d4-9ed2-ebb8696445c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249628024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2249628024
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2847228818
Short name T599
Test name
Test status
Simulation time 68958012 ps
CPU time 0.83 seconds
Started Aug 16 05:57:01 PM PDT 24
Finished Aug 16 05:57:02 PM PDT 24
Peak memory 206528 kb
Host smart-c6431b4b-2163-45a6-bacf-2b246dd06b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847228818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2847228818
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1943209087
Short name T171
Test name
Test status
Simulation time 62239458898 ps
CPU time 131.31 seconds
Started Aug 16 05:56:58 PM PDT 24
Finished Aug 16 05:59:09 PM PDT 24
Peak memory 249336 kb
Host smart-456838b0-aeb6-40e5-8269-5106dd85cc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943209087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1943209087
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1876571861
Short name T510
Test name
Test status
Simulation time 2210620780 ps
CPU time 29.38 seconds
Started Aug 16 05:56:53 PM PDT 24
Finished Aug 16 05:57:23 PM PDT 24
Peak memory 238072 kb
Host smart-759c00bb-6935-409d-9e3b-e17cfe0b20ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876571861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1876571861
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2541156787
Short name T670
Test name
Test status
Simulation time 45949881009 ps
CPU time 56.29 seconds
Started Aug 16 05:56:28 PM PDT 24
Finished Aug 16 05:57:25 PM PDT 24
Peak memory 249644 kb
Host smart-7069f871-9ab8-4b2b-a28a-9fa11d14a101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541156787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2541156787
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3415262618
Short name T1003
Test name
Test status
Simulation time 4705360763 ps
CPU time 23.62 seconds
Started Aug 16 05:56:29 PM PDT 24
Finished Aug 16 05:56:53 PM PDT 24
Peak memory 224772 kb
Host smart-2e4617ec-1fb0-4927-87fa-278eeb8531d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415262618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3415262618
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2388572262
Short name T301
Test name
Test status
Simulation time 4927869194 ps
CPU time 36.65 seconds
Started Aug 16 05:56:36 PM PDT 24
Finished Aug 16 05:57:13 PM PDT 24
Peak memory 241172 kb
Host smart-507db676-0b4c-4e12-a40d-3c13fdcfaabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388572262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2388572262
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3833977057
Short name T211
Test name
Test status
Simulation time 2122288451 ps
CPU time 7.08 seconds
Started Aug 16 05:57:13 PM PDT 24
Finished Aug 16 05:57:20 PM PDT 24
Peak memory 232836 kb
Host smart-6a07267a-2cd2-4c5d-a19f-52bd736384fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833977057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3833977057
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4112268080
Short name T763
Test name
Test status
Simulation time 30389213 ps
CPU time 2.31 seconds
Started Aug 16 05:56:29 PM PDT 24
Finished Aug 16 05:56:32 PM PDT 24
Peak memory 232528 kb
Host smart-7ebfd749-7598-4fdf-b597-75fbd9899510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112268080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4112268080
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2167601094
Short name T641
Test name
Test status
Simulation time 470944762 ps
CPU time 5.38 seconds
Started Aug 16 05:56:59 PM PDT 24
Finished Aug 16 05:57:04 PM PDT 24
Peak memory 232812 kb
Host smart-8943afac-51f0-44e7-8ed3-039cf3695d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167601094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2167601094
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.582312883
Short name T673
Test name
Test status
Simulation time 296047762 ps
CPU time 2.6 seconds
Started Aug 16 05:56:32 PM PDT 24
Finished Aug 16 05:56:35 PM PDT 24
Peak memory 232516 kb
Host smart-85892ad7-3f60-42d3-ab50-6126d63ce553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582312883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.582312883
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4294574371
Short name T929
Test name
Test status
Simulation time 151299393 ps
CPU time 4.2 seconds
Started Aug 16 05:56:33 PM PDT 24
Finished Aug 16 05:56:38 PM PDT 24
Peak memory 221936 kb
Host smart-f17b1069-125e-42f3-be78-11b9c7c48260
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4294574371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4294574371
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3936111278
Short name T967
Test name
Test status
Simulation time 132719570 ps
CPU time 0.93 seconds
Started Aug 16 05:57:10 PM PDT 24
Finished Aug 16 05:57:11 PM PDT 24
Peak memory 206644 kb
Host smart-0403f792-0a7c-4eea-af2d-f36f1f37842c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936111278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3936111278
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2531763192
Short name T703
Test name
Test status
Simulation time 9128882732 ps
CPU time 12.5 seconds
Started Aug 16 05:56:30 PM PDT 24
Finished Aug 16 05:56:43 PM PDT 24
Peak memory 216576 kb
Host smart-7ce1af2a-f5cd-4903-acce-2eae16635282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531763192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2531763192
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2872599762
Short name T355
Test name
Test status
Simulation time 1163244999 ps
CPU time 3.13 seconds
Started Aug 16 05:57:10 PM PDT 24
Finished Aug 16 05:57:13 PM PDT 24
Peak memory 216480 kb
Host smart-c33786b2-1325-42b4-b89d-840b5015d806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872599762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2872599762
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2069113052
Short name T477
Test name
Test status
Simulation time 1179491481 ps
CPU time 3.22 seconds
Started Aug 16 05:56:35 PM PDT 24
Finished Aug 16 05:56:38 PM PDT 24
Peak memory 216492 kb
Host smart-abafbb06-9b72-49f4-8cc1-38622b01097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069113052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2069113052
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3834583733
Short name T653
Test name
Test status
Simulation time 135514527 ps
CPU time 0.9 seconds
Started Aug 16 05:56:55 PM PDT 24
Finished Aug 16 05:56:56 PM PDT 24
Peak memory 207096 kb
Host smart-ad6a8e14-b94b-46c6-8338-e60f9aac3f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834583733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3834583733
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.369843927
Short name T1034
Test name
Test status
Simulation time 1112398521 ps
CPU time 8.59 seconds
Started Aug 16 05:56:34 PM PDT 24
Finished Aug 16 05:56:43 PM PDT 24
Peak memory 232836 kb
Host smart-4fd1a951-4f19-4cc0-bc98-08ab37451285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369843927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.369843927
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.438497819
Short name T475
Test name
Test status
Simulation time 21295777 ps
CPU time 0.7 seconds
Started Aug 16 05:54:36 PM PDT 24
Finished Aug 16 05:54:37 PM PDT 24
Peak memory 205516 kb
Host smart-75444146-e085-4994-b817-cffbfb1d41b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438497819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.438497819
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2532816551
Short name T9
Test name
Test status
Simulation time 196887581 ps
CPU time 2.39 seconds
Started Aug 16 05:54:30 PM PDT 24
Finished Aug 16 05:54:32 PM PDT 24
Peak memory 224696 kb
Host smart-0494a35c-f287-4742-a289-7802a78aac0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532816551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2532816551
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.937816467
Short name T338
Test name
Test status
Simulation time 33524302 ps
CPU time 0.77 seconds
Started Aug 16 05:55:27 PM PDT 24
Finished Aug 16 05:55:33 PM PDT 24
Peak memory 205484 kb
Host smart-6216b0a2-f3c0-4f8d-961a-f75efe2a5803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937816467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.937816467
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2926227206
Short name T988
Test name
Test status
Simulation time 1837190531 ps
CPU time 13.93 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:55:07 PM PDT 24
Peak memory 249264 kb
Host smart-3708d2da-4e34-478d-b6a0-2134816be9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926227206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2926227206
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.151555037
Short name T230
Test name
Test status
Simulation time 103392622469 ps
CPU time 459.76 seconds
Started Aug 16 05:55:19 PM PDT 24
Finished Aug 16 06:02:59 PM PDT 24
Peak memory 249320 kb
Host smart-0654d7eb-d23e-4da6-8767-40f7c5bbbe48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151555037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.151555037
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2007444188
Short name T26
Test name
Test status
Simulation time 40888835477 ps
CPU time 48.9 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:55:37 PM PDT 24
Peak memory 221804 kb
Host smart-f0e44c8b-f1b3-4fab-812e-948971b4c693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007444188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2007444188
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3651555453
Short name T708
Test name
Test status
Simulation time 895871925 ps
CPU time 9.57 seconds
Started Aug 16 05:55:20 PM PDT 24
Finished Aug 16 05:55:29 PM PDT 24
Peak memory 232928 kb
Host smart-d7d1923f-50e1-4918-9700-8417dcb9e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651555453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3651555453
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2310445328
Short name T303
Test name
Test status
Simulation time 33023485977 ps
CPU time 76.17 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:56:09 PM PDT 24
Peak memory 249480 kb
Host smart-22663325-d1ca-460f-9ec3-907618210858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310445328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2310445328
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2320931895
Short name T805
Test name
Test status
Simulation time 391704160 ps
CPU time 2.31 seconds
Started Aug 16 05:54:37 PM PDT 24
Finished Aug 16 05:54:39 PM PDT 24
Peak memory 223940 kb
Host smart-26cd0e4c-841b-45e1-8311-32dc362332a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320931895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2320931895
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1582173090
Short name T594
Test name
Test status
Simulation time 11492369866 ps
CPU time 34.65 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:55:27 PM PDT 24
Peak memory 250692 kb
Host smart-af2cddc3-2f81-4f7b-89db-1521f4f586d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582173090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1582173090
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2066953782
Short name T364
Test name
Test status
Simulation time 63456190 ps
CPU time 1.09 seconds
Started Aug 16 05:55:32 PM PDT 24
Finished Aug 16 05:55:33 PM PDT 24
Peak memory 216724 kb
Host smart-f5b6c46f-c255-449f-ad08-9a7618dd68e1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066953782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2066953782
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.512542098
Short name T1020
Test name
Test status
Simulation time 3085347091 ps
CPU time 10.5 seconds
Started Aug 16 05:55:16 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 232920 kb
Host smart-b9892fd4-c7d6-4b28-9a25-fe842e3960ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512542098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
512542098
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1992166241
Short name T201
Test name
Test status
Simulation time 219828485 ps
CPU time 3.18 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:54:57 PM PDT 24
Peak memory 233032 kb
Host smart-52499c34-5ab0-41b3-8b6b-8025f53ad335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992166241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1992166241
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2648930867
Short name T897
Test name
Test status
Simulation time 1314763346 ps
CPU time 5.77 seconds
Started Aug 16 05:55:16 PM PDT 24
Finished Aug 16 05:55:22 PM PDT 24
Peak memory 222424 kb
Host smart-611058cd-3e49-42a6-b2f0-999d53c96685
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2648930867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2648930867
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2861933982
Short name T326
Test name
Test status
Simulation time 3919654135 ps
CPU time 25.93 seconds
Started Aug 16 05:55:17 PM PDT 24
Finished Aug 16 05:55:43 PM PDT 24
Peak memory 216532 kb
Host smart-6139cd7e-0d7f-4eda-8a31-639a749f567b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861933982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2861933982
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1546648568
Short name T575
Test name
Test status
Simulation time 1510027438 ps
CPU time 6.32 seconds
Started Aug 16 05:55:14 PM PDT 24
Finished Aug 16 05:55:20 PM PDT 24
Peak memory 216492 kb
Host smart-c36b1976-2830-4126-a5d4-e7737c7238c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546648568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1546648568
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1058065370
Short name T51
Test name
Test status
Simulation time 1485397314 ps
CPU time 2.1 seconds
Started Aug 16 05:54:48 PM PDT 24
Finished Aug 16 05:54:50 PM PDT 24
Peak memory 216448 kb
Host smart-3f8578a9-86bb-4e70-b99d-4d1caf0b5607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058065370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1058065370
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.809551057
Short name T359
Test name
Test status
Simulation time 22693850 ps
CPU time 0.81 seconds
Started Aug 16 05:55:20 PM PDT 24
Finished Aug 16 05:55:21 PM PDT 24
Peak memory 206156 kb
Host smart-de3429d4-4713-40dc-a3bf-b09f86cd9a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809551057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.809551057
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.740826618
Short name T836
Test name
Test status
Simulation time 8893018355 ps
CPU time 24.3 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:55:12 PM PDT 24
Peak memory 250544 kb
Host smart-baf2530d-f702-4d80-8103-4b43a5cd76b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740826618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.740826618
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.147569000
Short name T770
Test name
Test status
Simulation time 32933403 ps
CPU time 0.75 seconds
Started Aug 16 05:55:22 PM PDT 24
Finished Aug 16 05:55:23 PM PDT 24
Peak memory 205936 kb
Host smart-d3e94e41-a723-4b7a-ba4e-70227c2a9754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147569000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.147569000
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1106019143
Short name T942
Test name
Test status
Simulation time 1234367144 ps
CPU time 6.43 seconds
Started Aug 16 05:55:15 PM PDT 24
Finished Aug 16 05:55:21 PM PDT 24
Peak memory 232924 kb
Host smart-f4bcfb54-0180-46b3-9995-f0da22c7c2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106019143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1106019143
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1519556002
Short name T617
Test name
Test status
Simulation time 14494058 ps
CPU time 0.77 seconds
Started Aug 16 05:55:30 PM PDT 24
Finished Aug 16 05:55:32 PM PDT 24
Peak memory 206552 kb
Host smart-bbec65ad-aa23-461d-a625-80b188ceddb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519556002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1519556002
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.934276459
Short name T418
Test name
Test status
Simulation time 21174846 ps
CPU time 0.82 seconds
Started Aug 16 05:54:50 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 216016 kb
Host smart-6db54cc5-a9a5-4feb-8793-5105439482ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934276459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.934276459
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.738727783
Short name T204
Test name
Test status
Simulation time 4157879196 ps
CPU time 45.62 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:55:39 PM PDT 24
Peak memory 249580 kb
Host smart-673c365d-19a7-4fd2-9338-f63a11d1edef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738727783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.738727783
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.165507159
Short name T426
Test name
Test status
Simulation time 28102159 ps
CPU time 0.81 seconds
Started Aug 16 05:55:16 PM PDT 24
Finished Aug 16 05:55:17 PM PDT 24
Peak memory 217116 kb
Host smart-8817aeb6-ec3e-4f68-b25d-75d864806c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165507159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
165507159
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4036684763
Short name T174
Test name
Test status
Simulation time 1002151728 ps
CPU time 7.88 seconds
Started Aug 16 05:55:22 PM PDT 24
Finished Aug 16 05:55:30 PM PDT 24
Peak memory 249280 kb
Host smart-851bfde3-a8d7-4077-8855-faa60cd2372f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036684763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4036684763
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1242988304
Short name T941
Test name
Test status
Simulation time 4954143802 ps
CPU time 39.85 seconds
Started Aug 16 05:55:20 PM PDT 24
Finished Aug 16 05:56:00 PM PDT 24
Peak memory 236404 kb
Host smart-1b36e1bb-75f1-4e05-b9a7-c0993590811e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242988304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1242988304
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.805520584
Short name T234
Test name
Test status
Simulation time 14325455709 ps
CPU time 17.87 seconds
Started Aug 16 05:55:28 PM PDT 24
Finished Aug 16 05:55:46 PM PDT 24
Peak memory 224720 kb
Host smart-a739cb91-03b0-49a3-8541-28117bde695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805520584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.805520584
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3776729108
Short name T600
Test name
Test status
Simulation time 6040848380 ps
CPU time 30.82 seconds
Started Aug 16 05:55:27 PM PDT 24
Finished Aug 16 05:55:58 PM PDT 24
Peak memory 232944 kb
Host smart-6c7c70be-5c2e-4610-b481-c54147d94699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776729108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3776729108
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.291214367
Short name T814
Test name
Test status
Simulation time 131103045 ps
CPU time 0.99 seconds
Started Aug 16 05:55:32 PM PDT 24
Finished Aug 16 05:55:33 PM PDT 24
Peak memory 217960 kb
Host smart-aef25d39-09e7-42ea-b2d7-d1865d69492b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291214367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.291214367
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1770618683
Short name T626
Test name
Test status
Simulation time 4899701726 ps
CPU time 5.66 seconds
Started Aug 16 05:55:21 PM PDT 24
Finished Aug 16 05:55:27 PM PDT 24
Peak memory 224752 kb
Host smart-b81f293d-5b7f-4252-aac0-dd89449571b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770618683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1770618683
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.426483471
Short name T253
Test name
Test status
Simulation time 2791944492 ps
CPU time 10.87 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:55:04 PM PDT 24
Peak memory 240932 kb
Host smart-0d7f1373-a1ca-4185-9d43-cc0f1faf52c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426483471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.426483471
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4056147136
Short name T424
Test name
Test status
Simulation time 3677557655 ps
CPU time 8.23 seconds
Started Aug 16 05:54:39 PM PDT 24
Finished Aug 16 05:54:47 PM PDT 24
Peak memory 220140 kb
Host smart-c37d62e0-6e3c-4324-9b3d-7f235c35274f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4056147136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4056147136
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.574702894
Short name T270
Test name
Test status
Simulation time 10280441323 ps
CPU time 184.77 seconds
Started Aug 16 05:54:47 PM PDT 24
Finished Aug 16 05:57:51 PM PDT 24
Peak memory 257612 kb
Host smart-5b8a4b0a-8a41-4311-8e5f-6f98521b4617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574702894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.574702894
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.689548925
Short name T658
Test name
Test status
Simulation time 1915051740 ps
CPU time 24.63 seconds
Started Aug 16 05:55:13 PM PDT 24
Finished Aug 16 05:55:38 PM PDT 24
Peak memory 219980 kb
Host smart-16a2ca01-5295-4f34-9550-b61852bc0ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689548925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.689548925
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.373911411
Short name T84
Test name
Test status
Simulation time 8260652762 ps
CPU time 22.78 seconds
Started Aug 16 05:55:32 PM PDT 24
Finished Aug 16 05:55:55 PM PDT 24
Peak memory 216532 kb
Host smart-926b66f2-6750-48c4-a0fc-3d69fc95cf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373911411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.373911411
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2392280258
Short name T1000
Test name
Test status
Simulation time 77431697 ps
CPU time 1.41 seconds
Started Aug 16 05:54:49 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 216468 kb
Host smart-1355c808-2285-4dc0-bf85-9023babb82cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392280258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2392280258
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3206593593
Short name T935
Test name
Test status
Simulation time 99322612 ps
CPU time 0.99 seconds
Started Aug 16 05:55:15 PM PDT 24
Finished Aug 16 05:55:20 PM PDT 24
Peak memory 207104 kb
Host smart-b168c674-6c9f-4ec5-9adf-d07da7423e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206593593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3206593593
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2606717450
Short name T458
Test name
Test status
Simulation time 11164003938 ps
CPU time 10.19 seconds
Started Aug 16 05:54:32 PM PDT 24
Finished Aug 16 05:54:42 PM PDT 24
Peak memory 224716 kb
Host smart-5b0a356f-a0f0-47ee-8791-760acdba5b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606717450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2606717450
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1111800923
Short name T896
Test name
Test status
Simulation time 36858818 ps
CPU time 0.72 seconds
Started Aug 16 05:54:51 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 205540 kb
Host smart-eedf2607-5a4d-4a9f-a95e-ba669a76cd03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111800923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
111800923
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.366643028
Short name T861
Test name
Test status
Simulation time 940671724 ps
CPU time 2.75 seconds
Started Aug 16 05:54:59 PM PDT 24
Finished Aug 16 05:55:02 PM PDT 24
Peak memory 224620 kb
Host smart-969a4268-62ea-49e1-847e-f74ab2e5a4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366643028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.366643028
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.892739616
Short name T354
Test name
Test status
Simulation time 21924173 ps
CPU time 0.77 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:54:54 PM PDT 24
Peak memory 205712 kb
Host smart-3350e249-7be6-467c-ad9a-33f3833482d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892739616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.892739616
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.719185576
Short name T696
Test name
Test status
Simulation time 12651825 ps
CPU time 0.73 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 215928 kb
Host smart-8c518ac4-b911-414d-a32d-89cb38bfe4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719185576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.719185576
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3293624181
Short name T309
Test name
Test status
Simulation time 223359898004 ps
CPU time 460.64 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 06:03:04 PM PDT 24
Peak memory 265828 kb
Host smart-ff5a5921-0119-453a-b9c9-11a5d175c2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293624181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3293624181
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4180147742
Short name T1023
Test name
Test status
Simulation time 1704524592 ps
CPU time 21.07 seconds
Started Aug 16 05:55:30 PM PDT 24
Finished Aug 16 05:55:51 PM PDT 24
Peak memory 240988 kb
Host smart-1c1f81e7-a484-4f8d-94e3-fe70223c286a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180147742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4180147742
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2397849483
Short name T265
Test name
Test status
Simulation time 43754145272 ps
CPU time 322.13 seconds
Started Aug 16 05:55:11 PM PDT 24
Finished Aug 16 06:00:33 PM PDT 24
Peak memory 251588 kb
Host smart-02176fbc-f39a-4286-9401-8eae9d16506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397849483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2397849483
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1792746754
Short name T683
Test name
Test status
Simulation time 984093719 ps
CPU time 11.31 seconds
Started Aug 16 05:54:55 PM PDT 24
Finished Aug 16 05:55:06 PM PDT 24
Peak memory 232876 kb
Host smart-4551f1f2-b435-40c1-a9b6-71bb4d0bf3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792746754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1792746754
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2813775260
Short name T92
Test name
Test status
Simulation time 23463146236 ps
CPU time 52.83 seconds
Started Aug 16 05:55:49 PM PDT 24
Finished Aug 16 05:56:42 PM PDT 24
Peak memory 249872 kb
Host smart-b53b3baa-fe93-4220-9935-af6e9ab3724d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813775260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2813775260
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2059563117
Short name T492
Test name
Test status
Simulation time 54561941 ps
CPU time 1.03 seconds
Started Aug 16 05:55:10 PM PDT 24
Finished Aug 16 05:55:11 PM PDT 24
Peak memory 217904 kb
Host smart-e7d6fdbc-e307-42f3-a541-4015d83f24e9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059563117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2059563117
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2599518741
Short name T550
Test name
Test status
Simulation time 23779779033 ps
CPU time 22.86 seconds
Started Aug 16 05:54:55 PM PDT 24
Finished Aug 16 05:55:18 PM PDT 24
Peak memory 233824 kb
Host smart-4df43023-a456-41e0-9913-19138b9c13d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599518741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2599518741
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3579122275
Short name T245
Test name
Test status
Simulation time 2142175183 ps
CPU time 3.8 seconds
Started Aug 16 05:55:40 PM PDT 24
Finished Aug 16 05:55:44 PM PDT 24
Peak memory 224604 kb
Host smart-83590fd5-db5b-4d30-8113-bc089d60526e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579122275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3579122275
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2477433925
Short name T932
Test name
Test status
Simulation time 146747509 ps
CPU time 3.66 seconds
Started Aug 16 05:55:31 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 219420 kb
Host smart-69bc78f7-7413-412c-b340-6c8535ad53ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2477433925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2477433925
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3367971894
Short name T307
Test name
Test status
Simulation time 133968345785 ps
CPU time 352.07 seconds
Started Aug 16 05:54:50 PM PDT 24
Finished Aug 16 06:00:43 PM PDT 24
Peak memory 282180 kb
Host smart-1160b64a-c435-4ab2-a2c0-6e53a0b43b84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367971894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3367971894
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3306147505
Short name T427
Test name
Test status
Simulation time 1378275192 ps
CPU time 5.57 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:30 PM PDT 24
Peak memory 216728 kb
Host smart-92f777fd-102d-452f-90d8-dc5c2ebf7342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306147505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3306147505
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1990964755
Short name T700
Test name
Test status
Simulation time 50241824 ps
CPU time 1.05 seconds
Started Aug 16 05:55:22 PM PDT 24
Finished Aug 16 05:55:29 PM PDT 24
Peak memory 207224 kb
Host smart-cf12c836-e57c-4387-b9b6-e5753ee9285f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990964755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1990964755
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3450280261
Short name T350
Test name
Test status
Simulation time 72087146 ps
CPU time 1.23 seconds
Started Aug 16 05:54:54 PM PDT 24
Finished Aug 16 05:54:55 PM PDT 24
Peak memory 208256 kb
Host smart-8444a401-200a-41dd-9bc3-62d1628123f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450280261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3450280261
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.357583651
Short name T710
Test name
Test status
Simulation time 22917124 ps
CPU time 0.76 seconds
Started Aug 16 05:55:32 PM PDT 24
Finished Aug 16 05:55:38 PM PDT 24
Peak memory 206004 kb
Host smart-96d51e91-9103-4df5-9227-f731b9daea8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357583651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.357583651
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2787726201
Short name T734
Test name
Test status
Simulation time 1819060904 ps
CPU time 11.16 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:51 PM PDT 24
Peak memory 249200 kb
Host smart-6938da65-e82c-4beb-bc6a-949cc852d41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787726201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2787726201
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3194617413
Short name T656
Test name
Test status
Simulation time 38511307 ps
CPU time 0.72 seconds
Started Aug 16 05:55:31 PM PDT 24
Finished Aug 16 05:55:32 PM PDT 24
Peak memory 205916 kb
Host smart-c2bff538-294f-43d6-b0f0-214c8c14f785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194617413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
194617413
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1049689649
Short name T62
Test name
Test status
Simulation time 1560234201 ps
CPU time 8.02 seconds
Started Aug 16 05:54:56 PM PDT 24
Finished Aug 16 05:55:04 PM PDT 24
Peak memory 224720 kb
Host smart-ead57ed9-879d-4cb0-9377-e43144b0d1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049689649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1049689649
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1260768075
Short name T874
Test name
Test status
Simulation time 27265443 ps
CPU time 0.79 seconds
Started Aug 16 05:54:52 PM PDT 24
Finished Aug 16 05:54:53 PM PDT 24
Peak memory 206588 kb
Host smart-92e94229-af41-4946-a6c2-de2ce228df92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260768075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1260768075
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2032876751
Short name T413
Test name
Test status
Simulation time 9920663650 ps
CPU time 68.21 seconds
Started Aug 16 05:54:55 PM PDT 24
Finished Aug 16 05:56:04 PM PDT 24
Peak memory 237160 kb
Host smart-d0de8990-778a-47f3-9ece-771199d53eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032876751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2032876751
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1197175854
Short name T267
Test name
Test status
Simulation time 6874847038 ps
CPU time 92.5 seconds
Started Aug 16 05:55:32 PM PDT 24
Finished Aug 16 05:57:04 PM PDT 24
Peak memory 269196 kb
Host smart-7f0e5f73-8c12-4eb6-8660-b2892ae4ad27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197175854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1197175854
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1951056246
Short name T105
Test name
Test status
Simulation time 3136777530 ps
CPU time 7.56 seconds
Started Aug 16 05:55:34 PM PDT 24
Finished Aug 16 05:55:42 PM PDT 24
Peak memory 224708 kb
Host smart-1ae055b1-92ce-444f-a3ec-636446c74c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951056246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1951056246
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.263094323
Short name T378
Test name
Test status
Simulation time 875013086 ps
CPU time 23.06 seconds
Started Aug 16 05:54:51 PM PDT 24
Finished Aug 16 05:55:14 PM PDT 24
Peak memory 249304 kb
Host smart-07b563ab-ee62-491d-9bda-a2035fd1f8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263094323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
263094323
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2773078231
Short name T257
Test name
Test status
Simulation time 4702829559 ps
CPU time 4.78 seconds
Started Aug 16 05:55:33 PM PDT 24
Finished Aug 16 05:55:38 PM PDT 24
Peak memory 224716 kb
Host smart-55d7e270-f2e6-4ed1-a0d4-fac3ce44e0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773078231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2773078231
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3652267720
Short name T218
Test name
Test status
Simulation time 1481503454 ps
CPU time 17.96 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:55:11 PM PDT 24
Peak memory 248980 kb
Host smart-7beb544a-7647-4134-9d78-0db5994f09de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652267720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3652267720
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3275653444
Short name T974
Test name
Test status
Simulation time 49170399 ps
CPU time 1.11 seconds
Started Aug 16 05:54:49 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 216680 kb
Host smart-d0108e02-7f13-48f0-885f-7e269dc457c4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275653444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3275653444
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2288109964
Short name T221
Test name
Test status
Simulation time 11175967280 ps
CPU time 8.99 seconds
Started Aug 16 05:55:44 PM PDT 24
Finished Aug 16 05:55:53 PM PDT 24
Peak memory 238108 kb
Host smart-8a290738-3d3f-4c61-9eb0-ed72d2fedebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288109964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2288109964
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1748825549
Short name T63
Test name
Test status
Simulation time 17776535235 ps
CPU time 18.93 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:55:12 PM PDT 24
Peak memory 233088 kb
Host smart-67544922-afde-4c6f-ac7b-d27415593065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748825549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1748825549
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.106194566
Short name T86
Test name
Test status
Simulation time 1248702424 ps
CPU time 9.42 seconds
Started Aug 16 05:55:37 PM PDT 24
Finished Aug 16 05:55:46 PM PDT 24
Peak memory 219192 kb
Host smart-0e0d49bc-c622-4243-940b-70c77a87e7ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=106194566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.106194566
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1607413616
Short name T330
Test name
Test status
Simulation time 3491806761 ps
CPU time 15.73 seconds
Started Aug 16 05:55:33 PM PDT 24
Finished Aug 16 05:55:54 PM PDT 24
Peak memory 216636 kb
Host smart-4f4556c3-453e-4bb4-a595-9938abaea256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607413616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1607413616
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1638219559
Short name T372
Test name
Test status
Simulation time 173946470 ps
CPU time 1.78 seconds
Started Aug 16 05:54:50 PM PDT 24
Finished Aug 16 05:54:52 PM PDT 24
Peak memory 216256 kb
Host smart-cc34b4e7-0524-4d18-a567-f6fe8bc4e6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638219559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1638219559
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2280745409
Short name T387
Test name
Test status
Simulation time 97083140 ps
CPU time 1.2 seconds
Started Aug 16 05:55:11 PM PDT 24
Finished Aug 16 05:55:12 PM PDT 24
Peak memory 216424 kb
Host smart-2ff591f8-fe39-4390-a429-e3fd49760c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280745409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2280745409
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2003168561
Short name T620
Test name
Test status
Simulation time 278875683 ps
CPU time 0.86 seconds
Started Aug 16 05:54:55 PM PDT 24
Finished Aug 16 05:54:56 PM PDT 24
Peak memory 206060 kb
Host smart-8a269155-3238-45ab-8dd6-e77018866485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003168561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2003168561
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1216839440
Short name T731
Test name
Test status
Simulation time 422169319 ps
CPU time 3.03 seconds
Started Aug 16 05:55:28 PM PDT 24
Finished Aug 16 05:55:31 PM PDT 24
Peak memory 224692 kb
Host smart-d9400147-92d1-46af-9f7d-726a31987a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216839440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1216839440
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2751750111
Short name T342
Test name
Test status
Simulation time 20589573 ps
CPU time 0.72 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:35 PM PDT 24
Peak memory 205024 kb
Host smart-7696cba0-225d-4de6-a05a-861f9253fe79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751750111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
751750111
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2551460654
Short name T536
Test name
Test status
Simulation time 230734819 ps
CPU time 2.31 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 224612 kb
Host smart-600f1b76-1413-41aa-bd2b-c9aaec55be39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551460654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2551460654
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1634998046
Short name T560
Test name
Test status
Simulation time 93478355 ps
CPU time 0.74 seconds
Started Aug 16 05:54:52 PM PDT 24
Finished Aug 16 05:54:53 PM PDT 24
Peak memory 205508 kb
Host smart-85fb5c99-5e54-4903-bdce-0950928d1ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634998046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1634998046
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2299124699
Short name T581
Test name
Test status
Simulation time 1536537193 ps
CPU time 22.23 seconds
Started Aug 16 05:55:35 PM PDT 24
Finished Aug 16 05:55:58 PM PDT 24
Peak memory 249296 kb
Host smart-ffb6ecb0-d510-4088-a451-80766aa4fa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299124699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2299124699
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3277149371
Short name T809
Test name
Test status
Simulation time 11922991110 ps
CPU time 128.63 seconds
Started Aug 16 05:54:59 PM PDT 24
Finished Aug 16 05:57:07 PM PDT 24
Peak memory 257608 kb
Host smart-5c17582d-5791-4bfc-bc22-674ce24bc12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277149371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3277149371
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2465159443
Short name T231
Test name
Test status
Simulation time 150750278519 ps
CPU time 271.39 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:59:25 PM PDT 24
Peak memory 257588 kb
Host smart-8fc67317-ab75-4cc1-9499-9846ed71761e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465159443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2465159443
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3107072784
Short name T738
Test name
Test status
Simulation time 372517268 ps
CPU time 7.86 seconds
Started Aug 16 05:55:25 PM PDT 24
Finished Aug 16 05:55:33 PM PDT 24
Peak memory 236852 kb
Host smart-85dad472-83ca-47f4-9bcf-9ca443b0380a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107072784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3107072784
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.553774757
Short name T186
Test name
Test status
Simulation time 2141797116 ps
CPU time 19.06 seconds
Started Aug 16 05:55:30 PM PDT 24
Finished Aug 16 05:55:50 PM PDT 24
Peak memory 235780 kb
Host smart-2a229bef-5d2c-4186-9bde-841aeffe36f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553774757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
553774757
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3001001659
Short name T965
Test name
Test status
Simulation time 469842255 ps
CPU time 2.87 seconds
Started Aug 16 05:55:29 PM PDT 24
Finished Aug 16 05:55:32 PM PDT 24
Peak memory 224564 kb
Host smart-62665448-fef2-4ba2-ab60-f133ae364809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001001659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3001001659
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.126741961
Short name T136
Test name
Test status
Simulation time 40935269907 ps
CPU time 26.86 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:56:03 PM PDT 24
Peak memory 232916 kb
Host smart-612ce54d-a300-461f-a12d-11e557eae4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126741961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.126741961
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.313321853
Short name T748
Test name
Test status
Simulation time 24674199 ps
CPU time 1.09 seconds
Started Aug 16 05:54:50 PM PDT 24
Finished Aug 16 05:54:51 PM PDT 24
Peak memory 216716 kb
Host smart-527a9147-7ad3-48ef-85c4-258be408f255
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313321853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.313321853
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.986375259
Short name T1030
Test name
Test status
Simulation time 296963351 ps
CPU time 6.46 seconds
Started Aug 16 05:55:23 PM PDT 24
Finished Aug 16 05:55:30 PM PDT 24
Peak memory 232880 kb
Host smart-2b700060-45df-4508-aa6e-aeab46c0878e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986375259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
986375259
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4289720873
Short name T47
Test name
Test status
Simulation time 8900286423 ps
CPU time 10.97 seconds
Started Aug 16 05:55:15 PM PDT 24
Finished Aug 16 05:55:26 PM PDT 24
Peak memory 232992 kb
Host smart-a01b5191-a164-4574-a332-d82e374882ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289720873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4289720873
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.573873672
Short name T39
Test name
Test status
Simulation time 910374140 ps
CPU time 5.84 seconds
Started Aug 16 05:55:37 PM PDT 24
Finished Aug 16 05:55:44 PM PDT 24
Peak memory 223468 kb
Host smart-18dfd0c4-f512-456f-aeef-05656ea662a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=573873672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.573873672
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.64898182
Short name T905
Test name
Test status
Simulation time 12247626656 ps
CPU time 19.3 seconds
Started Aug 16 05:54:53 PM PDT 24
Finished Aug 16 05:55:13 PM PDT 24
Peak memory 216528 kb
Host smart-17a281ce-20a9-42e0-9145-8dac88616ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64898182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.64898182
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.261450840
Short name T632
Test name
Test status
Simulation time 62759795 ps
CPU time 1.34 seconds
Started Aug 16 05:55:19 PM PDT 24
Finished Aug 16 05:55:20 PM PDT 24
Peak memory 207284 kb
Host smart-75133f0b-e6aa-40fd-9ae0-5076dc105abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261450840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.261450840
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2508271348
Short name T933
Test name
Test status
Simulation time 77794561 ps
CPU time 1.63 seconds
Started Aug 16 05:55:24 PM PDT 24
Finished Aug 16 05:55:25 PM PDT 24
Peak memory 216468 kb
Host smart-d1746ee4-40b0-4fd4-a711-3a234f920365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508271348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2508271348
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3499403440
Short name T352
Test name
Test status
Simulation time 30307499 ps
CPU time 0.85 seconds
Started Aug 16 05:54:54 PM PDT 24
Finished Aug 16 05:54:55 PM PDT 24
Peak memory 206272 kb
Host smart-c5f612aa-e826-4513-8960-6627916a0367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499403440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3499403440
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.615786381
Short name T697
Test name
Test status
Simulation time 38160969964 ps
CPU time 27.97 seconds
Started Aug 16 05:55:36 PM PDT 24
Finished Aug 16 05:56:04 PM PDT 24
Peak memory 241100 kb
Host smart-4e359ae4-a37f-49e3-9e19-d76a70c89768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615786381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.615786381
Directory /workspace/9.spi_device_upload/latest
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