Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2532536	1			T1	1		T2	505		T4	5653
all_values[1]	2532536	1			T1	1		T2	505		T4	5653
all_values[2]	2532536	1			T1	1		T2	505		T4	5653
all_values[3]	2532536	1			T1	1		T2	505		T4	5653
all_values[4]	2532536	1			T1	1		T2	505		T4	5653
all_values[5]	2532536	1			T1	1		T2	505		T4	5653
all_values[6]	2532536	1			T1	1		T2	505		T4	5653
all_values[7]	2532536	1			T1	1		T2	505		T4	5653

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19391354

1

T1

8

T2

4040

T4

45224

auto[1]

868934

1

T17

120

T18

69

T22

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20237098

1

T1

8

T2

4040

T4

45224

auto[1]

23190

1

T8

36

T10

15

T17

70

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2416621	1			T1	1		T2	505		T4	5653
all_values[0]	auto[0]	auto[1]	10467	1			T8	36		T10	15		T17	2
all_values[0]	auto[1]	auto[0]	104899	1			T17	10		T18	7		T22	6
all_values[0]	auto[1]	auto[1]	549	1			T17	6		T18	3		T23	4
all_values[1]	auto[0]	auto[0]	2333618	1			T1	1		T2	505		T4	5653
all_values[1]	auto[0]	auto[1]	6964	1			T17	2		T28	31		T29	18
all_values[1]	auto[1]	auto[0]	191320	1			T17	8		T18	8		T22	8
all_values[1]	auto[1]	auto[1]	634	1			T17	6		T18	4		T22	1
all_values[2]	auto[0]	auto[0]	2485215	1			T1	1		T2	505		T4	5653
all_values[2]	auto[0]	auto[1]	2648	1			T17	2		T28	5		T29	17
all_values[2]	auto[1]	auto[0]	44495	1			T17	7		T18	8		T22	4
all_values[2]	auto[1]	auto[1]	178	1			T17	7		T18	4		T22	2
all_values[3]	auto[0]	auto[0]	2355016	1			T1	1		T2	505		T4	5653
all_values[3]	auto[0]	auto[1]	219	1			T17	3		T18	8		T22	4
all_values[3]	auto[1]	auto[0]	177123	1			T17	9		T18	6		T22	5
all_values[3]	auto[1]	auto[1]	178	1			T17	9		T18	3		T30	5
all_values[4]	auto[0]	auto[0]	2502759	1			T1	1		T2	505		T4	5653
all_values[4]	auto[0]	auto[1]	155	1			T17	1		T18	1		T22	1
all_values[4]	auto[1]	auto[0]	29428	1			T17	9		T18	5		T22	6
all_values[4]	auto[1]	auto[1]	194	1			T17	5		T18	4		T22	3
all_values[5]	auto[0]	auto[0]	2438000	1			T1	1		T2	505		T4	5653
all_values[5]	auto[0]	auto[1]	146	1			T17	2		T18	3		T22	1
all_values[5]	auto[1]	auto[0]	94236	1			T17	13		T18	6		T22	5
all_values[5]	auto[1]	auto[1]	154	1			T17	3		T18	1		T22	2
all_values[6]	auto[0]	auto[0]	2423116	1			T1	1		T2	505		T4	5653
all_values[6]	auto[0]	auto[1]	183	1			T17	7		T18	6		T22	3
all_values[6]	auto[1]	auto[0]	109059	1			T17	4		T18	3		T22	2
all_values[6]	auto[1]	auto[1]	178	1			T17	8		T18	3		T22	2
all_values[7]	auto[0]	auto[0]	2416069	1			T1	1		T2	505		T4	5653
all_values[7]	auto[0]	auto[1]	158	1			T17	1		T18	5		T22	2
all_values[7]	auto[1]	auto[0]	116124	1			T17	10		T18	2		T22	1
all_values[7]	auto[1]	auto[1]	185	1			T17	6		T18	2		T23	2