Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35383	1			T2	2		T4	298		T8	29
auto[SpiFlashAddrCfg]	7511	1			T4	47		T8	2		T10	12
auto[SpiFlashAddr3b]	9060	1			T1	4		T2	4		T4	55
auto[SpiFlashAddr4b]	7704	1			T4	40		T8	19		T10	21

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32925

1

T1

4

T2

6

T4

309

auto[1]

26733

1

T4

131

T8

19

T10

46

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30963

1

T2

2

T4

243

T8

34

auto[1]

28695

1

T1

4

T2

4

T4

197

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39982	1			T2	2		T4	320		T8	31
values[1]	1191	1			T2	2		T4	7		T8	6
values[2]	1356	1			T4	20		T8	5		T10	10
values[3]	1504	1			T4	10		T10	2		T11	2
values[4]	1454	1			T4	8		T8	3		T10	1
values[5]	1378	1			T4	4		T8	2		T10	3
values[6]	1351	1			T2	2		T4	6		T8	2
values[7]	1407	1			T4	7		T10	3		T11	2
values[8]	10035	1			T1	4		T4	58		T8	17

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31341

1

T1

4

T2

6

T8

66

auto[1]

28317

1

T4

440

T10

104

T15

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56465

1

T1

4

T2

6

T4

417

write

3193

1

T4

23

T8

2

T10

7

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19068

1

T1

4

T2

4

T4

114

valids[0x1]

40590

1

T2

2

T4

326

T8

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1563	1			T4	8		T8	2		T10	5
internal_process_ops[0x5a]	1456	1			T4	8		T8	1		T10	4
internal_process_ops[0x05]	21613	1			T4	211		T8	8		T10	10
internal_process_ops[0x35]	1592	1			T4	11		T8	3		T10	5
internal_process_ops[0x15]	1604	1			T4	11		T10	4		T11	2
internal_process_ops[0x03]	1088	1			T4	2		T8	2		T10	1
internal_process_ops[0x0b]	1120	1			T4	3		T8	3		T10	1
internal_process_ops[0x3b]	1049	1			T1	4		T4	4		T8	2
internal_process_ops[0x6b]	1054	1			T4	2		T8	3		T10	1
internal_process_ops[0xbb]	1061	1			T4	4		T8	2		T10	2
internal_process_ops[0xeb]	1091	1			T4	5		T8	1		T10	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58109

1

T1

4

T2

6

T4

433

auto[1]

1549

1

T4

7

T10

3

T13

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57450

1

T1

4

T2

6

T4

424

auto[1]

2208

1

T4

16

T8

1

T10

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10165

1

T2

2

T8

25

T13

60

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6479

1

T8

3

T11

4

T13

25

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2085

1

T13

18

T17

1

T44

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1890

1

T8

2

T13

34

T38

18

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2650

1

T1

4

T2

4

T8

12

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2240

1

T8

3

T11

8

T13

24

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2231

1

T8

8

T13

19

T14

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1972

1

T8

11

T11

6

T13

35

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

164

1

T8

1

T13

1

T38

5

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

105

1

T45

1

T29

3

T41

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

99

1

T13

1

T45

2

T46

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

96

1

T13

4

T29

1

T154

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

116

1

T13

1

T38

1

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

76

1

T13

1

T38

1

T41

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

88

1

T38

1

T45

1

T29

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

112

1

T38

2

T45

3

T29

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

103

1

T8

1

T38

1

T41

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

86

1

T45

2

T46

2

T41

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

85

1

T38

2

T45

2

T49

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

85

1

T13

1

T38

1

T45

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

111

1

T17

1

T38

2

T29

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

101

1

T45

1

T29

1

T20

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

88

1

T13

1

T38

2

T29

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

114

1

T29

1

T83

1

T21

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9643

1

T4

238

T10

36

T39

159

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8246

1

T4

58

T10

11

T39

184

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1415

1

T4

17

T10

6

T15

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1347

1

T4

21

T10

3

T39

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1729

1

T4

22

T10

4

T15

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1682

1

T4

25

T10

19

T39

26

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1331

1

T4

16

T10

8

T15

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1360

1

T4

20

T10

10

T39

24

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

106

1

T4

1

T10

1

T19

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

96

1

T39

6

T18

1

T19

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

82

1

T39

2

T28

1

T84

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

102

1

T4

1

T19

1

T20

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

117

1

T4

6

T10

1

T39

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

88

1

T4

2

T39

5

T40

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

97

1

T4

1

T10

2

T39

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

80

1

T20

1

T155

1

T23

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

104

1

T4

3

T28

1

T40

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

105

1

T4

2

T19

1

T20

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

95

1

T4

1

T39

3

T20

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

96

1

T4

2

T39

3

T28

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

85

1

T4

2

T39

2

T19

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

113

1

T10

2

T39

4

T40

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

104

1

T4

2

T39

4

T20

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

94

1

T10

1

T20

1

T84

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3783	1			T2	2		T8	13		T11	2
auto[0]	values[0]	valids[0x1]	15754	1			T8	18		T11	4		T13	66
auto[0]	values[1]	valids[0x1]	650	1			T2	2		T8	6		T13	3
auto[0]	values[2]	valids[0x0]	497	1			T8	2		T11	2		T13	5
auto[0]	values[2]	valids[0x1]	291	1			T8	3		T13	5		T44	4
auto[0]	values[3]	valids[0x0]	597	1			T13	2		T17	3		T38	5
auto[0]	values[3]	valids[0x1]	323	1			T11	2		T13	4		T17	2
auto[0]	values[4]	valids[0x0]	588	1			T8	2		T13	4		T38	4
auto[0]	values[4]	valids[0x1]	349	1			T8	1		T13	5		T14	2
auto[0]	values[5]	valids[0x0]	567	1			T8	2		T13	13		T17	1
auto[0]	values[5]	valids[0x1]	279	1			T13	2		T38	1		T45	2
auto[0]	values[6]	valids[0x0]	546	1			T2	2		T8	1		T11	2
auto[0]	values[6]	valids[0x1]	260	1			T8	1		T13	3		T38	1
auto[0]	values[7]	valids[0x0]	540	1			T11	2		T13	6		T17	3
auto[0]	values[7]	valids[0x1]	260	1			T13	3		T38	3		T45	5
auto[0]	values[8]	valids[0x0]	3739	1			T1	4		T8	14		T11	2
auto[0]	values[8]	valids[0x1]	2318	1			T8	3		T11	2		T13	30
auto[1]	values[0]	valids[0x0]	3764	1			T4	41		T10	20		T39	53
auto[1]	values[0]	valids[0x1]	16681	1			T4	279		T10	34		T15	1
auto[1]	values[1]	valids[0x1]	541	1			T4	7		T10	2		T39	1
auto[1]	values[2]	valids[0x0]	365	1			T4	8		T10	9		T39	7
auto[1]	values[2]	valids[0x1]	203	1			T4	12		T10	1		T39	4
auto[1]	values[3]	valids[0x0]	354	1			T4	7		T10	1		T39	5
auto[1]	values[3]	valids[0x1]	230	1			T4	3		T10	1		T39	4
auto[1]	values[4]	valids[0x0]	321	1			T4	4		T10	1		T39	4
auto[1]	values[4]	valids[0x1]	196	1			T4	4		T39	1		T19	6
auto[1]	values[5]	valids[0x0]	330	1			T4	4		T10	3		T39	13
auto[1]	values[5]	valids[0x1]	202	1			T39	3		T40	4		T19	1
auto[1]	values[6]	valids[0x0]	342	1			T4	6		T10	5		T39	8
auto[1]	values[6]	valids[0x1]	203	1			T10	3		T39	2		T28	4
auto[1]	values[7]	valids[0x0]	375	1			T4	6		T39	9		T28	1
auto[1]	values[7]	valids[0x1]	232	1			T4	1		T10	3		T39	2
auto[1]	values[8]	valids[0x0]	2360	1			T4	38		T10	14		T15	4
auto[1]	values[8]	valids[0x1]	1618	1			T4	20		T10	7		T39	29