Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3198862

1

T1

2454

T2

1

T4

13721

auto[1]

34853

1

T4

200

T8

6

T10

4

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

722593

1

T1

2454

T2

1

T4

86

auto[1]

2511122

1

T4

13835

T8

2885

T10

6099

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	641830	1			T1	520		T2	1		T4	3510
auto[524288:1048575]	412743	1			T1	301		T4	1038		T8	2620
auto[1048576:1572863]	345754	1			T1	248		T4	1435		T10	1558
auto[1572864:2097151]	388839	1			T1	185		T4	952		T10	3
auto[2097152:2621439]	356432	1			T1	53		T8	2		T13	127
auto[2621440:3145727]	357251	1			T1	361		T4	25		T8	5
auto[3145728:3670015]	440592	1			T1	210		T4	6033		T8	2
auto[3670016:4194303]	290274	1			T1	576		T4	928		T8	260

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2541983

1

T1

273

T2

1

T4

13905

auto[1]

691732

1

T1

2181

T4

16

T13

11

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2779660

1

T1

2454

T2

1

T4

12457

auto[1]

454055

1

T4

1464

T8

2493

T10

1339

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	192511	1			T1	520		T2	1		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	380360	1			T4	2658		T8	1		T10	2056
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	76423	1			T1	301		T4	6		T8	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	259307	1			T4	700		T8	128		T10	1153
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	55767	1			T1	248		T4	5		T10	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	232083	1			T4	1428		T10	1554		T13	4409
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	87183	1			T1	185		T4	16		T10	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	248207	1			T4	879		T10	1		T13	4183
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	66475	1			T1	53		T13	75		T16	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	216698	1			T13	1		T17	1558		T38	254
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	49182	1			T1	361		T4	3		T8	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	264905	1			T4	3		T8	4		T13	516
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	119349	1			T1	210		T4	21		T8	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	265255	1			T4	5681		T13	512		T38	1155
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	64587	1			T1	576		T4	1		T8	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	172114	1			T4	927		T8	256		T10	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	911	1			T4	3		T45	16		T28	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	63697	1			T4	829		T10	307		T28	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	655	1			T4	2		T13	4		T38	10
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	70570	1			T4	281		T8	2491		T46	62
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1304	1			T4	2		T13	46		T38	13
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	53086	1			T13	3145		T39	1		T45	3241
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1450	1			T4	2		T13	10		T38	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	47170	1			T4	1		T28	1		T29	1307
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	448	1			T8	2		T13	4		T38	10
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	69818	1			T39	1448		T19	1777		T41	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1627	1			T4	2		T38	38		T39	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	35288	1			T4	1		T38	4		T39	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	625	1			T4	6		T10	5		T13	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	52110	1			T4	263		T10	1027		T28	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	613	1			T13	5		T39	4		T28	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	49084	1			T39	1		T28	129		T29	1506
auto[1]	auto[0]	auto[0:524287]	auto[0]	473	1			T4	1		T8	1		T39	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3388	1			T4	18		T8	5		T39	18
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	394	1			T4	3		T10	1		T13	8
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	4649	1			T4	21		T13	182		T39	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	285	1			T10	1		T13	3		T38	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2087	1			T39	21		T45	2		T18	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	393	1			T4	2		T10	1		T13	12
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3915	1			T4	30		T13	128		T39	49
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	337	1			T45	7		T28	1		T29	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2044	1			T13	47		T28	11		T29	14
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	393	1			T4	1		T13	4		T38	15
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	4822	1			T4	7		T13	153		T38	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	272	1			T4	4		T13	3		T28	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2543	1			T4	41		T28	5		T29	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	295	1			T10	1		T13	12		T38	9
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2964	1			T39	26		T19	2		T41	28
auto[1]	auto[1]	auto[0:524287]	auto[0]	85	1			T28	1		T48	1		T167	19
auto[1]	auto[1]	auto[0:524287]	auto[1]	405	1			T28	1		T48	9		T64	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	105	1			T4	1		T13	5		T19	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	640	1			T4	24		T41	23		T21	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	98	1			T39	1		T45	11		T20	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1044	1			T39	14		T45	256		T155	14
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	85	1			T4	1		T28	1		T40	16
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	436	1			T4	21		T20	5		T155	16
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	60	1			T39	1		T19	1		T41	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	552	1			T39	9		T19	2		T41	109
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	76	1			T4	1		T39	1		T20	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	958	1			T4	7		T39	10		T84	20
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	69	1			T4	2		T28	1		T23	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	369	1			T4	15		T28	1		T23	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	63	1			T39	1		T28	1		T19	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	554	1			T39	9		T28	2		T167	142

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2062327	1			T1	273		T2	1		T4	12324
auto[0]	auto[0]	auto[1]	688079	1			T1	2181		T4	5		T15	2239
auto[0]	auto[1]	auto[0]	445450	1			T4	1390		T8	2493		T10	1339
auto[0]	auto[1]	auto[1]	3006	1			T4	2		T39	2		T41	3
auto[1]	auto[0]	auto[0]	28716	1			T4	123		T8	6		T10	4
auto[1]	auto[0]	auto[1]	538	1			T4	5		T13	10		T38	6
auto[1]	auto[1]	auto[0]	5490	1			T4	68		T13	4		T39	43
auto[1]	auto[1]	auto[1]	109	1			T4	4		T13	1		T39	3