Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2532536	1			T1	1		T2	505		T4	5653
all_pins[1]	2532536	1			T1	1		T2	505		T4	5653
all_pins[2]	2532536	1			T1	1		T2	505		T4	5653
all_pins[3]	2532536	1			T1	1		T2	505		T4	5653
all_pins[4]	2532536	1			T1	1		T2	505		T4	5653
all_pins[5]	2532536	1			T1	1		T2	505		T4	5653
all_pins[6]	2532536	1			T1	1		T2	505		T4	5653
all_pins[7]	2532536	1			T1	1		T2	505		T4	5653

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20147993	1			T1	8		T2	4040		T4	45224
values[0x1]	112295	1			T17	50		T18	24		T22	10
transitions[0x0=>0x1]	111614	1			T17	32		T18	19		T22	9
transitions[0x1=>0x0]	111628	1			T17	32		T18	20		T22	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2531939	1			T1	1		T2	505		T4	5653
all_pins[0]	values[0x1]	597	1			T17	6		T18	3		T23	15
all_pins[0]	transitions[0x0=>0x1]	261	1			T17	4		T18	2		T23	6
all_pins[0]	transitions[0x1=>0x0]	353	1			T17	4		T18	3		T22	1
all_pins[1]	values[0x0]	2531847	1			T1	1		T2	505		T4	5653
all_pins[1]	values[0x1]	689	1			T17	6		T18	4		T22	1
all_pins[1]	transitions[0x0=>0x1]	636	1			T17	2		T18	3		T22	1
all_pins[1]	transitions[0x1=>0x0]	130	1			T17	3		T18	3		T22	2
all_pins[2]	values[0x0]	2532353	1			T1	1		T2	505		T4	5653
all_pins[2]	values[0x1]	183	1			T17	7		T18	4		T22	2
all_pins[2]	transitions[0x0=>0x1]	134	1			T17	3		T18	4		T22	2
all_pins[2]	transitions[0x1=>0x0]	129	1			T17	5		T18	3		T30	4
all_pins[3]	values[0x0]	2532358	1			T1	1		T2	505		T4	5653
all_pins[3]	values[0x1]	178	1			T17	9		T18	3		T30	5
all_pins[3]	transitions[0x0=>0x1]	119	1			T17	7		T18	1		T30	5
all_pins[3]	transitions[0x1=>0x0]	135	1			T17	3		T18	2		T22	3
all_pins[4]	values[0x0]	2532342	1			T1	1		T2	505		T4	5653
all_pins[4]	values[0x1]	194	1			T17	5		T18	4		T22	3
all_pins[4]	transitions[0x0=>0x1]	146	1			T17	4		T18	4		T22	2
all_pins[4]	transitions[0x1=>0x0]	1314	1			T17	2		T18	1		T22	1
all_pins[5]	values[0x0]	2531174	1			T1	1		T2	505		T4	5653
all_pins[5]	values[0x1]	1362	1			T17	3		T18	1		T22	2
all_pins[5]	transitions[0x0=>0x1]	1325	1			T17	2		T18	1		T22	2
all_pins[5]	transitions[0x1=>0x0]	108870	1			T17	7		T18	3		T22	2
all_pins[6]	values[0x0]	2423629	1			T1	1		T2	505		T4	5653
all_pins[6]	values[0x1]	108907	1			T17	8		T18	3		T22	2
all_pins[6]	transitions[0x0=>0x1]	108860	1			T17	6		T18	3		T22	2
all_pins[6]	transitions[0x1=>0x0]	138	1			T17	4		T18	2		T23	2
all_pins[7]	values[0x0]	2532351	1			T1	1		T2	505		T4	5653
all_pins[7]	values[0x1]	185	1			T17	6		T18	2		T23	2
all_pins[7]	transitions[0x0=>0x1]	133	1			T17	4		T18	1		T23	1
all_pins[7]	transitions[0x1=>0x0]	559	1			T17	4		T18	3		T23	14