Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17993

1

T1

4

T2

6

T8

47

auto[1]

13348

1

T8

19

T11

18

T13

125

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4438	1			T1	4		T13	20		T17	20
values[1]	3623	1			T8	26		T14	6		T38	20
values[2]	4161	1			T2	6		T8	20		T13	40
values[3]	3342	1			T38	20		T45	20		T29	61
values[4]	3778	1			T13	100		T16	4		T45	20
values[5]	4614	1			T38	40		T45	20		T29	46
values[6]	3497	1			T8	20		T11	18		T13	60
values[7]	3888	1			T13	20		T38	20		T45	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3834	1			T13	20		T16	4		T17	20
values[1]	4447	1			T13	40		T38	40		T45	40
values[2]	3970	1			T8	20		T13	40		T44	14
values[3]	3773	1			T8	20		T11	18		T14	6
values[4]	3350	1			T2	6		T13	20		T38	20
values[5]	4181	1			T13	80		T38	60		T45	20
values[6]	3733	1			T38	20		T46	22		T41	171
values[7]	4053	1			T1	4		T8	26		T13	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	248	1			T17	15		T38	11		T29	12
auto[0]	values[0]	values[1]	321	1			T90	12		T154	10		T164	15
auto[0]	values[0]	values[2]	502	1			T13	11		T44	14		T41	14
auto[0]	values[0]	values[3]	364	1			T83	8		T20	16		T48	23
auto[0]	values[0]	values[4]	254	1			T45	9		T30	13		T183	9
auto[0]	values[0]	values[5]	317	1			T154	11		T190	14		T175	14
auto[0]	values[0]	values[6]	294	1			T48	14		T167	13		T202	11
auto[0]	values[0]	values[7]	192	1			T1	4		T214	2		T203	14
auto[0]	values[1]	values[0]	305	1			T21	27		T85	24		T194	14
auto[0]	values[1]	values[1]	389	1			T38	13		T215	14		T182	29
auto[0]	values[1]	values[2]	329	1			T85	22		T172	20		T167	14
auto[0]	values[1]	values[3]	164	1			T14	6		T41	15		T30	14
auto[0]	values[1]	values[4]	442	1			T48	12		T216	2		T85	15
auto[0]	values[1]	values[5]	140	1			T85	29		T186	14		T217	12
auto[0]	values[1]	values[6]	244	1			T164	10		T218	8		T219	10
auto[0]	values[1]	values[7]	220	1			T8	17		T48	19		T220	2
auto[0]	values[2]	values[0]	265	1			T38	15		T41	12		T20	19
auto[0]	values[2]	values[1]	269	1			T38	5		T41	13		T171	13
auto[0]	values[2]	values[2]	255	1			T8	18		T13	10		T85	26
auto[0]	values[2]	values[3]	332	1			T17	10		T191	39		T204	8
auto[0]	values[2]	values[4]	244	1			T2	6		T50	9		T85	24
auto[0]	values[2]	values[5]	307	1			T13	13		T221	2		T222	2
auto[0]	values[2]	values[6]	292	1			T154	13		T175	13		T194	6
auto[0]	values[2]	values[7]	318	1			T38	10		T223	4		T202	16
auto[0]	values[3]	values[0]	190	1			T154	11		T164	11		T205	6
auto[0]	values[3]	values[1]	244	1			T45	16		T29	18		T21	10
auto[0]	values[3]	values[2]	293	1			T21	14		T224	4		T192	44
auto[0]	values[3]	values[3]	244	1			T20	10		T154	11		T172	11
auto[0]	values[3]	values[4]	319	1			T225	10		T21	6		T50	10
auto[0]	values[3]	values[5]	219	1			T38	11		T29	8		T49	14
auto[0]	values[3]	values[6]	114	1			T171	8		T164	10		T175	10
auto[0]	values[3]	values[7]	179	1			T226	12		T164	11		T227	42
auto[0]	values[4]	values[0]	311	1			T13	7		T16	4		T29	15
auto[0]	values[4]	values[1]	256	1			T13	7		T83	15		T154	12
auto[0]	values[4]	values[2]	152	1			T29	15		T175	30		T188	16
auto[0]	values[4]	values[3]	278	1			T45	13		T29	16		T201	12
auto[0]	values[4]	values[4]	125	1			T13	9		T29	8		T179	15
auto[0]	values[4]	values[5]	290	1			T13	20		T46	16		T85	12
auto[0]	values[4]	values[6]	362	1			T41	107		T164	12		T228	15
auto[0]	values[4]	values[7]	267	1			T173	16		T183	12		T203	24
auto[0]	values[5]	values[0]	345	1			T29	8		T164	10		T85	24
auto[0]	values[5]	values[1]	373	1			T83	11		T21	9		T30	10
auto[0]	values[5]	values[2]	235	1			T38	7		T29	14		T48	6
auto[0]	values[5]	values[3]	462	1			T48	21		T21	12		T229	2
auto[0]	values[5]	values[4]	260	1			T21	9		T30	12		T230	10
auto[0]	values[5]	values[5]	263	1			T85	9		T193	15		T64	20
auto[0]	values[5]	values[6]	262	1			T38	9		T48	9		T30	14
auto[0]	values[5]	values[7]	517	1			T45	7		T21	98		T168	28
auto[0]	values[6]	values[0]	296	1			T30	27		T154	13		T203	13
auto[0]	values[6]	values[1]	281	1			T13	9		T231	8		T232	13
auto[0]	values[6]	values[2]	316	1			T83	36		T48	10		T183	10
auto[0]	values[6]	values[3]	238	1			T8	12		T203	15		T197	24
auto[0]	values[6]	values[4]	155	1			T41	9		T154	12		T167	22
auto[0]	values[6]	values[5]	335	1			T13	11		T38	27		T180	12
auto[0]	values[6]	values[6]	246	1			T85	11		T184	11		T233	22
auto[0]	values[6]	values[7]	314	1			T13	9		T45	10		T172	30
auto[0]	values[7]	values[0]	368	1			T29	27		T154	13		T164	11
auto[0]	values[7]	values[1]	335	1			T45	14		T41	22		T126	16
auto[0]	values[7]	values[2]	297	1			T29	13		T48	12		T49	11
auto[0]	values[7]	values[3]	96	1			T234	2		T235	10		T33	16
auto[0]	values[7]	values[4]	213	1			T38	6		T29	7		T21	11
auto[0]	values[7]	values[5]	314	1			T45	13		T41	39		T171	12
auto[0]	values[7]	values[6]	317	1			T46	11		T41	51		T49	11
auto[0]	values[7]	values[7]	305	1			T13	9		T29	17		T30	12
auto[1]	values[0]	values[0]	129	1			T17	5		T38	9		T29	8
auto[1]	values[0]	values[1]	279	1			T90	8		T154	10		T164	5
auto[1]	values[0]	values[2]	393	1			T13	9		T41	189		T48	15
auto[1]	values[0]	values[3]	413	1			T83	12		T20	46		T236	8
auto[1]	values[0]	values[4]	267	1			T45	11		T30	7		T183	11
auto[1]	values[0]	values[5]	211	1			T154	9		T175	16		T173	13
auto[1]	values[0]	values[6]	131	1			T48	6		T167	7		T202	9
auto[1]	values[0]	values[7]	123	1			T203	6		T207	11		T188	6
auto[1]	values[1]	values[0]	71	1			T21	4		T85	9		T194	6
auto[1]	values[1]	values[1]	194	1			T38	7		T182	12		T197	70
auto[1]	values[1]	values[2]	128	1			T85	6		T172	9		T167	6
auto[1]	values[1]	values[3]	260	1			T41	50		T30	6		T167	7
auto[1]	values[1]	values[4]	158	1			T48	8		T85	10		T175	7
auto[1]	values[1]	values[5]	140	1			T85	15		T186	6		T217	10
auto[1]	values[1]	values[6]	149	1			T164	10		T182	12		T197	11
auto[1]	values[1]	values[7]	290	1			T8	9		T48	1		T154	15
auto[1]	values[2]	values[0]	176	1			T38	5		T41	8		T20	5
auto[1]	values[2]	values[1]	186	1			T38	15		T41	70		T171	7
auto[1]	values[2]	values[2]	270	1			T8	2		T13	10		T85	18
auto[1]	values[2]	values[3]	164	1			T17	10		T164	14		T85	8
auto[1]	values[2]	values[4]	136	1			T50	11		T85	17		T192	6
auto[1]	values[2]	values[5]	236	1			T13	7		T183	46		T197	8
auto[1]	values[2]	values[6]	360	1			T154	7		T175	7		T194	14
auto[1]	values[2]	values[7]	351	1			T38	10		T202	4		T194	19
auto[1]	values[3]	values[0]	120	1			T154	9		T164	9		T202	10
auto[1]	values[3]	values[1]	348	1			T45	4		T29	23		T21	10
auto[1]	values[3]	values[2]	171	1			T21	6		T237	18		T192	7
auto[1]	values[3]	values[3]	191	1			T20	10		T154	9		T238	8
auto[1]	values[3]	values[4]	185	1			T21	14		T50	10		T85	18
auto[1]	values[3]	values[5]	242	1			T38	9		T29	12		T49	6
auto[1]	values[3]	values[6]	188	1			T171	12		T164	10		T175	10
auto[1]	values[3]	values[7]	95	1			T164	9		T227	8		T210	56
auto[1]	values[4]	values[0]	309	1			T13	13		T29	6		T49	8
auto[1]	values[4]	values[1]	227	1			T13	13		T83	5		T154	8
auto[1]	values[4]	values[2]	132	1			T29	6		T175	6		T188	4
auto[1]	values[4]	values[3]	191	1			T45	7		T29	4		T179	9
auto[1]	values[4]	values[4]	158	1			T13	11		T29	12		T179	5
auto[1]	values[4]	values[5]	359	1			T13	20		T46	4		T85	8
auto[1]	values[4]	values[6]	198	1			T41	6		T164	8		T228	7
auto[1]	values[4]	values[7]	163	1			T173	4		T183	8		T203	18
auto[1]	values[5]	values[0]	304	1			T29	12		T164	10		T85	11
auto[1]	values[5]	values[1]	303	1			T83	17		T21	21		T30	10
auto[1]	values[5]	values[2]	118	1			T38	13		T29	12		T48	14
auto[1]	values[5]	values[3]	135	1			T48	7		T21	8		T186	73
auto[1]	values[5]	values[4]	159	1			T21	16		T30	8		T173	11
auto[1]	values[5]	values[5]	308	1			T239	8		T85	37		T193	8
auto[1]	values[5]	values[6]	209	1			T38	11		T48	11		T30	27
auto[1]	values[5]	values[7]	361	1			T45	13		T47	12		T21	12
auto[1]	values[6]	values[0]	146	1			T30	14		T154	7		T203	7
auto[1]	values[6]	values[1]	158	1			T13	11		T232	7		T227	6
auto[1]	values[6]	values[2]	175	1			T83	11		T48	17		T183	10
auto[1]	values[6]	values[3]	171	1			T8	8		T11	18		T203	5
auto[1]	values[6]	values[4]	124	1			T41	11		T154	8		T167	18
auto[1]	values[6]	values[5]	183	1			T13	9		T38	13		T240	8
auto[1]	values[6]	values[6]	162	1			T85	14		T241	18		T184	9
auto[1]	values[6]	values[7]	197	1			T13	11		T45	10		T172	11
auto[1]	values[7]	values[0]	251	1			T29	8		T154	7		T164	9
auto[1]	values[7]	values[1]	284	1			T45	6		T41	18		T21	9
auto[1]	values[7]	values[2]	204	1			T29	7		T48	8		T49	9
auto[1]	values[7]	values[3]	70	1			T62	2		T235	10		T33	4
auto[1]	values[7]	values[4]	151	1			T38	14		T29	19		T21	12
auto[1]	values[7]	values[5]	317	1			T45	7		T41	10		T171	8
auto[1]	values[7]	values[6]	205	1			T46	11		T41	7		T49	9
auto[1]	values[7]	values[7]	161	1			T13	11		T29	9		T30	8