Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	419	1			T1	2		T8	2		T13	3
auto[ReadAddrCrossIntoMailbox]	328	1			T8	2		T13	3		T17	4
auto[ReadAddrCrossOutOfMailbox]	324	1			T8	3		T13	5		T38	1
auto[ReadAddrCrossAllMailbox]	221	1			T1	2		T8	3		T13	3
auto[ReadAddrOutsideMailbox]	3689	1			T8	3		T11	4		T13	43

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2466

1

T1

2

T8

3

T11

2

auto[1]

2515

1

T1

2

T8

10

T11

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	859	1			T8	2		T13	12		T14	2
read_ops[0x0b]	842	1			T8	3		T13	9		T17	3
read_ops[0x3b]	825	1			T1	4		T8	2		T13	7
read_ops[0x6b]	778	1			T8	3		T11	2		T13	7
read_ops[0xbb]	824	1			T8	2		T11	2		T13	9
read_ops[0xeb]	853	1			T8	1		T13	13		T17	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T13	1		T45	1		T29	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T8	1		T17	1		T48	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T38	2		T29	1		T21	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T48	1		T21	1		T164	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T29	1		T48	1		T85	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	38	1			T38	1		T29	1		T41	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T13	2		T48	1		T196	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T21	1		T49	1		T196	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	301	1			T13	5		T14	1		T17	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	338	1			T8	1		T13	4		T14	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T29	2		T83	1		T30	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T38	3		T49	1		T222	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T83	1		T85	1		T173	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T8	1		T17	2		T167	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T8	1		T164	1		T172	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T13	1		T41	1		T30	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T49	1		T164	1		T85	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T8	1		T48	1		T85	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	312	1			T17	1		T44	1		T45	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T13	8		T44	1		T38	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T1	1		T29	1		T46	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T1	1		T8	1		T45	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T38	1		T30	2		T205	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T45	1		T48	1		T30	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T13	1		T29	1		T46	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T41	2		T21	1		T85	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T1	1		T29	1		T20	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T1	1		T29	1		T21	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	307	1			T13	2		T38	1		T45	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	282	1			T8	1		T13	4		T38	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T29	2		T30	1		T167	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T13	1		T29	1		T41	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T13	1		T41	1		T30	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T8	1		T41	1		T49	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T41	1		T242	1		T183	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T41	1		T85	1		T172	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T30	2		T171	1		T205	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T8	1		T49	1		T171	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T8	1		T11	1		T13	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	253	1			T11	1		T13	3		T17	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T38	3		T164	1		T85	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T45	1		T46	1		T21	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T17	1		T30	1		T173	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T45	1		T20	1		T154	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T29	1		T49	1		T186	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T8	1		T13	1		T48	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	30	1			T17	1		T48	1		T196	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T8	1		T45	1		T46	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T11	1		T13	2		T17	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T11	1		T13	6		T38	6
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T29	1		T46	1		T49	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T13	1		T38	2		T90	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T13	1		T30	1		T154	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T13	1		T17	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T8	1		T13	2		T48	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T21	1		T85	1		T167	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T21	1		T49	1		T171	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T13	1		T21	1		T167	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	324	1			T13	2		T38	1		T29	8
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	326	1			T13	5		T38	1		T45	6