Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3515	1			T8	20		T17	20		T38	20
values[1]	3809	1			T1	4		T13	20		T38	20
values[2]	3705	1			T13	60		T14	6		T38	40
values[3]	3803	1			T2	6		T13	40		T17	20
values[4]	3820	1			T13	40		T38	40		T45	20
values[5]	3411	1			T13	20		T38	20		T45	20
values[6]	4724	1			T8	26		T13	20		T16	4
values[7]	4554	1			T8	20		T11	18		T13	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4141	1			T38	20		T45	20		T29	66
values[1]	3991	1			T8	46		T13	20		T44	14
values[2]	3899	1			T13	20		T38	20		T29	41
values[3]	3761	1			T1	4		T13	20		T17	20
values[4]	4186	1			T2	6		T13	40		T14	6
values[5]	4380	1			T13	60		T16	4		T38	20
values[6]	3545	1			T8	20		T11	18		T13	40
values[7]	3438	1			T13	40		T38	40		T29	47

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30566

1

T1

4

T2

6

T8

66

auto[1]

775

1

T13

6

T38

4

T45

9

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	458	1			T48	27		T21	20		T49	19
auto[0]	values[0]	values[1]	244	1			T45	19		T175	20		T202	19
auto[0]	values[0]	values[2]	257	1			T38	20		T178	4		T193	20
auto[0]	values[0]	values[3]	673	1			T45	16		T29	20		T85	23
auto[0]	values[0]	values[4]	456	1			T30	40		T174	16		T85	44
auto[0]	values[0]	values[5]	487	1			T83	28		T236	8		T154	20
auto[0]	values[0]	values[6]	223	1			T8	20		T17	20		T29	34
auto[0]	values[0]	values[7]	612	1			T41	54		T49	20		T30	69
auto[0]	values[1]	values[0]	386	1			T38	19		T29	45		T167	18
auto[0]	values[1]	values[1]	488	1			T204	8		T171	20		T164	20
auto[0]	values[1]	values[2]	393	1			T48	20		T175	35		T243	18
auto[0]	values[1]	values[3]	358	1			T1	4		T47	10		T226	12
auto[0]	values[1]	values[4]	525	1			T46	18		T48	40		T30	20
auto[0]	values[1]	values[5]	521	1			T48	28		T164	20		T203	20
auto[0]	values[1]	values[6]	645	1			T21	26		T154	20		T164	20
auto[0]	values[1]	values[7]	393	1			T13	20		T83	20		T41	20
auto[0]	values[2]	values[0]	604	1			T194	40		T182	52		T244	6
auto[0]	values[2]	values[1]	526	1			T83	46		T216	2		T224	4
auto[0]	values[2]	values[2]	445	1			T13	20		T30	20		T167	17
auto[0]	values[2]	values[3]	393	1			T13	19		T48	29		T30	19
auto[0]	values[2]	values[4]	513	1			T13	20		T14	6		T38	19
auto[0]	values[2]	values[5]	406	1			T38	20		T21	20		T164	20
auto[0]	values[2]	values[6]	328	1			T45	20		T245	20		T246	17
auto[0]	values[2]	values[7]	398	1			T29	21		T20	24		T126	16
auto[0]	values[3]	values[0]	416	1			T30	38		T85	20		T167	20
auto[0]	values[3]	values[1]	581	1			T44	14		T45	19		T154	20
auto[0]	values[3]	values[2]	400	1			T29	19		T41	63		T154	19
auto[0]	values[3]	values[3]	321	1			T17	20		T168	28		T49	20
auto[0]	values[3]	values[4]	501	1			T2	6		T237	18		T167	20
auto[0]	values[3]	values[5]	740	1			T13	20		T45	18		T21	54
auto[0]	values[3]	values[6]	441	1			T13	20		T41	20		T175	32
auto[0]	values[3]	values[7]	303	1			T49	20		T164	19		T173	18
auto[0]	values[4]	values[0]	463	1			T50	20		T247	16		T240	6
auto[0]	values[4]	values[1]	388	1			T13	18		T48	25		T191	39
auto[0]	values[4]	values[2]	652	1			T29	20		T248	57		T91	4
auto[0]	values[4]	values[3]	560	1			T45	20		T49	17		T85	63
auto[0]	values[4]	values[4]	273	1			T85	24		T167	19		T193	23
auto[0]	values[4]	values[5]	497	1			T200	18		T85	25		T175	88
auto[0]	values[4]	values[6]	662	1			T38	20		T154	20		T222	2
auto[0]	values[4]	values[7]	244	1			T13	20		T38	20		T249	2
auto[0]	values[5]	values[0]	273	1			T45	19		T21	20		T175	56
auto[0]	values[5]	values[1]	468	1			T171	18		T180	12		T183	130
auto[0]	values[5]	values[2]	544	1			T154	20		T183	20		T194	19
auto[0]	values[5]	values[3]	427	1			T167	19		T202	18		T203	42
auto[0]	values[5]	values[4]	443	1			T225	10		T171	16		T183	51
auto[0]	values[5]	values[5]	473	1			T13	20		T83	20		T171	19
auto[0]	values[5]	values[6]	289	1			T29	20		T48	20		T30	21
auto[0]	values[5]	values[7]	416	1			T38	20		T46	22		T175	18
auto[0]	values[6]	values[0]	434	1			T48	19		T239	8		T154	20
auto[0]	values[6]	values[1]	640	1			T8	26		T29	17		T30	20
auto[0]	values[6]	values[2]	574	1			T41	113		T250	8		T251	16
auto[0]	values[6]	values[3]	366	1			T38	58		T41	20		T50	18
auto[0]	values[6]	values[4]	699	1			T29	18		T41	20		T21	130
auto[0]	values[6]	values[5]	658	1			T13	19		T16	4		T41	49
auto[0]	values[6]	values[6]	629	1			T85	18		T252	16		T173	20
auto[0]	values[6]	values[7]	615	1			T41	299		T21	20		T85	54
auto[0]	values[7]	values[0]	988	1			T29	20		T164	20		T253	10
auto[0]	values[7]	values[1]	555	1			T8	20		T20	59		T48	20
auto[0]	values[7]	values[2]	547	1			T201	12		T195	75		T85	25
auto[0]	values[7]	values[3]	579	1			T48	20		T154	18		T171	20
auto[0]	values[7]	values[4]	658	1			T13	19		T90	20		T220	2
auto[0]	values[7]	values[5]	493	1			T29	21		T183	20		T182	65
auto[0]	values[7]	values[6]	240	1			T11	18		T13	19		T38	20
auto[0]	values[7]	values[7]	384	1			T29	26		T154	19		T231	8
auto[1]	values[0]	values[0]	15	1			T49	1		T173	6		T182	2
auto[1]	values[0]	values[1]	10	1			T45	1		T202	1		T193	2
auto[1]	values[0]	values[2]	11	1			T193	2		T187	2		T131	1
auto[1]	values[0]	values[3]	14	1			T45	4		T172	1		T182	1
auto[1]	values[0]	values[4]	14	1			T30	1		T85	2		T172	2
auto[1]	values[0]	values[5]	14	1			T202	1		T192	3		T210	1
auto[1]	values[0]	values[6]	14	1			T29	1		T21	3		T85	4
auto[1]	values[0]	values[7]	13	1			T41	4		T30	1		T154	1
auto[1]	values[1]	values[0]	16	1			T38	1		T29	1		T167	2
auto[1]	values[1]	values[1]	7	1			T194	1		T197	2		T254	1
auto[1]	values[1]	values[2]	12	1			T175	2		T207	1		T192	1
auto[1]	values[1]	values[3]	8	1			T47	2		T49	3		T255	1
auto[1]	values[1]	values[4]	21	1			T46	2		T175	3		T202	1
auto[1]	values[1]	values[5]	7	1			T256	3		T257	2		T258	1
auto[1]	values[1]	values[6]	25	1			T21	4		T85	3		T167	5
auto[1]	values[1]	values[7]	4	1			T259	1		T260	1		T261	2
auto[1]	values[2]	values[0]	11	1			T197	1		T179	1		T262	1
auto[1]	values[2]	values[1]	19	1			T83	1		T85	2		T175	1
auto[1]	values[2]	values[2]	17	1			T30	1		T167	3		T183	1
auto[1]	values[2]	values[3]	7	1			T13	1		T48	1		T30	1
auto[1]	values[2]	values[4]	19	1			T38	1		T238	2		T202	1
auto[1]	values[2]	values[5]	10	1			T194	1		T182	5		T263	4
auto[1]	values[2]	values[6]	5	1			T246	3		T132	1		T58	1
auto[1]	values[2]	values[7]	4	1			T30	1		T167	1		T175	1
auto[1]	values[3]	values[0]	14	1			T30	2		T184	2		T264	2
auto[1]	values[3]	values[1]	17	1			T45	1		T173	1		T194	1
auto[1]	values[3]	values[2]	10	1			T29	1		T41	2		T154	1
auto[1]	values[3]	values[3]	6	1			T203	2		T259	1		T213	1
auto[1]	values[3]	values[4]	14	1			T232	1		T227	2		T198	2
auto[1]	values[3]	values[5]	15	1			T45	2		T154	4		T193	2
auto[1]	values[3]	values[6]	10	1			T188	5		T184	2		T33	1
auto[1]	values[3]	values[7]	14	1			T164	1		T173	2		T235	3
auto[1]	values[4]	values[0]	19	1			T240	2		T179	4		T217	2
auto[1]	values[4]	values[1]	5	1			T13	2		T48	1		T265	1
auto[1]	values[4]	values[2]	9	1			T29	1		T217	1		T33	3
auto[1]	values[4]	values[3]	15	1			T49	3		T266	2		T267	3
auto[1]	values[4]	values[4]	10	1			T85	1		T167	1		T187	1
auto[1]	values[4]	values[5]	10	1			T175	4		T202	1		T217	1
auto[1]	values[4]	values[6]	8	1			T173	3		T268	2		T266	1
auto[1]	values[4]	values[7]	5	1			T235	2		T257	3		-	-
auto[1]	values[5]	values[0]	9	1			T45	1		T182	1		T213	1
auto[1]	values[5]	values[1]	9	1			T171	2		T183	1		T192	1
auto[1]	values[5]	values[2]	8	1			T194	1		T269	1		T132	2
auto[1]	values[5]	values[3]	8	1			T167	1		T202	2		T188	2
auto[1]	values[5]	values[4]	13	1			T171	4		T183	2		T207	1
auto[1]	values[5]	values[5]	12	1			T171	1		T203	1		T197	1
auto[1]	values[5]	values[6]	12	1			T30	2		T175	3		T270	1
auto[1]	values[5]	values[7]	7	1			T175	2		T271	2		T272	1
auto[1]	values[6]	values[0]	16	1			T48	1		T85	3		T203	1
auto[1]	values[6]	values[1]	20	1			T29	3		T85	1		T64	1
auto[1]	values[6]	values[2]	3	1			T273	3		-	-		-	-
auto[1]	values[6]	values[3]	8	1			T38	2		T50	2		T132	1
auto[1]	values[6]	values[4]	10	1			T29	2		T85	4		T274	1
auto[1]	values[6]	values[5]	21	1			T13	1		T164	2		T193	1
auto[1]	values[6]	values[6]	11	1			T85	2		T197	1		T188	2
auto[1]	values[6]	values[7]	20	1			T41	7		T265	2		T275	1
auto[1]	values[7]	values[0]	19	1			T173	1		T32	4		T254	4
auto[1]	values[7]	values[1]	14	1			T20	3		T49	2		T188	3
auto[1]	values[7]	values[2]	17	1			T85	3		T167	2		T32	2
auto[1]	values[7]	values[3]	18	1			T154	2		T167	3		T276	2
auto[1]	values[7]	values[4]	17	1			T13	1		T197	1		T192	2
auto[1]	values[7]	values[5]	16	1			T182	2		T259	2		T227	1
auto[1]	values[7]	values[6]	3	1			T13	1		T277	2		-	-
auto[1]	values[7]	values[7]	6	1			T154	1		T265	2		T213	2