Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	754	1			T17	18		T18	14		T22	8
all_values[1]	754	1			T17	18		T18	14		T22	8
all_values[2]	754	1			T17	18		T18	14		T22	8
all_values[3]	754	1			T17	18		T18	14		T22	8
all_values[4]	754	1			T17	18		T18	14		T22	8
all_values[5]	754	1			T17	18		T18	14		T22	8
all_values[6]	754	1			T17	18		T18	14		T22	8
all_values[7]	754	1			T17	18		T18	14		T22	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3180

1

T17

59

T18

64

T22

40

auto[1]

2852

1

T17

85

T18

48

T22

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2446

1

T17

58

T18

37

T22

29

auto[1]

3586

1

T17

86

T18

75

T22

35

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3479

1

T17

93

T18

60

T22

38

auto[1]

2553

1

T17

51

T18

52

T22

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	174	1			T17	2		T22	1		T23	1
all_values[0]	auto[0]	auto[0]	auto[1]	68	1			T17	2		T18	2		T22	1
all_values[0]	auto[0]	auto[1]	auto[0]	136	1			T17	6		T18	4		T22	3
all_values[0]	auto[0]	auto[1]	auto[1]	59	1			T17	1		T23	1		T153	1
all_values[0]	auto[1]	auto[0]	auto[1]	172	1			T17	3		T18	6		T22	3
all_values[0]	auto[1]	auto[1]	auto[1]	145	1			T17	4		T18	2		T23	3
all_values[1]	auto[0]	auto[0]	auto[0]	133	1			T17	4		T23	1		T30	2
all_values[1]	auto[0]	auto[0]	auto[1]	83	1			T17	2		T18	3		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	144	1			T17	4		T18	3		T22	4
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T17	1		T18	1		T85	1
all_values[1]	auto[1]	auto[0]	auto[1]	167	1			T17	1		T18	2		T22	3
all_values[1]	auto[1]	auto[1]	auto[1]	147	1			T17	6		T18	5		T30	4
all_values[2]	auto[0]	auto[0]	auto[0]	162	1			T17	4		T18	2		T23	3
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T17	3		T18	2		T22	1
all_values[2]	auto[0]	auto[1]	auto[0]	131	1			T17	3		T18	2		T22	2
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T17	4		T18	2		T22	1
all_values[2]	auto[1]	auto[0]	auto[1]	163	1			T17	1		T18	2		T22	3
all_values[2]	auto[1]	auto[1]	auto[1]	146	1			T17	3		T18	4		T22	1
all_values[3]	auto[0]	auto[0]	auto[0]	136	1			T22	1		T23	1		T30	5
all_values[3]	auto[0]	auto[0]	auto[1]	89	1			T17	3		T18	4		T22	1
all_values[3]	auto[0]	auto[1]	auto[0]	107	1			T17	4		T18	1		T22	2
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T17	3		T18	2		T30	2
all_values[3]	auto[1]	auto[0]	auto[1]	195	1			T17	3		T18	5		T22	3
all_values[3]	auto[1]	auto[1]	auto[1]	150	1			T17	5		T18	2		T22	1
all_values[4]	auto[0]	auto[0]	auto[0]	151	1			T17	4		T18	4		T22	1
all_values[4]	auto[0]	auto[0]	auto[1]	62	1			T23	2		T30	4		T31	2
all_values[4]	auto[0]	auto[1]	auto[0]	134	1			T17	4		T18	3		T22	2
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T17	3		T18	1		T22	1
all_values[4]	auto[1]	auto[0]	auto[1]	163	1			T17	2		T18	3		T22	2
all_values[4]	auto[1]	auto[1]	auto[1]	169	1			T17	5		T18	3		T22	2
all_values[5]	auto[0]	auto[0]	auto[0]	250	1			T17	3		T18	6		T22	4
all_values[5]	auto[0]	auto[1]	auto[0]	204	1			T17	10		T18	4		T22	1
all_values[5]	auto[1]	auto[0]	auto[1]	154	1			T18	3		T22	1		T23	4
all_values[5]	auto[1]	auto[1]	auto[1]	146	1			T17	5		T18	1		T22	2
all_values[6]	auto[0]	auto[0]	auto[0]	150	1			T17	2		T18	1		T22	3
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T17	6		T18	2		T22	1
all_values[6]	auto[0]	auto[1]	auto[0]	144	1			T18	1		T30	2		T85	1
all_values[6]	auto[0]	auto[1]	auto[1]	78	1			T17	3		T18	1		T22	1
all_values[6]	auto[1]	auto[0]	auto[1]	164	1			T17	5		T18	8		T22	2
all_values[6]	auto[1]	auto[1]	auto[1]	140	1			T17	2		T18	1		T22	1
all_values[7]	auto[0]	auto[0]	auto[0]	160	1			T17	5		T18	3		T22	5
all_values[7]	auto[0]	auto[0]	auto[1]	57	1			T17	1		T18	2		T22	1
all_values[7]	auto[0]	auto[1]	auto[0]	130	1			T17	3		T18	3		T23	2
all_values[7]	auto[0]	auto[1]	auto[1]	75	1			T17	3		T18	1		T23	2
all_values[7]	auto[1]	auto[0]	auto[1]	174	1			T17	3		T18	4		T22	2
all_values[7]	auto[1]	auto[1]	auto[1]	158	1			T17	3		T18	1		T30	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal