Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1752

1

T5

6

T6

15

T8

5

auto[1]

1714

1

T5

8

T6

22

T10

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1792

1

T5

10

T8

4

T10

7

auto[1]

1674

1

T5

4

T6

37

T8

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2787

1

T5

9

T6

37

T8

4

auto[1]

679

1

T5

5

T8

1

T10

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	703	1			T5	5		T6	7		T8	1
valid[1]	681	1			T6	10		T10	1		T12	3
valid[2]	722	1			T5	3		T6	8		T10	1
valid[3]	688	1			T6	8		T12	2		T27	3
valid[4]	672	1			T5	6		T6	4		T8	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	120	1			T8	1		T10	1		T12	1
auto[0]	auto[0]	valid[0]	auto[1]	168	1			T5	1		T6	5		T12	1
auto[0]	auto[0]	valid[1]	auto[0]	112	1			T12	1		T28	1		T29	3
auto[0]	auto[0]	valid[1]	auto[1]	154	1			T6	5		T17	1		T27	2
auto[0]	auto[0]	valid[2]	auto[0]	124	1			T12	2		T18	1		T19	2
auto[0]	auto[0]	valid[2]	auto[1]	181	1			T6	2		T27	1		T89	1
auto[0]	auto[0]	valid[3]	auto[0]	103	1			T28	1		T46	1		T83	1
auto[0]	auto[0]	valid[3]	auto[1]	168	1			T6	2		T27	2		T18	1
auto[0]	auto[0]	valid[4]	auto[0]	109	1			T5	2		T8	2		T10	1
auto[0]	auto[0]	valid[4]	auto[1]	170	1			T5	2		T6	1		T8	1
auto[0]	auto[1]	valid[0]	auto[0]	109	1			T5	3		T10	1		T28	1
auto[0]	auto[1]	valid[0]	auto[1]	179	1			T6	2		T306	1		T307	2
auto[0]	auto[1]	valid[1]	auto[0]	107	1			T83	1		T19	3		T20	2
auto[0]	auto[1]	valid[1]	auto[1]	163	1			T6	5		T12	2		T27	1
auto[0]	auto[1]	valid[2]	auto[0]	107	1			T46	1		T19	1		T21	5
auto[0]	auto[1]	valid[2]	auto[1]	166	1			T5	1		T6	6		T12	2
auto[0]	auto[1]	valid[3]	auto[0]	110	1			T28	1		T29	1		T19	1
auto[0]	auto[1]	valid[3]	auto[1]	170	1			T6	6		T27	1		T306	1
auto[0]	auto[1]	valid[4]	auto[0]	112	1			T10	2		T28	1		T46	3
auto[0]	auto[1]	valid[4]	auto[1]	155	1			T6	3		T89	2		T90	1
auto[1]	auto[0]	valid[0]	auto[0]	67	1			T12	1		T46	1		T18	2
auto[1]	auto[0]	valid[1]	auto[0]	70	1			T46	1		T18	2		T19	1
auto[1]	auto[0]	valid[2]	auto[0]	78	1			T10	1		T29	1		T21	1
auto[1]	auto[0]	valid[3]	auto[0]	66	1			T12	1		T28	1		T21	1
auto[1]	auto[0]	valid[4]	auto[0]	62	1			T5	1		T8	1		T18	1
auto[1]	auto[1]	valid[0]	auto[0]	60	1			T5	1		T90	1		T20	1
auto[1]	auto[1]	valid[1]	auto[0]	75	1			T10	1		T29	1		T19	1
auto[1]	auto[1]	valid[2]	auto[0]	66	1			T5	2		T46	1		T19	1
auto[1]	auto[1]	valid[3]	auto[0]	71	1			T12	1		T29	1		T18	1
auto[1]	auto[1]	valid[4]	auto[0]	64	1			T5	1		T20	1		T300	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal