Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45072

1

T5

332

T7

8

T8

187

auto[1]

17339

1

T5

60

T6

441

T8

36

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46136

1

T5

270

T6

441

T7

4

auto[1]

16275

1

T5

122

T7

4

T8

70

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32265	1			T5	222		T6	228		T7	3
others[1]	5156	1			T5	27		T6	41		T8	25
others[2]	5249	1			T5	28		T6	29		T7	1
others[3]	6045	1			T5	36		T6	52		T7	3
interest[1]	3451	1			T5	27		T6	17		T8	7
interest[4]	21066	1			T5	143		T6	144		T7	3
interest[64]	10245	1			T5	52		T6	74		T7	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14741	1			T5	118		T7	2		T8	55
auto[0]	auto[0]	others[1]	2377	1			T5	11		T8	11		T10	16
auto[0]	auto[0]	others[2]	2462	1			T5	17		T7	1		T8	8
auto[0]	auto[0]	others[3]	2817	1			T5	18		T8	17		T10	28
auto[0]	auto[0]	interest[1]	1609	1			T5	17		T8	3		T10	10
auto[0]	auto[0]	interest[4]	9616	1			T5	76		T7	2		T8	40
auto[0]	auto[0]	interest[64]	4791	1			T5	29		T7	1		T8	23
auto[0]	auto[1]	others[0]	9102	1			T5	35		T6	228		T8	17
auto[0]	auto[1]	others[1]	1433	1			T5	6		T6	41		T8	4
auto[0]	auto[1]	others[2]	1403	1			T5	6		T6	29		T8	1
auto[0]	auto[1]	others[3]	1626	1			T5	4		T6	52		T8	5
auto[0]	auto[1]	interest[1]	932	1			T5	3		T6	17		T8	2
auto[0]	auto[1]	interest[4]	6065	1			T5	19		T6	144		T8	11
auto[0]	auto[1]	interest[64]	2843	1			T5	6		T6	74		T8	7
auto[1]	auto[0]	others[0]	8422	1			T5	69		T7	1		T8	25
auto[1]	auto[0]	others[1]	1346	1			T5	10		T8	10		T10	5
auto[1]	auto[0]	others[2]	1384	1			T5	5		T8	6		T10	13
auto[1]	auto[0]	others[3]	1602	1			T5	14		T7	3		T8	10
auto[1]	auto[0]	interest[1]	910	1			T5	7		T8	2		T10	5
auto[1]	auto[0]	interest[4]	5385	1			T5	48		T7	1		T8	17
auto[1]	auto[0]	interest[64]	2611	1			T5	17		T8	17		T10	9

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal