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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1150
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T99 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2078058083 Aug 17 06:12:42 PM PDT 24 Aug 17 06:12:59 PM PDT 24 1342500944 ps
T1036 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1971471608 Aug 17 06:12:51 PM PDT 24 Aug 17 06:12:52 PM PDT 24 12646789 ps
T112 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.162519533 Aug 17 06:12:51 PM PDT 24 Aug 17 06:12:53 PM PDT 24 345869966 ps
T1037 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1918275226 Aug 17 06:12:52 PM PDT 24 Aug 17 06:12:53 PM PDT 24 20762633 ps
T1038 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3047663222 Aug 17 06:12:57 PM PDT 24 Aug 17 06:12:57 PM PDT 24 67396555 ps
T113 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2537561839 Aug 17 06:12:51 PM PDT 24 Aug 17 06:13:12 PM PDT 24 308434581 ps
T1039 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2465521749 Aug 17 06:12:52 PM PDT 24 Aug 17 06:12:53 PM PDT 24 15324759 ps
T1040 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2595188797 Aug 17 06:12:50 PM PDT 24 Aug 17 06:12:50 PM PDT 24 12959358 ps
T105 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2254318214 Aug 17 06:12:40 PM PDT 24 Aug 17 06:12:45 PM PDT 24 555522768 ps
T101 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.905560673 Aug 17 06:12:46 PM PDT 24 Aug 17 06:12:54 PM PDT 24 328915431 ps
T103 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3450238162 Aug 17 06:12:53 PM PDT 24 Aug 17 06:12:58 PM PDT 24 368430030 ps
T104 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3626863777 Aug 17 06:12:31 PM PDT 24 Aug 17 06:12:34 PM PDT 24 103128784 ps
T143 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2965074003 Aug 17 06:12:53 PM PDT 24 Aug 17 06:12:55 PM PDT 24 85713547 ps
T114 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3788687417 Aug 17 06:12:33 PM PDT 24 Aug 17 06:13:13 PM PDT 24 2734482735 ps
T144 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2019488833 Aug 17 06:12:54 PM PDT 24 Aug 17 06:12:56 PM PDT 24 58495845 ps
T115 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.729375267 Aug 17 06:12:50 PM PDT 24 Aug 17 06:12:51 PM PDT 24 47658682 ps
T116 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1624381295 Aug 17 06:12:46 PM PDT 24 Aug 17 06:12:47 PM PDT 24 31860452 ps
T145 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.438600337 Aug 17 06:13:06 PM PDT 24 Aug 17 06:13:09 PM PDT 24 1078114258 ps
T157 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2114428819 Aug 17 06:12:28 PM PDT 24 Aug 17 06:12:47 PM PDT 24 610494034 ps
T86 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.400224216 Aug 17 06:12:53 PM PDT 24 Aug 17 06:12:54 PM PDT 24 22869605 ps
T146 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3997002087 Aug 17 06:12:48 PM PDT 24 Aug 17 06:12:55 PM PDT 24 299892489 ps
T1041 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1709566335 Aug 17 06:12:33 PM PDT 24 Aug 17 06:12:34 PM PDT 24 16238994 ps
T1042 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1252941622 Aug 17 06:12:54 PM PDT 24 Aug 17 06:12:55 PM PDT 24 12334762 ps
T1043 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4254074285 Aug 17 06:12:50 PM PDT 24 Aug 17 06:12:51 PM PDT 24 34485053 ps
T1044 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3087181893 Aug 17 06:13:11 PM PDT 24 Aug 17 06:13:14 PM PDT 24 459658758 ps
T160 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3168476379 Aug 17 06:12:48 PM PDT 24 Aug 17 06:13:09 PM PDT 24 3292124546 ps
T106 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4170989424 Aug 17 06:13:06 PM PDT 24 Aug 17 06:13:09 PM PDT 24 60992023 ps
T117 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.723690059 Aug 17 06:12:49 PM PDT 24 Aug 17 06:12:51 PM PDT 24 79431128 ps
T1045 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2970003548 Aug 17 06:12:55 PM PDT 24 Aug 17 06:12:58 PM PDT 24 88746953 ps
T118 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.659235641 Aug 17 06:13:01 PM PDT 24 Aug 17 06:13:03 PM PDT 24 65766978 ps
T1046 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2901957254 Aug 17 06:12:50 PM PDT 24 Aug 17 06:12:51 PM PDT 24 11484441 ps
T87 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3057536909 Aug 17 06:13:08 PM PDT 24 Aug 17 06:13:09 PM PDT 24 105870620 ps
T163 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1599061896 Aug 17 06:12:54 PM PDT 24 Aug 17 06:13:08 PM PDT 24 208202316 ps
T161 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3619555387 Aug 17 06:12:53 PM PDT 24 Aug 17 06:13:14 PM PDT 24 778039959 ps
T1047 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3786069673 Aug 17 06:12:48 PM PDT 24 Aug 17 06:12:54 PM PDT 24 227233803 ps
T147 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2140124036 Aug 17 06:13:05 PM PDT 24 Aug 17 06:13:08 PM PDT 24 241058585 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4230851057 Aug 17 06:12:47 PM PDT 24 Aug 17 06:12:49 PM PDT 24 32806191 ps
T1049 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.192601882 Aug 17 06:12:58 PM PDT 24 Aug 17 06:13:00 PM PDT 24 33170432 ps
T1050 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2589498820 Aug 17 06:13:04 PM PDT 24 Aug 17 06:13:05 PM PDT 24 13183698 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2284339287 Aug 17 06:12:37 PM PDT 24 Aug 17 06:12:41 PM PDT 24 187232131 ps
T158 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.659041576 Aug 17 06:12:41 PM PDT 24 Aug 17 06:13:05 PM PDT 24 1144173794 ps
T1052 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2273778329 Aug 17 06:12:53 PM PDT 24 Aug 17 06:12:53 PM PDT 24 14036765 ps
T1053 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2950892194 Aug 17 06:12:59 PM PDT 24 Aug 17 06:13:01 PM PDT 24 27538821 ps
T1054 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.952049913 Aug 17 06:12:55 PM PDT 24 Aug 17 06:12:56 PM PDT 24 12412846 ps
T1055 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2494688230 Aug 17 06:12:41 PM PDT 24 Aug 17 06:12:46 PM PDT 24 71116113 ps
T119 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3474492015 Aug 17 06:12:33 PM PDT 24 Aug 17 06:12:35 PM PDT 24 125176212 ps
T1056 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1610851094 Aug 17 06:13:10 PM PDT 24 Aug 17 06:13:11 PM PDT 24 35971653 ps
T1057 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1693285704 Aug 17 06:13:16 PM PDT 24 Aug 17 06:13:17 PM PDT 24 15951719 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3179207085 Aug 17 06:12:35 PM PDT 24 Aug 17 06:12:36 PM PDT 24 12282867 ps
T1059 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1313688047 Aug 17 06:12:50 PM PDT 24 Aug 17 06:12:58 PM PDT 24 265088560 ps
T120 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2258052327 Aug 17 06:13:03 PM PDT 24 Aug 17 06:13:06 PM PDT 24 383935420 ps
T1060 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.191694253 Aug 17 06:12:32 PM PDT 24 Aug 17 06:12:35 PM PDT 24 39867675 ps
T156 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2432384970 Aug 17 06:12:40 PM PDT 24 Aug 17 06:12:45 PM PDT 24 228227249 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1492148017 Aug 17 06:12:51 PM PDT 24 Aug 17 06:12:53 PM PDT 24 14244657 ps
T1062 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.634714305 Aug 17 06:12:58 PM PDT 24 Aug 17 06:13:02 PM PDT 24 644789033 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4212875979 Aug 17 06:13:02 PM PDT 24 Aug 17 06:13:12 PM PDT 24 552247104 ps
T159 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1636118791 Aug 17 06:12:42 PM PDT 24 Aug 17 06:13:00 PM PDT 24 298429439 ps
T1064 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1721451739 Aug 17 06:12:37 PM PDT 24 Aug 17 06:12:50 PM PDT 24 715886444 ps
T1065 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3907304012 Aug 17 06:12:37 PM PDT 24 Aug 17 06:12:41 PM PDT 24 290441163 ps
T1066 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2074268410 Aug 17 06:12:46 PM PDT 24 Aug 17 06:12:50 PM PDT 24 324803312 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3642670600 Aug 17 06:12:51 PM PDT 24 Aug 17 06:12:53 PM PDT 24 58610751 ps
T1068 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.387658538 Aug 17 06:12:59 PM PDT 24 Aug 17 06:12:59 PM PDT 24 14573875 ps
T1069 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3407456114 Aug 17 06:12:49 PM PDT 24 Aug 17 06:12:51 PM PDT 24 61918303 ps
T1070 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2128949789 Aug 17 06:12:51 PM PDT 24 Aug 17 06:12:53 PM PDT 24 85608888 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3208275879 Aug 17 06:12:27 PM PDT 24 Aug 17 06:12:44 PM PDT 24 2421462851 ps
T121 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2302837641 Aug 17 06:12:58 PM PDT 24 Aug 17 06:13:00 PM PDT 24 157244247 ps
T1072 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3517521065 Aug 17 06:13:11 PM PDT 24 Aug 17 06:13:12 PM PDT 24 117801157 ps
T122 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.541077738 Aug 17 06:12:44 PM PDT 24 Aug 17 06:13:16 PM PDT 24 2087447618 ps
T1073 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3575047091 Aug 17 06:13:08 PM PDT 24 Aug 17 06:13:09 PM PDT 24 18159614 ps
T1074 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2251830699 Aug 17 06:12:34 PM PDT 24 Aug 17 06:12:56 PM PDT 24 1632434727 ps
T123 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.458289884 Aug 17 06:12:37 PM PDT 24 Aug 17 06:12:39 PM PDT 24 207611643 ps
T1075 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.8988451 Aug 17 06:12:57 PM PDT 24 Aug 17 06:12:58 PM PDT 24 31649612 ps
T1076 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1134869035 Aug 17 06:12:58 PM PDT 24 Aug 17 06:13:00 PM PDT 24 65960245 ps
T1077 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2519207862 Aug 17 06:12:29 PM PDT 24 Aug 17 06:12:31 PM PDT 24 122189074 ps
T1078 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1052793136 Aug 17 06:12:49 PM PDT 24 Aug 17 06:12:51 PM PDT 24 163490945 ps
T1079 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3132569009 Aug 17 06:13:01 PM PDT 24 Aug 17 06:13:02 PM PDT 24 46161247 ps
T1080 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.714041709 Aug 17 06:12:50 PM PDT 24 Aug 17 06:12:52 PM PDT 24 37120018 ps
T1081 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1851794059 Aug 17 06:13:09 PM PDT 24 Aug 17 06:13:09 PM PDT 24 13432228 ps
T1082 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3969449525 Aug 17 06:13:12 PM PDT 24 Aug 17 06:13:13 PM PDT 24 12484527 ps
T1083 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2461993413 Aug 17 06:12:56 PM PDT 24 Aug 17 06:12:57 PM PDT 24 16317412 ps
T1084 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1818803480 Aug 17 06:12:52 PM PDT 24 Aug 17 06:12:54 PM PDT 24 91189638 ps
T1085 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3255587730 Aug 17 06:12:30 PM PDT 24 Aug 17 06:12:32 PM PDT 24 20981545 ps
T1086 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1102779993 Aug 17 06:12:42 PM PDT 24 Aug 17 06:12:44 PM PDT 24 88029656 ps
T1087 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2076486237 Aug 17 06:12:41 PM PDT 24 Aug 17 06:12:43 PM PDT 24 810485266 ps
T1088 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.751130722 Aug 17 06:12:36 PM PDT 24 Aug 17 06:12:40 PM PDT 24 535913874 ps
T1089 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4172754787 Aug 17 06:13:03 PM PDT 24 Aug 17 06:13:07 PM PDT 24 215891101 ps
T124 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1062423222 Aug 17 06:12:51 PM PDT 24 Aug 17 06:13:07 PM PDT 24 611188049 ps
T1090 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2028600947 Aug 17 06:13:00 PM PDT 24 Aug 17 06:13:01 PM PDT 24 62527966 ps
T1091 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3073177712 Aug 17 06:12:48 PM PDT 24 Aug 17 06:12:51 PM PDT 24 82767349 ps
T1092 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.747750200 Aug 17 06:12:58 PM PDT 24 Aug 17 06:12:59 PM PDT 24 42243897 ps
T1093 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1052801125 Aug 17 06:12:59 PM PDT 24 Aug 17 06:12:59 PM PDT 24 23924033 ps
T1094 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1230591268 Aug 17 06:12:39 PM PDT 24 Aug 17 06:12:41 PM PDT 24 52332288 ps
T1095 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3705201074 Aug 17 06:12:52 PM PDT 24 Aug 17 06:12:54 PM PDT 24 56009903 ps
T1096 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.921366988 Aug 17 06:13:03 PM PDT 24 Aug 17 06:13:03 PM PDT 24 65188844 ps
T88 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3470872823 Aug 17 06:12:53 PM PDT 24 Aug 17 06:12:55 PM PDT 24 78443693 ps
T1097 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2040546392 Aug 17 06:13:05 PM PDT 24 Aug 17 06:13:06 PM PDT 24 135876016 ps
T1098 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2861835679 Aug 17 06:13:09 PM PDT 24 Aug 17 06:13:10 PM PDT 24 37592112 ps
T162 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3977069589 Aug 17 06:12:51 PM PDT 24 Aug 17 06:13:16 PM PDT 24 3341028619 ps
T1099 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2502505489 Aug 17 06:12:48 PM PDT 24 Aug 17 06:12:49 PM PDT 24 85037050 ps
T1100 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3159877793 Aug 17 06:12:53 PM PDT 24 Aug 17 06:12:54 PM PDT 24 20448277 ps
T1101 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2080171591 Aug 17 06:12:57 PM PDT 24 Aug 17 06:12:58 PM PDT 24 13508853 ps
T1102 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2412606424 Aug 17 06:12:41 PM PDT 24 Aug 17 06:12:57 PM PDT 24 559924541 ps
T1103 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1486262982 Aug 17 06:12:35 PM PDT 24 Aug 17 06:12:42 PM PDT 24 105104315 ps
T1104 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2425954297 Aug 17 06:13:04 PM PDT 24 Aug 17 06:13:08 PM PDT 24 554700907 ps
T1105 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2883235036 Aug 17 06:13:12 PM PDT 24 Aug 17 06:13:12 PM PDT 24 16689118 ps
T1106 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.909227308 Aug 17 06:12:48 PM PDT 24 Aug 17 06:12:52 PM PDT 24 325191152 ps
T1107 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.965530763 Aug 17 06:13:13 PM PDT 24 Aug 17 06:13:14 PM PDT 24 28119327 ps
T1108 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3335919393 Aug 17 06:12:53 PM PDT 24 Aug 17 06:12:55 PM PDT 24 53987917 ps
T1109 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1724872544 Aug 17 06:12:54 PM PDT 24 Aug 17 06:12:57 PM PDT 24 327332000 ps
T1110 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3072806535 Aug 17 06:12:27 PM PDT 24 Aug 17 06:12:29 PM PDT 24 110441657 ps
T1111 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2661034418 Aug 17 06:13:02 PM PDT 24 Aug 17 06:13:02 PM PDT 24 44790113 ps
T1112 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2248544998 Aug 17 06:12:46 PM PDT 24 Aug 17 06:12:49 PM PDT 24 87073543 ps
T1113 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2286305349 Aug 17 06:12:57 PM PDT 24 Aug 17 06:12:58 PM PDT 24 37744244 ps
T1114 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2896365756 Aug 17 06:12:56 PM PDT 24 Aug 17 06:13:02 PM PDT 24 168838621 ps
T1115 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1774055347 Aug 17 06:12:51 PM PDT 24 Aug 17 06:12:53 PM PDT 24 216358270 ps
T1116 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4162915393 Aug 17 06:13:05 PM PDT 24 Aug 17 06:13:08 PM PDT 24 109931641 ps
T1117 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3645989066 Aug 17 06:12:35 PM PDT 24 Aug 17 06:12:48 PM PDT 24 934278486 ps
T1118 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.438958406 Aug 17 06:12:59 PM PDT 24 Aug 17 06:13:00 PM PDT 24 71546196 ps
T1119 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2647681602 Aug 17 06:12:53 PM PDT 24 Aug 17 06:12:53 PM PDT 24 17481353 ps
T1120 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1904918609 Aug 17 06:12:53 PM PDT 24 Aug 17 06:13:17 PM PDT 24 368199783 ps
T1121 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4201214445 Aug 17 06:12:49 PM PDT 24 Aug 17 06:12:50 PM PDT 24 14834164 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4233490102 Aug 17 06:12:38 PM PDT 24 Aug 17 06:12:39 PM PDT 24 22374350 ps
T1123 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1818014387 Aug 17 06:12:32 PM PDT 24 Aug 17 06:12:35 PM PDT 24 44160898 ps
T1124 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.582310158 Aug 17 06:12:53 PM PDT 24 Aug 17 06:12:56 PM PDT 24 405813743 ps
T1125 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1783442472 Aug 17 06:12:54 PM PDT 24 Aug 17 06:12:55 PM PDT 24 18602236 ps
T1126 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2938062445 Aug 17 06:12:51 PM PDT 24 Aug 17 06:13:00 PM PDT 24 342631369 ps
T1127 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3534697714 Aug 17 06:12:51 PM PDT 24 Aug 17 06:12:51 PM PDT 24 20760578 ps
T1128 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1743372377 Aug 17 06:12:52 PM PDT 24 Aug 17 06:13:16 PM PDT 24 1409612014 ps
T1129 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2557798786 Aug 17 06:12:52 PM PDT 24 Aug 17 06:12:56 PM PDT 24 137374519 ps
T1130 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2805269537 Aug 17 06:13:09 PM PDT 24 Aug 17 06:13:11 PM PDT 24 61100284 ps
T1131 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3073698368 Aug 17 06:12:58 PM PDT 24 Aug 17 06:13:04 PM PDT 24 100565723 ps
T1132 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2959430607 Aug 17 06:12:53 PM PDT 24 Aug 17 06:12:56 PM PDT 24 47752875 ps
T1133 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1580230768 Aug 17 06:12:55 PM PDT 24 Aug 17 06:13:19 PM PDT 24 4386135206 ps
T1134 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1702363679 Aug 17 06:13:09 PM PDT 24 Aug 17 06:13:09 PM PDT 24 132757545 ps
T1135 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2497232355 Aug 17 06:12:48 PM PDT 24 Aug 17 06:12:49 PM PDT 24 49589887 ps
T1136 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1122898683 Aug 17 06:12:42 PM PDT 24 Aug 17 06:12:44 PM PDT 24 88479370 ps
T1137 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3653880391 Aug 17 06:12:37 PM PDT 24 Aug 17 06:12:39 PM PDT 24 55922623 ps
T1138 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.470162208 Aug 17 06:12:58 PM PDT 24 Aug 17 06:13:01 PM PDT 24 174434869 ps
T1139 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3473128026 Aug 17 06:12:54 PM PDT 24 Aug 17 06:12:58 PM PDT 24 1425819044 ps
T1140 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1710343466 Aug 17 06:13:05 PM PDT 24 Aug 17 06:13:08 PM PDT 24 52741096 ps
T1141 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.979387542 Aug 17 06:12:58 PM PDT 24 Aug 17 06:13:00 PM PDT 24 108781638 ps
T1142 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1012381633 Aug 17 06:13:00 PM PDT 24 Aug 17 06:13:20 PM PDT 24 1664574583 ps
T1143 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2192130355 Aug 17 06:13:10 PM PDT 24 Aug 17 06:13:11 PM PDT 24 29991764 ps
T1144 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4067004447 Aug 17 06:12:37 PM PDT 24 Aug 17 06:12:38 PM PDT 24 14343107 ps
T1145 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3805076418 Aug 17 06:12:33 PM PDT 24 Aug 17 06:12:36 PM PDT 24 84985788 ps
T1146 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.764632301 Aug 17 06:13:10 PM PDT 24 Aug 17 06:13:11 PM PDT 24 46705071 ps
T1147 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2564233448 Aug 17 06:12:55 PM PDT 24 Aug 17 06:12:57 PM PDT 24 29055164 ps
T1148 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2554493705 Aug 17 06:12:48 PM PDT 24 Aug 17 06:12:51 PM PDT 24 321573094 ps
T1149 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1428285993 Aug 17 06:13:07 PM PDT 24 Aug 17 06:13:08 PM PDT 24 18239597 ps
T1150 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2971090915 Aug 17 06:12:46 PM PDT 24 Aug 17 06:12:47 PM PDT 24 58178413 ps

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1475011840
Short name T8
Test name
Test status
Simulation time 3450136516 ps
CPU time 47.42 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:19:32 PM PDT 24
Peak memory 241176 kb
Host smart-572a4971-0642-4f37-9d93-18d83d74ed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475011840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1475011840
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1326163065
Short name T29
Test name
Test status
Simulation time 14222785732 ps
CPU time 176.36 seconds
Started Aug 17 06:17:12 PM PDT 24
Finished Aug 17 06:20:09 PM PDT 24
Peak memory 263912 kb
Host smart-7a07f441-b5c5-4b3f-84af-9ba47c1f76bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326163065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1326163065
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3909252984
Short name T85
Test name
Test status
Simulation time 306622578260 ps
CPU time 1409.85 seconds
Started Aug 17 06:18:27 PM PDT 24
Finished Aug 17 06:41:57 PM PDT 24
Peak memory 306724 kb
Host smart-a4473b75-7200-4623-b25f-6003cd473620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909252984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3909252984
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1986811698
Short name T98
Test name
Test status
Simulation time 998399023 ps
CPU time 21.56 seconds
Started Aug 17 06:12:39 PM PDT 24
Finished Aug 17 06:13:01 PM PDT 24
Peak memory 215976 kb
Host smart-ea3ec7e4-df76-47c8-bb81-d6cad5d349c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986811698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1986811698
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.850857002
Short name T19
Test name
Test status
Simulation time 34931984129 ps
CPU time 366.3 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:23:57 PM PDT 24
Peak memory 265224 kb
Host smart-f9fc6b92-243c-40b1-ba28-64f7a3d79855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850857002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.850857002
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3198435147
Short name T68
Test name
Test status
Simulation time 73259450 ps
CPU time 0.74 seconds
Started Aug 17 06:17:29 PM PDT 24
Finished Aug 17 06:17:30 PM PDT 24
Peak memory 216156 kb
Host smart-6dc95466-0038-498f-a337-3ef3c4cbbcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198435147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3198435147
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3981703796
Short name T179
Test name
Test status
Simulation time 229428161648 ps
CPU time 848.79 seconds
Started Aug 17 06:18:51 PM PDT 24
Finished Aug 17 06:33:00 PM PDT 24
Peak memory 267804 kb
Host smart-7d9e81dc-348c-494a-b5ee-01f34e77a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981703796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3981703796
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1783294037
Short name T13
Test name
Test status
Simulation time 18649393075 ps
CPU time 183.1 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:20:00 PM PDT 24
Peak memory 251340 kb
Host smart-a35605e2-3326-4eb2-a5d5-2b52fb04afae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783294037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1783294037
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1387786577
Short name T23
Test name
Test status
Simulation time 11746277213 ps
CPU time 164.88 seconds
Started Aug 17 06:17:00 PM PDT 24
Finished Aug 17 06:19:45 PM PDT 24
Peak memory 273272 kb
Host smart-d619a9b8-f1d6-4964-942c-61a294addb52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387786577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1387786577
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2952523349
Short name T100
Test name
Test status
Simulation time 77401013 ps
CPU time 5.45 seconds
Started Aug 17 06:12:41 PM PDT 24
Finished Aug 17 06:12:46 PM PDT 24
Peak memory 216152 kb
Host smart-2a97fcc8-8794-4561-8918-4b702a6ecff7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952523349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
952523349
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3669671248
Short name T182
Test name
Test status
Simulation time 24045122843 ps
CPU time 252.5 seconds
Started Aug 17 06:17:05 PM PDT 24
Finished Aug 17 06:21:17 PM PDT 24
Peak memory 268852 kb
Host smart-36fec642-d61f-44c9-8271-ec270ab36c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669671248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3669671248
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2137694115
Short name T15
Test name
Test status
Simulation time 4099494302 ps
CPU time 19.23 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:17:43 PM PDT 24
Peak memory 232964 kb
Host smart-9d206f05-afeb-456e-b15a-bcaef0e25627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137694115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2137694115
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.916554630
Short name T26
Test name
Test status
Simulation time 68039425 ps
CPU time 0.71 seconds
Started Aug 17 06:17:05 PM PDT 24
Finished Aug 17 06:17:06 PM PDT 24
Peak memory 204988 kb
Host smart-eca18988-3569-4d81-a19b-d15f609f5dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916554630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.916554630
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1984923238
Short name T33
Test name
Test status
Simulation time 28189051846 ps
CPU time 303.24 seconds
Started Aug 17 06:17:26 PM PDT 24
Finished Aug 17 06:22:29 PM PDT 24
Peak memory 265732 kb
Host smart-c47556b3-3349-4b72-addd-a341209f1fe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984923238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1984923238
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2123370757
Short name T203
Test name
Test status
Simulation time 7520031789 ps
CPU time 142.11 seconds
Started Aug 17 06:18:35 PM PDT 24
Finished Aug 17 06:20:58 PM PDT 24
Peak memory 270156 kb
Host smart-06c2e4ae-4aa0-4fb0-baee-1195348f3403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123370757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2123370757
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.642211364
Short name T227
Test name
Test status
Simulation time 18800134264 ps
CPU time 152.33 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:19:30 PM PDT 24
Peak memory 265264 kb
Host smart-98059e70-d1b6-4547-988e-253b090adca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642211364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
642211364
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.400224216
Short name T86
Test name
Test status
Simulation time 22869605 ps
CPU time 0.97 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:54 PM PDT 24
Peak memory 207476 kb
Host smart-8238012d-2593-46db-8a69-2646e2667f0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400224216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.400224216
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2933078134
Short name T275
Test name
Test status
Simulation time 106963617778 ps
CPU time 1028.18 seconds
Started Aug 17 06:18:56 PM PDT 24
Finished Aug 17 06:36:04 PM PDT 24
Peak memory 289728 kb
Host smart-dae3fde6-b3fd-4fef-81d6-a0334e3fa45b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933078134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2933078134
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1812981299
Short name T202
Test name
Test status
Simulation time 69437630399 ps
CPU time 484.51 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:25:56 PM PDT 24
Peak memory 257584 kb
Host smart-a1227bce-21e2-4228-909d-a287b1eb9b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812981299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1812981299
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3291041239
Short name T645
Test name
Test status
Simulation time 53563177 ps
CPU time 1.02 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:17:25 PM PDT 24
Peak memory 215660 kb
Host smart-e55796da-3d5f-4dc1-96d2-1c969ce07433
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291041239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3291041239
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.754845003
Short name T6
Test name
Test status
Simulation time 1753163088 ps
CPU time 9.95 seconds
Started Aug 17 06:18:05 PM PDT 24
Finished Aug 17 06:18:15 PM PDT 24
Peak memory 216508 kb
Host smart-9f4a5ab0-63ac-40d0-b7f5-1c504e4e2080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754845003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.754845003
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3358757865
Short name T69
Test name
Test status
Simulation time 59575982 ps
CPU time 1 seconds
Started Aug 17 06:16:51 PM PDT 24
Finished Aug 17 06:16:52 PM PDT 24
Peak memory 235540 kb
Host smart-2508af7a-9d65-48e2-9ef8-3d8d532fe5e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358757865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3358757865
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2965098281
Short name T30
Test name
Test status
Simulation time 151489248017 ps
CPU time 328.48 seconds
Started Aug 17 06:17:36 PM PDT 24
Finished Aug 17 06:23:05 PM PDT 24
Peak memory 264656 kb
Host smart-966b98cb-f8ef-4eee-9bee-b29e70a0a794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965098281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2965098281
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.67951002
Short name T48
Test name
Test status
Simulation time 38127023013 ps
CPU time 284.91 seconds
Started Aug 17 06:17:19 PM PDT 24
Finished Aug 17 06:22:04 PM PDT 24
Peak memory 249372 kb
Host smart-a5d2f717-3507-47f4-8e05-be7b53051e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67951002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.67951002
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.199991391
Short name T52
Test name
Test status
Simulation time 119735162315 ps
CPU time 135.87 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:21:16 PM PDT 24
Peak memory 260932 kb
Host smart-154e681d-96da-4f8e-b74c-394a13499d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199991391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.199991391
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2095496210
Short name T132
Test name
Test status
Simulation time 248683365329 ps
CPU time 593.02 seconds
Started Aug 17 06:18:23 PM PDT 24
Finished Aug 17 06:28:16 PM PDT 24
Peak memory 269288 kb
Host smart-ec7b747d-c6ff-4171-bdc5-064c02c8c870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095496210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2095496210
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3128206616
Short name T49
Test name
Test status
Simulation time 53361740552 ps
CPU time 95.98 seconds
Started Aug 17 06:18:42 PM PDT 24
Finished Aug 17 06:20:19 PM PDT 24
Peak memory 256072 kb
Host smart-8267c830-0fc2-4a08-b312-5e536bdaa3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128206616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3128206616
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2992567036
Short name T32
Test name
Test status
Simulation time 13232474443 ps
CPU time 94.58 seconds
Started Aug 17 06:18:58 PM PDT 24
Finished Aug 17 06:20:33 PM PDT 24
Peak memory 268324 kb
Host smart-1aa8b1d9-8483-4b8a-9d6d-6054f11775aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992567036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2992567036
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.723821712
Short name T192
Test name
Test status
Simulation time 184837016902 ps
CPU time 439.8 seconds
Started Aug 17 06:16:53 PM PDT 24
Finished Aug 17 06:24:19 PM PDT 24
Peak memory 272936 kb
Host smart-6f1a8f34-73cf-49e8-bda6-46724dc17f86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723821712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.723821712
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2114428819
Short name T157
Test name
Test status
Simulation time 610494034 ps
CPU time 18.27 seconds
Started Aug 17 06:12:28 PM PDT 24
Finished Aug 17 06:12:47 PM PDT 24
Peak memory 215996 kb
Host smart-92de2785-84c1-4be6-9811-6feb9b90cb3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114428819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2114428819
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2219910641
Short name T279
Test name
Test status
Simulation time 7731126952 ps
CPU time 28.28 seconds
Started Aug 17 06:17:46 PM PDT 24
Finished Aug 17 06:18:14 PM PDT 24
Peak memory 233056 kb
Host smart-9ac45277-861b-4be1-b41f-17a1e1a5779d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219910641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2219910641
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1964228109
Short name T188
Test name
Test status
Simulation time 404896840644 ps
CPU time 354.93 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:22:52 PM PDT 24
Peak memory 257508 kb
Host smart-bdb750cc-57ad-498f-83cd-017048dc51ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964228109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1964228109
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4170989424
Short name T106
Test name
Test status
Simulation time 60992023 ps
CPU time 3.46 seconds
Started Aug 17 06:13:06 PM PDT 24
Finished Aug 17 06:13:09 PM PDT 24
Peak memory 216336 kb
Host smart-78f313aa-f1b5-453b-8611-e504452f9ce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170989424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4170989424
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3977069589
Short name T162
Test name
Test status
Simulation time 3341028619 ps
CPU time 24.27 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:13:16 PM PDT 24
Peak memory 216216 kb
Host smart-6f1bb433-1d30-431d-a6a0-59f82f2f80fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977069589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3977069589
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3424049495
Short name T84
Test name
Test status
Simulation time 45379855086 ps
CPU time 98.07 seconds
Started Aug 17 06:17:07 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 249288 kb
Host smart-d0cfc74a-cba6-4106-8cd8-5ac4426442e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424049495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3424049495
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.871685641
Short name T254
Test name
Test status
Simulation time 186905605063 ps
CPU time 314.38 seconds
Started Aug 17 06:17:18 PM PDT 24
Finished Aug 17 06:22:32 PM PDT 24
Peak memory 265788 kb
Host smart-eac3353a-638e-4c27-861a-62db76846467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871685641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.871685641
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3568259170
Short name T257
Test name
Test status
Simulation time 13196458553 ps
CPU time 83.55 seconds
Started Aug 17 06:17:39 PM PDT 24
Finished Aug 17 06:19:03 PM PDT 24
Peak memory 264280 kb
Host smart-ed97fd8a-5f55-4cff-bc78-a5c4f74ca492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568259170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3568259170
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2790816616
Short name T193
Test name
Test status
Simulation time 202540893069 ps
CPU time 477.97 seconds
Started Aug 17 06:17:40 PM PDT 24
Finished Aug 17 06:25:38 PM PDT 24
Peak memory 264260 kb
Host smart-2cd2b2f2-f82f-4c93-861b-830370a16c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790816616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2790816616
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4197865449
Short name T735
Test name
Test status
Simulation time 31947882540 ps
CPU time 293.41 seconds
Started Aug 17 06:18:23 PM PDT 24
Finished Aug 17 06:23:17 PM PDT 24
Peak memory 256976 kb
Host smart-4e70df2f-13d1-4d47-b05b-e62d655e7728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197865449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4197865449
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2054393512
Short name T175
Test name
Test status
Simulation time 158881237016 ps
CPU time 291.17 seconds
Started Aug 17 06:17:23 PM PDT 24
Finished Aug 17 06:22:14 PM PDT 24
Peak memory 255292 kb
Host smart-57082cef-59e2-4b73-8dfd-f8d7e2b763ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054393512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2054393512
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1933543873
Short name T419
Test name
Test status
Simulation time 986603495 ps
CPU time 23.26 seconds
Started Aug 17 06:17:37 PM PDT 24
Finished Aug 17 06:18:00 PM PDT 24
Peak memory 249300 kb
Host smart-112100e1-7a42-432a-86ff-4b48a969aa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933543873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1933543873
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3652598156
Short name T213
Test name
Test status
Simulation time 21920057932 ps
CPU time 175.8 seconds
Started Aug 17 06:17:32 PM PDT 24
Finished Aug 17 06:20:27 PM PDT 24
Peak memory 249360 kb
Host smart-4b9d38c4-4e1e-4943-94ac-15a81f951b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652598156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3652598156
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1483521427
Short name T281
Test name
Test status
Simulation time 1153984446 ps
CPU time 12.19 seconds
Started Aug 17 06:17:32 PM PDT 24
Finished Aug 17 06:17:44 PM PDT 24
Peak memory 232912 kb
Host smart-706c7b3c-876d-438b-97dc-ad7665338c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483521427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1483521427
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1774532640
Short name T800
Test name
Test status
Simulation time 9697217525 ps
CPU time 19.47 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:18:03 PM PDT 24
Peak memory 224716 kb
Host smart-ccaf4cf1-e945-4c74-a747-814e45fc4232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774532640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1774532640
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.830743166
Short name T646
Test name
Test status
Simulation time 667983177 ps
CPU time 8.4 seconds
Started Aug 17 06:17:53 PM PDT 24
Finished Aug 17 06:18:01 PM PDT 24
Peak memory 241088 kb
Host smart-17ce6266-52ca-4a86-9723-2c48a7b11961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830743166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.830743166
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3318973106
Short name T259
Test name
Test status
Simulation time 33604184736 ps
CPU time 170.25 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:20:39 PM PDT 24
Peak memory 255868 kb
Host smart-c766855b-7644-43d0-9d9c-ea758b800990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318973106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3318973106
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1260290090
Short name T46
Test name
Test status
Simulation time 49745382544 ps
CPU time 113.79 seconds
Started Aug 17 06:18:29 PM PDT 24
Finished Aug 17 06:20:23 PM PDT 24
Peak memory 240312 kb
Host smart-de8f10cd-2896-4557-b27c-d7a3ec848d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260290090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1260290090
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3320753329
Short name T273
Test name
Test status
Simulation time 59008409101 ps
CPU time 76.64 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:20:05 PM PDT 24
Peak memory 250356 kb
Host smart-a9f071e0-e094-4b9d-90ca-6e373a0551e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320753329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3320753329
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.403831281
Short name T44
Test name
Test status
Simulation time 6936699419 ps
CPU time 11.94 seconds
Started Aug 17 06:17:01 PM PDT 24
Finished Aug 17 06:17:18 PM PDT 24
Peak memory 232976 kb
Host smart-416c95fb-12b7-4e7c-ab25-8ab517de822d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403831281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.403831281
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.11030424
Short name T42
Test name
Test status
Simulation time 727483108 ps
CPU time 10.16 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:17:34 PM PDT 24
Peak memory 222840 kb
Host smart-4b898b98-fc35-4440-affa-2f5e537014fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=11030424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direc
t.11030424
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3208275879
Short name T1071
Test name
Test status
Simulation time 2421462851 ps
CPU time 16.49 seconds
Started Aug 17 06:12:27 PM PDT 24
Finished Aug 17 06:12:44 PM PDT 24
Peak memory 215964 kb
Host smart-4c4eaf72-1516-4a75-afc8-af834d335167
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208275879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3208275879
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.541077738
Short name T122
Test name
Test status
Simulation time 2087447618 ps
CPU time 32.18 seconds
Started Aug 17 06:12:44 PM PDT 24
Finished Aug 17 06:13:16 PM PDT 24
Peak memory 207696 kb
Host smart-d49c46ec-7d71-4013-b66b-107d761acb11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541077738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.541077738
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3470872823
Short name T88
Test name
Test status
Simulation time 78443693 ps
CPU time 1.39 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:55 PM PDT 24
Peak memory 216976 kb
Host smart-41cef763-c717-4df7-a91c-a66ed0833c81
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470872823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3470872823
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2019488833
Short name T144
Test name
Test status
Simulation time 58495845 ps
CPU time 1.65 seconds
Started Aug 17 06:12:54 PM PDT 24
Finished Aug 17 06:12:56 PM PDT 24
Peak memory 215988 kb
Host smart-6ed92213-5e4b-4a50-8c48-7580aab3cbae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019488833 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2019488833
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2248544998
Short name T1112
Test name
Test status
Simulation time 87073543 ps
CPU time 2.53 seconds
Started Aug 17 06:12:46 PM PDT 24
Finished Aug 17 06:12:49 PM PDT 24
Peak memory 215904 kb
Host smart-801ae0d6-1c22-4d4e-9b82-b9637bd5c4f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248544998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
248544998
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2971090915
Short name T1150
Test name
Test status
Simulation time 58178413 ps
CPU time 0.73 seconds
Started Aug 17 06:12:46 PM PDT 24
Finished Aug 17 06:12:47 PM PDT 24
Peak memory 204668 kb
Host smart-11e390f5-8b6b-4f0c-b077-11d330274ca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971090915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
971090915
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1230591268
Short name T1094
Test name
Test status
Simulation time 52332288 ps
CPU time 1.74 seconds
Started Aug 17 06:12:39 PM PDT 24
Finished Aug 17 06:12:41 PM PDT 24
Peak memory 215892 kb
Host smart-ebe0be08-73f0-4008-b6d1-f6ad52978b87
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230591268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1230591268
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3132569009
Short name T1079
Test name
Test status
Simulation time 46161247 ps
CPU time 0.67 seconds
Started Aug 17 06:13:01 PM PDT 24
Finished Aug 17 06:13:02 PM PDT 24
Peak memory 204648 kb
Host smart-ba78c23f-d99e-445a-b174-a21e09f28f1f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132569009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3132569009
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3072806535
Short name T1110
Test name
Test status
Simulation time 110441657 ps
CPU time 1.81 seconds
Started Aug 17 06:12:27 PM PDT 24
Finished Aug 17 06:12:29 PM PDT 24
Peak memory 215964 kb
Host smart-cff34c1c-ff98-4113-8357-786ac38030c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072806535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3072806535
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3073177712
Short name T1091
Test name
Test status
Simulation time 82767349 ps
CPU time 2.51 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 216044 kb
Host smart-f4840588-d6fd-46f4-8add-0cbbd22da056
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073177712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
073177712
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1599061896
Short name T163
Test name
Test status
Simulation time 208202316 ps
CPU time 13.4 seconds
Started Aug 17 06:12:54 PM PDT 24
Finished Aug 17 06:13:08 PM PDT 24
Peak memory 216052 kb
Host smart-1d0dfea1-8019-4e18-9901-b6e33d7cb1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599061896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1599061896
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4212875979
Short name T1063
Test name
Test status
Simulation time 552247104 ps
CPU time 9.31 seconds
Started Aug 17 06:13:02 PM PDT 24
Finished Aug 17 06:13:12 PM PDT 24
Peak memory 215856 kb
Host smart-96279758-ad04-4793-91ff-df0601abfaf7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212875979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4212875979
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.313515354
Short name T1026
Test name
Test status
Simulation time 6997814681 ps
CPU time 21.44 seconds
Started Aug 17 06:12:42 PM PDT 24
Finished Aug 17 06:13:04 PM PDT 24
Peak memory 207804 kb
Host smart-84ed025a-0071-47ff-835d-54ccd1191db7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313515354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.313515354
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3057536909
Short name T87
Test name
Test status
Simulation time 105870620 ps
CPU time 1.26 seconds
Started Aug 17 06:13:08 PM PDT 24
Finished Aug 17 06:13:09 PM PDT 24
Peak memory 207764 kb
Host smart-b2af2738-7f84-4114-b6d8-b258a038ebe9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057536909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3057536909
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1818014387
Short name T1123
Test name
Test status
Simulation time 44160898 ps
CPU time 2.9 seconds
Started Aug 17 06:12:32 PM PDT 24
Finished Aug 17 06:12:35 PM PDT 24
Peak memory 217084 kb
Host smart-dd86500b-9938-4865-b95d-d2a55aa0b22c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818014387 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1818014387
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3255587730
Short name T1085
Test name
Test status
Simulation time 20981545 ps
CPU time 1.2 seconds
Started Aug 17 06:12:30 PM PDT 24
Finished Aug 17 06:12:32 PM PDT 24
Peak memory 207696 kb
Host smart-af20cc5d-f434-4058-b011-ce718aea729b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255587730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
255587730
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4201214445
Short name T1121
Test name
Test status
Simulation time 14834164 ps
CPU time 0.76 seconds
Started Aug 17 06:12:49 PM PDT 24
Finished Aug 17 06:12:50 PM PDT 24
Peak memory 204652 kb
Host smart-bb0ade9e-95cd-4507-96e8-183560a41428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201214445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
201214445
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2519207862
Short name T1077
Test name
Test status
Simulation time 122189074 ps
CPU time 1.3 seconds
Started Aug 17 06:12:29 PM PDT 24
Finished Aug 17 06:12:31 PM PDT 24
Peak memory 215912 kb
Host smart-47008df7-c3fd-41a2-9f22-d3b80bdf0a89
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519207862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2519207862
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2273778329
Short name T1052
Test name
Test status
Simulation time 14036765 ps
CPU time 0.68 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 204584 kb
Host smart-60420ee1-94b5-4167-89e0-8d63b74a005b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273778329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2273778329
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3642670600
Short name T1067
Test name
Test status
Simulation time 58610751 ps
CPU time 1.74 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 215900 kb
Host smart-2754a122-048e-4440-a185-b43e3d2a6773
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642670600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3642670600
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.191694253
Short name T1060
Test name
Test status
Simulation time 39867675 ps
CPU time 2.46 seconds
Started Aug 17 06:12:32 PM PDT 24
Finished Aug 17 06:12:35 PM PDT 24
Peak memory 216168 kb
Host smart-a153f63d-7084-4461-8f57-042172014dea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191694253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.191694253
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1052793136
Short name T1078
Test name
Test status
Simulation time 163490945 ps
CPU time 1.84 seconds
Started Aug 17 06:12:49 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 215988 kb
Host smart-633790ad-95f5-4513-a873-bdbdf3bd6e57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052793136 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1052793136
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1463409450
Short name T135
Test name
Test status
Simulation time 374323881 ps
CPU time 1.3 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:12:52 PM PDT 24
Peak memory 216032 kb
Host smart-9188bc4d-26fd-4d10-9811-82ada4960c46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463409450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1463409450
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2000033435
Short name T1029
Test name
Test status
Simulation time 20352412 ps
CPU time 0.73 seconds
Started Aug 17 06:12:52 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 204336 kb
Host smart-c7b1e7e5-1ccc-4730-b8d4-67fcdae1205d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000033435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2000033435
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.582310158
Short name T1124
Test name
Test status
Simulation time 405813743 ps
CPU time 2.91 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:56 PM PDT 24
Peak memory 215804 kb
Host smart-88732e59-42a2-43e9-a8f2-98628c43fa6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582310158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.582310158
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2494688230
Short name T1055
Test name
Test status
Simulation time 71116113 ps
CPU time 4.39 seconds
Started Aug 17 06:12:41 PM PDT 24
Finished Aug 17 06:12:46 PM PDT 24
Peak memory 216040 kb
Host smart-1f870c48-8967-427b-ade5-72ded56a38b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494688230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2494688230
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.659041576
Short name T158
Test name
Test status
Simulation time 1144173794 ps
CPU time 23.73 seconds
Started Aug 17 06:12:41 PM PDT 24
Finished Aug 17 06:13:05 PM PDT 24
Peak memory 215992 kb
Host smart-7e4b6b25-6db9-48af-b806-1de008794b9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659041576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.659041576
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.634714305
Short name T1062
Test name
Test status
Simulation time 644789033 ps
CPU time 3.8 seconds
Started Aug 17 06:12:58 PM PDT 24
Finished Aug 17 06:13:02 PM PDT 24
Peak memory 218728 kb
Host smart-8d497d01-bfe6-4bfa-bfef-3b23f70508ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634714305 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.634714305
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.162519533
Short name T112
Test name
Test status
Simulation time 345869966 ps
CPU time 2.67 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 215916 kb
Host smart-0b485a89-cdbb-40c0-9d21-26e2b1a72891
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162519533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.162519533
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1052801125
Short name T1093
Test name
Test status
Simulation time 23924033 ps
CPU time 0.7 seconds
Started Aug 17 06:12:59 PM PDT 24
Finished Aug 17 06:12:59 PM PDT 24
Peak memory 204372 kb
Host smart-f287c0f9-e642-47b5-ba90-4fa4c5066928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052801125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1052801125
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3705201074
Short name T1095
Test name
Test status
Simulation time 56009903 ps
CPU time 1.68 seconds
Started Aug 17 06:12:52 PM PDT 24
Finished Aug 17 06:12:54 PM PDT 24
Peak memory 215944 kb
Host smart-0d67f3a6-e580-4f2e-83a2-e85352a8a90e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705201074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3705201074
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3363469223
Short name T102
Test name
Test status
Simulation time 284826273 ps
CPU time 2.14 seconds
Started Aug 17 06:12:49 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 216068 kb
Host smart-f6b56cca-18c8-405b-a1bb-e050605c4163
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363469223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3363469223
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3168476379
Short name T160
Test name
Test status
Simulation time 3292124546 ps
CPU time 21.46 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:13:09 PM PDT 24
Peak memory 216016 kb
Host smart-bee2b3e4-b3b2-44b4-b95e-66f86229412e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168476379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3168476379
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3335919393
Short name T1108
Test name
Test status
Simulation time 53987917 ps
CPU time 1.77 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:55 PM PDT 24
Peak memory 216064 kb
Host smart-f2306f33-84d4-419a-8d63-7c0ac8f60e62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335919393 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3335919393
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1774055347
Short name T1115
Test name
Test status
Simulation time 216358270 ps
CPU time 1.29 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 207776 kb
Host smart-53825033-ff9f-4597-8ae7-0b2c9a8179bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774055347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1774055347
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2465521749
Short name T1039
Test name
Test status
Simulation time 15324759 ps
CPU time 0.74 seconds
Started Aug 17 06:12:52 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 204272 kb
Host smart-5cd6b054-0e99-45db-a804-42f56a635484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465521749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2465521749
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2959430607
Short name T1132
Test name
Test status
Simulation time 47752875 ps
CPU time 2.9 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:56 PM PDT 24
Peak memory 215872 kb
Host smart-e86ab35d-866a-4a7d-8351-4fd7d2a0382f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959430607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2959430607
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1818803480
Short name T1084
Test name
Test status
Simulation time 91189638 ps
CPU time 2.29 seconds
Started Aug 17 06:12:52 PM PDT 24
Finished Aug 17 06:12:54 PM PDT 24
Peak memory 216100 kb
Host smart-1daefead-679b-4ee5-8789-a44fde46f651
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818803480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1818803480
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.905560673
Short name T101
Test name
Test status
Simulation time 328915431 ps
CPU time 8.11 seconds
Started Aug 17 06:12:46 PM PDT 24
Finished Aug 17 06:12:54 PM PDT 24
Peak memory 216496 kb
Host smart-389a9c51-10f9-4d0d-9e2b-81042d08b7a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905560673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.905560673
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2076486237
Short name T1087
Test name
Test status
Simulation time 810485266 ps
CPU time 1.67 seconds
Started Aug 17 06:12:41 PM PDT 24
Finished Aug 17 06:12:43 PM PDT 24
Peak memory 216136 kb
Host smart-65c3027f-5e05-4b8d-a832-bf00902b92e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076486237 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2076486237
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1122898683
Short name T1136
Test name
Test status
Simulation time 88479370 ps
CPU time 2.05 seconds
Started Aug 17 06:12:42 PM PDT 24
Finished Aug 17 06:12:44 PM PDT 24
Peak memory 207804 kb
Host smart-e0b5858e-60fb-4008-b277-d54bfcc5d7cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122898683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1122898683
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2726212957
Short name T1028
Test name
Test status
Simulation time 31999963 ps
CPU time 0.76 seconds
Started Aug 17 06:13:08 PM PDT 24
Finished Aug 17 06:13:09 PM PDT 24
Peak memory 204332 kb
Host smart-31895e8f-c610-4a78-a9d5-e85cb495c024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726212957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2726212957
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1102779993
Short name T1086
Test name
Test status
Simulation time 88029656 ps
CPU time 1.82 seconds
Started Aug 17 06:12:42 PM PDT 24
Finished Aug 17 06:12:44 PM PDT 24
Peak memory 215888 kb
Host smart-600e7bd6-10ce-4e33-b4f6-86b71b9889c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102779993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1102779993
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2557798786
Short name T1129
Test name
Test status
Simulation time 137374519 ps
CPU time 3.61 seconds
Started Aug 17 06:12:52 PM PDT 24
Finished Aug 17 06:12:56 PM PDT 24
Peak memory 216104 kb
Host smart-870f9c30-0ace-49bc-a3a8-123897f87e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557798786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2557798786
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3073698368
Short name T1131
Test name
Test status
Simulation time 100565723 ps
CPU time 6.76 seconds
Started Aug 17 06:12:58 PM PDT 24
Finished Aug 17 06:13:04 PM PDT 24
Peak memory 215984 kb
Host smart-056dd9f0-1c4c-44e6-872e-1257010b8a01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073698368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3073698368
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4172754787
Short name T1089
Test name
Test status
Simulation time 215891101 ps
CPU time 4 seconds
Started Aug 17 06:13:03 PM PDT 24
Finished Aug 17 06:13:07 PM PDT 24
Peak memory 218668 kb
Host smart-f7d24119-942c-4e76-83ea-b752cc4d52c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172754787 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4172754787
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.659235641
Short name T118
Test name
Test status
Simulation time 65766978 ps
CPU time 1.93 seconds
Started Aug 17 06:13:01 PM PDT 24
Finished Aug 17 06:13:03 PM PDT 24
Peak memory 207720 kb
Host smart-b0037643-8f45-4c24-a7fb-4af86d9fe0e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659235641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.659235641
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3903321985
Short name T1025
Test name
Test status
Simulation time 15061654 ps
CPU time 0.71 seconds
Started Aug 17 06:13:05 PM PDT 24
Finished Aug 17 06:13:06 PM PDT 24
Peak memory 204660 kb
Host smart-83293b91-e74f-4859-9831-5f4f5da2340a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903321985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3903321985
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2425954297
Short name T1104
Test name
Test status
Simulation time 554700907 ps
CPU time 4.1 seconds
Started Aug 17 06:13:04 PM PDT 24
Finished Aug 17 06:13:08 PM PDT 24
Peak memory 215916 kb
Host smart-81fe60b5-b656-4e52-ae38-029eed718a89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425954297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2425954297
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.979387542
Short name T1141
Test name
Test status
Simulation time 108781638 ps
CPU time 1.96 seconds
Started Aug 17 06:12:58 PM PDT 24
Finished Aug 17 06:13:00 PM PDT 24
Peak memory 216092 kb
Host smart-28550631-f50e-4c71-93ec-7f127e2552b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979387542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.979387542
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2078058083
Short name T99
Test name
Test status
Simulation time 1342500944 ps
CPU time 16.62 seconds
Started Aug 17 06:12:42 PM PDT 24
Finished Aug 17 06:12:59 PM PDT 24
Peak memory 215920 kb
Host smart-0c36564c-5509-4f92-a15e-1cd211bc6d75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078058083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2078058083
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2140124036
Short name T147
Test name
Test status
Simulation time 241058585 ps
CPU time 3 seconds
Started Aug 17 06:13:05 PM PDT 24
Finished Aug 17 06:13:08 PM PDT 24
Peak memory 217524 kb
Host smart-fce573a5-3bf7-4400-a12b-46e91b2d7cdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140124036 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2140124036
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2302837641
Short name T121
Test name
Test status
Simulation time 157244247 ps
CPU time 2.08 seconds
Started Aug 17 06:12:58 PM PDT 24
Finished Aug 17 06:13:00 PM PDT 24
Peak memory 216000 kb
Host smart-3ff3e7b0-26de-44a6-b865-21cf38a7db25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302837641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2302837641
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1918275226
Short name T1037
Test name
Test status
Simulation time 20762633 ps
CPU time 0.76 seconds
Started Aug 17 06:12:52 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 204272 kb
Host smart-822f168e-b577-45d3-9ec9-3b06b9e52e29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918275226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1918275226
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.470162208
Short name T1138
Test name
Test status
Simulation time 174434869 ps
CPU time 2.86 seconds
Started Aug 17 06:12:58 PM PDT 24
Finished Aug 17 06:13:01 PM PDT 24
Peak memory 215904 kb
Host smart-5f8015ea-5464-42bc-94ba-f40f6e50af6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470162208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.470162208
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2412606424
Short name T1102
Test name
Test status
Simulation time 559924541 ps
CPU time 15.83 seconds
Started Aug 17 06:12:41 PM PDT 24
Finished Aug 17 06:12:57 PM PDT 24
Peak memory 216780 kb
Host smart-f99f3dad-c6fe-4f3e-9f55-7f50ebe6f379
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412606424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2412606424
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1710343466
Short name T1140
Test name
Test status
Simulation time 52741096 ps
CPU time 3.57 seconds
Started Aug 17 06:13:05 PM PDT 24
Finished Aug 17 06:13:08 PM PDT 24
Peak memory 218092 kb
Host smart-9ff2033b-dab1-463c-8b97-8aae4d1250a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710343466 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1710343466
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.438600337
Short name T145
Test name
Test status
Simulation time 1078114258 ps
CPU time 2.67 seconds
Started Aug 17 06:13:06 PM PDT 24
Finished Aug 17 06:13:09 PM PDT 24
Peak memory 216000 kb
Host smart-beb84d4a-55f1-4fed-b676-30962b7fedc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438600337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.438600337
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1702363679
Short name T1134
Test name
Test status
Simulation time 132757545 ps
CPU time 0.75 seconds
Started Aug 17 06:13:09 PM PDT 24
Finished Aug 17 06:13:09 PM PDT 24
Peak memory 204328 kb
Host smart-e3903f9f-08bf-4c64-95e5-004d5b514039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702363679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1702363679
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2476171952
Short name T134
Test name
Test status
Simulation time 68264836 ps
CPU time 4.39 seconds
Started Aug 17 06:12:50 PM PDT 24
Finished Aug 17 06:12:55 PM PDT 24
Peak memory 215872 kb
Host smart-e386ab89-acb6-4fcd-a1d2-610702021081
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476171952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2476171952
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3786069673
Short name T1047
Test name
Test status
Simulation time 227233803 ps
CPU time 5.73 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:12:54 PM PDT 24
Peak memory 216088 kb
Host smart-2800f92a-71ec-4b50-b2dc-355ae6c3e98a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786069673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3786069673
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2970003548
Short name T1045
Test name
Test status
Simulation time 88746953 ps
CPU time 2.53 seconds
Started Aug 17 06:12:55 PM PDT 24
Finished Aug 17 06:12:58 PM PDT 24
Peak memory 216980 kb
Host smart-abbec82e-0766-431e-81fc-27ce0db8a47a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970003548 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2970003548
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.729375267
Short name T115
Test name
Test status
Simulation time 47658682 ps
CPU time 1.66 seconds
Started Aug 17 06:12:50 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 207820 kb
Host smart-fc719c9a-2314-45bc-88e3-0cf95b0fa72b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729375267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.729375267
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.8988451
Short name T1075
Test name
Test status
Simulation time 31649612 ps
CPU time 0.69 seconds
Started Aug 17 06:12:57 PM PDT 24
Finished Aug 17 06:12:58 PM PDT 24
Peak memory 204332 kb
Host smart-a0f1604c-3ea0-408a-b53f-ed698bb1b63d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8988451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.8988451
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3816273383
Short name T1033
Test name
Test status
Simulation time 106673629 ps
CPU time 4.15 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:57 PM PDT 24
Peak memory 215884 kb
Host smart-27a5a397-f3ca-4bdd-ac28-601e64808c19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816273383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3816273383
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1134869035
Short name T1076
Test name
Test status
Simulation time 65960245 ps
CPU time 1.92 seconds
Started Aug 17 06:12:58 PM PDT 24
Finished Aug 17 06:13:00 PM PDT 24
Peak memory 216036 kb
Host smart-1f69aaaa-e944-451a-82dd-ef691ea106f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134869035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1134869035
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1012381633
Short name T1142
Test name
Test status
Simulation time 1664574583 ps
CPU time 19.81 seconds
Started Aug 17 06:13:00 PM PDT 24
Finished Aug 17 06:13:20 PM PDT 24
Peak memory 216504 kb
Host smart-e5e4927b-60e3-4835-b216-5e2ab19e6b8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012381633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1012381633
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3517521065
Short name T1072
Test name
Test status
Simulation time 117801157 ps
CPU time 1.8 seconds
Started Aug 17 06:13:11 PM PDT 24
Finished Aug 17 06:13:12 PM PDT 24
Peak memory 216988 kb
Host smart-1a2cd71a-9f1a-4b5f-a402-6cdf09ef82b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517521065 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3517521065
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2370225955
Short name T109
Test name
Test status
Simulation time 43668827 ps
CPU time 1.32 seconds
Started Aug 17 06:12:41 PM PDT 24
Finished Aug 17 06:12:43 PM PDT 24
Peak memory 207788 kb
Host smart-1f749292-832b-4962-bbbd-9899d904ec99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370225955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2370225955
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4254074285
Short name T1043
Test name
Test status
Simulation time 34485053 ps
CPU time 0.74 seconds
Started Aug 17 06:12:50 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 204328 kb
Host smart-ebea3999-e9da-41d2-bb7c-d23ce382dffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254074285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4254074285
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4162915393
Short name T1116
Test name
Test status
Simulation time 109931641 ps
CPU time 2.85 seconds
Started Aug 17 06:13:05 PM PDT 24
Finished Aug 17 06:13:08 PM PDT 24
Peak memory 215912 kb
Host smart-d40676a3-ae5b-42f0-95c3-23dc005baf9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162915393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4162915393
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2564233448
Short name T1147
Test name
Test status
Simulation time 29055164 ps
CPU time 2.02 seconds
Started Aug 17 06:12:55 PM PDT 24
Finished Aug 17 06:12:57 PM PDT 24
Peak memory 216176 kb
Host smart-1ddf7ee7-06eb-4048-ba7b-f528faac5d72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564233448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2564233448
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3997002087
Short name T146
Test name
Test status
Simulation time 299892489 ps
CPU time 7.55 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:12:55 PM PDT 24
Peak memory 216088 kb
Host smart-e600e4c6-6ae2-4f5d-ac31-13ccf233935f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997002087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3997002087
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2896365756
Short name T1114
Test name
Test status
Simulation time 168838621 ps
CPU time 1.74 seconds
Started Aug 17 06:12:56 PM PDT 24
Finished Aug 17 06:13:02 PM PDT 24
Peak memory 216104 kb
Host smart-884d1ef8-2b18-4dfb-b126-a747c41cbdbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896365756 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2896365756
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2286305349
Short name T1113
Test name
Test status
Simulation time 37744244 ps
CPU time 1.29 seconds
Started Aug 17 06:12:57 PM PDT 24
Finished Aug 17 06:12:58 PM PDT 24
Peak memory 207768 kb
Host smart-3c218748-ca40-425a-897f-a2e7641b1284
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286305349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2286305349
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2595188797
Short name T1040
Test name
Test status
Simulation time 12959358 ps
CPU time 0.72 seconds
Started Aug 17 06:12:50 PM PDT 24
Finished Aug 17 06:12:50 PM PDT 24
Peak memory 204340 kb
Host smart-fbae4804-3e15-4c2d-a02f-319f174608b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595188797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2595188797
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2965074003
Short name T143
Test name
Test status
Simulation time 85713547 ps
CPU time 1.78 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:55 PM PDT 24
Peak memory 215936 kb
Host smart-f6eed6fd-5a56-4676-9e58-4b772ac637cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965074003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2965074003
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1458578475
Short name T97
Test name
Test status
Simulation time 89613129 ps
CPU time 2.28 seconds
Started Aug 17 06:13:08 PM PDT 24
Finished Aug 17 06:13:10 PM PDT 24
Peak memory 215976 kb
Host smart-6d5fa70e-cfde-4e93-9576-c735f9787167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458578475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1458578475
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1580230768
Short name T1133
Test name
Test status
Simulation time 4386135206 ps
CPU time 23.63 seconds
Started Aug 17 06:12:55 PM PDT 24
Finished Aug 17 06:13:19 PM PDT 24
Peak memory 215972 kb
Host smart-5788c218-dcb4-4b40-ac36-f3ec3599e7ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580230768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1580230768
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1062423222
Short name T124
Test name
Test status
Simulation time 611188049 ps
CPU time 15.41 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:13:07 PM PDT 24
Peak memory 207656 kb
Host smart-2b0d9bcf-66a4-4bc9-ab50-6174773d4ee0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062423222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1062423222
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1743372377
Short name T1128
Test name
Test status
Simulation time 1409612014 ps
CPU time 24.44 seconds
Started Aug 17 06:12:52 PM PDT 24
Finished Aug 17 06:13:16 PM PDT 24
Peak memory 215868 kb
Host smart-19882d1f-da92-4aff-8492-f2064c211aa5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743372377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1743372377
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2502505489
Short name T1099
Test name
Test status
Simulation time 85037050 ps
CPU time 1.01 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:12:49 PM PDT 24
Peak memory 207460 kb
Host smart-de7b7868-d828-438c-9b1f-9fee44b67b62
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502505489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2502505489
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2854609097
Short name T108
Test name
Test status
Simulation time 1727733067 ps
CPU time 3.46 seconds
Started Aug 17 06:12:35 PM PDT 24
Finished Aug 17 06:12:38 PM PDT 24
Peak memory 218500 kb
Host smart-f49c4c7b-a5af-48e9-8bc3-f0dc15bca480
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854609097 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2854609097
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1624381295
Short name T116
Test name
Test status
Simulation time 31860452 ps
CPU time 1.29 seconds
Started Aug 17 06:12:46 PM PDT 24
Finished Aug 17 06:12:47 PM PDT 24
Peak memory 207884 kb
Host smart-ed5f21f8-0120-48b8-afbc-04a89f93eeb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624381295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
624381295
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2483113044
Short name T1027
Test name
Test status
Simulation time 28575734 ps
CPU time 0.74 seconds
Started Aug 17 06:12:49 PM PDT 24
Finished Aug 17 06:12:50 PM PDT 24
Peak memory 204324 kb
Host smart-9aeda42a-04ff-434e-bbf7-abaec6a4dde5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483113044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
483113044
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.723690059
Short name T117
Test name
Test status
Simulation time 79431128 ps
CPU time 1.9 seconds
Started Aug 17 06:12:49 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 215916 kb
Host smart-a65698b7-343a-4f3a-8104-ddebe0c08043
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723690059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.723690059
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3179207085
Short name T1058
Test name
Test status
Simulation time 12282867 ps
CPU time 0.66 seconds
Started Aug 17 06:12:35 PM PDT 24
Finished Aug 17 06:12:36 PM PDT 24
Peak memory 204292 kb
Host smart-a03c2ae8-7f13-4ce2-83df-8d22103a8e41
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179207085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3179207085
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2284339287
Short name T1051
Test name
Test status
Simulation time 187232131 ps
CPU time 3.04 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:41 PM PDT 24
Peak memory 215924 kb
Host smart-0cf28ae8-6889-43b0-a10c-818c82bc96ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284339287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2284339287
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3626863777
Short name T104
Test name
Test status
Simulation time 103128784 ps
CPU time 3.13 seconds
Started Aug 17 06:12:31 PM PDT 24
Finished Aug 17 06:12:34 PM PDT 24
Peak memory 217092 kb
Host smart-904d1a2c-c229-415f-bfe9-c6d8ca7a4c78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626863777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
626863777
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3645989066
Short name T1117
Test name
Test status
Simulation time 934278486 ps
CPU time 13.56 seconds
Started Aug 17 06:12:35 PM PDT 24
Finished Aug 17 06:12:48 PM PDT 24
Peak memory 215928 kb
Host smart-07e47e8d-7b6a-486f-89df-a4322acb9d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645989066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3645989066
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1330568744
Short name T1031
Test name
Test status
Simulation time 118974078 ps
CPU time 0.73 seconds
Started Aug 17 06:12:54 PM PDT 24
Finished Aug 17 06:13:00 PM PDT 24
Peak memory 204620 kb
Host smart-120fa8a0-674b-4b8f-89bd-4c6439f2d958
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330568744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1330568744
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.952049913
Short name T1054
Test name
Test status
Simulation time 12412846 ps
CPU time 0.73 seconds
Started Aug 17 06:12:55 PM PDT 24
Finished Aug 17 06:12:56 PM PDT 24
Peak memory 204344 kb
Host smart-772c58b7-781b-4329-9746-e019f9281d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952049913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.952049913
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.438958406
Short name T1118
Test name
Test status
Simulation time 71546196 ps
CPU time 0.76 seconds
Started Aug 17 06:12:59 PM PDT 24
Finished Aug 17 06:13:00 PM PDT 24
Peak memory 204260 kb
Host smart-639f8205-5aaa-490e-b5fb-dc7da36a6ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438958406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.438958406
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1851794059
Short name T1081
Test name
Test status
Simulation time 13432228 ps
CPU time 0.7 seconds
Started Aug 17 06:13:09 PM PDT 24
Finished Aug 17 06:13:09 PM PDT 24
Peak memory 204568 kb
Host smart-0c6dc296-e787-4450-8e94-f70364986c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851794059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1851794059
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1693285704
Short name T1057
Test name
Test status
Simulation time 15951719 ps
CPU time 0.76 seconds
Started Aug 17 06:13:16 PM PDT 24
Finished Aug 17 06:13:17 PM PDT 24
Peak memory 204656 kb
Host smart-dcf599e7-3bbf-44a9-890e-cf9624a6d470
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693285704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1693285704
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.965530763
Short name T1107
Test name
Test status
Simulation time 28119327 ps
CPU time 0.81 seconds
Started Aug 17 06:13:13 PM PDT 24
Finished Aug 17 06:13:14 PM PDT 24
Peak memory 204632 kb
Host smart-f0209890-8f8b-4640-819e-eeed434800eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965530763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.965530763
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1428285993
Short name T1149
Test name
Test status
Simulation time 18239597 ps
CPU time 0.84 seconds
Started Aug 17 06:13:07 PM PDT 24
Finished Aug 17 06:13:08 PM PDT 24
Peak memory 204656 kb
Host smart-458d43c3-82b4-4ef3-9622-56d8a6b93f56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428285993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1428285993
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1252941622
Short name T1042
Test name
Test status
Simulation time 12334762 ps
CPU time 0.7 seconds
Started Aug 17 06:12:54 PM PDT 24
Finished Aug 17 06:12:55 PM PDT 24
Peak memory 204176 kb
Host smart-ec2f51cb-31c8-4e25-a259-780f470f55ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252941622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1252941622
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3969449525
Short name T1082
Test name
Test status
Simulation time 12484527 ps
CPU time 0.76 seconds
Started Aug 17 06:13:12 PM PDT 24
Finished Aug 17 06:13:13 PM PDT 24
Peak memory 204324 kb
Host smart-e73f5b2e-613b-4007-849c-4486785d7571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969449525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3969449525
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2883235036
Short name T1105
Test name
Test status
Simulation time 16689118 ps
CPU time 0.69 seconds
Started Aug 17 06:13:12 PM PDT 24
Finished Aug 17 06:13:12 PM PDT 24
Peak memory 204564 kb
Host smart-005611d4-03ef-4497-8f75-53d799673ad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883235036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2883235036
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2537561839
Short name T113
Test name
Test status
Simulation time 308434581 ps
CPU time 21.55 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:13:12 PM PDT 24
Peak memory 207728 kb
Host smart-d3540be7-e56c-4915-bc58-6bf1aeb9388a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537561839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2537561839
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3788687417
Short name T114
Test name
Test status
Simulation time 2734482735 ps
CPU time 40.07 seconds
Started Aug 17 06:12:33 PM PDT 24
Finished Aug 17 06:13:13 PM PDT 24
Peak memory 207848 kb
Host smart-e7fc4877-3cf0-4944-a53f-92fbe1f29cde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788687417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3788687417
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4233490102
Short name T1122
Test name
Test status
Simulation time 22374350 ps
CPU time 1 seconds
Started Aug 17 06:12:38 PM PDT 24
Finished Aug 17 06:12:39 PM PDT 24
Peak memory 207512 kb
Host smart-467cde68-0f85-459f-9646-5f6e3b61a9ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233490102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4233490102
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3244902952
Short name T94
Test name
Test status
Simulation time 44009076 ps
CPU time 2.98 seconds
Started Aug 17 06:12:35 PM PDT 24
Finished Aug 17 06:12:38 PM PDT 24
Peak memory 218512 kb
Host smart-186c340e-863e-41ff-b2df-a385c07746c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244902952 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3244902952
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.821017173
Short name T110
Test name
Test status
Simulation time 40360539 ps
CPU time 1.35 seconds
Started Aug 17 06:12:38 PM PDT 24
Finished Aug 17 06:12:39 PM PDT 24
Peak memory 207728 kb
Host smart-7b85747f-313e-4989-811d-69bfd6d7e3c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821017173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.821017173
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2647681602
Short name T1119
Test name
Test status
Simulation time 17481353 ps
CPU time 0.76 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 204188 kb
Host smart-f441a7f7-4894-46e9-a9d5-44f78cbe59a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647681602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
647681602
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4230851057
Short name T1048
Test name
Test status
Simulation time 32806191 ps
CPU time 1.29 seconds
Started Aug 17 06:12:47 PM PDT 24
Finished Aug 17 06:12:49 PM PDT 24
Peak memory 215912 kb
Host smart-5671f428-5067-4fa7-9d9e-1f10a434314d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230851057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4230851057
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1709566335
Short name T1041
Test name
Test status
Simulation time 16238994 ps
CPU time 0.68 seconds
Started Aug 17 06:12:33 PM PDT 24
Finished Aug 17 06:12:34 PM PDT 24
Peak memory 204608 kb
Host smart-b7ad39ef-88d4-4493-94d5-794d4b888941
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709566335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1709566335
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3805076418
Short name T1145
Test name
Test status
Simulation time 84985788 ps
CPU time 2.73 seconds
Started Aug 17 06:12:33 PM PDT 24
Finished Aug 17 06:12:36 PM PDT 24
Peak memory 215968 kb
Host smart-039b1efc-5dc4-47e4-92ab-59bbaaf55bd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805076418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3805076418
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2948976596
Short name T107
Test name
Test status
Simulation time 81660290 ps
CPU time 1.55 seconds
Started Aug 17 06:12:35 PM PDT 24
Finished Aug 17 06:12:37 PM PDT 24
Peak memory 218212 kb
Host smart-4049b1e1-0b1f-4843-951f-1455c4e4b6ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948976596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
948976596
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1313688047
Short name T1059
Test name
Test status
Simulation time 265088560 ps
CPU time 7.5 seconds
Started Aug 17 06:12:50 PM PDT 24
Finished Aug 17 06:12:58 PM PDT 24
Peak memory 216660 kb
Host smart-522a558e-a3aa-4066-82cd-068b6e528a3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313688047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1313688047
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2461993413
Short name T1083
Test name
Test status
Simulation time 16317412 ps
CPU time 0.75 seconds
Started Aug 17 06:12:56 PM PDT 24
Finished Aug 17 06:12:57 PM PDT 24
Peak memory 204328 kb
Host smart-9b373a35-477a-47b4-ba4a-69b8f2c5a0fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461993413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2461993413
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3534697714
Short name T1127
Test name
Test status
Simulation time 20760578 ps
CPU time 0.77 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 204572 kb
Host smart-91a39e35-8896-4f5e-91b6-ef15372522ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534697714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3534697714
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2192130355
Short name T1143
Test name
Test status
Simulation time 29991764 ps
CPU time 0.72 seconds
Started Aug 17 06:13:10 PM PDT 24
Finished Aug 17 06:13:11 PM PDT 24
Peak memory 204272 kb
Host smart-a9705258-1480-4479-9f5f-2c0bee580d4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192130355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2192130355
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3047663222
Short name T1038
Test name
Test status
Simulation time 67396555 ps
CPU time 0.74 seconds
Started Aug 17 06:12:57 PM PDT 24
Finished Aug 17 06:12:57 PM PDT 24
Peak memory 204600 kb
Host smart-a607bd23-158f-4aef-8ad9-77c1921c1f97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047663222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3047663222
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1971471608
Short name T1036
Test name
Test status
Simulation time 12646789 ps
CPU time 0.74 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:12:52 PM PDT 24
Peak memory 204648 kb
Host smart-bd55ce25-48d6-41c6-b4bd-e575cbefaa98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971471608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1971471608
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2589498820
Short name T1050
Test name
Test status
Simulation time 13183698 ps
CPU time 0.78 seconds
Started Aug 17 06:13:04 PM PDT 24
Finished Aug 17 06:13:05 PM PDT 24
Peak memory 204416 kb
Host smart-c0d0ed1b-46e3-4ed6-af7c-b3095cbd2620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589498820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2589498820
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2861835679
Short name T1098
Test name
Test status
Simulation time 37592112 ps
CPU time 0.74 seconds
Started Aug 17 06:13:09 PM PDT 24
Finished Aug 17 06:13:10 PM PDT 24
Peak memory 204328 kb
Host smart-609d4c25-4eaa-41f1-89e9-39269d72c613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861835679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2861835679
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.764632301
Short name T1146
Test name
Test status
Simulation time 46705071 ps
CPU time 0.87 seconds
Started Aug 17 06:13:10 PM PDT 24
Finished Aug 17 06:13:11 PM PDT 24
Peak memory 204360 kb
Host smart-be400ec0-c467-4811-9b46-be6aff082adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764632301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.764632301
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2080171591
Short name T1101
Test name
Test status
Simulation time 13508853 ps
CPU time 0.7 seconds
Started Aug 17 06:12:57 PM PDT 24
Finished Aug 17 06:12:58 PM PDT 24
Peak memory 204608 kb
Host smart-e7edd7e4-faec-4c9c-9172-87d8eebb00b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080171591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2080171591
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3159877793
Short name T1100
Test name
Test status
Simulation time 20448277 ps
CPU time 0.7 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:54 PM PDT 24
Peak memory 204628 kb
Host smart-1a829e47-85b5-48c8-98a8-488382d855b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159877793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3159877793
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1721451739
Short name T1064
Test name
Test status
Simulation time 715886444 ps
CPU time 7.9 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:50 PM PDT 24
Peak memory 215912 kb
Host smart-e1c234eb-6a4e-49ba-be6e-17166bbb0235
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721451739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1721451739
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1904918609
Short name T1120
Test name
Test status
Simulation time 368199783 ps
CPU time 24.17 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:13:17 PM PDT 24
Peak memory 215792 kb
Host smart-4fa97e0c-513a-41f1-8581-df49047b766e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904918609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1904918609
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.751130722
Short name T1088
Test name
Test status
Simulation time 535913874 ps
CPU time 3.59 seconds
Started Aug 17 06:12:36 PM PDT 24
Finished Aug 17 06:12:40 PM PDT 24
Peak memory 217092 kb
Host smart-a760b599-26a8-4690-95f1-f86ace8f6a18
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751130722 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.751130722
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3653880391
Short name T1137
Test name
Test status
Simulation time 55922623 ps
CPU time 1.38 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:39 PM PDT 24
Peak memory 207776 kb
Host smart-771d98d9-9db9-4951-aadb-d7d152d01571
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653880391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
653880391
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1492148017
Short name T1061
Test name
Test status
Simulation time 14244657 ps
CPU time 0.73 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 204312 kb
Host smart-c4ba6f09-59a8-4667-ad05-e320f5693dc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492148017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
492148017
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.458289884
Short name T123
Test name
Test status
Simulation time 207611643 ps
CPU time 1.91 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:39 PM PDT 24
Peak memory 215972 kb
Host smart-c2387057-61da-42a9-a5d3-c601ca9f5777
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458289884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.458289884
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1739576159
Short name T1035
Test name
Test status
Simulation time 12201736 ps
CPU time 0.74 seconds
Started Aug 17 06:12:34 PM PDT 24
Finished Aug 17 06:12:35 PM PDT 24
Peak memory 204212 kb
Host smart-245dd7ee-3760-4544-8380-a05bd367a129
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739576159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1739576159
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3907304012
Short name T1065
Test name
Test status
Simulation time 290441163 ps
CPU time 3.86 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:41 PM PDT 24
Peak memory 215988 kb
Host smart-fe59a313-4cfd-4447-8831-f5b0127562f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907304012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3907304012
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2432384970
Short name T156
Test name
Test status
Simulation time 228227249 ps
CPU time 4.72 seconds
Started Aug 17 06:12:40 PM PDT 24
Finished Aug 17 06:12:45 PM PDT 24
Peak memory 216012 kb
Host smart-86840e6f-29fe-4447-ae45-0767a2488985
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432384970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
432384970
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1486262982
Short name T1103
Test name
Test status
Simulation time 105104315 ps
CPU time 6.26 seconds
Started Aug 17 06:12:35 PM PDT 24
Finished Aug 17 06:12:42 PM PDT 24
Peak memory 216016 kb
Host smart-d1a4790c-e933-490f-bdac-03dcf8633294
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486262982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1486262982
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.387658538
Short name T1068
Test name
Test status
Simulation time 14573875 ps
CPU time 0.73 seconds
Started Aug 17 06:12:59 PM PDT 24
Finished Aug 17 06:12:59 PM PDT 24
Peak memory 204304 kb
Host smart-b7aa0c0f-1d2c-48ba-9f5f-b95fbd98b902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387658538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.387658538
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2901957254
Short name T1046
Test name
Test status
Simulation time 11484441 ps
CPU time 0.69 seconds
Started Aug 17 06:12:50 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 204368 kb
Host smart-6fc0f9ef-b58f-4ecb-be44-687c3ef8bffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901957254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2901957254
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2028600947
Short name T1090
Test name
Test status
Simulation time 62527966 ps
CPU time 0.75 seconds
Started Aug 17 06:13:00 PM PDT 24
Finished Aug 17 06:13:01 PM PDT 24
Peak memory 204588 kb
Host smart-a74bb353-0de5-4f4d-b4e4-7493900cf6fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028600947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2028600947
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2040546392
Short name T1097
Test name
Test status
Simulation time 135876016 ps
CPU time 0.76 seconds
Started Aug 17 06:13:05 PM PDT 24
Finished Aug 17 06:13:06 PM PDT 24
Peak memory 204272 kb
Host smart-1e87225b-0ec8-40e2-8be4-6084db6f7035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040546392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2040546392
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1783442472
Short name T1125
Test name
Test status
Simulation time 18602236 ps
CPU time 0.79 seconds
Started Aug 17 06:12:54 PM PDT 24
Finished Aug 17 06:12:55 PM PDT 24
Peak memory 204332 kb
Host smart-adafd986-0752-4ab8-afc7-7bf35120f241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783442472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1783442472
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.921366988
Short name T1096
Test name
Test status
Simulation time 65188844 ps
CPU time 0.68 seconds
Started Aug 17 06:13:03 PM PDT 24
Finished Aug 17 06:13:03 PM PDT 24
Peak memory 204644 kb
Host smart-8a0bbe81-f758-4d1f-b226-a9c227aa22a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921366988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.921366988
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1610851094
Short name T1056
Test name
Test status
Simulation time 35971653 ps
CPU time 0.71 seconds
Started Aug 17 06:13:10 PM PDT 24
Finished Aug 17 06:13:11 PM PDT 24
Peak memory 204336 kb
Host smart-541941e1-fac5-4f43-b995-9d88fd538c49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610851094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1610851094
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.747750200
Short name T1092
Test name
Test status
Simulation time 42243897 ps
CPU time 0.75 seconds
Started Aug 17 06:12:58 PM PDT 24
Finished Aug 17 06:12:59 PM PDT 24
Peak memory 204376 kb
Host smart-1a420690-5a62-4333-a4d0-ecf80470fa9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747750200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.747750200
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2661034418
Short name T1111
Test name
Test status
Simulation time 44790113 ps
CPU time 0.73 seconds
Started Aug 17 06:13:02 PM PDT 24
Finished Aug 17 06:13:02 PM PDT 24
Peak memory 204260 kb
Host smart-c34aee38-bb70-490b-9a14-563f14630add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661034418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2661034418
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3575047091
Short name T1073
Test name
Test status
Simulation time 18159614 ps
CPU time 0.8 seconds
Started Aug 17 06:13:08 PM PDT 24
Finished Aug 17 06:13:09 PM PDT 24
Peak memory 204360 kb
Host smart-2f0d5f28-4a08-48b5-a0bc-07d078bbef34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575047091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3575047091
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.572082801
Short name T95
Test name
Test status
Simulation time 124830392 ps
CPU time 3.46 seconds
Started Aug 17 06:12:41 PM PDT 24
Finished Aug 17 06:12:45 PM PDT 24
Peak memory 218144 kb
Host smart-f5cc553e-e01d-41f5-b6a3-5ba324bf317e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572082801 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.572082801
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3474492015
Short name T119
Test name
Test status
Simulation time 125176212 ps
CPU time 2.33 seconds
Started Aug 17 06:12:33 PM PDT 24
Finished Aug 17 06:12:35 PM PDT 24
Peak memory 215892 kb
Host smart-50beb259-c041-473a-bfd1-a7ffc3b9fa73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474492015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
474492015
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4067004447
Short name T1144
Test name
Test status
Simulation time 14343107 ps
CPU time 0.7 seconds
Started Aug 17 06:12:37 PM PDT 24
Finished Aug 17 06:12:38 PM PDT 24
Peak memory 204312 kb
Host smart-b348714a-3b7c-49f7-ac58-4a6358c0fd8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067004447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.4
067004447
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1724872544
Short name T1109
Test name
Test status
Simulation time 327332000 ps
CPU time 2.79 seconds
Started Aug 17 06:12:54 PM PDT 24
Finished Aug 17 06:12:57 PM PDT 24
Peak memory 215972 kb
Host smart-fae4af5e-70b6-4ea7-977c-8b63eae059bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724872544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1724872544
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3450238162
Short name T103
Test name
Test status
Simulation time 368430030 ps
CPU time 5.52 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:12:58 PM PDT 24
Peak memory 216144 kb
Host smart-20cd5c5a-4d63-42fa-b261-90ac24159f76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450238162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
450238162
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2251830699
Short name T1074
Test name
Test status
Simulation time 1632434727 ps
CPU time 21.88 seconds
Started Aug 17 06:12:34 PM PDT 24
Finished Aug 17 06:12:56 PM PDT 24
Peak memory 215844 kb
Host smart-b6c93b00-0856-47a5-9e9c-5b5f0bf5904e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251830699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2251830699
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3087181893
Short name T1044
Test name
Test status
Simulation time 459658758 ps
CPU time 3.55 seconds
Started Aug 17 06:13:11 PM PDT 24
Finished Aug 17 06:13:14 PM PDT 24
Peak memory 218036 kb
Host smart-ee055004-0490-4d68-aea1-65c1755cbdbc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087181893 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3087181893
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2258052327
Short name T120
Test name
Test status
Simulation time 383935420 ps
CPU time 2.65 seconds
Started Aug 17 06:13:03 PM PDT 24
Finished Aug 17 06:13:06 PM PDT 24
Peak memory 215912 kb
Host smart-fa7a3db7-5ccc-4022-8f38-773f3a47a6b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258052327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
258052327
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3513505813
Short name T1032
Test name
Test status
Simulation time 12155457 ps
CPU time 0.7 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:12:52 PM PDT 24
Peak memory 204344 kb
Host smart-2fe489ae-4c98-4aed-bfcc-7113935eb796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513505813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
513505813
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2805269537
Short name T1130
Test name
Test status
Simulation time 61100284 ps
CPU time 1.85 seconds
Started Aug 17 06:13:09 PM PDT 24
Finished Aug 17 06:13:11 PM PDT 24
Peak memory 215908 kb
Host smart-bc6ebf42-a045-4d57-ba43-18849b179dd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805269537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2805269537
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2128949789
Short name T1070
Test name
Test status
Simulation time 85608888 ps
CPU time 1.64 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:12:53 PM PDT 24
Peak memory 216064 kb
Host smart-73288686-fea8-4548-a1ff-d68165d899ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128949789 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2128949789
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.371220639
Short name T111
Test name
Test status
Simulation time 101553564 ps
CPU time 2.96 seconds
Started Aug 17 06:12:47 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 216000 kb
Host smart-0dc0a854-6bed-434d-b1a2-c89886aac209
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371220639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.371220639
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2497232355
Short name T1135
Test name
Test status
Simulation time 49589887 ps
CPU time 0.7 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:12:49 PM PDT 24
Peak memory 204624 kb
Host smart-e8be4632-fa56-4545-8917-0f7d61237f83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497232355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
497232355
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.909227308
Short name T1106
Test name
Test status
Simulation time 325191152 ps
CPU time 4.34 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:12:52 PM PDT 24
Peak memory 215892 kb
Host smart-8afe0e56-bd56-4c0a-be9a-002e647f8a97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909227308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.909227308
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1833016601
Short name T96
Test name
Test status
Simulation time 191908858 ps
CPU time 5.61 seconds
Started Aug 17 06:12:40 PM PDT 24
Finished Aug 17 06:12:46 PM PDT 24
Peak memory 216020 kb
Host smart-81eef6fa-c208-4cd4-8d69-bd7499fa88c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833016601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
833016601
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1636118791
Short name T159
Test name
Test status
Simulation time 298429439 ps
CPU time 17.32 seconds
Started Aug 17 06:12:42 PM PDT 24
Finished Aug 17 06:13:00 PM PDT 24
Peak memory 215924 kb
Host smart-0225fe1b-b9db-4024-8f94-5460921e232d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636118791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1636118791
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3473128026
Short name T1139
Test name
Test status
Simulation time 1425819044 ps
CPU time 3.63 seconds
Started Aug 17 06:12:54 PM PDT 24
Finished Aug 17 06:12:58 PM PDT 24
Peak memory 218780 kb
Host smart-fd7c5c31-dc6b-4c0c-a645-efbc78b31d8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473128026 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3473128026
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.714041709
Short name T1080
Test name
Test status
Simulation time 37120018 ps
CPU time 1.53 seconds
Started Aug 17 06:12:50 PM PDT 24
Finished Aug 17 06:12:52 PM PDT 24
Peak memory 215824 kb
Host smart-d64e4ba6-a2f0-41d5-be3d-3175792e3212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714041709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.714041709
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.877827960
Short name T1034
Test name
Test status
Simulation time 17900186 ps
CPU time 0.76 seconds
Started Aug 17 06:12:47 PM PDT 24
Finished Aug 17 06:12:48 PM PDT 24
Peak memory 204296 kb
Host smart-0f25cbd7-38e8-42bf-b727-83f001e29f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877827960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.877827960
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2074268410
Short name T1066
Test name
Test status
Simulation time 324803312 ps
CPU time 4.08 seconds
Started Aug 17 06:12:46 PM PDT 24
Finished Aug 17 06:12:50 PM PDT 24
Peak memory 216472 kb
Host smart-dddb4c0a-fd42-473a-96fc-9c8aa80c0836
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074268410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2074268410
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2254318214
Short name T105
Test name
Test status
Simulation time 555522768 ps
CPU time 5.82 seconds
Started Aug 17 06:12:40 PM PDT 24
Finished Aug 17 06:12:45 PM PDT 24
Peak memory 216204 kb
Host smart-5db23823-422a-40b2-ba38-5c0c2924da28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254318214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
254318214
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3619555387
Short name T161
Test name
Test status
Simulation time 778039959 ps
CPU time 21.33 seconds
Started Aug 17 06:12:53 PM PDT 24
Finished Aug 17 06:13:14 PM PDT 24
Peak memory 217620 kb
Host smart-e7990ad7-abe3-44fd-bd0b-9ea075c60079
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619555387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3619555387
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2554493705
Short name T1148
Test name
Test status
Simulation time 321573094 ps
CPU time 2.68 seconds
Started Aug 17 06:12:48 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 218072 kb
Host smart-bd787463-8afc-4e83-a81d-2e7f9c6b7bb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554493705 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2554493705
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2950892194
Short name T1053
Test name
Test status
Simulation time 27538821 ps
CPU time 1.77 seconds
Started Aug 17 06:12:59 PM PDT 24
Finished Aug 17 06:13:01 PM PDT 24
Peak memory 207668 kb
Host smart-36c55aa9-f246-41da-b221-be755e510d5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950892194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
950892194
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1783975038
Short name T1030
Test name
Test status
Simulation time 24105648 ps
CPU time 0.69 seconds
Started Aug 17 06:12:50 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 204308 kb
Host smart-7f019447-3724-463d-bbcf-1d705f3ace2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783975038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
783975038
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3407456114
Short name T1069
Test name
Test status
Simulation time 61918303 ps
CPU time 1.79 seconds
Started Aug 17 06:12:49 PM PDT 24
Finished Aug 17 06:12:51 PM PDT 24
Peak memory 215964 kb
Host smart-e02453b6-1dcc-400a-867c-184702e82e1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407456114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3407456114
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.192601882
Short name T1049
Test name
Test status
Simulation time 33170432 ps
CPU time 2.15 seconds
Started Aug 17 06:12:58 PM PDT 24
Finished Aug 17 06:13:00 PM PDT 24
Peak memory 216072 kb
Host smart-b0d3a566-e4cd-43b3-8d93-b62757b4fbfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192601882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.192601882
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2938062445
Short name T1126
Test name
Test status
Simulation time 342631369 ps
CPU time 8.11 seconds
Started Aug 17 06:12:51 PM PDT 24
Finished Aug 17 06:13:00 PM PDT 24
Peak memory 215932 kb
Host smart-37f622a8-8212-45ae-b110-426cb9b6accd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938062445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2938062445
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1309415038
Short name T541
Test name
Test status
Simulation time 786935877 ps
CPU time 6.39 seconds
Started Aug 17 06:16:53 PM PDT 24
Finished Aug 17 06:16:59 PM PDT 24
Peak memory 224660 kb
Host smart-4802f4d7-8664-47e8-9437-caceac42d1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309415038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1309415038
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1463715949
Short name T832
Test name
Test status
Simulation time 16636021 ps
CPU time 0.81 seconds
Started Aug 17 06:16:58 PM PDT 24
Finished Aug 17 06:16:59 PM PDT 24
Peak memory 206616 kb
Host smart-cef6933c-b41b-4190-922c-9a815d025aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463715949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1463715949
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3787182147
Short name T738
Test name
Test status
Simulation time 6689925011 ps
CPU time 46.42 seconds
Started Aug 17 06:16:52 PM PDT 24
Finished Aug 17 06:17:38 PM PDT 24
Peak memory 249332 kb
Host smart-72c0c303-8cf7-47b8-bec2-61a3fd5a5c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787182147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3787182147
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.4138818197
Short name T1006
Test name
Test status
Simulation time 4569833470 ps
CPU time 128.16 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:19:04 PM PDT 24
Peak memory 270636 kb
Host smart-64b05f47-3bd8-49a7-9691-ae714bf08376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138818197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.4138818197
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1608464645
Short name T125
Test name
Test status
Simulation time 115590232 ps
CPU time 5.19 seconds
Started Aug 17 06:16:54 PM PDT 24
Finished Aug 17 06:16:59 PM PDT 24
Peak memory 232908 kb
Host smart-7168920c-43c6-4950-9696-cecf5b5083e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608464645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1608464645
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3306828886
Short name T870
Test name
Test status
Simulation time 4166249492 ps
CPU time 10.58 seconds
Started Aug 17 06:17:01 PM PDT 24
Finished Aug 17 06:17:11 PM PDT 24
Peak memory 224700 kb
Host smart-7c4631bf-79c5-48e4-a06b-99ddc1678806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306828886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3306828886
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2330717508
Short name T129
Test name
Test status
Simulation time 58055418 ps
CPU time 2.46 seconds
Started Aug 17 06:16:52 PM PDT 24
Finished Aug 17 06:16:54 PM PDT 24
Peak memory 232416 kb
Host smart-3f8f72e7-a47a-409d-ba83-455719170426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330717508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2330717508
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1570541752
Short name T1003
Test name
Test status
Simulation time 14295163 ps
CPU time 1.04 seconds
Started Aug 17 06:17:09 PM PDT 24
Finished Aug 17 06:17:10 PM PDT 24
Peak memory 216712 kb
Host smart-c2957cbd-421e-4020-a062-6af26feb2583
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570541752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1570541752
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3138791372
Short name T394
Test name
Test status
Simulation time 21296776106 ps
CPU time 9.62 seconds
Started Aug 17 06:16:52 PM PDT 24
Finished Aug 17 06:17:02 PM PDT 24
Peak memory 232944 kb
Host smart-eea8647e-9738-4a4f-922b-772be4044cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138791372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3138791372
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4098091315
Short name T420
Test name
Test status
Simulation time 12696676112 ps
CPU time 37.15 seconds
Started Aug 17 06:16:50 PM PDT 24
Finished Aug 17 06:17:27 PM PDT 24
Peak memory 232852 kb
Host smart-e8b645fe-16ab-4f59-822d-cc9495d8d4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098091315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4098091315
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.753874960
Short name T460
Test name
Test status
Simulation time 522855411 ps
CPU time 4.84 seconds
Started Aug 17 06:16:53 PM PDT 24
Finished Aug 17 06:16:58 PM PDT 24
Peak memory 222660 kb
Host smart-d803f55d-f1dd-4380-a9f1-9c8858702a33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=753874960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.753874960
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2741395736
Short name T274
Test name
Test status
Simulation time 27554992104 ps
CPU time 246.04 seconds
Started Aug 17 06:17:01 PM PDT 24
Finished Aug 17 06:21:07 PM PDT 24
Peak memory 251260 kb
Host smart-a14307a0-9621-4ded-a09a-4ab4c88866e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741395736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2741395736
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3536346984
Short name T821
Test name
Test status
Simulation time 11968960623 ps
CPU time 23.16 seconds
Started Aug 17 06:17:04 PM PDT 24
Finished Aug 17 06:17:27 PM PDT 24
Peak memory 220032 kb
Host smart-383d8273-b0a0-4716-9718-9314042b22fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536346984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3536346984
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.160241419
Short name T656
Test name
Test status
Simulation time 2373362770 ps
CPU time 4.45 seconds
Started Aug 17 06:16:54 PM PDT 24
Finished Aug 17 06:17:04 PM PDT 24
Peak memory 216504 kb
Host smart-6f354379-8402-4707-9717-84e6bedf441b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160241419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.160241419
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3232183489
Short name T826
Test name
Test status
Simulation time 502494463 ps
CPU time 1.22 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:16:58 PM PDT 24
Peak memory 216468 kb
Host smart-1a8becc4-32ca-43c9-b65d-a1d66b62a745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232183489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3232183489
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2230440494
Short name T853
Test name
Test status
Simulation time 114747799 ps
CPU time 0.95 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:16:58 PM PDT 24
Peak memory 206084 kb
Host smart-ae1b78ff-7f79-4402-81da-1a4cb950cec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230440494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2230440494
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3323921327
Short name T248
Test name
Test status
Simulation time 2111777394 ps
CPU time 9.31 seconds
Started Aug 17 06:16:58 PM PDT 24
Finished Aug 17 06:17:08 PM PDT 24
Peak memory 232900 kb
Host smart-7d092b8d-b87f-4e8d-af3e-b35bbec50353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323921327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3323921327
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2550607680
Short name T315
Test name
Test status
Simulation time 15410789 ps
CPU time 0.75 seconds
Started Aug 17 06:16:52 PM PDT 24
Finished Aug 17 06:16:53 PM PDT 24
Peak memory 205436 kb
Host smart-fa84876e-c362-445a-9d04-c582f0fb24b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550607680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
550607680
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2985559629
Short name T16
Test name
Test status
Simulation time 764843924 ps
CPU time 3.94 seconds
Started Aug 17 06:16:55 PM PDT 24
Finished Aug 17 06:16:59 PM PDT 24
Peak memory 224628 kb
Host smart-da21d05e-aa9d-4dbb-ad53-be8182f909d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985559629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2985559629
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.538630573
Short name T843
Test name
Test status
Simulation time 122830588 ps
CPU time 0.78 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:16:57 PM PDT 24
Peak memory 206600 kb
Host smart-66eaa74d-ed55-4140-8947-146f03386b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538630573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.538630573
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.398402766
Short name T745
Test name
Test status
Simulation time 25311393585 ps
CPU time 50.2 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:17:47 PM PDT 24
Peak memory 249360 kb
Host smart-7c1a7aa9-87aa-480a-8e8d-45a16d7e928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398402766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.398402766
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.654199062
Short name T924
Test name
Test status
Simulation time 7225877321 ps
CPU time 49.18 seconds
Started Aug 17 06:16:58 PM PDT 24
Finished Aug 17 06:17:47 PM PDT 24
Peak memory 254680 kb
Host smart-7f0f00e2-a478-4165-ae0c-7fe1f815edda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654199062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.654199062
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3179264030
Short name T63
Test name
Test status
Simulation time 10603347900 ps
CPU time 18.08 seconds
Started Aug 17 06:16:52 PM PDT 24
Finished Aug 17 06:17:10 PM PDT 24
Peak memory 217688 kb
Host smart-5936790f-97c1-45d2-a828-46954e973274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179264030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3179264030
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1086304547
Short name T675
Test name
Test status
Simulation time 6710613060 ps
CPU time 23.18 seconds
Started Aug 17 06:16:53 PM PDT 24
Finished Aug 17 06:17:16 PM PDT 24
Peak memory 249976 kb
Host smart-216a0535-5e2f-4d89-a227-fdee0f1215d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086304547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1086304547
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3748706382
Short name T272
Test name
Test status
Simulation time 24783349652 ps
CPU time 108.64 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:19:05 PM PDT 24
Peak memory 264448 kb
Host smart-26926013-0658-477d-bec0-2c94560f5cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748706382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3748706382
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4257498179
Short name T787
Test name
Test status
Simulation time 4533022182 ps
CPU time 9.88 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:17:06 PM PDT 24
Peak memory 224720 kb
Host smart-beaa1001-e015-485a-b1b9-c89255cdf5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257498179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4257498179
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1037109814
Short name T651
Test name
Test status
Simulation time 105342714 ps
CPU time 2.29 seconds
Started Aug 17 06:16:54 PM PDT 24
Finished Aug 17 06:16:56 PM PDT 24
Peak memory 224300 kb
Host smart-7fd27408-8039-475b-952a-6c7610e132c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037109814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1037109814
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.166649942
Short name T690
Test name
Test status
Simulation time 30095171 ps
CPU time 1.04 seconds
Started Aug 17 06:16:46 PM PDT 24
Finished Aug 17 06:16:47 PM PDT 24
Peak memory 216728 kb
Host smart-93044ac9-93ff-443f-a1a7-d3a22bd0211e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166649942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.166649942
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4190786386
Short name T244
Test name
Test status
Simulation time 861077094 ps
CPU time 4.34 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:17:01 PM PDT 24
Peak memory 224596 kb
Host smart-c71d88a1-8026-45a3-a6af-edbfe497945b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190786386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4190786386
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2741965051
Short name T410
Test name
Test status
Simulation time 826886058 ps
CPU time 5.48 seconds
Started Aug 17 06:17:06 PM PDT 24
Finished Aug 17 06:17:12 PM PDT 24
Peak memory 221600 kb
Host smart-b4dbdf29-dbb8-4500-8f76-39ae51f8b986
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2741965051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2741965051
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.154645870
Short name T73
Test name
Test status
Simulation time 290136726 ps
CPU time 1.13 seconds
Started Aug 17 06:16:52 PM PDT 24
Finished Aug 17 06:16:53 PM PDT 24
Peak memory 235564 kb
Host smart-7af60e83-93b0-4b01-acff-a233f791546b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154645870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.154645870
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1107219838
Short name T458
Test name
Test status
Simulation time 2277867521 ps
CPU time 41.87 seconds
Started Aug 17 06:16:53 PM PDT 24
Finished Aug 17 06:17:36 PM PDT 24
Peak memory 249796 kb
Host smart-4885d602-305a-445f-a1e9-9203732a2550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107219838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1107219838
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3659215534
Short name T916
Test name
Test status
Simulation time 2107951698 ps
CPU time 12.62 seconds
Started Aug 17 06:16:49 PM PDT 24
Finished Aug 17 06:17:02 PM PDT 24
Peak memory 219028 kb
Host smart-350c3cb2-e6fa-4311-9ce1-210bc3cc2602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659215534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3659215534
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.385921833
Short name T480
Test name
Test status
Simulation time 6284685275 ps
CPU time 10.89 seconds
Started Aug 17 06:16:58 PM PDT 24
Finished Aug 17 06:17:09 PM PDT 24
Peak memory 216540 kb
Host smart-fe238380-b886-4c89-bb32-add71248ec89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385921833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.385921833
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.910987893
Short name T365
Test name
Test status
Simulation time 27433161 ps
CPU time 0.72 seconds
Started Aug 17 06:17:09 PM PDT 24
Finished Aug 17 06:17:10 PM PDT 24
Peak memory 205608 kb
Host smart-74d9931d-c420-42c4-9a45-7f1382f3c96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910987893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.910987893
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3427423119
Short name T27
Test name
Test status
Simulation time 109962638 ps
CPU time 0.87 seconds
Started Aug 17 06:16:53 PM PDT 24
Finished Aug 17 06:16:55 PM PDT 24
Peak memory 206056 kb
Host smart-6cc7025a-cbc8-4f77-977c-abe9706c2997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427423119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3427423119
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3884881906
Short name T764
Test name
Test status
Simulation time 930364593 ps
CPU time 2.27 seconds
Started Aug 17 06:17:02 PM PDT 24
Finished Aug 17 06:17:05 PM PDT 24
Peak memory 224632 kb
Host smart-e80a6934-04b2-4a29-9592-02439526cb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884881906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3884881906
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2718890783
Short name T383
Test name
Test status
Simulation time 13120864 ps
CPU time 0.72 seconds
Started Aug 17 06:17:34 PM PDT 24
Finished Aug 17 06:17:35 PM PDT 24
Peak memory 205880 kb
Host smart-77517e19-b274-4e36-a0c0-9fab431a92f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718890783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2718890783
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.373665723
Short name T525
Test name
Test status
Simulation time 45844020 ps
CPU time 2.49 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:24 PM PDT 24
Peak memory 232900 kb
Host smart-69ad0728-1fc7-4dba-b2af-0182b313f441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373665723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.373665723
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2087844185
Short name T432
Test name
Test status
Simulation time 74952252 ps
CPU time 0.76 seconds
Started Aug 17 06:17:15 PM PDT 24
Finished Aug 17 06:17:16 PM PDT 24
Peak memory 205568 kb
Host smart-29898c83-7ef6-4d1f-aea0-9ba6e9d65f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087844185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2087844185
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2196980106
Short name T550
Test name
Test status
Simulation time 27817206177 ps
CPU time 38.42 seconds
Started Aug 17 06:17:39 PM PDT 24
Finished Aug 17 06:18:18 PM PDT 24
Peak memory 224760 kb
Host smart-beb9f95e-1022-417d-b209-5e79e180d896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196980106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2196980106
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1560050337
Short name T831
Test name
Test status
Simulation time 869290300 ps
CPU time 5.09 seconds
Started Aug 17 06:17:15 PM PDT 24
Finished Aug 17 06:17:21 PM PDT 24
Peak memory 217648 kb
Host smart-b9a9c640-6998-4be5-9c90-4f3381c35b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560050337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1560050337
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3504251646
Short name T886
Test name
Test status
Simulation time 119901402 ps
CPU time 3.66 seconds
Started Aug 17 06:17:28 PM PDT 24
Finished Aug 17 06:17:32 PM PDT 24
Peak memory 232744 kb
Host smart-8e58aac5-d9ee-40bb-a84a-e6d95a595b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504251646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3504251646
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1214342967
Short name T710
Test name
Test status
Simulation time 8874893416 ps
CPU time 41.18 seconds
Started Aug 17 06:17:19 PM PDT 24
Finished Aug 17 06:18:01 PM PDT 24
Peak memory 232932 kb
Host smart-2fe4749b-37b3-405c-a260-28382be0c8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214342967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1214342967
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2594766735
Short name T724
Test name
Test status
Simulation time 50567229 ps
CPU time 1.1 seconds
Started Aug 17 06:17:20 PM PDT 24
Finished Aug 17 06:17:22 PM PDT 24
Peak memory 216712 kb
Host smart-54f6e804-0c23-4300-8bb5-b7b60bb9a806
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594766735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2594766735
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3877202659
Short name T711
Test name
Test status
Simulation time 10029821854 ps
CPU time 10.83 seconds
Started Aug 17 06:17:31 PM PDT 24
Finished Aug 17 06:17:42 PM PDT 24
Peak memory 224640 kb
Host smart-459522e8-bed4-4c01-ba4c-bd1f919b8587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877202659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3877202659
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3266000961
Short name T249
Test name
Test status
Simulation time 83014922 ps
CPU time 2.39 seconds
Started Aug 17 06:17:17 PM PDT 24
Finished Aug 17 06:17:20 PM PDT 24
Peak memory 232900 kb
Host smart-81b5fd0c-518e-42e0-bc75-fa41bfa87b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266000961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3266000961
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3554716831
Short name T674
Test name
Test status
Simulation time 446261563 ps
CPU time 3.9 seconds
Started Aug 17 06:17:20 PM PDT 24
Finished Aug 17 06:17:24 PM PDT 24
Peak memory 219052 kb
Host smart-4c29de70-417e-49e8-a428-f40fb28cc067
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3554716831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3554716831
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2612688180
Short name T751
Test name
Test status
Simulation time 1351089892 ps
CPU time 9.22 seconds
Started Aug 17 06:17:15 PM PDT 24
Finished Aug 17 06:17:25 PM PDT 24
Peak memory 219820 kb
Host smart-a3bcee48-c132-4287-8b4d-304e0c7f1e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612688180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2612688180
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2427544813
Short name T412
Test name
Test status
Simulation time 1380576331 ps
CPU time 4.22 seconds
Started Aug 17 06:17:32 PM PDT 24
Finished Aug 17 06:17:36 PM PDT 24
Peak memory 216456 kb
Host smart-a635c0d3-2e2a-44ff-ab20-8a5924d56b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427544813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2427544813
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3483901966
Short name T998
Test name
Test status
Simulation time 143905359 ps
CPU time 1.28 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:23 PM PDT 24
Peak memory 216468 kb
Host smart-1f1358e3-84ad-4238-9b60-2dc025275b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483901966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3483901966
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.105839449
Short name T543
Test name
Test status
Simulation time 34549398 ps
CPU time 0.85 seconds
Started Aug 17 06:17:15 PM PDT 24
Finished Aug 17 06:17:16 PM PDT 24
Peak memory 206128 kb
Host smart-37f4a62d-912f-4220-b458-c6942423ed94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105839449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.105839449
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3326478949
Short name T341
Test name
Test status
Simulation time 167861310 ps
CPU time 2.45 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:23 PM PDT 24
Peak memory 223728 kb
Host smart-2788cc29-b97c-4b3d-b266-41b63616db43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326478949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3326478949
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3799557499
Short name T667
Test name
Test status
Simulation time 25164571 ps
CPU time 0.71 seconds
Started Aug 17 06:17:33 PM PDT 24
Finished Aug 17 06:17:34 PM PDT 24
Peak memory 205372 kb
Host smart-18c5e7c5-0578-4054-a425-c6a8a36d844b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799557499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3799557499
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3642435389
Short name T940
Test name
Test status
Simulation time 156840677 ps
CPU time 2.6 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:17:46 PM PDT 24
Peak memory 232876 kb
Host smart-3fdcafc1-219c-4e17-b323-6d8afc925d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642435389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3642435389
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1087285455
Short name T914
Test name
Test status
Simulation time 20755535 ps
CPU time 0.8 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:17:17 PM PDT 24
Peak memory 206612 kb
Host smart-4b78fc13-1e2f-4e73-947c-bff5cff11f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087285455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1087285455
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2700955078
Short name T687
Test name
Test status
Simulation time 11972137403 ps
CPU time 160.73 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:20:02 PM PDT 24
Peak memory 256048 kb
Host smart-e1c01957-d485-46fc-86fc-c37bf0134c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700955078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2700955078
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3480468437
Short name T1020
Test name
Test status
Simulation time 5077091356 ps
CPU time 86.58 seconds
Started Aug 17 06:17:25 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 255020 kb
Host smart-f216a5ee-e9ae-4721-9d4c-9c997e23c341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480468437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3480468437
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1984332684
Short name T128
Test name
Test status
Simulation time 640602035 ps
CPU time 13.35 seconds
Started Aug 17 06:17:15 PM PDT 24
Finished Aug 17 06:17:28 PM PDT 24
Peak memory 248212 kb
Host smart-e5e58249-9d99-4d27-a349-5458080ed40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984332684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1984332684
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3395395874
Short name T255
Test name
Test status
Simulation time 217746050904 ps
CPU time 397.98 seconds
Started Aug 17 06:17:18 PM PDT 24
Finished Aug 17 06:23:56 PM PDT 24
Peak memory 249316 kb
Host smart-4bc0a8b2-2564-4a4e-ac98-4542e7d9b0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395395874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3395395874
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.599703695
Short name T570
Test name
Test status
Simulation time 31959095 ps
CPU time 2.41 seconds
Started Aug 17 06:17:27 PM PDT 24
Finished Aug 17 06:17:29 PM PDT 24
Peak memory 232484 kb
Host smart-fa513659-4462-4154-a1ef-d603a1001ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599703695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.599703695
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3167544105
Short name T126
Test name
Test status
Simulation time 3017671702 ps
CPU time 29.22 seconds
Started Aug 17 06:17:11 PM PDT 24
Finished Aug 17 06:17:40 PM PDT 24
Peak memory 224556 kb
Host smart-d2065241-4ac8-4c3a-b197-df47bf597558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167544105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3167544105
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3842208156
Short name T276
Test name
Test status
Simulation time 1726399334 ps
CPU time 4.87 seconds
Started Aug 17 06:17:39 PM PDT 24
Finished Aug 17 06:17:44 PM PDT 24
Peak memory 232884 kb
Host smart-1f5d8a73-5aa0-48b7-bed8-4eb8c98de05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842208156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3842208156
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1869224130
Short name T905
Test name
Test status
Simulation time 272501956 ps
CPU time 2.22 seconds
Started Aug 17 06:17:39 PM PDT 24
Finished Aug 17 06:17:42 PM PDT 24
Peak memory 224596 kb
Host smart-5ecb6f48-c5dd-4266-8bb2-d6cccf28a957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869224130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1869224130
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1655318298
Short name T857
Test name
Test status
Simulation time 5804286350 ps
CPU time 15.56 seconds
Started Aug 17 06:17:40 PM PDT 24
Finished Aug 17 06:17:56 PM PDT 24
Peak memory 222348 kb
Host smart-4e949861-dcba-48a2-bced-43e794256de8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1655318298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1655318298
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4053862121
Short name T150
Test name
Test status
Simulation time 22529131832 ps
CPU time 148.92 seconds
Started Aug 17 06:17:30 PM PDT 24
Finished Aug 17 06:19:59 PM PDT 24
Peak memory 249404 kb
Host smart-0e83e71e-cd60-48ae-9f12-07522e167fa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053862121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4053862121
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.4016306023
Short name T931
Test name
Test status
Simulation time 4919902387 ps
CPU time 10.68 seconds
Started Aug 17 06:17:15 PM PDT 24
Finished Aug 17 06:17:26 PM PDT 24
Peak memory 217168 kb
Host smart-2aea0871-793b-45c4-8449-a756d6f921b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016306023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.4016306023
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.257889755
Short name T306
Test name
Test status
Simulation time 2172397546 ps
CPU time 6.1 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:17:29 PM PDT 24
Peak memory 216572 kb
Host smart-af22d53e-40c3-4ce0-af85-b48b0d0e3dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257889755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.257889755
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1315424935
Short name T943
Test name
Test status
Simulation time 45383037 ps
CPU time 0.72 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:17:17 PM PDT 24
Peak memory 205648 kb
Host smart-ed72e86d-8806-411b-b82d-2a35ffb9153b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315424935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1315424935
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.680140523
Short name T941
Test name
Test status
Simulation time 69970633 ps
CPU time 0.96 seconds
Started Aug 17 06:17:14 PM PDT 24
Finished Aug 17 06:17:15 PM PDT 24
Peak memory 206120 kb
Host smart-35dc9f11-1454-4f16-bc8f-37172c50b7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680140523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.680140523
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3032679202
Short name T680
Test name
Test status
Simulation time 3750642324 ps
CPU time 10.73 seconds
Started Aug 17 06:17:23 PM PDT 24
Finished Aug 17 06:17:34 PM PDT 24
Peak memory 232964 kb
Host smart-9946bc34-f800-4af9-8628-6821b77617ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032679202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3032679202
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1201719424
Short name T475
Test name
Test status
Simulation time 15950938 ps
CPU time 0.76 seconds
Started Aug 17 06:17:37 PM PDT 24
Finished Aug 17 06:17:37 PM PDT 24
Peak memory 205532 kb
Host smart-d8953c52-8740-4448-afb6-5718ecb03114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201719424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1201719424
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1231292005
Short name T960
Test name
Test status
Simulation time 295924245 ps
CPU time 6.56 seconds
Started Aug 17 06:17:42 PM PDT 24
Finished Aug 17 06:17:48 PM PDT 24
Peak memory 232916 kb
Host smart-18946988-6289-4c8c-80ce-fc203fa80c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231292005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1231292005
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2002172577
Short name T357
Test name
Test status
Simulation time 59422882 ps
CPU time 0.8 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:17:23 PM PDT 24
Peak memory 206600 kb
Host smart-b5b7ce27-f344-4d09-8285-317150769f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002172577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2002172577
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1999704810
Short name T197
Test name
Test status
Simulation time 40398757702 ps
CPU time 329.47 seconds
Started Aug 17 06:17:34 PM PDT 24
Finished Aug 17 06:23:04 PM PDT 24
Peak memory 254992 kb
Host smart-526170c4-9f5c-4827-9319-72b44e8d99cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999704810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1999704810
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.55349939
Short name T245
Test name
Test status
Simulation time 31680279113 ps
CPU time 153.8 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:19:55 PM PDT 24
Peak memory 241196 kb
Host smart-012f58f2-5d10-441d-8b9f-037c4cc12606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55349939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.55349939
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2613532328
Short name T901
Test name
Test status
Simulation time 8205473383 ps
CPU time 78.71 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:18:41 PM PDT 24
Peak memory 265304 kb
Host smart-ae28125a-b067-4bbe-b88a-7935e121f2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613532328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2613532328
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3822457552
Short name T560
Test name
Test status
Simulation time 1327775774 ps
CPU time 10.38 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:17:54 PM PDT 24
Peak memory 232924 kb
Host smart-7f2cdf4c-48ea-4d98-904b-ca32c0447c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822457552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3822457552
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.473694909
Short name T823
Test name
Test status
Simulation time 270061512767 ps
CPU time 317.9 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:23:03 PM PDT 24
Peak memory 250128 kb
Host smart-210eee9e-07eb-46a9-be88-5ca3cfe1bdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473694909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.473694909
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.490505677
Short name T512
Test name
Test status
Simulation time 244077884 ps
CPU time 2.68 seconds
Started Aug 17 06:17:27 PM PDT 24
Finished Aug 17 06:17:30 PM PDT 24
Peak memory 224652 kb
Host smart-23ec1f6d-363e-4ea9-b345-ff2cba2737cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490505677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.490505677
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3821560281
Short name T695
Test name
Test status
Simulation time 7395011177 ps
CPU time 48.86 seconds
Started Aug 17 06:17:30 PM PDT 24
Finished Aug 17 06:18:19 PM PDT 24
Peak memory 224724 kb
Host smart-779b9a44-92c0-49e1-8512-a92fc4693419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821560281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3821560281
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2458600809
Short name T904
Test name
Test status
Simulation time 109518578 ps
CPU time 1.07 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:17:23 PM PDT 24
Peak memory 216760 kb
Host smart-b2a2f8bc-23c3-4a90-8b24-3823af8a3309
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458600809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2458600809
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1752076278
Short name T238
Test name
Test status
Simulation time 220531238 ps
CPU time 4.15 seconds
Started Aug 17 06:17:23 PM PDT 24
Finished Aug 17 06:17:27 PM PDT 24
Peak memory 224644 kb
Host smart-ee43e4d9-947c-4257-979d-b2be71016a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752076278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1752076278
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3982425703
Short name T641
Test name
Test status
Simulation time 6957922202 ps
CPU time 12.49 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:33 PM PDT 24
Peak memory 241076 kb
Host smart-57ef862f-b54c-40e2-9cd0-766b29bdaa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982425703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3982425703
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2448350373
Short name T797
Test name
Test status
Simulation time 305244484 ps
CPU time 3.61 seconds
Started Aug 17 06:17:18 PM PDT 24
Finished Aug 17 06:17:22 PM PDT 24
Peak memory 216564 kb
Host smart-61c7db25-99a8-4993-b4a8-94e11f03dec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448350373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2448350373
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4071951671
Short name T307
Test name
Test status
Simulation time 461314768 ps
CPU time 4.2 seconds
Started Aug 17 06:17:32 PM PDT 24
Finished Aug 17 06:17:37 PM PDT 24
Peak memory 216536 kb
Host smart-7eae04c3-834b-4ffb-b096-8b910159b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071951671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4071951671
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2123021187
Short name T539
Test name
Test status
Simulation time 67517121 ps
CPU time 1.12 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:22 PM PDT 24
Peak memory 216320 kb
Host smart-ca33316c-ed58-45ed-947b-e8ce26526bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123021187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2123021187
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.41601750
Short name T786
Test name
Test status
Simulation time 187002849 ps
CPU time 0.96 seconds
Started Aug 17 06:17:26 PM PDT 24
Finished Aug 17 06:17:27 PM PDT 24
Peak memory 207100 kb
Host smart-30a69d32-97f5-4265-a151-b0e517405b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41601750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.41601750
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2247327292
Short name T794
Test name
Test status
Simulation time 616207516 ps
CPU time 3.4 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:24 PM PDT 24
Peak memory 224596 kb
Host smart-ee551d40-6e50-4cf0-bd39-6eff7646b8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247327292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2247327292
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.936918892
Short name T929
Test name
Test status
Simulation time 12335696 ps
CPU time 0.68 seconds
Started Aug 17 06:17:35 PM PDT 24
Finished Aug 17 06:17:36 PM PDT 24
Peak memory 205388 kb
Host smart-ec51d772-7263-46a9-8cab-b46efbaae1e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936918892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.936918892
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2457381393
Short name T665
Test name
Test status
Simulation time 247977907 ps
CPU time 3.16 seconds
Started Aug 17 06:17:39 PM PDT 24
Finished Aug 17 06:17:42 PM PDT 24
Peak memory 232740 kb
Host smart-4af01de9-666d-4670-83d0-8edc22663b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457381393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2457381393
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2453449742
Short name T411
Test name
Test status
Simulation time 56734888 ps
CPU time 0.75 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:22 PM PDT 24
Peak memory 205528 kb
Host smart-0d1dcc15-0742-4dbc-be63-ebb037e1cf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453449742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2453449742
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1689664885
Short name T702
Test name
Test status
Simulation time 27559981077 ps
CPU time 46.31 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:18:10 PM PDT 24
Peak memory 224716 kb
Host smart-094865a7-c282-4856-bd7b-e58bb16eff60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689664885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1689664885
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.859347042
Short name T842
Test name
Test status
Simulation time 338964992390 ps
CPU time 234.53 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:21:16 PM PDT 24
Peak memory 265076 kb
Host smart-3dc4a0d7-4e37-46a5-b5fe-4bfaa00ddb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859347042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.859347042
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3379498748
Short name T294
Test name
Test status
Simulation time 48623645862 ps
CPU time 131.31 seconds
Started Aug 17 06:17:39 PM PDT 24
Finished Aug 17 06:19:51 PM PDT 24
Peak memory 249604 kb
Host smart-1714139e-5e26-43af-baf0-105117da4c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379498748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3379498748
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.236392074
Short name T649
Test name
Test status
Simulation time 8239014096 ps
CPU time 29.16 seconds
Started Aug 17 06:17:23 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 249224 kb
Host smart-0bb8f2d6-957c-468d-8959-3d53238f27c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236392074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.236392074
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3337141197
Short name T721
Test name
Test status
Simulation time 193961340 ps
CPU time 3.44 seconds
Started Aug 17 06:17:43 PM PDT 24
Finished Aug 17 06:17:46 PM PDT 24
Peak memory 232924 kb
Host smart-789a238d-d529-4062-9edb-3713cfadfb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337141197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3337141197
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2772709447
Short name T180
Test name
Test status
Simulation time 3137685426 ps
CPU time 15.18 seconds
Started Aug 17 06:17:35 PM PDT 24
Finished Aug 17 06:17:50 PM PDT 24
Peak memory 224624 kb
Host smart-903b0f2f-ebbf-4433-98e1-b4e5f0fb2b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772709447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2772709447
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2254242625
Short name T726
Test name
Test status
Simulation time 30385856 ps
CPU time 1.08 seconds
Started Aug 17 06:17:23 PM PDT 24
Finished Aug 17 06:17:24 PM PDT 24
Peak memory 216732 kb
Host smart-bcd46efa-ab73-48ca-ab4d-58d4ef6fe6ff
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254242625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2254242625
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1491711543
Short name T9
Test name
Test status
Simulation time 104022815 ps
CPU time 2.16 seconds
Started Aug 17 06:17:27 PM PDT 24
Finished Aug 17 06:17:30 PM PDT 24
Peak memory 232472 kb
Host smart-48726a1e-6ade-4557-9d72-9f686bcc57b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491711543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1491711543
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.325151898
Short name T199
Test name
Test status
Simulation time 14765156621 ps
CPU time 23.38 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:17:48 PM PDT 24
Peak memory 232884 kb
Host smart-fe2deace-2ead-4193-a30a-65ad5f25393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325151898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.325151898
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.624751742
Short name T136
Test name
Test status
Simulation time 3744261811 ps
CPU time 5.5 seconds
Started Aug 17 06:17:29 PM PDT 24
Finished Aug 17 06:17:34 PM PDT 24
Peak memory 220516 kb
Host smart-f6c2a1e5-2c5c-4a90-ba88-dba10c6f4cfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=624751742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.624751742
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.173824497
Short name T470
Test name
Test status
Simulation time 57195815 ps
CPU time 0.99 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:17:23 PM PDT 24
Peak memory 206668 kb
Host smart-1fdfe95c-00de-442c-bbc7-9cbb448bcea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173824497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.173824497
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2694410315
Short name T296
Test name
Test status
Simulation time 3856889240 ps
CPU time 26.56 seconds
Started Aug 17 06:17:31 PM PDT 24
Finished Aug 17 06:17:57 PM PDT 24
Peak memory 216404 kb
Host smart-464ee5e0-9bf0-4c5b-a831-c8453f7e8468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694410315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2694410315
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2423061537
Short name T386
Test name
Test status
Simulation time 779397545 ps
CPU time 6.16 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:17:28 PM PDT 24
Peak memory 216472 kb
Host smart-bf364134-edee-4454-b32e-afaa420bec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423061537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2423061537
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.220747703
Short name T51
Test name
Test status
Simulation time 68977835 ps
CPU time 1.37 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:17:45 PM PDT 24
Peak memory 216544 kb
Host smart-9d3866e6-ac72-47c7-b2f7-642e1bd23f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220747703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.220747703
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.421196550
Short name T953
Test name
Test status
Simulation time 30694790 ps
CPU time 0.82 seconds
Started Aug 17 06:17:28 PM PDT 24
Finished Aug 17 06:17:29 PM PDT 24
Peak memory 206128 kb
Host smart-595476d4-ac4c-442f-8f7f-ddb91258bed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421196550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.421196550
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.821266230
Short name T230
Test name
Test status
Simulation time 334549113 ps
CPU time 4.09 seconds
Started Aug 17 06:17:20 PM PDT 24
Finished Aug 17 06:17:24 PM PDT 24
Peak memory 224636 kb
Host smart-9127d0a5-463b-45e3-bfc8-ca4e60eb3101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821266230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.821266230
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3370608252
Short name T638
Test name
Test status
Simulation time 19255723 ps
CPU time 0.75 seconds
Started Aug 17 06:17:38 PM PDT 24
Finished Aug 17 06:17:39 PM PDT 24
Peak memory 204956 kb
Host smart-4c0cdefb-e6ea-4686-a02f-5f7aafb93836
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370608252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3370608252
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2391753934
Short name T225
Test name
Test status
Simulation time 510670218 ps
CPU time 4.52 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:17:51 PM PDT 24
Peak memory 224628 kb
Host smart-35a8963b-1ae7-4d36-a30c-c71196994a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391753934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2391753934
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2677232273
Short name T976
Test name
Test status
Simulation time 42490988 ps
CPU time 0.76 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:22 PM PDT 24
Peak memory 205524 kb
Host smart-a95b47d0-d81c-43e5-9255-8df7d847db69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677232273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2677232273
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2736627225
Short name T587
Test name
Test status
Simulation time 118748109252 ps
CPU time 208.78 seconds
Started Aug 17 06:17:46 PM PDT 24
Finished Aug 17 06:21:15 PM PDT 24
Peak memory 249384 kb
Host smart-446f7d2d-2dce-4652-9288-6dbb467d7843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736627225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2736627225
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.51666478
Short name T534
Test name
Test status
Simulation time 60839172217 ps
CPU time 140.85 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:19:43 PM PDT 24
Peak memory 256036 kb
Host smart-c3de4db6-98ff-44e5-8f18-f0f5f46043d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51666478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.51666478
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2460851536
Short name T206
Test name
Test status
Simulation time 2100238935 ps
CPU time 37.56 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:18:29 PM PDT 24
Peak memory 249356 kb
Host smart-2ea440dd-c892-47ff-aa4a-7dfe69dcba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460851536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2460851536
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.635213379
Short name T753
Test name
Test status
Simulation time 150033785 ps
CPU time 7.18 seconds
Started Aug 17 06:17:37 PM PDT 24
Finished Aug 17 06:17:44 PM PDT 24
Peak memory 241108 kb
Host smart-51dc1d13-a6c5-476c-8890-720928926b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635213379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.635213379
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2731367328
Short name T215
Test name
Test status
Simulation time 2935391758 ps
CPU time 19.18 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:18:03 PM PDT 24
Peak memory 232916 kb
Host smart-fef09d45-cbe2-4a55-9b31-6422e3a9131c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731367328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2731367328
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2509045132
Short name T828
Test name
Test status
Simulation time 189614801 ps
CPU time 0.95 seconds
Started Aug 17 06:17:18 PM PDT 24
Finished Aug 17 06:17:19 PM PDT 24
Peak memory 217972 kb
Host smart-0899bbe8-46cb-4cf5-8eca-9dc7e40bc6df
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509045132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2509045132
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2212554670
Short name T754
Test name
Test status
Simulation time 5379462589 ps
CPU time 10.49 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:17:56 PM PDT 24
Peak memory 240576 kb
Host smart-275f9cc4-56f8-4ba0-a1d3-d0b932b595f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212554670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2212554670
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3578026997
Short name T390
Test name
Test status
Simulation time 3551267286 ps
CPU time 13.48 seconds
Started Aug 17 06:17:34 PM PDT 24
Finished Aug 17 06:17:48 PM PDT 24
Peak memory 232972 kb
Host smart-54602d21-c087-4fb8-a454-f532a5df2890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578026997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3578026997
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1823554669
Short name T140
Test name
Test status
Simulation time 73001213 ps
CPU time 3.31 seconds
Started Aug 17 06:17:34 PM PDT 24
Finished Aug 17 06:17:37 PM PDT 24
Peak memory 219484 kb
Host smart-c87b0b99-607e-4c9d-922d-4449b14bfdaa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1823554669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1823554669
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3060648650
Short name T392
Test name
Test status
Simulation time 10293696364 ps
CPU time 54.72 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:18:40 PM PDT 24
Peak memory 216584 kb
Host smart-1efdeff9-b47e-4524-aab9-8e0bb789684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060648650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3060648650
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3963704803
Short name T954
Test name
Test status
Simulation time 6298394531 ps
CPU time 6.33 seconds
Started Aug 17 06:17:18 PM PDT 24
Finished Aug 17 06:17:25 PM PDT 24
Peak memory 216508 kb
Host smart-181f5c74-2d20-4f86-b081-cd501d64d7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963704803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3963704803
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1402896521
Short name T404
Test name
Test status
Simulation time 81385928 ps
CPU time 1.09 seconds
Started Aug 17 06:17:41 PM PDT 24
Finished Aug 17 06:17:43 PM PDT 24
Peak memory 216488 kb
Host smart-6c5c5b81-ed82-46c9-9f69-27c7ed78e9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402896521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1402896521
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2595018660
Short name T835
Test name
Test status
Simulation time 71037299 ps
CPU time 0.75 seconds
Started Aug 17 06:17:19 PM PDT 24
Finished Aug 17 06:17:20 PM PDT 24
Peak memory 206120 kb
Host smart-ee2e002e-e8bc-4844-bd93-741535fdc952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595018660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2595018660
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.379181004
Short name T762
Test name
Test status
Simulation time 230754241 ps
CPU time 3.56 seconds
Started Aug 17 06:17:37 PM PDT 24
Finished Aug 17 06:17:40 PM PDT 24
Peak memory 232908 kb
Host smart-e2e1376a-dba2-43de-8f05-3481b518f515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379181004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.379181004
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1920506746
Short name T325
Test name
Test status
Simulation time 54923284 ps
CPU time 0.71 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:17:45 PM PDT 24
Peak memory 204960 kb
Host smart-7ac5fe5f-fe09-4659-aac2-6b8864091533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920506746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1920506746
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.420007515
Short name T555
Test name
Test status
Simulation time 2054258513 ps
CPU time 8.05 seconds
Started Aug 17 06:17:28 PM PDT 24
Finished Aug 17 06:17:36 PM PDT 24
Peak memory 232944 kb
Host smart-4f77209a-8c9e-4122-9db9-58b2e2c86347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420007515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.420007515
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2189691862
Short name T616
Test name
Test status
Simulation time 64636903 ps
CPU time 0.83 seconds
Started Aug 17 06:17:48 PM PDT 24
Finished Aug 17 06:17:49 PM PDT 24
Peak memory 206588 kb
Host smart-255394fc-c17e-4af1-8714-c7b7a2f03372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189691862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2189691862
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4066671977
Short name T505
Test name
Test status
Simulation time 4731107256 ps
CPU time 84.27 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:18:48 PM PDT 24
Peak memory 265768 kb
Host smart-fe2e6fd5-6b1b-4a62-aeac-3656788820ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066671977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4066671977
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2775191430
Short name T447
Test name
Test status
Simulation time 2256008797 ps
CPU time 53.08 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:18:38 PM PDT 24
Peak memory 253892 kb
Host smart-f3f68340-70ec-466d-8eae-3bf61f84d381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775191430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2775191430
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2595427860
Short name T401
Test name
Test status
Simulation time 42886766547 ps
CPU time 125.24 seconds
Started Aug 17 06:17:46 PM PDT 24
Finished Aug 17 06:19:51 PM PDT 24
Peak memory 249392 kb
Host smart-a0f55fda-1554-49d2-84b2-34500a5b67f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595427860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2595427860
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1219627446
Short name T759
Test name
Test status
Simulation time 333004193 ps
CPU time 9.01 seconds
Started Aug 17 06:17:26 PM PDT 24
Finished Aug 17 06:17:35 PM PDT 24
Peak memory 241092 kb
Host smart-dc39ae4a-7d78-4417-93f4-d7344d08cfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219627446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1219627446
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.4034852968
Short name T367
Test name
Test status
Simulation time 11144146812 ps
CPU time 63.42 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:18:27 PM PDT 24
Peak memory 249624 kb
Host smart-18936526-14b9-46eb-91cf-8ad48092c1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034852968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.4034852968
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1141693794
Short name T181
Test name
Test status
Simulation time 3326832143 ps
CPU time 5.47 seconds
Started Aug 17 06:17:27 PM PDT 24
Finished Aug 17 06:17:33 PM PDT 24
Peak memory 224752 kb
Host smart-29537342-4ab2-49ba-9b9d-a9fa7162b1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141693794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1141693794
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3168412107
Short name T806
Test name
Test status
Simulation time 3464802010 ps
CPU time 13.16 seconds
Started Aug 17 06:17:25 PM PDT 24
Finished Aug 17 06:17:38 PM PDT 24
Peak memory 232940 kb
Host smart-3b7ff6d3-0ffe-4cc4-8b41-49ac7b8115d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168412107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3168412107
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3738216029
Short name T37
Test name
Test status
Simulation time 23854110 ps
CPU time 1.12 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:17:51 PM PDT 24
Peak memory 216692 kb
Host smart-2eae333f-c426-4902-84df-48e9aee3ffda
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738216029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3738216029
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1292578048
Short name T693
Test name
Test status
Simulation time 3360385626 ps
CPU time 6.78 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 224732 kb
Host smart-2342ca46-3dfa-4bf8-a0ad-be299104a83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292578048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1292578048
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.680022660
Short name T866
Test name
Test status
Simulation time 331776908 ps
CPU time 3.88 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:17:49 PM PDT 24
Peak memory 232832 kb
Host smart-5441aa71-1fb9-4471-9d53-cb0cc2528e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680022660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.680022660
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2528447166
Short name T349
Test name
Test status
Simulation time 997909812 ps
CPU time 10.14 seconds
Started Aug 17 06:17:42 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 220520 kb
Host smart-04b99ee8-cc8b-415f-8a86-3ffcd3769b80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2528447166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2528447166
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.426520487
Short name T53
Test name
Test status
Simulation time 90828308387 ps
CPU time 774.61 seconds
Started Aug 17 06:17:54 PM PDT 24
Finished Aug 17 06:30:48 PM PDT 24
Peak memory 272236 kb
Host smart-1ea2ced3-8d35-438a-8e47-5cba09f540b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426520487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.426520487
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2064899629
Short name T338
Test name
Test status
Simulation time 356541157 ps
CPU time 6.15 seconds
Started Aug 17 06:17:46 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 216552 kb
Host smart-92034f56-9ac9-4e50-ac0e-515b8168a840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064899629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2064899629
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3662967491
Short name T545
Test name
Test status
Simulation time 3579064202 ps
CPU time 11 seconds
Started Aug 17 06:17:23 PM PDT 24
Finished Aug 17 06:17:34 PM PDT 24
Peak memory 216580 kb
Host smart-5a83c42e-01b4-40f3-830d-14acf7bcb620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662967491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3662967491
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2195965715
Short name T727
Test name
Test status
Simulation time 80336331 ps
CPU time 1.51 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:17:47 PM PDT 24
Peak memory 208280 kb
Host smart-fc74bc9f-c56d-47e3-877f-5add09c6814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195965715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2195965715
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.4273455416
Short name T371
Test name
Test status
Simulation time 31630037 ps
CPU time 0.74 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:17:25 PM PDT 24
Peak memory 206076 kb
Host smart-b49bdd2a-9c78-4cdf-83ef-1ed00abc1d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273455416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4273455416
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1482606497
Short name T221
Test name
Test status
Simulation time 71487222 ps
CPU time 2.18 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 232908 kb
Host smart-2483c32f-f0de-4740-a985-a6c5a90db848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482606497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1482606497
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1742353658
Short name T366
Test name
Test status
Simulation time 12186025 ps
CPU time 0.75 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:17:50 PM PDT 24
Peak memory 205528 kb
Host smart-67ca43f1-615f-4af9-bc7a-a9f6efcb9228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742353658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1742353658
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3257385555
Short name T474
Test name
Test status
Simulation time 47576038 ps
CPU time 2.44 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 232852 kb
Host smart-7154ee09-8877-41f4-a434-e1aaa6211215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257385555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3257385555
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.695832274
Short name T598
Test name
Test status
Simulation time 50173359 ps
CPU time 0.76 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:17:25 PM PDT 24
Peak memory 206960 kb
Host smart-af08791f-f488-4f39-a99d-1a65254b6988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695832274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.695832274
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.423549596
Short name T739
Test name
Test status
Simulation time 24571073992 ps
CPU time 109.07 seconds
Started Aug 17 06:17:27 PM PDT 24
Finished Aug 17 06:19:16 PM PDT 24
Peak memory 256972 kb
Host smart-32078613-a78b-4a0e-9335-8ad9b29cdb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423549596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.423549596
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.445510482
Short name T809
Test name
Test status
Simulation time 5481185529 ps
CPU time 61.97 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 249412 kb
Host smart-bdb5fedf-122b-40ae-9484-189fe67e0085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445510482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.445510482
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2392692190
Short name T669
Test name
Test status
Simulation time 23995206185 ps
CPU time 180.78 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:20:46 PM PDT 24
Peak memory 257608 kb
Host smart-f0655e61-b214-4568-affb-50932fd2fc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392692190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2392692190
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3384485224
Short name T785
Test name
Test status
Simulation time 127208167 ps
CPU time 3.09 seconds
Started Aug 17 06:17:42 PM PDT 24
Finished Aug 17 06:17:45 PM PDT 24
Peak memory 224708 kb
Host smart-6f5bd87b-7714-4141-b74e-068304beffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384485224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3384485224
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.259379307
Short name T522
Test name
Test status
Simulation time 967044550 ps
CPU time 13.41 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:18:02 PM PDT 24
Peak memory 238736 kb
Host smart-b80ce887-167a-428b-929d-abfda51d35e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259379307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.259379307
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1160838402
Short name T433
Test name
Test status
Simulation time 971407161 ps
CPU time 11.2 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:17:57 PM PDT 24
Peak memory 232848 kb
Host smart-0626cca8-d418-4dd9-add4-e8a3bec9d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160838402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1160838402
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2196263549
Short name T640
Test name
Test status
Simulation time 4256644887 ps
CPU time 37.31 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:18:29 PM PDT 24
Peak memory 232992 kb
Host smart-2447ac06-7c85-4bc0-87a7-efd83a8ab756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196263549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2196263549
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3884028957
Short name T35
Test name
Test status
Simulation time 16661076 ps
CPU time 1.02 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 217960 kb
Host smart-4fc82f1e-744e-4f3a-86dc-ddf36aaabd5f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884028957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3884028957
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1033453222
Short name T314
Test name
Test status
Simulation time 75990108 ps
CPU time 2.3 seconds
Started Aug 17 06:17:48 PM PDT 24
Finished Aug 17 06:17:51 PM PDT 24
Peak memory 223928 kb
Host smart-2a0e3482-34c0-4235-bf1c-14475b6602ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033453222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1033453222
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3156733896
Short name T529
Test name
Test status
Simulation time 3315521606 ps
CPU time 5.25 seconds
Started Aug 17 06:17:28 PM PDT 24
Finished Aug 17 06:17:33 PM PDT 24
Peak memory 232892 kb
Host smart-b1c6cea8-b021-4fa5-94f5-86900bcffe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156733896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3156733896
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3954786693
Short name T765
Test name
Test status
Simulation time 620422516 ps
CPU time 9.96 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:17:55 PM PDT 24
Peak memory 223112 kb
Host smart-c8832621-7034-40ae-8791-65083a792ef8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3954786693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3954786693
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2227070076
Short name T624
Test name
Test status
Simulation time 46602467 ps
CPU time 1.06 seconds
Started Aug 17 06:17:48 PM PDT 24
Finished Aug 17 06:17:49 PM PDT 24
Peak memory 206820 kb
Host smart-27aafa88-9ae7-4cfa-ae2c-cb057406d365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227070076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2227070076
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4038640248
Short name T581
Test name
Test status
Simulation time 5192300588 ps
CPU time 32.47 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:17:57 PM PDT 24
Peak memory 216516 kb
Host smart-64d0424c-390c-4a45-be58-4fb8ff0ba63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038640248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4038640248
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.518526253
Short name T376
Test name
Test status
Simulation time 17283199036 ps
CPU time 11.54 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:17:40 PM PDT 24
Peak memory 216592 kb
Host smart-ec214e52-401d-4f1e-ac7c-42ec23ef1278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518526253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.518526253
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2407804578
Short name T694
Test name
Test status
Simulation time 75516191 ps
CPU time 1.42 seconds
Started Aug 17 06:17:46 PM PDT 24
Finished Aug 17 06:17:48 PM PDT 24
Peak memory 216064 kb
Host smart-4f72abe6-20bb-4cbd-b1b7-a4113df0db27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407804578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2407804578
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1342283408
Short name T768
Test name
Test status
Simulation time 61328818 ps
CPU time 0.68 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 206144 kb
Host smart-55d09e0b-e917-477c-823e-e7c24e39ce03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342283408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1342283408
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.876761229
Short name T427
Test name
Test status
Simulation time 755485679 ps
CPU time 7.69 seconds
Started Aug 17 06:17:43 PM PDT 24
Finished Aug 17 06:17:51 PM PDT 24
Peak memory 232884 kb
Host smart-f651fa1d-d3c0-4ae6-b214-5d3025fe90b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876761229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.876761229
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.684221174
Short name T348
Test name
Test status
Simulation time 35888490 ps
CPU time 0.72 seconds
Started Aug 17 06:17:52 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 205556 kb
Host smart-ca4b58a9-1ce2-4064-81eb-fbbaa3c9b4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684221174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.684221174
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.7950711
Short name T937
Test name
Test status
Simulation time 238565771 ps
CPU time 3.23 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 232812 kb
Host smart-0d6b47fa-1655-4313-98a2-2068d3b3a84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7950711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.7950711
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3858468284
Short name T699
Test name
Test status
Simulation time 34005391 ps
CPU time 0.81 seconds
Started Aug 17 06:17:48 PM PDT 24
Finished Aug 17 06:17:49 PM PDT 24
Peak memory 205920 kb
Host smart-9b66f4e8-07db-46bd-887c-c8f28cbcd499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858468284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3858468284
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1636670277
Short name T232
Test name
Test status
Simulation time 18002134551 ps
CPU time 98.49 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:19:26 PM PDT 24
Peak memory 251376 kb
Host smart-d640b255-ad5e-4123-bbcd-c16da1a913e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636670277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1636670277
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1417745527
Short name T453
Test name
Test status
Simulation time 3826814328 ps
CPU time 50.47 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:18:41 PM PDT 24
Peak memory 250420 kb
Host smart-b78c8060-d92f-419d-ab08-3c7475b3ce10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417745527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1417745527
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4167519641
Short name T270
Test name
Test status
Simulation time 1234654007 ps
CPU time 28.36 seconds
Started Aug 17 06:17:42 PM PDT 24
Finished Aug 17 06:18:10 PM PDT 24
Peak memory 251784 kb
Host smart-b84c7dcc-fc2c-426a-9d14-793d7b89c584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167519641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4167519641
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1004236971
Short name T139
Test name
Test status
Simulation time 3997699410 ps
CPU time 8.95 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 224676 kb
Host smart-3b4e5095-f423-42ed-8533-09d3201eb86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004236971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1004236971
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3114659606
Short name T256
Test name
Test status
Simulation time 55641333800 ps
CPU time 401.04 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:24:05 PM PDT 24
Peak memory 250384 kb
Host smart-65ebb1c3-586c-45c1-afab-7438c1e83cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114659606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3114659606
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3870001305
Short name T728
Test name
Test status
Simulation time 28987140 ps
CPU time 2.55 seconds
Started Aug 17 06:17:43 PM PDT 24
Finished Aug 17 06:17:46 PM PDT 24
Peak memory 232520 kb
Host smart-c919001f-ae3c-4afe-81d3-a0d59e8ff15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870001305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3870001305
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2062085253
Short name T222
Test name
Test status
Simulation time 3417313280 ps
CPU time 18.41 seconds
Started Aug 17 06:17:36 PM PDT 24
Finished Aug 17 06:17:54 PM PDT 24
Peak memory 232984 kb
Host smart-c063b053-2e28-410f-b79b-f8b134c3796e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062085253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2062085253
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.949620160
Short name T556
Test name
Test status
Simulation time 52305154 ps
CPU time 1.11 seconds
Started Aug 17 06:17:46 PM PDT 24
Finished Aug 17 06:17:47 PM PDT 24
Peak memory 216732 kb
Host smart-50df9f3e-f241-439d-a950-a604c71c01bc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949620160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.949620160
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3885063026
Short name T462
Test name
Test status
Simulation time 6239982398 ps
CPU time 15.64 seconds
Started Aug 17 06:17:46 PM PDT 24
Finished Aug 17 06:18:02 PM PDT 24
Peak memory 224724 kb
Host smart-7953b060-206c-4ec4-9c62-ca1e7d2c5860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885063026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3885063026
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1596739768
Short name T561
Test name
Test status
Simulation time 483439401 ps
CPU time 7.72 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:17:59 PM PDT 24
Peak memory 232824 kb
Host smart-2bd43499-22b2-483e-a771-386f21bbf11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596739768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1596739768
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3025738922
Short name T657
Test name
Test status
Simulation time 1538821643 ps
CPU time 17.24 seconds
Started Aug 17 06:17:39 PM PDT 24
Finished Aug 17 06:18:02 PM PDT 24
Peak memory 220268 kb
Host smart-ef7837f4-52e9-4099-bd7c-2e5563578e1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3025738922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3025738922
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.932509797
Short name T149
Test name
Test status
Simulation time 40614403230 ps
CPU time 105.7 seconds
Started Aug 17 06:17:48 PM PDT 24
Finished Aug 17 06:19:34 PM PDT 24
Peak memory 253440 kb
Host smart-2064775f-585b-45c5-be72-03095abcb553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932509797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.932509797
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.824513568
Short name T293
Test name
Test status
Simulation time 9850001779 ps
CPU time 12.41 seconds
Started Aug 17 06:17:53 PM PDT 24
Finished Aug 17 06:18:05 PM PDT 24
Peak memory 219780 kb
Host smart-92c00afd-f2ab-4ccd-81fb-76e508d9d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824513568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.824513568
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.305389278
Short name T483
Test name
Test status
Simulation time 1651832144 ps
CPU time 6.53 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:17:57 PM PDT 24
Peak memory 216440 kb
Host smart-a197019f-0885-464b-9565-cca214455ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305389278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.305389278
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2205176137
Short name T398
Test name
Test status
Simulation time 970698678 ps
CPU time 2.28 seconds
Started Aug 17 06:17:53 PM PDT 24
Finished Aug 17 06:17:55 PM PDT 24
Peak memory 216460 kb
Host smart-aee8cf91-dfb4-4df8-a7df-e39534aad7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205176137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2205176137
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3494039891
Short name T708
Test name
Test status
Simulation time 120556653 ps
CPU time 0.89 seconds
Started Aug 17 06:17:27 PM PDT 24
Finished Aug 17 06:17:28 PM PDT 24
Peak memory 206136 kb
Host smart-479f462a-6dc0-4160-924f-ccd57b25641e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494039891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3494039891
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.897842315
Short name T485
Test name
Test status
Simulation time 16701916039 ps
CPU time 30.59 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:18:17 PM PDT 24
Peak memory 232900 kb
Host smart-91fea7a7-2af4-4ff3-9091-231f2c3f2918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897842315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.897842315
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3827577225
Short name T737
Test name
Test status
Simulation time 16009596 ps
CPU time 0.73 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:17:46 PM PDT 24
Peak memory 205568 kb
Host smart-b370bfa6-b203-40e1-9645-ba3f783f4290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827577225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3827577225
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3478918676
Short name T93
Test name
Test status
Simulation time 119545785 ps
CPU time 3.03 seconds
Started Aug 17 06:17:36 PM PDT 24
Finished Aug 17 06:17:40 PM PDT 24
Peak memory 232912 kb
Host smart-5892e8ea-13a6-4282-8151-f90158fc880a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478918676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3478918676
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.97406352
Short name T320
Test name
Test status
Simulation time 43011686 ps
CPU time 0.81 seconds
Started Aug 17 06:17:31 PM PDT 24
Finished Aug 17 06:17:32 PM PDT 24
Peak memory 206620 kb
Host smart-b1620697-9946-4f76-915e-5042b5db4d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97406352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.97406352
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1594026508
Short name T426
Test name
Test status
Simulation time 5106206686 ps
CPU time 55.51 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 253016 kb
Host smart-ae497bdc-0b20-44af-8b65-d49401ce51d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594026508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1594026508
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1264026012
Short name T553
Test name
Test status
Simulation time 3514077651 ps
CPU time 54.69 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:18:40 PM PDT 24
Peak memory 251468 kb
Host smart-88fd5e24-6a89-44be-bc9a-9f0b984cfeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264026012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1264026012
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1209573266
Short name T375
Test name
Test status
Simulation time 1325777907 ps
CPU time 10.31 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:17:57 PM PDT 24
Peak memory 217580 kb
Host smart-bd8c39be-9261-4676-a561-456732fd67c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209573266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1209573266
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4045569110
Short name T585
Test name
Test status
Simulation time 1861195518 ps
CPU time 20.98 seconds
Started Aug 17 06:17:53 PM PDT 24
Finished Aug 17 06:18:14 PM PDT 24
Peak memory 234900 kb
Host smart-7fe37314-7940-43f7-9d43-567ef86aab4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045569110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4045569110
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3372604757
Short name T75
Test name
Test status
Simulation time 734820849 ps
CPU time 7.53 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:17:55 PM PDT 24
Peak memory 232860 kb
Host smart-c320a4f6-92e0-4c81-bce4-a119f15b26d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372604757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3372604757
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2563960506
Short name T456
Test name
Test status
Simulation time 2319141667 ps
CPU time 24.79 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:18:10 PM PDT 24
Peak memory 232916 kb
Host smart-fea51473-b876-4cdf-9201-357586de1add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563960506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2563960506
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.902330894
Short name T647
Test name
Test status
Simulation time 121972282 ps
CPU time 1.1 seconds
Started Aug 17 06:17:52 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 216692 kb
Host smart-c7491f5d-bdeb-4913-ad6d-0fde07485188
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902330894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.902330894
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.965427775
Short name T744
Test name
Test status
Simulation time 918071007 ps
CPU time 3.42 seconds
Started Aug 17 06:17:37 PM PDT 24
Finished Aug 17 06:17:40 PM PDT 24
Peak memory 232860 kb
Host smart-263572be-decb-4820-916c-b60568ce3312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965427775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.965427775
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3529367046
Short name T894
Test name
Test status
Simulation time 114137688 ps
CPU time 2.08 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:17:47 PM PDT 24
Peak memory 224044 kb
Host smart-ae90f06f-ade9-46ff-bd0b-8b6db8c66c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529367046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3529367046
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.85719275
Short name T874
Test name
Test status
Simulation time 3240314913 ps
CPU time 15.46 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:18:06 PM PDT 24
Peak memory 222424 kb
Host smart-e03d3ff9-2442-4201-9710-bf9315fdb5a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=85719275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direc
t.85719275
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3901383364
Short name T22
Test name
Test status
Simulation time 257197332 ps
CPU time 1 seconds
Started Aug 17 06:17:53 PM PDT 24
Finished Aug 17 06:17:54 PM PDT 24
Peak memory 206916 kb
Host smart-d71c278c-12cd-4733-9cec-87984ae897d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901383364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3901383364
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1551577031
Short name T652
Test name
Test status
Simulation time 1050731344 ps
CPU time 8.4 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:17:56 PM PDT 24
Peak memory 219840 kb
Host smart-b494c381-0986-41ea-b62b-cb7c4bea178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551577031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1551577031
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.102274860
Short name T323
Test name
Test status
Simulation time 61460258091 ps
CPU time 13.23 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:18:04 PM PDT 24
Peak memory 216548 kb
Host smart-3938e78a-7484-455a-b5a6-56ff05cea432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102274860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.102274860
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4089539795
Short name T716
Test name
Test status
Simulation time 78520165 ps
CPU time 1.41 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:17:45 PM PDT 24
Peak memory 208316 kb
Host smart-98f1931a-513c-4465-aecc-01c45b3f617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089539795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4089539795
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1351467912
Short name T391
Test name
Test status
Simulation time 143928144 ps
CPU time 0.84 seconds
Started Aug 17 06:17:46 PM PDT 24
Finished Aug 17 06:17:47 PM PDT 24
Peak memory 206076 kb
Host smart-0294562b-4642-4fad-879f-1258f74cc2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351467912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1351467912
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2311229941
Short name T625
Test name
Test status
Simulation time 496916455 ps
CPU time 3.99 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:17:51 PM PDT 24
Peak memory 232840 kb
Host smart-ae5bb7c9-4c06-4e3f-88f1-87f7797f9ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311229941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2311229941
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1796232819
Short name T767
Test name
Test status
Simulation time 15268591 ps
CPU time 0.75 seconds
Started Aug 17 06:17:46 PM PDT 24
Finished Aug 17 06:17:47 PM PDT 24
Peak memory 205504 kb
Host smart-8c733771-1308-4ed7-adc6-48a5393f7070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796232819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1796232819
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2773368995
Short name T877
Test name
Test status
Simulation time 182420927 ps
CPU time 3.13 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:17:49 PM PDT 24
Peak memory 232880 kb
Host smart-d580fe91-0698-4fe0-a128-a3348d47fbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773368995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2773368995
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.452807061
Short name T891
Test name
Test status
Simulation time 20055373 ps
CPU time 0.76 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:17:57 PM PDT 24
Peak memory 206960 kb
Host smart-c219038f-8e7f-45e4-91f2-1b067e8c9154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452807061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.452807061
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2903900262
Short name T713
Test name
Test status
Simulation time 2399759879 ps
CPU time 15.24 seconds
Started Aug 17 06:17:46 PM PDT 24
Finished Aug 17 06:18:02 PM PDT 24
Peak memory 236344 kb
Host smart-5b1ca36d-7c7f-43f0-97a2-edcbbc6a2bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903900262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2903900262
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3938086767
Short name T731
Test name
Test status
Simulation time 7353454346 ps
CPU time 35.47 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:18:26 PM PDT 24
Peak memory 217956 kb
Host smart-1c21fe4f-d972-492e-bc6d-b78267e13d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938086767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3938086767
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.704027839
Short name T830
Test name
Test status
Simulation time 365060459953 ps
CPU time 227.37 seconds
Started Aug 17 06:17:55 PM PDT 24
Finished Aug 17 06:21:43 PM PDT 24
Peak memory 257264 kb
Host smart-0c207b01-b81e-44b6-b96a-8902393da99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704027839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.704027839
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3664152135
Short name T207
Test name
Test status
Simulation time 66886905886 ps
CPU time 471.89 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:25:48 PM PDT 24
Peak memory 270752 kb
Host smart-88850e96-1908-4e99-9d71-dcc9f3c06776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664152135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3664152135
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3897985925
Short name T725
Test name
Test status
Simulation time 257824190 ps
CPU time 2.72 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 232836 kb
Host smart-c942177d-2715-493d-a099-0fd976872175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897985925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3897985925
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2351510389
Short name T965
Test name
Test status
Simulation time 2720836471 ps
CPU time 27.27 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:18:14 PM PDT 24
Peak memory 240668 kb
Host smart-2135f869-d006-412d-8e8b-fb1dcd9665e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351510389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2351510389
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2968630329
Short name T484
Test name
Test status
Simulation time 130114553 ps
CPU time 1.12 seconds
Started Aug 17 06:17:37 PM PDT 24
Finished Aug 17 06:17:38 PM PDT 24
Peak memory 216676 kb
Host smart-2aa4026c-015f-4b53-ae63-19375e0d6e2a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968630329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2968630329
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2845224898
Short name T62
Test name
Test status
Simulation time 148030502 ps
CPU time 2.4 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 224616 kb
Host smart-5e753462-f05e-474c-a7b6-a69ad2bbe147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845224898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2845224898
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1495371514
Short name T538
Test name
Test status
Simulation time 1195161427 ps
CPU time 5.81 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:17:55 PM PDT 24
Peak memory 232784 kb
Host smart-3755a963-719c-4193-a945-bebea840a02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495371514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1495371514
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2722257346
Short name T604
Test name
Test status
Simulation time 4267854328 ps
CPU time 9.19 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:18:00 PM PDT 24
Peak memory 218900 kb
Host smart-e8f65ee8-f985-4742-8270-6be70062a4eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2722257346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2722257346
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1765077672
Short name T915
Test name
Test status
Simulation time 101104219259 ps
CPU time 252.19 seconds
Started Aug 17 06:17:42 PM PDT 24
Finished Aug 17 06:21:55 PM PDT 24
Peak memory 257580 kb
Host smart-5345df58-32ff-458f-b1c9-8aa75f99231f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765077672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1765077672
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4078874708
Short name T666
Test name
Test status
Simulation time 22370783 ps
CPU time 0.74 seconds
Started Aug 17 06:17:52 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 205756 kb
Host smart-d8106332-9a2d-45fc-a9d7-1375f19cc002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078874708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4078874708
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4235822993
Short name T892
Test name
Test status
Simulation time 330950813 ps
CPU time 2.62 seconds
Started Aug 17 06:17:52 PM PDT 24
Finished Aug 17 06:17:55 PM PDT 24
Peak memory 216508 kb
Host smart-f4c34526-dbb4-4197-a818-cf4742e5386d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235822993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4235822993
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.4025937848
Short name T643
Test name
Test status
Simulation time 22945930 ps
CPU time 0.85 seconds
Started Aug 17 06:17:54 PM PDT 24
Finished Aug 17 06:17:55 PM PDT 24
Peak memory 206072 kb
Host smart-f1cd7c68-2b1d-4d24-a9c6-9af6fdd4a5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025937848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.4025937848
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.873240112
Short name T576
Test name
Test status
Simulation time 25088623 ps
CPU time 0.8 seconds
Started Aug 17 06:17:55 PM PDT 24
Finished Aug 17 06:17:56 PM PDT 24
Peak memory 206136 kb
Host smart-c3f2c800-155b-4f65-9dc5-de9a04e6135a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873240112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.873240112
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1162670359
Short name T897
Test name
Test status
Simulation time 68389770605 ps
CPU time 27.36 seconds
Started Aug 17 06:17:54 PM PDT 24
Finished Aug 17 06:18:22 PM PDT 24
Peak memory 232908 kb
Host smart-7acd4409-fb32-45ff-885a-59c3d873fb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162670359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1162670359
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3568034616
Short name T395
Test name
Test status
Simulation time 11119391 ps
CPU time 0.71 seconds
Started Aug 17 06:16:58 PM PDT 24
Finished Aug 17 06:17:04 PM PDT 24
Peak memory 204956 kb
Host smart-41857d5e-05aa-4374-b7e1-f028fb67c31a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568034616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
568034616
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1217079018
Short name T740
Test name
Test status
Simulation time 309854171 ps
CPU time 2.45 seconds
Started Aug 17 06:17:02 PM PDT 24
Finished Aug 17 06:17:05 PM PDT 24
Peak memory 224200 kb
Host smart-1c7c2a2d-3ea9-4436-896d-4fd57f998c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217079018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1217079018
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3620967022
Short name T430
Test name
Test status
Simulation time 24451409 ps
CPU time 0.76 seconds
Started Aug 17 06:17:01 PM PDT 24
Finished Aug 17 06:17:02 PM PDT 24
Peak memory 206612 kb
Host smart-e66d12eb-664d-4828-a16e-6ced3bca8a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620967022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3620967022
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.528332057
Short name T955
Test name
Test status
Simulation time 18968028183 ps
CPU time 76.86 seconds
Started Aug 17 06:16:52 PM PDT 24
Finished Aug 17 06:18:09 PM PDT 24
Peak memory 249636 kb
Host smart-93cc55da-65be-4166-b5ac-b70573888326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528332057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.528332057
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3333925946
Short name T304
Test name
Test status
Simulation time 109082931792 ps
CPU time 136.89 seconds
Started Aug 17 06:16:55 PM PDT 24
Finished Aug 17 06:19:12 PM PDT 24
Peak memory 252964 kb
Host smart-eded1b30-d6d4-4bf7-a77e-443975a95866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333925946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3333925946
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1902145192
Short name T287
Test name
Test status
Simulation time 533470706 ps
CPU time 9.76 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:17:07 PM PDT 24
Peak memory 238060 kb
Host smart-4612ab7d-495c-405f-87cc-40fdde380f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902145192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1902145192
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3187969588
Short name T593
Test name
Test status
Simulation time 11164546003 ps
CPU time 28.57 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:17:26 PM PDT 24
Peak memory 224784 kb
Host smart-b2f3beb5-4a2b-43de-8d4b-fb9c771805f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187969588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3187969588
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1121850437
Short name T814
Test name
Test status
Simulation time 3137321139 ps
CPU time 16.72 seconds
Started Aug 17 06:16:52 PM PDT 24
Finished Aug 17 06:17:09 PM PDT 24
Peak memory 234184 kb
Host smart-02b171f6-fd6d-40b9-a0ba-72fddaa659d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121850437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1121850437
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3649981392
Short name T476
Test name
Test status
Simulation time 27893145 ps
CPU time 1.1 seconds
Started Aug 17 06:17:02 PM PDT 24
Finished Aug 17 06:17:03 PM PDT 24
Peak memory 217968 kb
Host smart-dd210c8d-722c-4a11-8031-c394112db7ab
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649981392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3649981392
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2373157748
Short name T528
Test name
Test status
Simulation time 287195679 ps
CPU time 3.69 seconds
Started Aug 17 06:16:51 PM PDT 24
Finished Aug 17 06:16:54 PM PDT 24
Peak memory 232900 kb
Host smart-99159f46-d328-4d31-aae3-36706f56fe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373157748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2373157748
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3933327684
Short name T986
Test name
Test status
Simulation time 27455117329 ps
CPU time 23.17 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:17:20 PM PDT 24
Peak memory 232940 kb
Host smart-b0127e74-0806-4470-a807-6ecd3e2f0a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933327684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3933327684
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.213384638
Short name T846
Test name
Test status
Simulation time 96525209 ps
CPU time 4.22 seconds
Started Aug 17 06:17:06 PM PDT 24
Finished Aug 17 06:17:10 PM PDT 24
Peak memory 223148 kb
Host smart-c3933df0-e6e7-4707-8509-752dcaa2352b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=213384638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.213384638
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3682107633
Short name T70
Test name
Test status
Simulation time 230322742 ps
CPU time 1.06 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:16:57 PM PDT 24
Peak memory 235484 kb
Host smart-aed68482-c91e-4a26-b953-1b95657463a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682107633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3682107633
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3966203637
Short name T131
Test name
Test status
Simulation time 133674770169 ps
CPU time 590.41 seconds
Started Aug 17 06:17:11 PM PDT 24
Finished Aug 17 06:27:02 PM PDT 24
Peak memory 257588 kb
Host smart-349e2d0f-cccc-4f78-a954-288cea6e6417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966203637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3966203637
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2518534698
Short name T779
Test name
Test status
Simulation time 10490733415 ps
CPU time 32.19 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:17:35 PM PDT 24
Peak memory 216556 kb
Host smart-b62d6578-18aa-4107-9556-d2272bb69466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518534698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2518534698
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.770158297
Short name T554
Test name
Test status
Simulation time 1115244391 ps
CPU time 7.55 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:17:03 PM PDT 24
Peak memory 216496 kb
Host smart-4e92be76-2e36-46cb-a212-00a08357e8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770158297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.770158297
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.671168596
Short name T491
Test name
Test status
Simulation time 638852797 ps
CPU time 1.71 seconds
Started Aug 17 06:16:52 PM PDT 24
Finished Aug 17 06:16:54 PM PDT 24
Peak memory 216472 kb
Host smart-86cd837a-54ba-49c3-94db-5d4ca2d1ed12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671168596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.671168596
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1030831339
Short name T531
Test name
Test status
Simulation time 100551341 ps
CPU time 0.75 seconds
Started Aug 17 06:17:01 PM PDT 24
Finished Aug 17 06:17:02 PM PDT 24
Peak memory 206080 kb
Host smart-e1fc5bcf-a5d2-45ac-af0d-ec2f38acc371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030831339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1030831339
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1972378549
Short name T792
Test name
Test status
Simulation time 22363325157 ps
CPU time 22.87 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:17:19 PM PDT 24
Peak memory 232952 kb
Host smart-3296bb29-8006-4300-8ee3-561caa70a9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972378549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1972378549
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2373879275
Short name T802
Test name
Test status
Simulation time 20258719 ps
CPU time 0.72 seconds
Started Aug 17 06:17:58 PM PDT 24
Finished Aug 17 06:17:59 PM PDT 24
Peak memory 205592 kb
Host smart-6b57ece0-8e20-4439-9984-766089b99f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373879275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2373879275
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2680770685
Short name T557
Test name
Test status
Simulation time 594812629 ps
CPU time 2.56 seconds
Started Aug 17 06:17:53 PM PDT 24
Finished Aug 17 06:17:56 PM PDT 24
Peak memory 232832 kb
Host smart-1e8b39ff-3fb6-44c2-b1d6-05de1ec00e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680770685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2680770685
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1858053698
Short name T362
Test name
Test status
Simulation time 50377489 ps
CPU time 0.74 seconds
Started Aug 17 06:17:42 PM PDT 24
Finished Aug 17 06:17:43 PM PDT 24
Peak memory 205896 kb
Host smart-041658ef-7506-4362-b912-203021004e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858053698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1858053698
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.564925536
Short name T549
Test name
Test status
Simulation time 22539919126 ps
CPU time 102.18 seconds
Started Aug 17 06:17:42 PM PDT 24
Finished Aug 17 06:19:25 PM PDT 24
Peak memory 250444 kb
Host smart-9e4091df-47fc-4557-a85d-25ac2f5024ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564925536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.564925536
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2336937930
Short name T90
Test name
Test status
Simulation time 12277172271 ps
CPU time 48.7 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:18:39 PM PDT 24
Peak memory 254312 kb
Host smart-bcfc7e70-9f22-4ffb-91c7-74f79fd443f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336937930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2336937930
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1614424509
Short name T28
Test name
Test status
Simulation time 2225843838 ps
CPU time 47.13 seconds
Started Aug 17 06:17:52 PM PDT 24
Finished Aug 17 06:18:39 PM PDT 24
Peak memory 249088 kb
Host smart-82c455b6-5b44-4c9b-a071-286be04c9e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614424509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1614424509
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3633164699
Short name T280
Test name
Test status
Simulation time 3654282631 ps
CPU time 17.86 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:18:09 PM PDT 24
Peak memory 235000 kb
Host smart-4bdbca06-bb6c-438e-b0e5-39cbd8ecc7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633164699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3633164699
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3643421887
Short name T1018
Test name
Test status
Simulation time 2485257378 ps
CPU time 7.25 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:17:57 PM PDT 24
Peak memory 224748 kb
Host smart-02b16af5-ad6d-44cf-b341-61143c6d0965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643421887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3643421887
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3957063593
Short name T875
Test name
Test status
Simulation time 16190567934 ps
CPU time 33.21 seconds
Started Aug 17 06:17:43 PM PDT 24
Finished Aug 17 06:18:16 PM PDT 24
Peak memory 232992 kb
Host smart-f8d46b46-f4fe-45ad-acf7-83db887c9318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957063593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3957063593
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3878396392
Short name T241
Test name
Test status
Simulation time 680146074 ps
CPU time 6.32 seconds
Started Aug 17 06:17:31 PM PDT 24
Finished Aug 17 06:17:37 PM PDT 24
Peak memory 224652 kb
Host smart-f13711d1-326c-4198-ac68-fd7d8a9f086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878396392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3878396392
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3762545100
Short name T995
Test name
Test status
Simulation time 932899857 ps
CPU time 2.88 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:17:47 PM PDT 24
Peak memory 232852 kb
Host smart-2cf24abc-87ea-43cd-a87f-d63bd50db7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762545100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3762545100
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4227325411
Short name T930
Test name
Test status
Simulation time 74911907 ps
CPU time 3.16 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:17:59 PM PDT 24
Peak memory 218908 kb
Host smart-a296d915-baaf-46ba-9516-507224da8e9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4227325411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4227325411
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3823996938
Short name T723
Test name
Test status
Simulation time 5236247636 ps
CPU time 29.5 seconds
Started Aug 17 06:17:43 PM PDT 24
Finished Aug 17 06:18:12 PM PDT 24
Peak memory 216520 kb
Host smart-ecd91dab-9ca8-4d29-a066-288963a78e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823996938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3823996938
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4241230884
Short name T859
Test name
Test status
Simulation time 34312188399 ps
CPU time 15.85 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:18:00 PM PDT 24
Peak memory 216572 kb
Host smart-89a6e552-5d3c-4383-82bc-9846d14a258b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241230884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4241230884
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2902221240
Short name T312
Test name
Test status
Simulation time 506874278 ps
CPU time 1.63 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:17:45 PM PDT 24
Peak memory 216476 kb
Host smart-3d4449a6-ef49-48aa-9864-72b3692687a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902221240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2902221240
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2895936935
Short name T326
Test name
Test status
Simulation time 32812371 ps
CPU time 0.78 seconds
Started Aug 17 06:17:52 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 206116 kb
Host smart-d588200f-e293-42f4-bfbb-d3816e79b199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895936935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2895936935
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3354308751
Short name T578
Test name
Test status
Simulation time 1114355746 ps
CPU time 3.89 seconds
Started Aug 17 06:17:43 PM PDT 24
Finished Aug 17 06:17:47 PM PDT 24
Peak memory 224700 kb
Host smart-6f6beca1-ecc8-4210-895e-c0da62cbd17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354308751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3354308751
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3889735309
Short name T319
Test name
Test status
Simulation time 45410334 ps
CPU time 0.71 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:17:51 PM PDT 24
Peak memory 205512 kb
Host smart-601b2765-d8fa-4402-8c22-1413a250c658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889735309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3889735309
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1353385758
Short name T732
Test name
Test status
Simulation time 630566762 ps
CPU time 2.23 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 224672 kb
Host smart-622c8153-b223-49f1-8a6c-fb2d88968e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353385758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1353385758
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3905884954
Short name T817
Test name
Test status
Simulation time 19778202 ps
CPU time 0.79 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 206580 kb
Host smart-8f9fa962-82f9-4901-bf8b-751a935b7091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905884954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3905884954
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3126752934
Short name T926
Test name
Test status
Simulation time 110863718 ps
CPU time 0.78 seconds
Started Aug 17 06:17:48 PM PDT 24
Finished Aug 17 06:17:49 PM PDT 24
Peak memory 215868 kb
Host smart-d2531bf6-d249-40ac-9e4b-4c711dd0f389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126752934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3126752934
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3777126930
Short name T169
Test name
Test status
Simulation time 18510010003 ps
CPU time 157.68 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:20:29 PM PDT 24
Peak memory 273260 kb
Host smart-dcfb5a58-eeb5-4012-8911-aaa2d790193a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777126930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3777126930
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2665956248
Short name T1001
Test name
Test status
Simulation time 50886400287 ps
CPU time 67.5 seconds
Started Aug 17 06:17:57 PM PDT 24
Finished Aug 17 06:19:05 PM PDT 24
Peak memory 250492 kb
Host smart-e52a030a-10e3-40c9-b93e-52ad64b3826e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665956248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2665956248
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3745305066
Short name T810
Test name
Test status
Simulation time 52425306 ps
CPU time 3.34 seconds
Started Aug 17 06:17:52 PM PDT 24
Finished Aug 17 06:17:55 PM PDT 24
Peak memory 232900 kb
Host smart-f4984824-61de-4c64-96e3-caa41ee229e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745305066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3745305066
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3700474154
Short name T166
Test name
Test status
Simulation time 21905014009 ps
CPU time 133.77 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:20:04 PM PDT 24
Peak memory 252464 kb
Host smart-2255cd2b-76e3-49be-9168-88a002881309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700474154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3700474154
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.181640042
Short name T518
Test name
Test status
Simulation time 3519540383 ps
CPU time 8.12 seconds
Started Aug 17 06:19:19 PM PDT 24
Finished Aug 17 06:19:27 PM PDT 24
Peak memory 232472 kb
Host smart-cb7e9741-2ef1-4649-8913-c3204eab39da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181640042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.181640042
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2621248981
Short name T454
Test name
Test status
Simulation time 42548492569 ps
CPU time 23.72 seconds
Started Aug 17 06:17:48 PM PDT 24
Finished Aug 17 06:18:12 PM PDT 24
Peak memory 241100 kb
Host smart-03153432-a422-48d2-bfe3-1de48dd37560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621248981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2621248981
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2771895351
Short name T47
Test name
Test status
Simulation time 28927954633 ps
CPU time 19.07 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:18:15 PM PDT 24
Peak memory 232984 kb
Host smart-319ca246-7f26-48c0-b328-a72c0eceae2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771895351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2771895351
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1137621405
Short name T1019
Test name
Test status
Simulation time 14015917761 ps
CPU time 13.4 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:18:04 PM PDT 24
Peak memory 232952 kb
Host smart-b1220a72-ebc3-44b4-94ca-5d726a4bc811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137621405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1137621405
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3707742565
Short name T559
Test name
Test status
Simulation time 264521422 ps
CPU time 5 seconds
Started Aug 17 06:17:44 PM PDT 24
Finished Aug 17 06:17:49 PM PDT 24
Peak memory 220784 kb
Host smart-36c45902-14a3-4ce1-ad15-6cbaa62aae26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3707742565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3707742565
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3704968897
Short name T10
Test name
Test status
Simulation time 56263149965 ps
CPU time 122.3 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:19:52 PM PDT 24
Peak memory 248788 kb
Host smart-460b4585-660a-4ec9-85b4-191d740de6b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704968897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3704968897
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1883285996
Short name T292
Test name
Test status
Simulation time 1301622978 ps
CPU time 7.49 seconds
Started Aug 17 06:17:53 PM PDT 24
Finished Aug 17 06:18:01 PM PDT 24
Peak memory 216660 kb
Host smart-eb5e095d-b1c9-46f5-a84e-135f20a36473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883285996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1883285996
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1542135177
Short name T329
Test name
Test status
Simulation time 4145621017 ps
CPU time 3.7 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:18:00 PM PDT 24
Peak memory 216544 kb
Host smart-0e48ddd3-9f2a-4987-9299-4aa1ec919e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542135177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1542135177
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3514153088
Short name T481
Test name
Test status
Simulation time 29531306 ps
CPU time 1.14 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:17:51 PM PDT 24
Peak memory 207540 kb
Host smart-5f4ea1f8-6183-496d-9efc-7e246036e310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514153088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3514153088
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1224557143
Short name T324
Test name
Test status
Simulation time 87845440 ps
CPU time 0.82 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:17:57 PM PDT 24
Peak memory 206136 kb
Host smart-70688029-7944-445c-8201-9ab75c6a5691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224557143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1224557143
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.189892771
Short name T443
Test name
Test status
Simulation time 778263932 ps
CPU time 3.03 seconds
Started Aug 17 06:17:55 PM PDT 24
Finished Aug 17 06:17:58 PM PDT 24
Peak memory 224548 kb
Host smart-b8ba7e4f-069b-4c4c-8b3f-5084d3774ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189892771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.189892771
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2574567353
Short name T380
Test name
Test status
Simulation time 100136735 ps
CPU time 0.72 seconds
Started Aug 17 06:17:52 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 205540 kb
Host smart-abb2abae-afd5-4da9-bed3-ff470615107b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574567353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2574567353
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.110826918
Short name T467
Test name
Test status
Simulation time 2537465168 ps
CPU time 25.97 seconds
Started Aug 17 06:19:12 PM PDT 24
Finished Aug 17 06:19:39 PM PDT 24
Peak memory 223400 kb
Host smart-5444da42-eb0c-4d39-9cd1-dc0ddddc6a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110826918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.110826918
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1543512576
Short name T677
Test name
Test status
Simulation time 14817948 ps
CPU time 0.76 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 205888 kb
Host smart-5ce28521-b221-4d65-bd0f-bcab10bd83cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543512576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1543512576
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2132216086
Short name T1023
Test name
Test status
Simulation time 106789051906 ps
CPU time 355.49 seconds
Started Aug 17 06:17:54 PM PDT 24
Finished Aug 17 06:23:50 PM PDT 24
Peak memory 263276 kb
Host smart-428e7149-9a05-4201-8acd-7444c6a6ab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132216086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2132216086
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.56213257
Short name T788
Test name
Test status
Simulation time 9674050905 ps
CPU time 87.55 seconds
Started Aug 17 06:17:54 PM PDT 24
Finished Aug 17 06:19:22 PM PDT 24
Peak memory 240880 kb
Host smart-c6cbdb0b-25b7-467f-ad97-6601fde52017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56213257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.56213257
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3828651474
Short name T540
Test name
Test status
Simulation time 4878799073 ps
CPU time 95.95 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:19:23 PM PDT 24
Peak memory 256136 kb
Host smart-171b4939-d7a1-46c0-9704-d1354d056b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828651474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3828651474
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.657473877
Short name T288
Test name
Test status
Simulation time 1057183773 ps
CPU time 15.83 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:18:05 PM PDT 24
Peak memory 238468 kb
Host smart-81d2bb45-23f4-48f5-85b7-8ee0a03c8008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657473877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.657473877
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1645330406
Short name T473
Test name
Test status
Simulation time 5368859828 ps
CPU time 60.58 seconds
Started Aug 17 06:17:53 PM PDT 24
Finished Aug 17 06:18:53 PM PDT 24
Peak memory 251532 kb
Host smart-91125cb9-44f6-4330-85b6-767cba56ea9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645330406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1645330406
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.749123765
Short name T253
Test name
Test status
Simulation time 487371300 ps
CPU time 6.44 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:18:02 PM PDT 24
Peak memory 224696 kb
Host smart-b982863c-35f0-475a-84f3-9b9f68b2d7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749123765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.749123765
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2605829509
Short name T497
Test name
Test status
Simulation time 3495746167 ps
CPU time 32.72 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:18:20 PM PDT 24
Peak memory 232912 kb
Host smart-a0ef1316-c7f1-40d1-a8de-90448813cfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605829509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2605829509
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.894667853
Short name T547
Test name
Test status
Simulation time 57113618144 ps
CPU time 25.71 seconds
Started Aug 17 06:17:55 PM PDT 24
Finished Aug 17 06:18:21 PM PDT 24
Peak memory 256576 kb
Host smart-46d56b3f-ea5d-48dc-84f2-b26955d167b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894667853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.894667853
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2213137566
Short name T201
Test name
Test status
Simulation time 5347566472 ps
CPU time 18.38 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:18:09 PM PDT 24
Peak memory 232956 kb
Host smart-e4af8e78-798b-4645-8ad3-528f039ecdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213137566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2213137566
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1093102931
Short name T437
Test name
Test status
Simulation time 1172291862 ps
CPU time 5.78 seconds
Started Aug 17 06:17:57 PM PDT 24
Finished Aug 17 06:18:03 PM PDT 24
Peak memory 218840 kb
Host smart-6244cf65-ab04-46b9-add5-622d462973c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1093102931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1093102931
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2672158606
Short name T962
Test name
Test status
Simulation time 144971246 ps
CPU time 0.94 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 206592 kb
Host smart-62ace9d6-e10f-4f96-acb0-50a72065ac93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672158606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2672158606
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1712101930
Short name T689
Test name
Test status
Simulation time 11290116419 ps
CPU time 12.23 seconds
Started Aug 17 06:17:54 PM PDT 24
Finished Aug 17 06:18:07 PM PDT 24
Peak memory 216552 kb
Host smart-b299c696-3626-4ac3-9d87-d35a96824705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712101930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1712101930
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2995470369
Short name T378
Test name
Test status
Simulation time 614156188 ps
CPU time 1.25 seconds
Started Aug 17 06:17:55 PM PDT 24
Finished Aug 17 06:17:56 PM PDT 24
Peak memory 208048 kb
Host smart-d059db3f-cbbb-4957-a350-715e4f2b683c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995470369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2995470369
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.490126192
Short name T580
Test name
Test status
Simulation time 236678146 ps
CPU time 2.01 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 216424 kb
Host smart-bf0bba92-df5d-4d0e-956a-290860c8c33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490126192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.490126192
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3070446886
Short name T619
Test name
Test status
Simulation time 98509920 ps
CPU time 0.79 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:17:51 PM PDT 24
Peak memory 206092 kb
Host smart-6e5445da-0fa5-4b82-8c0c-f2f32d65faf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070446886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3070446886
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2660612944
Short name T860
Test name
Test status
Simulation time 3984493472 ps
CPU time 13.24 seconds
Started Aug 17 06:17:54 PM PDT 24
Finished Aug 17 06:18:07 PM PDT 24
Peak memory 232948 kb
Host smart-92bab10c-5c6d-4c3f-8878-429fd5984cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660612944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2660612944
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2723108511
Short name T671
Test name
Test status
Simulation time 27780240 ps
CPU time 0.72 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 204872 kb
Host smart-1ff216d3-7c16-41cb-b68d-f1e4c9968f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723108511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2723108511
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.635975374
Short name T700
Test name
Test status
Simulation time 138063752 ps
CPU time 2.91 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:17:53 PM PDT 24
Peak memory 232848 kb
Host smart-e2e494f2-f43e-47ac-a3ae-8977c6f899a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635975374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.635975374
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.76978582
Short name T333
Test name
Test status
Simulation time 26340716 ps
CPU time 0.75 seconds
Started Aug 17 06:17:58 PM PDT 24
Finished Aug 17 06:17:59 PM PDT 24
Peak memory 205504 kb
Host smart-cc19c034-3bed-4040-b215-9a6baf1d5d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76978582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.76978582
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3673027389
Short name T133
Test name
Test status
Simulation time 524450988117 ps
CPU time 249.1 seconds
Started Aug 17 06:19:12 PM PDT 24
Finished Aug 17 06:23:22 PM PDT 24
Peak memory 251472 kb
Host smart-86df3164-1eea-4ebc-8291-9516b7305b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673027389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3673027389
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.88838084
Short name T399
Test name
Test status
Simulation time 6867962711 ps
CPU time 18.24 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:18:08 PM PDT 24
Peak memory 217880 kb
Host smart-1cdb8281-d13e-4825-9603-63f20511403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88838084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.88838084
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.734270832
Short name T622
Test name
Test status
Simulation time 13960126270 ps
CPU time 50.01 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 251396 kb
Host smart-dee80b9a-61ee-4b04-aa4c-cf4b2e848005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734270832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.734270832
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3474776140
Short name T999
Test name
Test status
Simulation time 53794002 ps
CPU time 3.04 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 232864 kb
Host smart-a13fed66-64b6-4f0e-a808-999c566b2b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474776140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3474776140
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3861717167
Short name T1
Test name
Test status
Simulation time 827130472 ps
CPU time 19.67 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 249024 kb
Host smart-83306262-26a3-4b5f-90d4-1c5539e6709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861717167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3861717167
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.593191047
Short name T482
Test name
Test status
Simulation time 217952572 ps
CPU time 3.7 seconds
Started Aug 17 06:18:00 PM PDT 24
Finished Aug 17 06:18:04 PM PDT 24
Peak memory 232876 kb
Host smart-2691cea3-8ee9-4872-8493-b7b1ad037625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593191047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.593191047
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2549203202
Short name T393
Test name
Test status
Simulation time 658169043 ps
CPU time 3.42 seconds
Started Aug 17 06:17:55 PM PDT 24
Finished Aug 17 06:17:59 PM PDT 24
Peak memory 224644 kb
Host smart-9b5b42ae-2301-4392-811d-0c2f5f3e8bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549203202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2549203202
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.793445703
Short name T949
Test name
Test status
Simulation time 1461177394 ps
CPU time 11.2 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:18:02 PM PDT 24
Peak memory 219472 kb
Host smart-0c160d91-b48c-4c1b-9130-fd3750c5e72f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=793445703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.793445703
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1019423447
Short name T153
Test name
Test status
Simulation time 201609476 ps
CPU time 1.1 seconds
Started Aug 17 06:17:55 PM PDT 24
Finished Aug 17 06:17:56 PM PDT 24
Peak memory 207084 kb
Host smart-7d87b957-41f6-45fc-b74f-d5dff1db018a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019423447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1019423447
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2471250888
Short name T414
Test name
Test status
Simulation time 21283500530 ps
CPU time 30.27 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:18:19 PM PDT 24
Peak memory 216476 kb
Host smart-f524e3a8-f351-4828-8f2f-ad3c4d794d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471250888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2471250888
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3174523577
Short name T679
Test name
Test status
Simulation time 5295283974 ps
CPU time 6.47 seconds
Started Aug 17 06:17:54 PM PDT 24
Finished Aug 17 06:18:01 PM PDT 24
Peak memory 216488 kb
Host smart-0f19d119-00e5-4e21-85df-8d15266f249f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174523577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3174523577
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1723231081
Short name T80
Test name
Test status
Simulation time 13059125 ps
CPU time 0.76 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:18:00 PM PDT 24
Peak memory 205664 kb
Host smart-37330de8-0525-42e8-9bb6-1fc13f054e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723231081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1723231081
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.228562604
Short name T442
Test name
Test status
Simulation time 1604738841 ps
CPU time 0.97 seconds
Started Aug 17 06:17:53 PM PDT 24
Finished Aug 17 06:17:54 PM PDT 24
Peak memory 207076 kb
Host smart-8bbba71f-697d-439a-93f8-087d05e06373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228562604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.228562604
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.668507512
Short name T370
Test name
Test status
Simulation time 2387901376 ps
CPU time 12.32 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:18:03 PM PDT 24
Peak memory 232992 kb
Host smart-2d88b29d-c603-4981-8eb1-6a6ce5f691d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668507512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.668507512
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1752808682
Short name T653
Test name
Test status
Simulation time 73838285 ps
CPU time 0.72 seconds
Started Aug 17 06:18:00 PM PDT 24
Finished Aug 17 06:18:00 PM PDT 24
Peak memory 204904 kb
Host smart-2fa1f285-b1ab-4221-b7bb-fc33a0437da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752808682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1752808682
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.650400250
Short name T920
Test name
Test status
Simulation time 34412586 ps
CPU time 2.63 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:17:54 PM PDT 24
Peak memory 232476 kb
Host smart-42cc61e7-1527-4ace-a4da-c3a3a4c35bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650400250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.650400250
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.891723934
Short name T608
Test name
Test status
Simulation time 31302704 ps
CPU time 0.8 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:17:46 PM PDT 24
Peak memory 206532 kb
Host smart-96c177a9-60a1-4d18-9b3a-a041a1e1dbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891723934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.891723934
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.4224425733
Short name T402
Test name
Test status
Simulation time 3774083305 ps
CPU time 66.41 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:19:02 PM PDT 24
Peak memory 265316 kb
Host smart-bba34660-65d0-4ea9-a865-96faa9728a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224425733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4224425733
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3054793438
Short name T928
Test name
Test status
Simulation time 7033186542 ps
CPU time 99.74 seconds
Started Aug 17 06:17:49 PM PDT 24
Finished Aug 17 06:19:28 PM PDT 24
Peak memory 240900 kb
Host smart-ba845c03-a57a-4936-b285-824da0182c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054793438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3054793438
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1686731772
Short name T840
Test name
Test status
Simulation time 6538123244 ps
CPU time 75.03 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:19:14 PM PDT 24
Peak memory 251620 kb
Host smart-bc5b97e2-31d8-4402-8abc-de502d4e6724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686731772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1686731772
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.194326625
Short name T829
Test name
Test status
Simulation time 182169024 ps
CPU time 3.35 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:17:59 PM PDT 24
Peak memory 232840 kb
Host smart-7e00465c-7c12-42f2-8bf8-6f21083ac623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194326625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.194326625
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1661496499
Short name T439
Test name
Test status
Simulation time 55888829 ps
CPU time 0.8 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:17:52 PM PDT 24
Peak memory 215860 kb
Host smart-22747c72-456f-4845-8c09-e543d9ae8d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661496499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1661496499
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2291200953
Short name T374
Test name
Test status
Simulation time 34513205 ps
CPU time 2.3 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:17:50 PM PDT 24
Peak memory 224688 kb
Host smart-917202c8-7236-48a7-ae1b-760bcd0f422e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291200953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2291200953
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4248564021
Short name T599
Test name
Test status
Simulation time 37552890886 ps
CPU time 35.27 seconds
Started Aug 17 06:17:45 PM PDT 24
Finished Aug 17 06:18:20 PM PDT 24
Peak memory 235532 kb
Host smart-567789e2-a330-4f81-b96e-bf7e6e971bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248564021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4248564021
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.232814300
Short name T778
Test name
Test status
Simulation time 60148528744 ps
CPU time 20.36 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:18:19 PM PDT 24
Peak memory 240700 kb
Host smart-3f08792c-11e5-4395-848c-d59dbdf781d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232814300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.232814300
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1412124415
Short name T982
Test name
Test status
Simulation time 410320462 ps
CPU time 2.42 seconds
Started Aug 17 06:17:48 PM PDT 24
Finished Aug 17 06:17:51 PM PDT 24
Peak memory 223988 kb
Host smart-d6130831-f35b-48d8-bcf4-e1363f884ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412124415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1412124415
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2710809606
Short name T672
Test name
Test status
Simulation time 1732619977 ps
CPU time 16.23 seconds
Started Aug 17 06:18:06 PM PDT 24
Finished Aug 17 06:18:22 PM PDT 24
Peak memory 220284 kb
Host smart-3ecf9fe3-5b92-4d1f-b19f-e1a98209f578
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2710809606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2710809606
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.210743119
Short name T449
Test name
Test status
Simulation time 106665086 ps
CPU time 1.02 seconds
Started Aug 17 06:17:57 PM PDT 24
Finished Aug 17 06:18:03 PM PDT 24
Peak memory 206928 kb
Host smart-3d32b707-f6a3-4621-92e1-1b1e20daa3da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210743119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.210743119
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1614145084
Short name T932
Test name
Test status
Simulation time 11701645879 ps
CPU time 8.92 seconds
Started Aug 17 06:18:06 PM PDT 24
Finished Aug 17 06:18:15 PM PDT 24
Peak memory 216560 kb
Host smart-b54b0309-2170-4245-b22e-96fced543fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614145084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1614145084
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.843089032
Short name T500
Test name
Test status
Simulation time 7799278826 ps
CPU time 8.79 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:13 PM PDT 24
Peak memory 216528 kb
Host smart-ecd4ea34-9039-47d0-af9c-acdf7bf9e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843089032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.843089032
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3221753162
Short name T527
Test name
Test status
Simulation time 29727969 ps
CPU time 0.82 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:18:00 PM PDT 24
Peak memory 206152 kb
Host smart-4c361481-5407-4075-a67d-4ddc6a0fc3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221753162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3221753162
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2447563218
Short name T883
Test name
Test status
Simulation time 79735093 ps
CPU time 0.88 seconds
Started Aug 17 06:17:57 PM PDT 24
Finished Aug 17 06:17:58 PM PDT 24
Peak memory 206152 kb
Host smart-7c76c733-6e2c-47e4-960f-af8f00501e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447563218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2447563218
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2826055102
Short name T596
Test name
Test status
Simulation time 23545794976 ps
CPU time 17 seconds
Started Aug 17 06:17:47 PM PDT 24
Finished Aug 17 06:18:04 PM PDT 24
Peak memory 224724 kb
Host smart-ab6d81b6-4e6d-4b34-a47e-1fe13d1eaf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826055102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2826055102
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3532232751
Short name T448
Test name
Test status
Simulation time 35937671 ps
CPU time 0.74 seconds
Started Aug 17 06:18:11 PM PDT 24
Finished Aug 17 06:18:12 PM PDT 24
Peak memory 205888 kb
Host smart-9d7ab250-a46d-4fa0-b206-aff811500a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532232751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3532232751
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3918321094
Short name T888
Test name
Test status
Simulation time 429928365 ps
CPU time 5.07 seconds
Started Aug 17 06:17:57 PM PDT 24
Finished Aug 17 06:18:02 PM PDT 24
Peak memory 224648 kb
Host smart-9299b796-b14c-447f-b61a-d38ce758aebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918321094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3918321094
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3035178769
Short name T925
Test name
Test status
Simulation time 116540026 ps
CPU time 0.77 seconds
Started Aug 17 06:18:07 PM PDT 24
Finished Aug 17 06:18:08 PM PDT 24
Peak memory 206936 kb
Host smart-43f748b3-0737-4f1b-bf30-868bf4a4e09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035178769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3035178769
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1248828929
Short name T686
Test name
Test status
Simulation time 1703492333 ps
CPU time 19.67 seconds
Started Aug 17 06:17:58 PM PDT 24
Finished Aug 17 06:18:17 PM PDT 24
Peak memory 255100 kb
Host smart-42c14824-c9ad-4956-b4e7-bc5a389222b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248828929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1248828929
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1958989265
Short name T262
Test name
Test status
Simulation time 6723007606 ps
CPU time 87.07 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:19:26 PM PDT 24
Peak memory 263732 kb
Host smart-dca42daa-8ec8-4dd0-9c7e-5a2012dd64b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958989265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1958989265
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2076616323
Short name T258
Test name
Test status
Simulation time 43542967696 ps
CPU time 429.84 seconds
Started Aug 17 06:17:48 PM PDT 24
Finished Aug 17 06:24:58 PM PDT 24
Peak memory 257200 kb
Host smart-db00825a-9067-4a43-b6e1-8844cd5fa1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076616323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2076616323
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.68737455
Short name T286
Test name
Test status
Simulation time 13375657090 ps
CPU time 15.35 seconds
Started Aug 17 06:17:55 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 224764 kb
Host smart-affe2141-9f43-408a-b705-3cacf7af3335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68737455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.68737455
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.261900307
Short name T985
Test name
Test status
Simulation time 3368922925 ps
CPU time 15.74 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 232892 kb
Host smart-9a942a56-5022-4091-8a3c-5d4477828c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261900307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.261900307
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1547647999
Short name T844
Test name
Test status
Simulation time 4568495643 ps
CPU time 9.83 seconds
Started Aug 17 06:17:52 PM PDT 24
Finished Aug 17 06:18:02 PM PDT 24
Peak memory 224780 kb
Host smart-d490c62e-4469-47d9-a3cb-defc7820a27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547647999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1547647999
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.424586860
Short name T993
Test name
Test status
Simulation time 40253462785 ps
CPU time 63.49 seconds
Started Aug 17 06:17:58 PM PDT 24
Finished Aug 17 06:19:01 PM PDT 24
Peak memory 232888 kb
Host smart-14c56ea3-a0d8-4307-874c-6fc599896c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424586860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.424586860
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.37215941
Short name T211
Test name
Test status
Simulation time 17474484618 ps
CPU time 9.28 seconds
Started Aug 17 06:17:58 PM PDT 24
Finished Aug 17 06:18:07 PM PDT 24
Peak memory 232944 kb
Host smart-6ee5b023-2977-48c6-bd0d-e1acd6a3ce81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37215941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.37215941
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1455223628
Short name T243
Test name
Test status
Simulation time 869288220 ps
CPU time 8.87 seconds
Started Aug 17 06:18:08 PM PDT 24
Finished Aug 17 06:18:17 PM PDT 24
Peak memory 240580 kb
Host smart-58bc645c-7062-4de2-88af-4798681c1cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455223628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1455223628
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3105701809
Short name T769
Test name
Test status
Simulation time 8845984654 ps
CPU time 13.53 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:18:05 PM PDT 24
Peak memory 222228 kb
Host smart-561e578c-8dd4-496c-8517-85a861e78512
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3105701809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3105701809
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2342481244
Short name T17
Test name
Test status
Simulation time 9337053176 ps
CPU time 75.67 seconds
Started Aug 17 06:18:00 PM PDT 24
Finished Aug 17 06:19:16 PM PDT 24
Peak memory 238480 kb
Host smart-4898d5e5-130f-47dc-9b11-3f2a2a666ef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342481244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2342481244
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1704901391
Short name T436
Test name
Test status
Simulation time 989376813 ps
CPU time 8.88 seconds
Started Aug 17 06:18:09 PM PDT 24
Finished Aug 17 06:18:18 PM PDT 24
Peak memory 219716 kb
Host smart-e682f640-7a16-48b2-96c8-026fedf7b892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704901391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1704901391
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3252606180
Short name T673
Test name
Test status
Simulation time 381034639 ps
CPU time 11.61 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:15 PM PDT 24
Peak memory 216416 kb
Host smart-7eaca8c1-dd4f-452c-b99d-8d5d3af2d80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252606180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3252606180
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.523643944
Short name T614
Test name
Test status
Simulation time 179144088 ps
CPU time 0.85 seconds
Started Aug 17 06:17:50 PM PDT 24
Finished Aug 17 06:17:51 PM PDT 24
Peak memory 206160 kb
Host smart-a5a352fc-ea64-4a1d-b377-469967e15405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523643944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.523643944
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.742816768
Short name T231
Test name
Test status
Simulation time 465340047 ps
CPU time 5.42 seconds
Started Aug 17 06:17:51 PM PDT 24
Finished Aug 17 06:17:57 PM PDT 24
Peak memory 224652 kb
Host smart-3c36d8ff-6daf-4b45-bf32-ac635253773b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742816768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.742816768
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3325258914
Short name T974
Test name
Test status
Simulation time 40761518 ps
CPU time 0.81 seconds
Started Aug 17 06:18:11 PM PDT 24
Finished Aug 17 06:18:12 PM PDT 24
Peak memory 205516 kb
Host smart-b798fedb-d292-4394-9346-19c14c92f104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325258914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3325258914
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3253568015
Short name T681
Test name
Test status
Simulation time 1222364423 ps
CPU time 5.23 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:18:02 PM PDT 24
Peak memory 224648 kb
Host smart-493327f4-505d-4e71-8fe7-4288874eef52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253568015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3253568015
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3944848302
Short name T600
Test name
Test status
Simulation time 37430034 ps
CPU time 0.78 seconds
Started Aug 17 06:17:58 PM PDT 24
Finished Aug 17 06:17:59 PM PDT 24
Peak memory 206956 kb
Host smart-f0fa9238-6562-4a8e-a566-133db2fb6cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944848302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3944848302
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.599744706
Short name T776
Test name
Test status
Simulation time 966149813 ps
CPU time 7.11 seconds
Started Aug 17 06:17:55 PM PDT 24
Finished Aug 17 06:18:02 PM PDT 24
Peak memory 235908 kb
Host smart-3972dc31-57ed-48bb-b039-15e782051fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599744706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.599744706
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1025659426
Short name T808
Test name
Test status
Simulation time 27381786718 ps
CPU time 254.54 seconds
Started Aug 17 06:18:10 PM PDT 24
Finished Aug 17 06:22:25 PM PDT 24
Peak memory 250700 kb
Host smart-7efd0e4e-c6c9-4c12-ace7-39c5ca87946b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025659426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1025659426
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1886374740
Short name T464
Test name
Test status
Simulation time 4299617328 ps
CPU time 47.13 seconds
Started Aug 17 06:18:03 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 235356 kb
Host smart-c70b1e4f-d793-4b83-98c1-3d76849dcf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886374740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1886374740
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2921917948
Short name T602
Test name
Test status
Simulation time 946167719 ps
CPU time 9.86 seconds
Started Aug 17 06:18:07 PM PDT 24
Finished Aug 17 06:18:17 PM PDT 24
Peak memory 235116 kb
Host smart-638d5141-512e-47d7-ae36-98484b0cb31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921917948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2921917948
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1305349289
Short name T339
Test name
Test status
Simulation time 4381916172 ps
CPU time 11.96 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:16 PM PDT 24
Peak memory 224748 kb
Host smart-ac1433b0-c69c-43e7-b099-da0c93c57a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305349289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1305349289
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2298778455
Short name T566
Test name
Test status
Simulation time 107861448 ps
CPU time 2.84 seconds
Started Aug 17 06:18:09 PM PDT 24
Finished Aug 17 06:18:12 PM PDT 24
Peak memory 227256 kb
Host smart-57cb71ef-2b4e-4a2a-bb6c-96ae663339e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298778455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2298778455
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.489376311
Short name T552
Test name
Test status
Simulation time 56289350 ps
CPU time 2.01 seconds
Started Aug 17 06:18:12 PM PDT 24
Finished Aug 17 06:18:14 PM PDT 24
Peak memory 223836 kb
Host smart-ce1dbfe1-e6cd-4833-b74e-ef78e37140ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489376311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.489376311
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3781068554
Short name T605
Test name
Test status
Simulation time 951614950 ps
CPU time 3.66 seconds
Started Aug 17 06:18:01 PM PDT 24
Finished Aug 17 06:18:05 PM PDT 24
Peak memory 232876 kb
Host smart-31e8c401-3135-4c3c-9bad-d51cf9bafde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781068554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3781068554
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1653334691
Short name T900
Test name
Test status
Simulation time 19983958778 ps
CPU time 15.87 seconds
Started Aug 17 06:18:00 PM PDT 24
Finished Aug 17 06:18:15 PM PDT 24
Peak memory 232900 kb
Host smart-29a6bff5-c94b-4412-af07-0f8f117406cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653334691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1653334691
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1240826678
Short name T839
Test name
Test status
Simulation time 628241812 ps
CPU time 7.93 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:12 PM PDT 24
Peak memory 219416 kb
Host smart-5712fa2f-fcb3-4e88-a7dc-ad692e599917
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1240826678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1240826678
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2708718399
Short name T988
Test name
Test status
Simulation time 52661389436 ps
CPU time 416.36 seconds
Started Aug 17 06:18:14 PM PDT 24
Finished Aug 17 06:25:10 PM PDT 24
Peak memory 273992 kb
Host smart-f601ca71-cdd8-4103-a9b2-d527a030f524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708718399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2708718399
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2457124739
Short name T302
Test name
Test status
Simulation time 4282969045 ps
CPU time 27.03 seconds
Started Aug 17 06:17:58 PM PDT 24
Finished Aug 17 06:18:25 PM PDT 24
Peak memory 216604 kb
Host smart-fd1491f9-0f42-41a1-a397-0f523840bf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457124739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2457124739
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3899435336
Short name T499
Test name
Test status
Simulation time 3444779433 ps
CPU time 8.67 seconds
Started Aug 17 06:18:03 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 216472 kb
Host smart-37363d11-5d91-443f-8a91-2ea7d075ded8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899435336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3899435336
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1486391528
Short name T446
Test name
Test status
Simulation time 71905795 ps
CPU time 1.71 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:17:58 PM PDT 24
Peak memory 216492 kb
Host smart-44cc9820-eafa-4e75-8111-b73047ac6c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486391528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1486391528
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3124776736
Short name T501
Test name
Test status
Simulation time 90940090 ps
CPU time 0.94 seconds
Started Aug 17 06:18:02 PM PDT 24
Finished Aug 17 06:18:03 PM PDT 24
Peak memory 206064 kb
Host smart-11bf4993-776c-460e-92e3-fa69291ceacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124776736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3124776736
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4143196678
Short name T542
Test name
Test status
Simulation time 12585058328 ps
CPU time 13.1 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:18:09 PM PDT 24
Peak memory 240248 kb
Host smart-52423e40-0b56-4276-b933-99f80eea0d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143196678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4143196678
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2182554911
Short name T308
Test name
Test status
Simulation time 53719944 ps
CPU time 0.71 seconds
Started Aug 17 06:18:10 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 204956 kb
Host smart-2b08f198-83fa-4aab-9459-4f1e52399327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182554911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2182554911
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.4059547704
Short name T994
Test name
Test status
Simulation time 123768287 ps
CPU time 3.86 seconds
Started Aug 17 06:18:09 PM PDT 24
Finished Aug 17 06:18:13 PM PDT 24
Peak memory 232860 kb
Host smart-72804bd2-7ab5-409e-8695-f4e41f088ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059547704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4059547704
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1336059603
Short name T648
Test name
Test status
Simulation time 81236332 ps
CPU time 0.8 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:18:00 PM PDT 24
Peak memory 206588 kb
Host smart-9a2923ae-6750-448c-909b-2a4df7cdef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336059603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1336059603
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1262650038
Short name T884
Test name
Test status
Simulation time 5088670464 ps
CPU time 64.93 seconds
Started Aug 17 06:18:11 PM PDT 24
Finished Aug 17 06:19:16 PM PDT 24
Peak memory 249348 kb
Host smart-5a0f1f50-dc18-46d7-b701-dbb6a45514ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262650038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1262650038
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1079998156
Short name T906
Test name
Test status
Simulation time 7074923086 ps
CPU time 66.02 seconds
Started Aug 17 06:18:03 PM PDT 24
Finished Aug 17 06:19:09 PM PDT 24
Peak memory 237696 kb
Host smart-df4a99db-5690-45f4-868b-2c3032f489c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079998156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1079998156
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1378198439
Short name T267
Test name
Test status
Simulation time 83146063724 ps
CPU time 139.55 seconds
Started Aug 17 06:18:05 PM PDT 24
Finished Aug 17 06:20:25 PM PDT 24
Peak memory 266328 kb
Host smart-4a8405f4-96c8-45ae-a542-12aa0a71025c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378198439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1378198439
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2022214744
Short name T455
Test name
Test status
Simulation time 212060963 ps
CPU time 2.86 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:07 PM PDT 24
Peak memory 224656 kb
Host smart-4e97b4eb-1f90-4281-9283-c6df657cc22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022214744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2022214744
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2536994258
Short name T38
Test name
Test status
Simulation time 32598316100 ps
CPU time 114.55 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:19:54 PM PDT 24
Peak memory 267836 kb
Host smart-2eb3778b-19d4-4777-b036-513882db6dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536994258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2536994258
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3419500729
Short name T858
Test name
Test status
Simulation time 5870492001 ps
CPU time 24.62 seconds
Started Aug 17 06:17:56 PM PDT 24
Finished Aug 17 06:18:21 PM PDT 24
Peak memory 232964 kb
Host smart-fce19df9-00fe-4da3-aab2-9cd8838e9f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419500729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3419500729
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1939886644
Short name T833
Test name
Test status
Simulation time 1212662359 ps
CPU time 16.47 seconds
Started Aug 17 06:18:03 PM PDT 24
Finished Aug 17 06:18:20 PM PDT 24
Peak memory 219060 kb
Host smart-5a4d1172-4b31-4dee-ae8d-64a322ef469b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939886644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1939886644
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2450773433
Short name T252
Test name
Test status
Simulation time 25680487343 ps
CPU time 11.62 seconds
Started Aug 17 06:17:55 PM PDT 24
Finished Aug 17 06:18:07 PM PDT 24
Peak memory 232908 kb
Host smart-ad51b652-ab33-418a-8d52-f0eb0fed7f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450773433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2450773433
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2064035907
Short name T1012
Test name
Test status
Simulation time 74761254 ps
CPU time 2.26 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:18:01 PM PDT 24
Peak memory 224176 kb
Host smart-fa8f3f6b-d335-4382-ba0d-765e65ba7139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064035907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2064035907
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1663208799
Short name T409
Test name
Test status
Simulation time 422916123 ps
CPU time 3.87 seconds
Started Aug 17 06:18:14 PM PDT 24
Finished Aug 17 06:18:18 PM PDT 24
Peak memory 222204 kb
Host smart-1834236f-f631-4b54-aad4-63663b3f2eec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1663208799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1663208799
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3635360976
Short name T265
Test name
Test status
Simulation time 8815306977 ps
CPU time 106.62 seconds
Started Aug 17 06:17:58 PM PDT 24
Finished Aug 17 06:19:45 PM PDT 24
Peak memory 266992 kb
Host smart-7df84da0-462f-47d5-ab98-d68bfda6c821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635360976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3635360976
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2987404232
Short name T579
Test name
Test status
Simulation time 21173461276 ps
CPU time 16.75 seconds
Started Aug 17 06:18:07 PM PDT 24
Finished Aug 17 06:18:24 PM PDT 24
Peak memory 216588 kb
Host smart-c833c72a-2ca5-400b-baa3-de9361f66e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987404232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2987404232
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3886858586
Short name T822
Test name
Test status
Simulation time 3255989840 ps
CPU time 8.12 seconds
Started Aug 17 06:18:13 PM PDT 24
Finished Aug 17 06:18:21 PM PDT 24
Peak memory 216568 kb
Host smart-631777d2-b1e8-49ad-92cb-7bc257075a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886858586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3886858586
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3597819801
Short name T523
Test name
Test status
Simulation time 210409169 ps
CPU time 2.13 seconds
Started Aug 17 06:18:11 PM PDT 24
Finished Aug 17 06:18:14 PM PDT 24
Peak memory 216456 kb
Host smart-cf1eb01e-589e-4c1a-a500-972fb9883fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597819801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3597819801
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3986667163
Short name T868
Test name
Test status
Simulation time 141986060 ps
CPU time 1.15 seconds
Started Aug 17 06:17:58 PM PDT 24
Finished Aug 17 06:17:59 PM PDT 24
Peak memory 207128 kb
Host smart-c286525b-1bfd-4f5e-a59f-4dd44e908a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986667163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3986667163
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4052482578
Short name T495
Test name
Test status
Simulation time 23247827425 ps
CPU time 38.67 seconds
Started Aug 17 06:18:02 PM PDT 24
Finished Aug 17 06:18:42 PM PDT 24
Peak memory 249692 kb
Host smart-c8422858-7e17-41d2-8fb6-ada8713b1a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052482578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4052482578
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.670668177
Short name T472
Test name
Test status
Simulation time 13402757 ps
CPU time 0.72 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:05 PM PDT 24
Peak memory 205800 kb
Host smart-3fa969c7-cc78-4578-aa28-a9790d3bef2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670668177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.670668177
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.200159657
Short name T691
Test name
Test status
Simulation time 4831164018 ps
CPU time 8.67 seconds
Started Aug 17 06:18:10 PM PDT 24
Finished Aug 17 06:18:19 PM PDT 24
Peak memory 232964 kb
Host smart-4248275a-a548-4ca1-b0aa-ca53ec0a85ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200159657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.200159657
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.854418293
Short name T980
Test name
Test status
Simulation time 31110345 ps
CPU time 0.78 seconds
Started Aug 17 06:18:00 PM PDT 24
Finished Aug 17 06:18:01 PM PDT 24
Peak memory 206976 kb
Host smart-685988a5-eff2-43d0-b5af-f233e268e473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854418293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.854418293
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.361818235
Short name T4
Test name
Test status
Simulation time 152702688564 ps
CPU time 294.29 seconds
Started Aug 17 06:18:05 PM PDT 24
Finished Aug 17 06:22:59 PM PDT 24
Peak memory 257552 kb
Host smart-7e0ed787-b73a-4b83-aca7-f3d6b6f98a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361818235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.361818235
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.315907998
Short name T564
Test name
Test status
Simulation time 5550752044 ps
CPU time 81.27 seconds
Started Aug 17 06:18:15 PM PDT 24
Finished Aug 17 06:19:36 PM PDT 24
Peak memory 252544 kb
Host smart-0d18d33f-7b40-4e75-b48c-3f48a42f9805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315907998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.315907998
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3206431697
Short name T568
Test name
Test status
Simulation time 8147181492 ps
CPU time 128.17 seconds
Started Aug 17 06:18:17 PM PDT 24
Finished Aug 17 06:20:25 PM PDT 24
Peak memory 257620 kb
Host smart-98fc8f12-2435-47d8-a282-963ba0f3dc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206431697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3206431697
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3431091803
Short name T784
Test name
Test status
Simulation time 825314836 ps
CPU time 7.29 seconds
Started Aug 17 06:18:14 PM PDT 24
Finished Aug 17 06:18:21 PM PDT 24
Peak memory 249272 kb
Host smart-942979e5-4ae9-4d00-863f-be2f48792f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431091803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3431091803
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.918555926
Short name T260
Test name
Test status
Simulation time 2522678664 ps
CPU time 25.78 seconds
Started Aug 17 06:18:15 PM PDT 24
Finished Aug 17 06:18:41 PM PDT 24
Peak memory 224788 kb
Host smart-65a63f9d-cd8a-4dd9-b26e-376fa0c7fd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918555926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.918555926
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3017095309
Short name T818
Test name
Test status
Simulation time 3163931901 ps
CPU time 5.22 seconds
Started Aug 17 06:18:02 PM PDT 24
Finished Aug 17 06:18:09 PM PDT 24
Peak memory 224692 kb
Host smart-408749ba-fc3c-4319-a337-971b7ebc6d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017095309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3017095309
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1346132524
Short name T226
Test name
Test status
Simulation time 1016642819 ps
CPU time 9.71 seconds
Started Aug 17 06:18:10 PM PDT 24
Finished Aug 17 06:18:20 PM PDT 24
Peak memory 224576 kb
Host smart-c50ee394-87ab-4799-9f0c-2d779a34c830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346132524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1346132524
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2925260916
Short name T237
Test name
Test status
Simulation time 8968764353 ps
CPU time 27.72 seconds
Started Aug 17 06:18:11 PM PDT 24
Finished Aug 17 06:18:39 PM PDT 24
Peak memory 232920 kb
Host smart-e758846f-065c-4cf1-9b81-e07f6375d2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925260916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2925260916
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2895207947
Short name T174
Test name
Test status
Simulation time 10562393478 ps
CPU time 28.01 seconds
Started Aug 17 06:18:06 PM PDT 24
Finished Aug 17 06:18:34 PM PDT 24
Peak memory 256704 kb
Host smart-0f3641fa-7ffc-4801-a1aa-bdaf85e69fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895207947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2895207947
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3747100189
Short name T360
Test name
Test status
Simulation time 274232012 ps
CPU time 5.17 seconds
Started Aug 17 06:18:06 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 218800 kb
Host smart-5cc94da7-c3a3-40e8-b44e-70851e0dd6a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3747100189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3747100189
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1895204430
Short name T970
Test name
Test status
Simulation time 17171994704 ps
CPU time 119.69 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:19:59 PM PDT 24
Peak memory 266692 kb
Host smart-987b53a9-9379-4157-9261-1d907c30b518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895204430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1895204430
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1792243123
Short name T948
Test name
Test status
Simulation time 5880234876 ps
CPU time 5.53 seconds
Started Aug 17 06:18:16 PM PDT 24
Finished Aug 17 06:18:22 PM PDT 24
Peak memory 216512 kb
Host smart-af778342-ee4b-479a-9d00-c58478766f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792243123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1792243123
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1484472963
Short name T637
Test name
Test status
Simulation time 5219835461 ps
CPU time 11.33 seconds
Started Aug 17 06:18:09 PM PDT 24
Finished Aug 17 06:18:20 PM PDT 24
Peak memory 216616 kb
Host smart-5a1a0a28-35b6-41b7-bbdc-043ddedd75eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484472963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1484472963
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.136576500
Short name T303
Test name
Test status
Simulation time 571978771 ps
CPU time 2.03 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:18:01 PM PDT 24
Peak memory 216536 kb
Host smart-4182a460-fe6e-49a7-8e94-b73bdb54a269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136576500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.136576500
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.942981927
Short name T987
Test name
Test status
Simulation time 29472868 ps
CPU time 0.85 seconds
Started Aug 17 06:18:11 PM PDT 24
Finished Aug 17 06:18:12 PM PDT 24
Peak memory 206140 kb
Host smart-e84c57a1-5f9b-4c59-81b1-866c82fd9d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942981927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.942981927
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2488193277
Short name T2
Test name
Test status
Simulation time 3450157529 ps
CPU time 14.37 seconds
Started Aug 17 06:18:11 PM PDT 24
Finished Aug 17 06:18:26 PM PDT 24
Peak memory 232892 kb
Host smart-05950238-fa71-4e84-a238-f6e965c0c307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488193277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2488193277
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3145815016
Short name T861
Test name
Test status
Simulation time 130125494 ps
CPU time 0.71 seconds
Started Aug 17 06:18:02 PM PDT 24
Finished Aug 17 06:18:02 PM PDT 24
Peak memory 205528 kb
Host smart-c2607dae-9f49-44b2-b60e-d124b4e79a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145815016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3145815016
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3063617518
Short name T224
Test name
Test status
Simulation time 61288848 ps
CPU time 2.17 seconds
Started Aug 17 06:18:09 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 224688 kb
Host smart-d4d5fd75-3143-473c-99d1-62b73458ae74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063617518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3063617518
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2419898255
Short name T774
Test name
Test status
Simulation time 263995841 ps
CPU time 0.81 seconds
Started Aug 17 06:18:00 PM PDT 24
Finished Aug 17 06:18:01 PM PDT 24
Peak memory 206532 kb
Host smart-06fb77f1-611f-4c94-bc20-6d8c52de6110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419898255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2419898255
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.345717816
Short name T885
Test name
Test status
Simulation time 2567264701 ps
CPU time 55.12 seconds
Started Aug 17 06:18:09 PM PDT 24
Finished Aug 17 06:19:05 PM PDT 24
Peak memory 255912 kb
Host smart-ab452658-ced9-4d1e-a943-02414b6d5cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345717816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.345717816
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2779507283
Short name T837
Test name
Test status
Simulation time 50811870353 ps
CPU time 32.8 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:39 PM PDT 24
Peak memory 217696 kb
Host smart-5b2168b7-ff82-4932-af11-d4b4c85f91b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779507283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2779507283
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3344187778
Short name T189
Test name
Test status
Simulation time 150909491269 ps
CPU time 225.41 seconds
Started Aug 17 06:18:16 PM PDT 24
Finished Aug 17 06:22:01 PM PDT 24
Peak memory 255564 kb
Host smart-f2a0fa20-a081-4975-8c33-00dcc270bd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344187778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3344187778
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2647700496
Short name T67
Test name
Test status
Simulation time 254340117 ps
CPU time 3.28 seconds
Started Aug 17 06:18:05 PM PDT 24
Finished Aug 17 06:18:09 PM PDT 24
Peak memory 224664 kb
Host smart-7ec6565f-da12-4a71-bb41-42d3d6c0bb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647700496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2647700496
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2612261021
Short name T165
Test name
Test status
Simulation time 2022754056 ps
CPU time 14.46 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:18 PM PDT 24
Peak memory 233848 kb
Host smart-11d1376c-c99c-40c3-92ee-2b1f24544640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612261021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2612261021
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1311918855
Short name T511
Test name
Test status
Simulation time 4464955835 ps
CPU time 10.22 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:14 PM PDT 24
Peak memory 224732 kb
Host smart-e461507c-3724-411e-9577-3e593adac129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311918855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1311918855
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2032955940
Short name T684
Test name
Test status
Simulation time 17205003822 ps
CPU time 53.28 seconds
Started Aug 17 06:18:01 PM PDT 24
Finished Aug 17 06:18:55 PM PDT 24
Peak memory 237352 kb
Host smart-8bc04129-f79e-4438-9a23-235f589f4d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032955940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2032955940
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.226271843
Short name T1002
Test name
Test status
Simulation time 11851898872 ps
CPU time 14.38 seconds
Started Aug 17 06:18:16 PM PDT 24
Finished Aug 17 06:18:30 PM PDT 24
Peak memory 232944 kb
Host smart-04674603-5b73-41cf-839e-c5965cfa2dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226271843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.226271843
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4012151350
Short name T950
Test name
Test status
Simulation time 320726181 ps
CPU time 5.63 seconds
Started Aug 17 06:18:11 PM PDT 24
Finished Aug 17 06:18:17 PM PDT 24
Peak memory 224612 kb
Host smart-da912979-167c-45cb-b36d-7c5f0deaa3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012151350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4012151350
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1990925608
Short name T488
Test name
Test status
Simulation time 1669674401 ps
CPU time 8.47 seconds
Started Aug 17 06:18:03 PM PDT 24
Finished Aug 17 06:18:12 PM PDT 24
Peak memory 222076 kb
Host smart-7c184f87-e910-4998-8c1d-ac6556a0620a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1990925608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1990925608
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1903492095
Short name T662
Test name
Test status
Simulation time 61170295 ps
CPU time 1.02 seconds
Started Aug 17 06:18:02 PM PDT 24
Finished Aug 17 06:18:04 PM PDT 24
Peak memory 206892 kb
Host smart-a7c38641-7e56-4b80-b847-2d14d597dd89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903492095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1903492095
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1255074807
Short name T12
Test name
Test status
Simulation time 1010130590 ps
CPU time 11.75 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:16 PM PDT 24
Peak memory 216688 kb
Host smart-dee796cb-c459-49ea-99b7-41df60ccba88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255074807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1255074807
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4220839897
Short name T408
Test name
Test status
Simulation time 40919352048 ps
CPU time 12.45 seconds
Started Aug 17 06:18:11 PM PDT 24
Finished Aug 17 06:18:23 PM PDT 24
Peak memory 216520 kb
Host smart-b0038670-c62a-422e-84f6-b2253814885c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220839897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4220839897
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2857918196
Short name T855
Test name
Test status
Simulation time 10960425 ps
CPU time 0.75 seconds
Started Aug 17 06:18:15 PM PDT 24
Finished Aug 17 06:18:16 PM PDT 24
Peak memory 205648 kb
Host smart-1f35d343-8f91-4413-806a-4ce60df64d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857918196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2857918196
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2852761966
Short name T520
Test name
Test status
Simulation time 11310392 ps
CPU time 0.72 seconds
Started Aug 17 06:18:02 PM PDT 24
Finished Aug 17 06:18:04 PM PDT 24
Peak memory 205636 kb
Host smart-a1c4aedc-24fe-4e41-84bd-c2d4d0cbe80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852761966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2852761966
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.504465746
Short name T775
Test name
Test status
Simulation time 10856975611 ps
CPU time 5.7 seconds
Started Aug 17 06:18:14 PM PDT 24
Finished Aug 17 06:18:20 PM PDT 24
Peak memory 232912 kb
Host smart-02b5af7e-7ea7-493b-84f4-9583bc0f1fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504465746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.504465746
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3232207904
Short name T346
Test name
Test status
Simulation time 37166909 ps
CPU time 0.66 seconds
Started Aug 17 06:16:51 PM PDT 24
Finished Aug 17 06:16:52 PM PDT 24
Peak memory 205524 kb
Host smart-a3abd6b6-9c1e-4b82-a199-288db83a2bc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232207904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
232207904
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2603913980
Short name T815
Test name
Test status
Simulation time 1609103517 ps
CPU time 18.14 seconds
Started Aug 17 06:16:54 PM PDT 24
Finished Aug 17 06:17:12 PM PDT 24
Peak memory 224712 kb
Host smart-75cccdb2-fbc1-4c2b-9714-9c2b3fa68ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603913980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2603913980
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.400030970
Short name T463
Test name
Test status
Simulation time 21251522 ps
CPU time 0.76 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:16:58 PM PDT 24
Peak memory 206964 kb
Host smart-4aebc347-f8fd-4f95-b7c0-3d80c84f1f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400030970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.400030970
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.199688233
Short name T266
Test name
Test status
Simulation time 3859136162 ps
CPU time 66.46 seconds
Started Aug 17 06:16:53 PM PDT 24
Finished Aug 17 06:18:00 PM PDT 24
Peak memory 257540 kb
Host smart-51e0fa93-47dd-4ad9-b31a-48b4376113af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199688233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.199688233
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2704146455
Short name T617
Test name
Test status
Simulation time 7004748133 ps
CPU time 28.36 seconds
Started Aug 17 06:16:55 PM PDT 24
Finished Aug 17 06:17:24 PM PDT 24
Peak memory 234848 kb
Host smart-6752dd49-f156-4f4a-8725-404ee9f1ea05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704146455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2704146455
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2365232677
Short name T79
Test name
Test status
Simulation time 423716751 ps
CPU time 4.04 seconds
Started Aug 17 06:16:54 PM PDT 24
Finished Aug 17 06:16:58 PM PDT 24
Peak memory 232916 kb
Host smart-ce0de27e-325a-48d1-bfff-41d320a1f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365232677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2365232677
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.4217146825
Short name T772
Test name
Test status
Simulation time 10912343294 ps
CPU time 10.41 seconds
Started Aug 17 06:17:03 PM PDT 24
Finished Aug 17 06:17:14 PM PDT 24
Peak memory 224724 kb
Host smart-6a096654-aa43-4f73-bc10-12872ad96e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217146825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.4217146825
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1611067368
Short name T359
Test name
Test status
Simulation time 111730810 ps
CPU time 2.14 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:16:59 PM PDT 24
Peak memory 218920 kb
Host smart-85762c88-eb47-49a6-a23d-1949f1db5f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611067368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1611067368
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3307320479
Short name T620
Test name
Test status
Simulation time 51353473 ps
CPU time 2.06 seconds
Started Aug 17 06:17:04 PM PDT 24
Finished Aug 17 06:17:06 PM PDT 24
Peak memory 224096 kb
Host smart-d494518b-d1bc-40cc-8db5-52bc01c70698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307320479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3307320479
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3258592348
Short name T583
Test name
Test status
Simulation time 55593063 ps
CPU time 1.04 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:16:57 PM PDT 24
Peak memory 216708 kb
Host smart-0e06f31d-b6cf-4bd1-a192-c97a517bd2cb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258592348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3258592348
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3616914237
Short name T340
Test name
Test status
Simulation time 33282320 ps
CPU time 2.39 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:16:59 PM PDT 24
Peak memory 232496 kb
Host smart-ed1c3d3c-d8db-413c-8dde-89f62e0cdd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616914237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3616914237
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1528556816
Short name T705
Test name
Test status
Simulation time 15669630070 ps
CPU time 21.53 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:17:18 PM PDT 24
Peak memory 232940 kb
Host smart-8f049655-f912-4b72-9e5b-6e05bf619b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528556816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1528556816
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2092463140
Short name T438
Test name
Test status
Simulation time 161837041 ps
CPU time 3.77 seconds
Started Aug 17 06:16:52 PM PDT 24
Finished Aug 17 06:16:56 PM PDT 24
Peak memory 223208 kb
Host smart-dd426285-cf09-4f2d-890b-6d5693d6426b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2092463140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2092463140
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3068934436
Short name T72
Test name
Test status
Simulation time 266675339 ps
CPU time 0.98 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:17:03 PM PDT 24
Peak memory 235944 kb
Host smart-98087a0f-b4f3-4b21-bd73-d9d655596998
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068934436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3068934436
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3503389006
Short name T5
Test name
Test status
Simulation time 1879270946 ps
CPU time 22.25 seconds
Started Aug 17 06:16:52 PM PDT 24
Finished Aug 17 06:17:15 PM PDT 24
Peak memory 219552 kb
Host smart-3a3890da-7324-4971-b34c-9ea7df860580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503389006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3503389006
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2329739797
Short name T952
Test name
Test status
Simulation time 4977254277 ps
CPU time 7.08 seconds
Started Aug 17 06:16:53 PM PDT 24
Finished Aug 17 06:17:00 PM PDT 24
Peak memory 216588 kb
Host smart-e42d1634-e8ac-4914-9841-eb9e6840acec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329739797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2329739797
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.489968537
Short name T396
Test name
Test status
Simulation time 71486495 ps
CPU time 1.66 seconds
Started Aug 17 06:16:59 PM PDT 24
Finished Aug 17 06:17:00 PM PDT 24
Peak memory 216472 kb
Host smart-233138b9-70d9-4a0c-b7a6-9c9e9abeaef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489968537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.489968537
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3540831578
Short name T639
Test name
Test status
Simulation time 38586392 ps
CPU time 0.69 seconds
Started Aug 17 06:16:53 PM PDT 24
Finished Aug 17 06:16:54 PM PDT 24
Peak memory 205652 kb
Host smart-57553f80-c43d-4bf7-b4b8-5c1c913570d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540831578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3540831578
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.41731805
Short name T387
Test name
Test status
Simulation time 351854432 ps
CPU time 7.22 seconds
Started Aug 17 06:16:58 PM PDT 24
Finished Aug 17 06:17:06 PM PDT 24
Peak memory 236816 kb
Host smart-ddef58ab-54cd-405b-b97d-43d9f11f20b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41731805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.41731805
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2863877600
Short name T654
Test name
Test status
Simulation time 12506865 ps
CPU time 0.75 seconds
Started Aug 17 06:18:12 PM PDT 24
Finished Aug 17 06:18:12 PM PDT 24
Peak memory 205568 kb
Host smart-dadf2711-357b-4f5e-a0ea-b3ed437545ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863877600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2863877600
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.347317597
Short name T917
Test name
Test status
Simulation time 1951053966 ps
CPU time 3.83 seconds
Started Aug 17 06:18:06 PM PDT 24
Finished Aug 17 06:18:10 PM PDT 24
Peak memory 232896 kb
Host smart-6b43d17a-f321-46ac-bf3e-5ce2ce34bb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347317597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.347317597
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4278875901
Short name T477
Test name
Test status
Simulation time 29120285 ps
CPU time 0.74 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:18:00 PM PDT 24
Peak memory 206960 kb
Host smart-325ffe05-91d5-4a60-89ac-93698f7dac2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278875901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4278875901
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.768362567
Short name T516
Test name
Test status
Simulation time 48271707 ps
CPU time 0.76 seconds
Started Aug 17 06:18:15 PM PDT 24
Finished Aug 17 06:18:16 PM PDT 24
Peak memory 215932 kb
Host smart-88e5d739-6cd2-4332-a318-4fb32a3dd23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768362567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.768362567
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1179003732
Short name T194
Test name
Test status
Simulation time 65466953315 ps
CPU time 545.9 seconds
Started Aug 17 06:18:06 PM PDT 24
Finished Aug 17 06:27:12 PM PDT 24
Peak memory 253976 kb
Host smart-ee24f3cf-d503-43b6-a74a-a61866f39533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179003732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1179003732
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3101750549
Short name T623
Test name
Test status
Simulation time 45947268625 ps
CPU time 165.14 seconds
Started Aug 17 06:18:13 PM PDT 24
Finished Aug 17 06:20:58 PM PDT 24
Peak memory 249428 kb
Host smart-3d4744c0-b674-4177-87f7-11019b725e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101750549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3101750549
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3254360709
Short name T834
Test name
Test status
Simulation time 2435924085 ps
CPU time 39.62 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:44 PM PDT 24
Peak memory 224748 kb
Host smart-c2f8e371-7016-4456-a155-9ab823c642c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254360709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3254360709
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2486382273
Short name T171
Test name
Test status
Simulation time 135176239636 ps
CPU time 230.37 seconds
Started Aug 17 06:18:11 PM PDT 24
Finished Aug 17 06:22:02 PM PDT 24
Peak memory 256968 kb
Host smart-6804d638-554c-4f36-8340-c25aa89a50b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486382273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2486382273
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1844129180
Short name T1013
Test name
Test status
Simulation time 1282971015 ps
CPU time 9.97 seconds
Started Aug 17 06:18:24 PM PDT 24
Finished Aug 17 06:18:34 PM PDT 24
Peak memory 224708 kb
Host smart-cd84c56c-1148-435c-bcc8-9cb924982065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844129180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1844129180
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3652727631
Short name T798
Test name
Test status
Simulation time 5669778872 ps
CPU time 34.24 seconds
Started Aug 17 06:18:13 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 232912 kb
Host smart-d418349f-84ab-48d0-b291-d2665b3dff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652727631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3652727631
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.929247665
Short name T492
Test name
Test status
Simulation time 2499487968 ps
CPU time 7.09 seconds
Started Aug 17 06:18:27 PM PDT 24
Finished Aug 17 06:18:35 PM PDT 24
Peak memory 232852 kb
Host smart-ccb10bfe-d5ca-4ac5-b5e0-bff8be0882ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929247665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.929247665
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1266519439
Short name T722
Test name
Test status
Simulation time 2520728815 ps
CPU time 4.52 seconds
Started Aug 17 06:18:12 PM PDT 24
Finished Aug 17 06:18:16 PM PDT 24
Peak memory 224704 kb
Host smart-c2faae46-713f-48c9-afa1-1aeac676d985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266519439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1266519439
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2263992028
Short name T881
Test name
Test status
Simulation time 988869652 ps
CPU time 11.26 seconds
Started Aug 17 06:18:16 PM PDT 24
Finished Aug 17 06:18:28 PM PDT 24
Peak memory 222328 kb
Host smart-32cb6559-f937-443f-9971-11ee2ade4ac5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2263992028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2263992028
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3131916234
Short name T890
Test name
Test status
Simulation time 83164985509 ps
CPU time 709.01 seconds
Started Aug 17 06:18:37 PM PDT 24
Finished Aug 17 06:30:26 PM PDT 24
Peak memory 261824 kb
Host smart-a3c61453-e80b-456a-94f4-fb966e82231d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131916234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3131916234
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3769237351
Short name T298
Test name
Test status
Simulation time 14358012274 ps
CPU time 39.02 seconds
Started Aug 17 06:17:59 PM PDT 24
Finished Aug 17 06:18:43 PM PDT 24
Peak memory 216564 kb
Host smart-2e663a68-a19a-4f0d-8c0d-7e611fe7e716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769237351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3769237351
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1409981291
Short name T66
Test name
Test status
Simulation time 4754667287 ps
CPU time 7.67 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 216600 kb
Host smart-63f7820e-4fbd-4e03-90e7-29d012d242b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409981291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1409981291
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3333811460
Short name T577
Test name
Test status
Simulation time 43870934 ps
CPU time 2.19 seconds
Started Aug 17 06:18:06 PM PDT 24
Finished Aug 17 06:18:08 PM PDT 24
Peak memory 216484 kb
Host smart-ee54290b-433b-451c-be7e-ed0d3a97346b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333811460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3333811460
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.213890067
Short name T434
Test name
Test status
Simulation time 86759875 ps
CPU time 0.89 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:05 PM PDT 24
Peak memory 206132 kb
Host smart-e0b8c3cb-edb1-40ee-b935-d50bf078b62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213890067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.213890067
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3843609813
Short name T562
Test name
Test status
Simulation time 669950139 ps
CPU time 3.42 seconds
Started Aug 17 06:18:15 PM PDT 24
Finished Aug 17 06:18:19 PM PDT 24
Peak memory 224704 kb
Host smart-e5ff261d-54c8-40c0-8078-2b68472a3db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843609813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3843609813
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3595373992
Short name T524
Test name
Test status
Simulation time 12122570 ps
CPU time 0.76 seconds
Started Aug 17 06:18:10 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 205576 kb
Host smart-bb950693-000e-4637-8441-ad5e0c822e84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595373992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3595373992
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3219408179
Short name T946
Test name
Test status
Simulation time 979798926 ps
CPU time 3.65 seconds
Started Aug 17 06:18:12 PM PDT 24
Finished Aug 17 06:18:16 PM PDT 24
Peak memory 224656 kb
Host smart-a92ab01d-125c-4874-b545-5bd2199504af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219408179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3219408179
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.678710582
Short name T720
Test name
Test status
Simulation time 35626648 ps
CPU time 0.82 seconds
Started Aug 17 06:18:18 PM PDT 24
Finished Aug 17 06:18:19 PM PDT 24
Peak memory 206596 kb
Host smart-6e2a36ec-05a9-4838-a0d7-924aaac2d3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678710582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.678710582
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3937741441
Short name T1009
Test name
Test status
Simulation time 29641782857 ps
CPU time 95.46 seconds
Started Aug 17 06:18:14 PM PDT 24
Finished Aug 17 06:19:50 PM PDT 24
Peak memory 249304 kb
Host smart-1354a03d-a847-408a-adc1-3e46a38b58ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937741441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3937741441
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4197424359
Short name T81
Test name
Test status
Simulation time 50105705437 ps
CPU time 78.65 seconds
Started Aug 17 06:18:11 PM PDT 24
Finished Aug 17 06:19:30 PM PDT 24
Peak memory 239236 kb
Host smart-aa0fe160-7126-4f81-a563-7c067a41c96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197424359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4197424359
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1407086207
Short name T591
Test name
Test status
Simulation time 2305505701 ps
CPU time 11.97 seconds
Started Aug 17 06:18:13 PM PDT 24
Finished Aug 17 06:18:25 PM PDT 24
Peak memory 232924 kb
Host smart-2245f0b6-3a11-44a9-99a8-8c7be5f9a6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407086207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1407086207
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.989535135
Short name T335
Test name
Test status
Simulation time 4423511602 ps
CPU time 20.94 seconds
Started Aug 17 06:18:29 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 235460 kb
Host smart-90fe319d-4776-469c-bba6-d26e97342589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989535135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.989535135
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1053416471
Short name T507
Test name
Test status
Simulation time 9309960381 ps
CPU time 20.63 seconds
Started Aug 17 06:18:29 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 232984 kb
Host smart-a3052f9c-d0da-4163-ae10-493acdfb7310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053416471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1053416471
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1711213677
Short name T251
Test name
Test status
Simulation time 6571452281 ps
CPU time 57.01 seconds
Started Aug 17 06:18:15 PM PDT 24
Finished Aug 17 06:19:12 PM PDT 24
Peak memory 232912 kb
Host smart-035a687c-467b-4dfd-84b0-152ed07db91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711213677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1711213677
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.73775287
Short name T356
Test name
Test status
Simulation time 377747155 ps
CPU time 4.88 seconds
Started Aug 17 06:18:12 PM PDT 24
Finished Aug 17 06:18:17 PM PDT 24
Peak memory 232816 kb
Host smart-f69a8e12-8607-4fc6-b963-bf7b1e1e4c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73775287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.73775287
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1350757664
Short name T546
Test name
Test status
Simulation time 25458753038 ps
CPU time 18.01 seconds
Started Aug 17 06:18:13 PM PDT 24
Finished Aug 17 06:18:31 PM PDT 24
Peak memory 224760 kb
Host smart-7662736a-9c4b-4502-9d29-65a56166aa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350757664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1350757664
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.283764808
Short name T628
Test name
Test status
Simulation time 4907956617 ps
CPU time 12.84 seconds
Started Aug 17 06:18:13 PM PDT 24
Finished Aug 17 06:18:26 PM PDT 24
Peak memory 219112 kb
Host smart-11347821-97ac-4d36-be8e-9836dc53e54b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=283764808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.283764808
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3086392332
Short name T151
Test name
Test status
Simulation time 87025587716 ps
CPU time 215.52 seconds
Started Aug 17 06:18:09 PM PDT 24
Finished Aug 17 06:21:45 PM PDT 24
Peak memory 265792 kb
Host smart-18c696f5-fe9d-4e6a-97c6-3383bf97496e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086392332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3086392332
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3370245733
Short name T445
Test name
Test status
Simulation time 3821091824 ps
CPU time 5.44 seconds
Started Aug 17 06:18:05 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 216600 kb
Host smart-6336dc24-c950-4e13-9146-608a4d831417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370245733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3370245733
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2083304823
Short name T1015
Test name
Test status
Simulation time 709401571 ps
CPU time 2.22 seconds
Started Aug 17 06:18:05 PM PDT 24
Finished Aug 17 06:18:08 PM PDT 24
Peak memory 216276 kb
Host smart-f1edf458-15ec-4c35-a666-4ae7b5250177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083304823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2083304823
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1028013530
Short name T760
Test name
Test status
Simulation time 60497754 ps
CPU time 1.24 seconds
Started Aug 17 06:18:16 PM PDT 24
Finished Aug 17 06:18:17 PM PDT 24
Peak memory 216500 kb
Host smart-4b11e63f-a541-4d6d-9c02-d80702999d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028013530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1028013530
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3224815015
Short name T421
Test name
Test status
Simulation time 110894892 ps
CPU time 1.02 seconds
Started Aug 17 06:18:10 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 206096 kb
Host smart-cab12ae8-7d58-4bc9-8d3c-0e6580283feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224815015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3224815015
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2968030812
Short name T688
Test name
Test status
Simulation time 5144019369 ps
CPU time 9.29 seconds
Started Aug 17 06:18:04 PM PDT 24
Finished Aug 17 06:18:13 PM PDT 24
Peak memory 224632 kb
Host smart-cead2313-d376-44bb-abe8-17b70603fe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968030812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2968030812
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.673245125
Short name T634
Test name
Test status
Simulation time 13627095 ps
CPU time 0.71 seconds
Started Aug 17 06:18:12 PM PDT 24
Finished Aug 17 06:18:13 PM PDT 24
Peak memory 205516 kb
Host smart-79d91720-b32a-461c-9d18-dfdec0722c3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673245125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.673245125
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1095923788
Short name T780
Test name
Test status
Simulation time 176853585 ps
CPU time 3.31 seconds
Started Aug 17 06:18:19 PM PDT 24
Finished Aug 17 06:18:22 PM PDT 24
Peak memory 232840 kb
Host smart-9e718b2e-c533-4ce7-92da-315dd307599a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095923788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1095923788
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1023783103
Short name T309
Test name
Test status
Simulation time 114656508 ps
CPU time 0.78 seconds
Started Aug 17 06:18:10 PM PDT 24
Finished Aug 17 06:18:11 PM PDT 24
Peak memory 206604 kb
Host smart-a7d81407-6d44-41c9-b983-05cac41b0258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023783103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1023783103
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.173690458
Short name T235
Test name
Test status
Simulation time 2183811076 ps
CPU time 58.54 seconds
Started Aug 17 06:18:29 PM PDT 24
Finished Aug 17 06:19:28 PM PDT 24
Peak memory 260568 kb
Host smart-7132763d-59c8-495b-97b6-6437463f45b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173690458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.173690458
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1202792461
Short name T996
Test name
Test status
Simulation time 2895054005 ps
CPU time 19.93 seconds
Started Aug 17 06:18:22 PM PDT 24
Finished Aug 17 06:18:42 PM PDT 24
Peak memory 217676 kb
Host smart-644240f0-aa5c-4a09-ab80-4573f30b06ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202792461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1202792461
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.392910701
Short name T756
Test name
Test status
Simulation time 6028887163 ps
CPU time 25.45 seconds
Started Aug 17 06:18:18 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 241180 kb
Host smart-b4ea6121-1edd-4176-af99-904b0b5be144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392910701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.392910701
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.626300764
Short name T187
Test name
Test status
Simulation time 71045276325 ps
CPU time 488.21 seconds
Started Aug 17 06:18:05 PM PDT 24
Finished Aug 17 06:26:14 PM PDT 24
Peak memory 255180 kb
Host smart-cdfeb59a-f735-42a0-a4fc-334ad42af598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626300764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.626300764
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1653792902
Short name T354
Test name
Test status
Simulation time 117387288 ps
CPU time 3.19 seconds
Started Aug 17 06:18:06 PM PDT 24
Finished Aug 17 06:18:09 PM PDT 24
Peak memory 224720 kb
Host smart-7a64f052-8e0f-47a6-a409-cade8fcf8738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653792902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1653792902
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.213054810
Short name T178
Test name
Test status
Simulation time 1646235850 ps
CPU time 10.47 seconds
Started Aug 17 06:18:05 PM PDT 24
Finished Aug 17 06:18:15 PM PDT 24
Peak memory 232864 kb
Host smart-6a8530f4-1a52-49fe-adfa-df531e8d4b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213054810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.213054810
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2438183107
Short name T236
Test name
Test status
Simulation time 4951807353 ps
CPU time 7.28 seconds
Started Aug 17 06:18:16 PM PDT 24
Finished Aug 17 06:18:23 PM PDT 24
Peak memory 232852 kb
Host smart-c834891f-94b9-425e-bbe7-f8c0150b7821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438183107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2438183107
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2419799130
Short name T381
Test name
Test status
Simulation time 1647330231 ps
CPU time 5.46 seconds
Started Aug 17 06:18:15 PM PDT 24
Finished Aug 17 06:18:21 PM PDT 24
Peak memory 232908 kb
Host smart-f3d4f43a-9a36-4132-959d-e1a65a684014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419799130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2419799130
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3286216669
Short name T535
Test name
Test status
Simulation time 444891290 ps
CPU time 7.02 seconds
Started Aug 17 06:18:30 PM PDT 24
Finished Aug 17 06:18:37 PM PDT 24
Peak memory 223044 kb
Host smart-55b677d3-0483-40fa-83d2-415ea585388c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3286216669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3286216669
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3602326250
Short name T295
Test name
Test status
Simulation time 2291047549 ps
CPU time 30.65 seconds
Started Aug 17 06:18:20 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 219504 kb
Host smart-cdc956a2-bb32-4def-8d8a-4258aa715615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602326250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3602326250
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.609240065
Short name T939
Test name
Test status
Simulation time 228611653 ps
CPU time 1.91 seconds
Started Aug 17 06:18:17 PM PDT 24
Finished Aug 17 06:18:19 PM PDT 24
Peak memory 216512 kb
Host smart-a7b03eb5-e32d-4a9a-8509-7095d3915726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609240065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.609240065
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2461561291
Short name T714
Test name
Test status
Simulation time 832318712 ps
CPU time 1.06 seconds
Started Aug 17 06:18:28 PM PDT 24
Finished Aug 17 06:18:30 PM PDT 24
Peak memory 207080 kb
Host smart-310e5094-d1f8-465b-bc09-4939a6d96697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461561291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2461561291
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.162909356
Short name T991
Test name
Test status
Simulation time 119758960 ps
CPU time 0.86 seconds
Started Aug 17 06:18:18 PM PDT 24
Finished Aug 17 06:18:19 PM PDT 24
Peak memory 206124 kb
Host smart-997c9406-930b-49b3-b462-f158a2a4f582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162909356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.162909356
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3422965315
Short name T879
Test name
Test status
Simulation time 30950221628 ps
CPU time 23.73 seconds
Started Aug 17 06:18:17 PM PDT 24
Finished Aug 17 06:18:41 PM PDT 24
Peak memory 233932 kb
Host smart-ef451a6a-7910-48e1-8199-2d9aa661d58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422965315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3422965315
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1197665737
Short name T498
Test name
Test status
Simulation time 14343330 ps
CPU time 0.75 seconds
Started Aug 17 06:18:17 PM PDT 24
Finished Aug 17 06:18:18 PM PDT 24
Peak memory 205924 kb
Host smart-638c470f-7ff2-426e-ae0b-0d417c741325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197665737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1197665737
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1753216702
Short name T777
Test name
Test status
Simulation time 157726544 ps
CPU time 2.41 seconds
Started Aug 17 06:18:23 PM PDT 24
Finished Aug 17 06:18:31 PM PDT 24
Peak memory 224664 kb
Host smart-409ad2b1-522b-482c-a5a7-47b576077cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753216702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1753216702
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1908106457
Short name T582
Test name
Test status
Simulation time 16792464 ps
CPU time 0.8 seconds
Started Aug 17 06:18:24 PM PDT 24
Finished Aug 17 06:18:26 PM PDT 24
Peak memory 206584 kb
Host smart-3d10c38e-81c5-452f-b14d-9a9125d5a0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908106457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1908106457
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2410891466
Short name T805
Test name
Test status
Simulation time 29640748167 ps
CPU time 60.31 seconds
Started Aug 17 06:18:20 PM PDT 24
Finished Aug 17 06:19:20 PM PDT 24
Peak memory 251480 kb
Host smart-e8a86577-f780-4296-84c1-be14bc4a0e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410891466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2410891466
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3528768207
Short name T887
Test name
Test status
Simulation time 3056089611 ps
CPU time 28.99 seconds
Started Aug 17 06:18:29 PM PDT 24
Finished Aug 17 06:18:58 PM PDT 24
Peak memory 241216 kb
Host smart-97fe58cb-63f4-4020-9863-e3dea57fed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528768207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3528768207
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.375151034
Short name T54
Test name
Test status
Simulation time 4702600664 ps
CPU time 93.1 seconds
Started Aug 17 06:18:23 PM PDT 24
Finished Aug 17 06:19:56 PM PDT 24
Peak memory 271912 kb
Host smart-4ae150b8-4e8d-4e10-bb91-323463925c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375151034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.375151034
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1305678595
Short name T504
Test name
Test status
Simulation time 610643286 ps
CPU time 11.76 seconds
Started Aug 17 06:18:37 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 233952 kb
Host smart-c607369a-8bcc-4713-bc53-989882175a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305678595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1305678595
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2592880025
Short name T508
Test name
Test status
Simulation time 61577986577 ps
CPU time 213.82 seconds
Started Aug 17 06:18:29 PM PDT 24
Finished Aug 17 06:22:03 PM PDT 24
Peak memory 252868 kb
Host smart-e335d377-5145-4a16-be2c-e3aad4048db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592880025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2592880025
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2821363395
Short name T521
Test name
Test status
Simulation time 2683799860 ps
CPU time 8.27 seconds
Started Aug 17 06:18:26 PM PDT 24
Finished Aug 17 06:18:34 PM PDT 24
Peak memory 232908 kb
Host smart-bfcef4c0-c012-43fc-8749-b5cf336e0492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821363395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2821363395
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1999015752
Short name T469
Test name
Test status
Simulation time 12095593919 ps
CPU time 31.2 seconds
Started Aug 17 06:18:19 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 232892 kb
Host smart-7fbe4000-ed49-4438-bfb4-4a90ee111aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999015752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1999015752
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3487726864
Short name T264
Test name
Test status
Simulation time 28553056582 ps
CPU time 21.48 seconds
Started Aug 17 06:18:19 PM PDT 24
Finished Aug 17 06:18:41 PM PDT 24
Peak memory 240700 kb
Host smart-91197fc1-1f51-4cd5-8234-57b3a7c9a61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487726864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3487726864
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2391765869
Short name T403
Test name
Test status
Simulation time 1594555110 ps
CPU time 8.56 seconds
Started Aug 17 06:18:24 PM PDT 24
Finished Aug 17 06:18:32 PM PDT 24
Peak memory 233840 kb
Host smart-2e0e66dd-adc4-4f05-86ad-eaeccef52365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391765869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2391765869
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3101554735
Short name T609
Test name
Test status
Simulation time 148725712 ps
CPU time 4.95 seconds
Started Aug 17 06:18:19 PM PDT 24
Finished Aug 17 06:18:24 PM PDT 24
Peak memory 223168 kb
Host smart-f03982a6-7c87-40ed-9254-0a58006fdec4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3101554735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3101554735
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2399367769
Short name T64
Test name
Test status
Simulation time 11554864182 ps
CPU time 99.93 seconds
Started Aug 17 06:18:35 PM PDT 24
Finished Aug 17 06:20:15 PM PDT 24
Peak memory 236396 kb
Host smart-9c304f02-ce1d-4dd0-880b-2dc5361c54d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399367769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2399367769
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.959602885
Short name T299
Test name
Test status
Simulation time 14338297664 ps
CPU time 20.53 seconds
Started Aug 17 06:18:19 PM PDT 24
Finished Aug 17 06:18:40 PM PDT 24
Peak memory 216536 kb
Host smart-30b1f319-6a2a-4e91-abee-e8c0dd8a6997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959602885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.959602885
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.635013118
Short name T478
Test name
Test status
Simulation time 2280636291 ps
CPU time 6.29 seconds
Started Aug 17 06:18:37 PM PDT 24
Finished Aug 17 06:18:44 PM PDT 24
Peak memory 216544 kb
Host smart-f2a55e2b-0f87-43aa-9e4e-ec0ba5014174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635013118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.635013118
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3972251125
Short name T876
Test name
Test status
Simulation time 23772079 ps
CPU time 1.49 seconds
Started Aug 17 06:18:35 PM PDT 24
Finished Aug 17 06:18:37 PM PDT 24
Peak memory 216476 kb
Host smart-7c35e7f9-ccda-4162-b6db-258890f62cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972251125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3972251125
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4163088013
Short name T494
Test name
Test status
Simulation time 91482307 ps
CPU time 0.99 seconds
Started Aug 17 06:18:24 PM PDT 24
Finished Aug 17 06:18:25 PM PDT 24
Peak memory 206132 kb
Host smart-e0fd53e9-6798-4fea-8e38-f44f10bd4ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163088013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4163088013
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1144314890
Short name T867
Test name
Test status
Simulation time 1458687596 ps
CPU time 3.79 seconds
Started Aug 17 06:18:30 PM PDT 24
Finished Aug 17 06:18:34 PM PDT 24
Peak memory 232856 kb
Host smart-b9dbe2dd-b156-4265-8964-a1d031830729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144314890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1144314890
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3815355789
Short name T377
Test name
Test status
Simulation time 34427227 ps
CPU time 0.7 seconds
Started Aug 17 06:18:38 PM PDT 24
Finished Aug 17 06:18:39 PM PDT 24
Peak memory 205796 kb
Host smart-cf667478-e756-481e-906c-7047e720be61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815355789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3815355789
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1888886497
Short name T250
Test name
Test status
Simulation time 1117702905 ps
CPU time 4.93 seconds
Started Aug 17 06:18:20 PM PDT 24
Finished Aug 17 06:18:25 PM PDT 24
Peak memory 232856 kb
Host smart-5b373e99-d419-407d-9233-013992fbfa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888886497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1888886497
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.344140920
Short name T313
Test name
Test status
Simulation time 12720350 ps
CPU time 0.75 seconds
Started Aug 17 06:18:37 PM PDT 24
Finished Aug 17 06:18:38 PM PDT 24
Peak memory 206896 kb
Host smart-7509f4f7-b20e-4bc3-936f-63d7528966be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344140920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.344140920
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1477085847
Short name T631
Test name
Test status
Simulation time 47254903422 ps
CPU time 316.16 seconds
Started Aug 17 06:18:21 PM PDT 24
Finished Aug 17 06:23:37 PM PDT 24
Peak memory 272148 kb
Host smart-b9899b70-d53b-4065-b919-38a172e1216e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477085847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1477085847
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.134175017
Short name T368
Test name
Test status
Simulation time 54998947428 ps
CPU time 136.36 seconds
Started Aug 17 06:18:20 PM PDT 24
Finished Aug 17 06:20:36 PM PDT 24
Peak memory 249392 kb
Host smart-3dcbe76b-df6b-491e-a82a-9d6bc59aa863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134175017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.134175017
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.507854720
Short name T1024
Test name
Test status
Simulation time 9090078015 ps
CPU time 94.3 seconds
Started Aug 17 06:18:20 PM PDT 24
Finished Aug 17 06:19:54 PM PDT 24
Peak memory 249352 kb
Host smart-0c04d596-2b90-4684-9404-e515a76bbfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507854720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.507854720
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3655362625
Short name T558
Test name
Test status
Simulation time 2510943714 ps
CPU time 21.63 seconds
Started Aug 17 06:18:22 PM PDT 24
Finished Aug 17 06:18:44 PM PDT 24
Peak memory 224772 kb
Host smart-e9b0324c-a38b-4a08-b650-45442f2c78ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655362625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3655362625
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3816690294
Short name T799
Test name
Test status
Simulation time 38575893897 ps
CPU time 78.5 seconds
Started Aug 17 06:18:32 PM PDT 24
Finished Aug 17 06:19:51 PM PDT 24
Peak memory 256100 kb
Host smart-a4d73840-d801-4341-9798-6860c2ef3623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816690294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3816690294
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2886582063
Short name T957
Test name
Test status
Simulation time 328035962 ps
CPU time 3.49 seconds
Started Aug 17 06:18:19 PM PDT 24
Finished Aug 17 06:18:22 PM PDT 24
Peak memory 224580 kb
Host smart-1eea5ae7-4d23-427e-b827-520fa9084765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886582063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2886582063
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3922032405
Short name T678
Test name
Test status
Simulation time 37258310 ps
CPU time 2.38 seconds
Started Aug 17 06:18:37 PM PDT 24
Finished Aug 17 06:18:39 PM PDT 24
Peak memory 232548 kb
Host smart-0233f5e5-2a01-419c-9a0d-24045865ae61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922032405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3922032405
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.318050845
Short name T795
Test name
Test status
Simulation time 9086956230 ps
CPU time 13.36 seconds
Started Aug 17 06:18:25 PM PDT 24
Finished Aug 17 06:18:39 PM PDT 24
Peak memory 232944 kb
Host smart-e73ba369-d02f-4793-b29b-3470524146e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318050845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.318050845
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3622788305
Short name T729
Test name
Test status
Simulation time 1006786773 ps
CPU time 8.04 seconds
Started Aug 17 06:18:18 PM PDT 24
Finished Aug 17 06:18:26 PM PDT 24
Peak memory 232832 kb
Host smart-0ce7e81c-cb17-43cd-a93d-db3aa436d11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622788305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3622788305
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3634649070
Short name T137
Test name
Test status
Simulation time 4001818488 ps
CPU time 4.08 seconds
Started Aug 17 06:18:40 PM PDT 24
Finished Aug 17 06:18:44 PM PDT 24
Peak memory 219124 kb
Host smart-7b896a4d-3080-4ac7-a551-17bc335c205c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3634649070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3634649070
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2010499515
Short name T300
Test name
Test status
Simulation time 7184583084 ps
CPU time 20.86 seconds
Started Aug 17 06:18:13 PM PDT 24
Finished Aug 17 06:18:34 PM PDT 24
Peak memory 216476 kb
Host smart-947eba24-a75a-4646-9931-183567b7bf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010499515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2010499515
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2646625424
Short name T384
Test name
Test status
Simulation time 2613906252 ps
CPU time 4.35 seconds
Started Aug 17 06:18:23 PM PDT 24
Finished Aug 17 06:18:28 PM PDT 24
Peak memory 216548 kb
Host smart-616afd75-ea9e-40f8-bcee-6b38c673a9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646625424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2646625424
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.365342768
Short name T397
Test name
Test status
Simulation time 66890439 ps
CPU time 1.03 seconds
Started Aug 17 06:18:16 PM PDT 24
Finished Aug 17 06:18:17 PM PDT 24
Peak memory 207180 kb
Host smart-047cf014-c495-4182-a6b0-51a9d8f6bd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365342768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.365342768
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4185682638
Short name T610
Test name
Test status
Simulation time 224193634 ps
CPU time 0.77 seconds
Started Aug 17 06:18:33 PM PDT 24
Finished Aug 17 06:18:34 PM PDT 24
Peak memory 206140 kb
Host smart-4dcbb6a5-cd2c-446d-89c8-0339411ea87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185682638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4185682638
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.440483583
Short name T170
Test name
Test status
Simulation time 7780455278 ps
CPU time 26.09 seconds
Started Aug 17 06:18:23 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 232924 kb
Host smart-26b4193d-7aec-4734-921e-0cc2856276ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440483583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.440483583
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1895280131
Short name T696
Test name
Test status
Simulation time 10594131 ps
CPU time 0.7 seconds
Started Aug 17 06:18:28 PM PDT 24
Finished Aug 17 06:18:29 PM PDT 24
Peak memory 204968 kb
Host smart-1d5c8a0e-f94c-4373-abdc-8d6906376d86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895280131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1895280131
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4288254802
Short name T613
Test name
Test status
Simulation time 1072832907 ps
CPU time 11.9 seconds
Started Aug 17 06:18:23 PM PDT 24
Finished Aug 17 06:18:35 PM PDT 24
Peak memory 232840 kb
Host smart-4c2bbd3f-9ae9-4b64-9538-b003382b3b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288254802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4288254802
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.613198379
Short name T836
Test name
Test status
Simulation time 38809908 ps
CPU time 0.8 seconds
Started Aug 17 06:18:22 PM PDT 24
Finished Aug 17 06:18:23 PM PDT 24
Peak memory 206608 kb
Host smart-8ac552a8-b2c9-4a6e-b5e7-7770d584644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613198379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.613198379
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2291482411
Short name T183
Test name
Test status
Simulation time 5883803187 ps
CPU time 100.11 seconds
Started Aug 17 06:18:19 PM PDT 24
Finished Aug 17 06:19:59 PM PDT 24
Peak memory 257504 kb
Host smart-99817713-3d86-42f6-925b-196b655f9794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291482411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2291482411
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.24236662
Short name T896
Test name
Test status
Simulation time 153948978463 ps
CPU time 245.99 seconds
Started Aug 17 06:18:27 PM PDT 24
Finished Aug 17 06:22:38 PM PDT 24
Peak memory 249632 kb
Host smart-5d4733da-1290-4da8-b31a-048bcd0a9543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24236662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.24236662
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2303028139
Short name T83
Test name
Test status
Simulation time 11385874952 ps
CPU time 45.81 seconds
Started Aug 17 06:18:27 PM PDT 24
Finished Aug 17 06:19:13 PM PDT 24
Peak memory 250704 kb
Host smart-0580034c-bd69-47af-96d7-2cf0f0f41d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303028139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2303028139
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1758753658
Short name T369
Test name
Test status
Simulation time 2096581207 ps
CPU time 9.7 seconds
Started Aug 17 06:18:23 PM PDT 24
Finished Aug 17 06:18:32 PM PDT 24
Peak memory 224668 kb
Host smart-e5f5ed71-e557-41a5-8b86-c2a97b8d4d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758753658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1758753658
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2087504282
Short name T827
Test name
Test status
Simulation time 38128142567 ps
CPU time 151.28 seconds
Started Aug 17 06:18:33 PM PDT 24
Finished Aug 17 06:21:04 PM PDT 24
Peak memory 256300 kb
Host smart-f6456668-788e-4b2e-8640-c0de99308575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087504282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2087504282
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2819845224
Short name T618
Test name
Test status
Simulation time 1841999549 ps
CPU time 11.51 seconds
Started Aug 17 06:18:31 PM PDT 24
Finished Aug 17 06:18:42 PM PDT 24
Peak memory 232868 kb
Host smart-8c21d27c-15c3-4258-8b1b-0e035acb0b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819845224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2819845224
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.611771320
Short name T664
Test name
Test status
Simulation time 1664811665 ps
CPU time 5.53 seconds
Started Aug 17 06:18:25 PM PDT 24
Finished Aug 17 06:18:31 PM PDT 24
Peak memory 232868 kb
Host smart-b1df3c92-4524-4585-bbfa-41531d3529ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611771320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.611771320
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3851955203
Short name T263
Test name
Test status
Simulation time 5872081193 ps
CPU time 25.44 seconds
Started Aug 17 06:18:24 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 249248 kb
Host smart-ba9c1486-52af-47fc-9a64-5d10ac597825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851955203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3851955203
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2501583638
Short name T486
Test name
Test status
Simulation time 25001509846 ps
CPU time 10.58 seconds
Started Aug 17 06:18:41 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 232304 kb
Host smart-63813dd3-9c6c-495a-8f26-470c3a73f3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501583638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2501583638
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3141666620
Short name T733
Test name
Test status
Simulation time 1234695693 ps
CPU time 5.67 seconds
Started Aug 17 06:18:35 PM PDT 24
Finished Aug 17 06:18:41 PM PDT 24
Peak memory 223248 kb
Host smart-f9eb1678-ee5d-4704-8611-ceb2d3fa8ac6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3141666620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3141666620
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2570934511
Short name T584
Test name
Test status
Simulation time 9382907316 ps
CPU time 46.53 seconds
Started Aug 17 06:18:35 PM PDT 24
Finished Aug 17 06:19:22 PM PDT 24
Peak memory 238048 kb
Host smart-c0bf5b7d-6df0-4491-8ff1-996680e1ad0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570934511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2570934511
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2991824362
Short name T503
Test name
Test status
Simulation time 18176302940 ps
CPU time 46.22 seconds
Started Aug 17 06:18:35 PM PDT 24
Finished Aug 17 06:19:21 PM PDT 24
Peak memory 216540 kb
Host smart-e91a2554-0fc0-4e5a-b0e3-95638ed91de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991824362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2991824362
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3814704141
Short name T627
Test name
Test status
Simulation time 1482890442 ps
CPU time 6.08 seconds
Started Aug 17 06:18:24 PM PDT 24
Finished Aug 17 06:18:30 PM PDT 24
Peak memory 216444 kb
Host smart-b3ff7bea-8d45-4a3b-bcb1-1f848b51ecb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814704141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3814704141
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3437594397
Short name T851
Test name
Test status
Simulation time 462959254 ps
CPU time 7.85 seconds
Started Aug 17 06:18:25 PM PDT 24
Finished Aug 17 06:18:33 PM PDT 24
Peak memory 216484 kb
Host smart-de1d7371-283f-43d4-ab55-2818056e613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437594397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3437594397
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3199126927
Short name T571
Test name
Test status
Simulation time 69049780 ps
CPU time 0.95 seconds
Started Aug 17 06:18:26 PM PDT 24
Finished Aug 17 06:18:27 PM PDT 24
Peak memory 207132 kb
Host smart-f3056f14-9d7d-4c1f-bdb2-2a7f17dc8705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199126927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3199126927
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2504716251
Short name T655
Test name
Test status
Simulation time 990954724 ps
CPU time 5.79 seconds
Started Aug 17 06:18:22 PM PDT 24
Finished Aug 17 06:18:27 PM PDT 24
Peak memory 239892 kb
Host smart-f05d0a0d-cc7e-43c2-b174-9d78f38b78e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504716251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2504716251
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3413765881
Short name T407
Test name
Test status
Simulation time 14726321 ps
CPU time 0.72 seconds
Started Aug 17 06:18:40 PM PDT 24
Finished Aug 17 06:18:41 PM PDT 24
Peak memory 205516 kb
Host smart-917c5406-c09b-4bd1-a891-9ef0ad18fb1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413765881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3413765881
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3424066023
Short name T935
Test name
Test status
Simulation time 101337832 ps
CPU time 3.29 seconds
Started Aug 17 06:18:36 PM PDT 24
Finished Aug 17 06:18:40 PM PDT 24
Peak memory 232900 kb
Host smart-f961b84b-a33b-4db2-8600-1d024df9d7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424066023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3424066023
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.365686195
Short name T487
Test name
Test status
Simulation time 15608727 ps
CPU time 0.81 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 206612 kb
Host smart-72765935-0655-4faf-a915-07e839b49027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365686195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.365686195
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3826703423
Short name T185
Test name
Test status
Simulation time 45646420079 ps
CPU time 83.04 seconds
Started Aug 17 06:18:41 PM PDT 24
Finished Aug 17 06:20:04 PM PDT 24
Peak memory 249360 kb
Host smart-e0665447-571a-4696-bfb9-9373506efa77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826703423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3826703423
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2640820129
Short name T268
Test name
Test status
Simulation time 4145801227 ps
CPU time 66.89 seconds
Started Aug 17 06:18:27 PM PDT 24
Finished Aug 17 06:19:34 PM PDT 24
Peak memory 249424 kb
Host smart-f2ad4b14-e516-4136-a569-ad7bf4898550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640820129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2640820129
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2010944099
Short name T947
Test name
Test status
Simulation time 126855820766 ps
CPU time 108 seconds
Started Aug 17 06:18:26 PM PDT 24
Finished Aug 17 06:20:14 PM PDT 24
Peak memory 256188 kb
Host smart-76682dc6-d1ae-4199-a1fa-bda4123ca386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010944099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2010944099
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.947174700
Short name T59
Test name
Test status
Simulation time 1236036485 ps
CPU time 9.09 seconds
Started Aug 17 06:18:41 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 232912 kb
Host smart-782a6f94-cb23-4d9a-b1b0-2c7fe261144b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947174700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.947174700
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3912513761
Short name T450
Test name
Test status
Simulation time 8928206211 ps
CPU time 41.64 seconds
Started Aug 17 06:18:37 PM PDT 24
Finished Aug 17 06:19:19 PM PDT 24
Peak memory 249352 kb
Host smart-d3b9d4fb-2080-4418-8131-dfea08807c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912513761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3912513761
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2817268890
Short name T748
Test name
Test status
Simulation time 109882226 ps
CPU time 4.15 seconds
Started Aug 17 06:18:40 PM PDT 24
Finished Aug 17 06:18:45 PM PDT 24
Peak memory 224648 kb
Host smart-184f4f4b-961e-463a-8045-121269f42aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817268890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2817268890
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3230450525
Short name T216
Test name
Test status
Simulation time 2282109914 ps
CPU time 10.09 seconds
Started Aug 17 06:18:36 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 232972 kb
Host smart-9dddabb6-29f2-4222-a8c9-bfdfecafb2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230450525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3230450525
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3528225140
Short name T990
Test name
Test status
Simulation time 636534960 ps
CPU time 8.92 seconds
Started Aug 17 06:18:38 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 224652 kb
Host smart-ab898c0d-609a-4d7d-a9a7-811d6bcde6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528225140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3528225140
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.793101303
Short name T190
Test name
Test status
Simulation time 416855845 ps
CPU time 4.23 seconds
Started Aug 17 06:18:25 PM PDT 24
Finished Aug 17 06:18:29 PM PDT 24
Peak memory 224624 kb
Host smart-3e7d6585-f7da-4a94-b9b2-497a627ebe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793101303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.793101303
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2893749785
Short name T373
Test name
Test status
Simulation time 1671027165 ps
CPU time 15.56 seconds
Started Aug 17 06:18:40 PM PDT 24
Finished Aug 17 06:18:56 PM PDT 24
Peak memory 218892 kb
Host smart-84ac388a-b085-4fce-b3ea-4999d031e8d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2893749785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2893749785
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2353338724
Short name T18
Test name
Test status
Simulation time 3993677532 ps
CPU time 44.81 seconds
Started Aug 17 06:18:25 PM PDT 24
Finished Aug 17 06:19:10 PM PDT 24
Peak memory 224776 kb
Host smart-2eaf63e5-1162-4370-a999-39274224e3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353338724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2353338724
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1957841631
Short name T903
Test name
Test status
Simulation time 10594305159 ps
CPU time 38.82 seconds
Started Aug 17 06:18:25 PM PDT 24
Finished Aug 17 06:19:04 PM PDT 24
Peak memory 216580 kb
Host smart-7b9e21c1-177a-4ad5-bd48-f1cbd69ed638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957841631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1957841631
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.718240164
Short name T379
Test name
Test status
Simulation time 8947210983 ps
CPU time 12.7 seconds
Started Aug 17 06:18:27 PM PDT 24
Finished Aug 17 06:18:40 PM PDT 24
Peak memory 216556 kb
Host smart-2e9d55f2-4bf2-4873-9059-f662ba84035b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718240164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.718240164
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.392336640
Short name T7
Test name
Test status
Simulation time 1130353353 ps
CPU time 8.56 seconds
Started Aug 17 06:18:40 PM PDT 24
Finished Aug 17 06:18:48 PM PDT 24
Peak memory 216492 kb
Host smart-42c89ff2-ba46-43da-851b-960571378a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392336640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.392336640
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.17222490
Short name T848
Test name
Test status
Simulation time 281566207 ps
CPU time 0.78 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 206136 kb
Host smart-5343ad32-ca65-404b-9c47-3ea828ed25ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17222490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.17222490
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1994649347
Short name T911
Test name
Test status
Simulation time 306727683 ps
CPU time 2.8 seconds
Started Aug 17 06:18:43 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 224668 kb
Host smart-63e37a04-c6c4-4288-a88b-719791415d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994649347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1994649347
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2214130860
Short name T790
Test name
Test status
Simulation time 235550890 ps
CPU time 0.75 seconds
Started Aug 17 06:18:43 PM PDT 24
Finished Aug 17 06:18:43 PM PDT 24
Peak memory 204956 kb
Host smart-b09e981a-c0bd-4fd0-b8c4-9b747ffb01c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214130860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2214130860
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.999223881
Short name T92
Test name
Test status
Simulation time 7226815853 ps
CPU time 17.54 seconds
Started Aug 17 06:18:28 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 224736 kb
Host smart-77b73669-bede-44c3-9a46-99672cb1b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999223881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.999223881
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2600255409
Short name T532
Test name
Test status
Simulation time 64952907 ps
CPU time 0.76 seconds
Started Aug 17 06:18:33 PM PDT 24
Finished Aug 17 06:18:34 PM PDT 24
Peak memory 206596 kb
Host smart-f1acefdc-4077-4d38-9793-fc246080cf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600255409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2600255409
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.4157328068
Short name T385
Test name
Test status
Simulation time 4191270482 ps
CPU time 55.56 seconds
Started Aug 17 06:18:43 PM PDT 24
Finished Aug 17 06:19:39 PM PDT 24
Peak memory 252924 kb
Host smart-95b1b00b-439f-431b-b364-e5d48bdc3504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157328068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4157328068
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2077763532
Short name T612
Test name
Test status
Simulation time 29697254341 ps
CPU time 61.28 seconds
Started Aug 17 06:18:27 PM PDT 24
Finished Aug 17 06:19:28 PM PDT 24
Peak memory 251676 kb
Host smart-4fd314d9-f63b-43d1-8ccf-7ea820b31777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077763532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2077763532
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1418966388
Short name T176
Test name
Test status
Simulation time 57789510043 ps
CPU time 109.5 seconds
Started Aug 17 06:18:40 PM PDT 24
Finished Aug 17 06:20:30 PM PDT 24
Peak memory 249432 kb
Host smart-5d667a6b-59b8-473d-a2c3-6d425a6fb28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418966388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1418966388
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2416979819
Short name T709
Test name
Test status
Simulation time 128756317 ps
CPU time 3.1 seconds
Started Aug 17 06:18:26 PM PDT 24
Finished Aug 17 06:18:29 PM PDT 24
Peak memory 232920 kb
Host smart-af495039-dafe-4906-89ad-0491d98a7786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416979819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2416979819
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3611542783
Short name T519
Test name
Test status
Simulation time 10463982 ps
CPU time 0.75 seconds
Started Aug 17 06:18:42 PM PDT 24
Finished Aug 17 06:18:42 PM PDT 24
Peak memory 215888 kb
Host smart-9a1df25b-63b5-4966-a43f-b851ec203917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611542783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3611542783
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3090270394
Short name T895
Test name
Test status
Simulation time 1050084080 ps
CPU time 10.02 seconds
Started Aug 17 06:18:32 PM PDT 24
Finished Aug 17 06:18:42 PM PDT 24
Peak memory 232852 kb
Host smart-2c919ab5-6da6-407a-bae7-640318abbbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090270394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3090270394
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4089180338
Short name T533
Test name
Test status
Simulation time 1415665561 ps
CPU time 17 seconds
Started Aug 17 06:18:29 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 232836 kb
Host smart-040daff5-aa24-40d4-bd21-69b6299acd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089180338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4089180338
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3054264036
Short name T934
Test name
Test status
Simulation time 3444583370 ps
CPU time 4.65 seconds
Started Aug 17 06:18:43 PM PDT 24
Finished Aug 17 06:18:48 PM PDT 24
Peak memory 224736 kb
Host smart-badbe735-a62b-4b15-8d34-29bf5eaafc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054264036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3054264036
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1963905083
Short name T921
Test name
Test status
Simulation time 110752952 ps
CPU time 2.57 seconds
Started Aug 17 06:18:28 PM PDT 24
Finished Aug 17 06:18:31 PM PDT 24
Peak memory 224644 kb
Host smart-81bed5f4-242e-4971-92ae-79e5010997ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963905083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1963905083
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1403019197
Short name T451
Test name
Test status
Simulation time 2192370866 ps
CPU time 9.04 seconds
Started Aug 17 06:18:31 PM PDT 24
Finished Aug 17 06:18:41 PM PDT 24
Peak memory 219048 kb
Host smart-9b8bf70e-1b45-47bc-bb69-50d516e763e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1403019197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1403019197
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2605850725
Short name T20
Test name
Test status
Simulation time 23794901276 ps
CPU time 250.19 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:22:54 PM PDT 24
Peak memory 273424 kb
Host smart-33e813ed-fdd9-4bcf-bbb0-6ff4a0877493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605850725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2605850725
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1722942271
Short name T589
Test name
Test status
Simulation time 25044308796 ps
CPU time 20.11 seconds
Started Aug 17 06:18:39 PM PDT 24
Finished Aug 17 06:18:59 PM PDT 24
Peak memory 216844 kb
Host smart-f7da134c-66b8-49c0-8cd0-78d6dcc868bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722942271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1722942271
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.92976138
Short name T316
Test name
Test status
Simulation time 438849837 ps
CPU time 2.35 seconds
Started Aug 17 06:18:40 PM PDT 24
Finished Aug 17 06:18:43 PM PDT 24
Peak memory 208120 kb
Host smart-1ab50093-59ed-42b3-a813-ff00f11487de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92976138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.92976138
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.970481139
Short name T405
Test name
Test status
Simulation time 41878943 ps
CPU time 0.71 seconds
Started Aug 17 06:18:37 PM PDT 24
Finished Aug 17 06:18:38 PM PDT 24
Peak memory 205672 kb
Host smart-b67fb703-0ad5-4917-a9a5-e84bef4a7572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970481139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.970481139
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3368033838
Short name T322
Test name
Test status
Simulation time 225022985 ps
CPU time 0.91 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:18:45 PM PDT 24
Peak memory 206544 kb
Host smart-0e6c491b-3444-4b04-9fb5-0365aaa45cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368033838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3368033838
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2020912465
Short name T969
Test name
Test status
Simulation time 20357024962 ps
CPU time 19.04 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:19:05 PM PDT 24
Peak memory 232996 kb
Host smart-805c3611-28af-4998-bdd4-100fe6734a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020912465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2020912465
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2243309998
Short name T718
Test name
Test status
Simulation time 61434430 ps
CPU time 0.72 seconds
Started Aug 17 06:18:39 PM PDT 24
Finished Aug 17 06:18:40 PM PDT 24
Peak memory 205476 kb
Host smart-b6862518-58df-4933-9513-410d181c2872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243309998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2243309998
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1033252410
Short name T435
Test name
Test status
Simulation time 5100654268 ps
CPU time 11.59 seconds
Started Aug 17 06:18:42 PM PDT 24
Finished Aug 17 06:18:54 PM PDT 24
Peak memory 232888 kb
Host smart-a09d7a1c-fccb-420c-95db-cfe7d5861ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033252410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1033252410
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.726643008
Short name T824
Test name
Test status
Simulation time 19476960 ps
CPU time 0.8 seconds
Started Aug 17 06:18:26 PM PDT 24
Finished Aug 17 06:18:27 PM PDT 24
Peak memory 206940 kb
Host smart-2026c602-f88a-4d92-a71d-23f3265c1e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726643008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.726643008
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4088266664
Short name T515
Test name
Test status
Simulation time 12168889 ps
CPU time 0.74 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 215892 kb
Host smart-90ead8b6-fa25-433c-b1fd-b0d1acb2b2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088266664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4088266664
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.18796919
Short name T979
Test name
Test status
Simulation time 20617364268 ps
CPU time 241.43 seconds
Started Aug 17 06:18:37 PM PDT 24
Finished Aug 17 06:22:39 PM PDT 24
Peak memory 256536 kb
Host smart-87932f96-5e71-45dc-9259-5c30bff3a69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18796919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.18796919
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.509145312
Short name T1005
Test name
Test status
Simulation time 9337069183 ps
CPU time 27.42 seconds
Started Aug 17 06:18:37 PM PDT 24
Finished Aug 17 06:19:04 PM PDT 24
Peak memory 249384 kb
Host smart-720c2ed8-76a8-45c6-8a71-2f594f55243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509145312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.509145312
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3205438833
Short name T429
Test name
Test status
Simulation time 134645571 ps
CPU time 3.89 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 232952 kb
Host smart-968eb942-763a-4ab8-8218-d44ce06cb00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205438833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3205438833
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3266524927
Short name T154
Test name
Test status
Simulation time 175699105064 ps
CPU time 348.44 seconds
Started Aug 17 06:18:43 PM PDT 24
Finished Aug 17 06:24:32 PM PDT 24
Peak memory 254796 kb
Host smart-6a6a33d0-e681-449b-9ba5-bc085bee9728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266524927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3266524927
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2845079266
Short name T415
Test name
Test status
Simulation time 618656131 ps
CPU time 4.83 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 232852 kb
Host smart-d4ae240f-d6a6-4f9b-a5ad-c282ff2d1fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845079266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2845079266
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1884209670
Short name T989
Test name
Test status
Simulation time 34136948 ps
CPU time 2.65 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 232496 kb
Host smart-ed24e5c9-e91b-4be4-b606-17b7d29501c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884209670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1884209670
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2305259848
Short name T11
Test name
Test status
Simulation time 614289020 ps
CPU time 5.72 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:18:53 PM PDT 24
Peak memory 232852 kb
Host smart-8f4be585-a75b-44ec-b12a-807aa2ccb05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305259848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2305259848
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3022219611
Short name T479
Test name
Test status
Simulation time 69091602988 ps
CPU time 12.95 seconds
Started Aug 17 06:18:36 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 232948 kb
Host smart-8c77a993-3ade-4ce7-ae72-46ba4264ef55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022219611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3022219611
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.5534639
Short name T342
Test name
Test status
Simulation time 402380737 ps
CPU time 3.67 seconds
Started Aug 17 06:18:33 PM PDT 24
Finished Aug 17 06:18:37 PM PDT 24
Peak memory 218896 kb
Host smart-683c6fe4-dfa5-4ffa-b0c0-729ae1f672b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=5534639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.5534639
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2356955038
Short name T55
Test name
Test status
Simulation time 236692873310 ps
CPU time 531.99 seconds
Started Aug 17 06:18:41 PM PDT 24
Finished Aug 17 06:27:33 PM PDT 24
Peak memory 265784 kb
Host smart-bf404519-1d1a-4ca3-85dd-3d24e86b98ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356955038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2356955038
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2387572694
Short name T301
Test name
Test status
Simulation time 1025836582 ps
CPU time 10.95 seconds
Started Aug 17 06:18:42 PM PDT 24
Finished Aug 17 06:18:53 PM PDT 24
Peak memory 216500 kb
Host smart-c7432be0-f755-4822-b596-830282c36232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387572694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2387572694
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2330159125
Short name T465
Test name
Test status
Simulation time 2781634318 ps
CPU time 5.86 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:18:53 PM PDT 24
Peak memory 216604 kb
Host smart-05836bf4-9abc-44aa-a442-3d936dab344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330159125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2330159125
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3602943865
Short name T352
Test name
Test status
Simulation time 356425539 ps
CPU time 3.85 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:18:48 PM PDT 24
Peak memory 216472 kb
Host smart-35a1189d-09a0-4048-942c-f83ef11263e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602943865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3602943865
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3351698683
Short name T863
Test name
Test status
Simulation time 67328527 ps
CPU time 0.9 seconds
Started Aug 17 06:18:36 PM PDT 24
Finished Aug 17 06:18:37 PM PDT 24
Peak memory 206128 kb
Host smart-c2ad7085-9eb0-431e-ad4c-11d60b1825d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351698683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3351698683
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.4218777594
Short name T14
Test name
Test status
Simulation time 37365425950 ps
CPU time 14.13 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:18:58 PM PDT 24
Peak memory 224796 kb
Host smart-46356d1b-7582-4680-b184-a9a54030bb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218777594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.4218777594
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4085745883
Short name T24
Test name
Test status
Simulation time 31525566 ps
CPU time 0.71 seconds
Started Aug 17 06:18:42 PM PDT 24
Finished Aug 17 06:18:43 PM PDT 24
Peak memory 204916 kb
Host smart-50440a11-0624-48e1-a412-a06db837b1aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085745883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4085745883
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2476162603
Short name T218
Test name
Test status
Simulation time 620962825 ps
CPU time 6.15 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:51 PM PDT 24
Peak memory 232820 kb
Host smart-51886e5f-2b95-4fb9-8f11-8526b4c91036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476162603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2476162603
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4171037689
Short name T328
Test name
Test status
Simulation time 24673279 ps
CPU time 0.76 seconds
Started Aug 17 06:18:42 PM PDT 24
Finished Aug 17 06:18:43 PM PDT 24
Peak memory 206940 kb
Host smart-e46a443f-2a5f-4896-8b4a-0b54855d0678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171037689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4171037689
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1325067729
Short name T269
Test name
Test status
Simulation time 804677655 ps
CPU time 6.32 seconds
Started Aug 17 06:18:36 PM PDT 24
Finished Aug 17 06:18:43 PM PDT 24
Peak memory 241072 kb
Host smart-a9dca1e4-e4d6-433c-a312-76cdc762a7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325067729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1325067729
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.598634364
Short name T945
Test name
Test status
Simulation time 103707343128 ps
CPU time 270.71 seconds
Started Aug 17 06:18:35 PM PDT 24
Finished Aug 17 06:23:06 PM PDT 24
Peak memory 269080 kb
Host smart-a881da72-39ca-42da-a7ed-ba4611a95006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598634364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.598634364
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2590757609
Short name T282
Test name
Test status
Simulation time 233693743 ps
CPU time 7.95 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:54 PM PDT 24
Peak memory 233232 kb
Host smart-4bf744f2-1f35-4113-9af4-8d716ddb9d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590757609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2590757609
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1969254430
Short name T164
Test name
Test status
Simulation time 4347604496 ps
CPU time 89.56 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:20:14 PM PDT 24
Peak memory 266688 kb
Host smart-a5b91299-010b-4a57-a003-a841f9eeccb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969254430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1969254430
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2947535230
Short name T575
Test name
Test status
Simulation time 766171005 ps
CPU time 7.83 seconds
Started Aug 17 06:18:41 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 232884 kb
Host smart-8b40b50d-322e-4d5d-9371-723de97fec34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947535230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2947535230
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3348567634
Short name T626
Test name
Test status
Simulation time 6790349158 ps
CPU time 12.8 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:59 PM PDT 24
Peak memory 224732 kb
Host smart-a5b1e924-cbed-4fcd-b169-4ccf981a362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348567634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3348567634
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1358002701
Short name T239
Test name
Test status
Simulation time 3904755308 ps
CPU time 14.37 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:19:00 PM PDT 24
Peak memory 232960 kb
Host smart-6df85504-5c01-49e7-b780-4d5971fd5e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358002701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1358002701
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.588314302
Short name T804
Test name
Test status
Simulation time 4471636909 ps
CPU time 10.28 seconds
Started Aug 17 06:18:43 PM PDT 24
Finished Aug 17 06:18:54 PM PDT 24
Peak memory 237952 kb
Host smart-db25349e-8c7d-4fac-8a6f-862d3ace8c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588314302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.588314302
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1473034681
Short name T138
Test name
Test status
Simulation time 1384829104 ps
CPU time 3.66 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 220604 kb
Host smart-e805530e-be59-410a-9282-64ca885f05ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1473034681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1473034681
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.326963649
Short name T517
Test name
Test status
Simulation time 155251097 ps
CPU time 3.4 seconds
Started Aug 17 06:18:42 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 216492 kb
Host smart-de12e967-4785-4178-946a-fdb5fcd3ee00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326963649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.326963649
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4024885352
Short name T74
Test name
Test status
Simulation time 12175499 ps
CPU time 0.77 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:18:48 PM PDT 24
Peak memory 205644 kb
Host smart-3c55f707-c57f-4def-a555-147a9aac2a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024885352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4024885352
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.855788815
Short name T807
Test name
Test status
Simulation time 393272973 ps
CPU time 1.94 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:48 PM PDT 24
Peak memory 216444 kb
Host smart-719d991e-dab2-48b1-a26c-d2c441110a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855788815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.855788815
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2741444702
Short name T898
Test name
Test status
Simulation time 64927324 ps
CPU time 0.8 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 206096 kb
Host smart-8cd54919-c68a-43c4-b4cb-f5ab2a40793f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741444702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2741444702
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1134494806
Short name T509
Test name
Test status
Simulation time 4598844696 ps
CPU time 8.23 seconds
Started Aug 17 06:18:41 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 232380 kb
Host smart-0ca5ba86-d9ed-40d7-b396-b7f43d581bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134494806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1134494806
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.979625051
Short name T978
Test name
Test status
Simulation time 14034221 ps
CPU time 0.77 seconds
Started Aug 17 06:17:08 PM PDT 24
Finished Aug 17 06:17:09 PM PDT 24
Peak memory 205864 kb
Host smart-a03a4283-edf8-48d0-a00b-43d0b753f89a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979625051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.979625051
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1735990643
Short name T310
Test name
Test status
Simulation time 29930306 ps
CPU time 2.17 seconds
Started Aug 17 06:16:59 PM PDT 24
Finished Aug 17 06:17:01 PM PDT 24
Peak memory 224580 kb
Host smart-b7393e2a-d1d5-425f-af3e-060fb5013e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735990643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1735990643
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.4123725721
Short name T78
Test name
Test status
Simulation time 20899331 ps
CPU time 0.82 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:16:57 PM PDT 24
Peak memory 206588 kb
Host smart-d7a5533d-d482-43b5-8896-6f85b738e4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123725721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.4123725721
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3398766412
Short name T750
Test name
Test status
Simulation time 34919201796 ps
CPU time 85.04 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 249524 kb
Host smart-b6d41014-c339-41c2-a932-1e808d240afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398766412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3398766412
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1055479329
Short name T57
Test name
Test status
Simulation time 3494907523 ps
CPU time 70.74 seconds
Started Aug 17 06:17:33 PM PDT 24
Finished Aug 17 06:18:44 PM PDT 24
Peak memory 252620 kb
Host smart-74ce2dea-d2ac-4d15-9682-ae36ea710fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055479329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1055479329
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2365873863
Short name T34
Test name
Test status
Simulation time 61216295223 ps
CPU time 118.06 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:19:14 PM PDT 24
Peak memory 251084 kb
Host smart-f3bb60ab-72ad-4352-bd0d-840c9a11e91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365873863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2365873863
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2398435696
Short name T992
Test name
Test status
Simulation time 13718791920 ps
CPU time 55.57 seconds
Started Aug 17 06:17:13 PM PDT 24
Finished Aug 17 06:18:09 PM PDT 24
Peak memory 239828 kb
Host smart-85cea762-1fcb-454d-a889-52223af34cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398435696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2398435696
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1572006948
Short name T212
Test name
Test status
Simulation time 41972585618 ps
CPU time 31.99 seconds
Started Aug 17 06:17:13 PM PDT 24
Finished Aug 17 06:17:45 PM PDT 24
Peak memory 241176 kb
Host smart-3ce3f506-dec6-4ea7-9f9b-004efba5cce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572006948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1572006948
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1220837434
Short name T548
Test name
Test status
Simulation time 306178683 ps
CPU time 2.82 seconds
Started Aug 17 06:16:59 PM PDT 24
Finished Aug 17 06:17:02 PM PDT 24
Peak memory 224652 kb
Host smart-d1f3050d-c973-4b4d-99c9-76266f1eb148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220837434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1220837434
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.161768394
Short name T743
Test name
Test status
Simulation time 151255558 ps
CPU time 2.22 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:23 PM PDT 24
Peak memory 223184 kb
Host smart-ea41df41-c3f6-47d9-9c4c-cb2267a4e183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161768394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.161768394
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2539403239
Short name T1022
Test name
Test status
Simulation time 61348854 ps
CPU time 1.07 seconds
Started Aug 17 06:16:58 PM PDT 24
Finished Aug 17 06:17:00 PM PDT 24
Peak memory 218012 kb
Host smart-127bdc0e-7389-4129-bd2d-50bae6c1e18e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539403239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2539403239
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3172997765
Short name T321
Test name
Test status
Simulation time 77104762 ps
CPU time 2.24 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:16:58 PM PDT 24
Peak memory 223212 kb
Host smart-1d6b7389-5f03-48f7-9848-907db0044813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172997765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3172997765
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2538242323
Short name T611
Test name
Test status
Simulation time 35445804860 ps
CPU time 18.95 seconds
Started Aug 17 06:17:09 PM PDT 24
Finished Aug 17 06:17:28 PM PDT 24
Peak memory 240884 kb
Host smart-7a65e236-0402-496f-a854-c8c9fef8063b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538242323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2538242323
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1065106501
Short name T757
Test name
Test status
Simulation time 7031802945 ps
CPU time 8.15 seconds
Started Aug 17 06:17:18 PM PDT 24
Finished Aug 17 06:17:26 PM PDT 24
Peak memory 222572 kb
Host smart-a526e810-aca8-4e26-a242-b46f8cfc4839
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1065106501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1065106501
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3139762674
Short name T71
Test name
Test status
Simulation time 143236835 ps
CPU time 0.95 seconds
Started Aug 17 06:16:57 PM PDT 24
Finished Aug 17 06:16:58 PM PDT 24
Peak memory 235556 kb
Host smart-400fbeb6-6e02-4408-b4fd-af726a30d645
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139762674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3139762674
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.4258863667
Short name T746
Test name
Test status
Simulation time 47271063 ps
CPU time 0.97 seconds
Started Aug 17 06:17:06 PM PDT 24
Finished Aug 17 06:17:07 PM PDT 24
Peak memory 206640 kb
Host smart-66bd3adf-cad6-4149-a31c-fb06cca05234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258863667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.4258863667
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1243097860
Short name T317
Test name
Test status
Simulation time 4735859420 ps
CPU time 4.27 seconds
Started Aug 17 06:17:04 PM PDT 24
Finished Aug 17 06:17:08 PM PDT 24
Peak memory 216504 kb
Host smart-0d21aa71-240f-4a7d-b096-37012e1c6ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243097860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1243097860
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1326626415
Short name T789
Test name
Test status
Simulation time 189196806 ps
CPU time 1.6 seconds
Started Aug 17 06:16:51 PM PDT 24
Finished Aug 17 06:16:53 PM PDT 24
Peak memory 207204 kb
Host smart-21abd469-8332-4c33-867b-124b4710c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326626415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1326626415
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2795354351
Short name T305
Test name
Test status
Simulation time 616469048 ps
CPU time 2.35 seconds
Started Aug 17 06:17:10 PM PDT 24
Finished Aug 17 06:17:12 PM PDT 24
Peak memory 216404 kb
Host smart-548bc708-7330-4591-a89c-89a0baea793e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795354351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2795354351
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1956692249
Short name T65
Test name
Test status
Simulation time 14017100 ps
CPU time 0.72 seconds
Started Aug 17 06:16:54 PM PDT 24
Finished Aug 17 06:16:54 PM PDT 24
Peak memory 206124 kb
Host smart-d6c851c3-4271-499c-a415-e89d5ddcaafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956692249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1956692249
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2792738290
Short name T318
Test name
Test status
Simulation time 164362876561 ps
CPU time 29.86 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:17:46 PM PDT 24
Peak memory 232964 kb
Host smart-689e43ae-0390-4d7b-96f7-764068402841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792738290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2792738290
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1645811038
Short name T635
Test name
Test status
Simulation time 37020365 ps
CPU time 0.74 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 205532 kb
Host smart-7fa2ae9c-32fb-4e81-a248-d44e630e8fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645811038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1645811038
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1681635887
Short name T850
Test name
Test status
Simulation time 117615687 ps
CPU time 2.31 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 224672 kb
Host smart-8a6de6b4-86b7-429d-be1c-49ac1e9371b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681635887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1681635887
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3456553541
Short name T513
Test name
Test status
Simulation time 13815548 ps
CPU time 0.8 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 206604 kb
Host smart-8d36f02f-0d3d-4443-a39b-9c35441ec675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456553541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3456553541
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2874026902
Short name T592
Test name
Test status
Simulation time 66576493450 ps
CPU time 120.45 seconds
Started Aug 17 06:18:43 PM PDT 24
Finished Aug 17 06:20:44 PM PDT 24
Peak memory 237320 kb
Host smart-3e62f65b-5da4-49c8-8fad-a0a0bca33766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874026902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2874026902
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1808946586
Short name T872
Test name
Test status
Simulation time 41630045810 ps
CPU time 235.9 seconds
Started Aug 17 06:18:40 PM PDT 24
Finished Aug 17 06:22:36 PM PDT 24
Peak memory 255200 kb
Host smart-1d672bd2-7d6b-4098-84b3-1d67713a9655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808946586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1808946586
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.948794043
Short name T184
Test name
Test status
Simulation time 15811085372 ps
CPU time 220.97 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:22:26 PM PDT 24
Peak memory 263808 kb
Host smart-1839385c-e90f-42e2-a47b-027e17c91946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948794043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.948794043
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4238491456
Short name T1008
Test name
Test status
Simulation time 516559527 ps
CPU time 9.59 seconds
Started Aug 17 06:18:43 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 224708 kb
Host smart-03266d8e-3594-48b8-8f28-31999e6ea0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238491456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4238491456
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1487832090
Short name T246
Test name
Test status
Simulation time 57726953274 ps
CPU time 119.85 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:20:46 PM PDT 24
Peak memory 255324 kb
Host smart-2317d74c-a8f2-4267-92da-06844043001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487832090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1487832090
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3283794385
Short name T388
Test name
Test status
Simulation time 2225706109 ps
CPU time 6.33 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:53 PM PDT 24
Peak memory 219964 kb
Host smart-6d39e849-eabf-4fa3-8b81-ea5e46058f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283794385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3283794385
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1147515497
Short name T704
Test name
Test status
Simulation time 50640479397 ps
CPU time 91.52 seconds
Started Aug 17 06:18:43 PM PDT 24
Finished Aug 17 06:20:14 PM PDT 24
Peak memory 240312 kb
Host smart-e40fc899-945d-4826-92f2-4914177bb72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147515497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1147515497
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3449590790
Short name T910
Test name
Test status
Simulation time 931761507 ps
CPU time 3.68 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 232856 kb
Host smart-2c800861-913d-455f-9b35-a91a9f0448c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449590790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3449590790
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1628271868
Short name T200
Test name
Test status
Simulation time 6298352998 ps
CPU time 20.43 seconds
Started Aug 17 06:18:50 PM PDT 24
Finished Aug 17 06:19:10 PM PDT 24
Peak memory 232972 kb
Host smart-783dc165-93c4-4bbd-ad1b-dc998739b8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628271868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1628271868
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1921731785
Short name T944
Test name
Test status
Simulation time 237454382 ps
CPU time 5.19 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 220368 kb
Host smart-d72fbef6-87a0-41b0-a950-c3ca9691fe3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1921731785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1921731785
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1359159098
Short name T927
Test name
Test status
Simulation time 1936856055 ps
CPU time 5.88 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 216544 kb
Host smart-efa7d223-4bbf-406d-b0a1-7eb64de1b661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359159098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1359159098
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3171260934
Short name T845
Test name
Test status
Simulation time 1019204313 ps
CPU time 5.94 seconds
Started Aug 17 06:18:43 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 216460 kb
Host smart-9c1f0190-fb7c-48ec-82d4-9912293fc5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171260934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3171260934
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1043711017
Short name T563
Test name
Test status
Simulation time 341483055 ps
CPU time 1.73 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 208228 kb
Host smart-cc57b258-32f5-459e-ad86-1484a7fa74ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043711017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1043711017
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1792134011
Short name T89
Test name
Test status
Simulation time 113833171 ps
CPU time 0.81 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:18:46 PM PDT 24
Peak memory 206100 kb
Host smart-3d1ffff3-fb93-49f2-b92e-62e455694053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792134011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1792134011
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.420617978
Short name T793
Test name
Test status
Simulation time 232030329 ps
CPU time 3.58 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 232792 kb
Host smart-e6d945a6-1979-40e0-b861-3792f71179ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420617978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.420617978
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.67202011
Short name T572
Test name
Test status
Simulation time 17925183 ps
CPU time 0.72 seconds
Started Aug 17 06:18:39 PM PDT 24
Finished Aug 17 06:18:40 PM PDT 24
Peak memory 205564 kb
Host smart-5bda892b-a0e1-4bed-bee0-c7239daf6cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67202011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.67202011
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3682677612
Short name T490
Test name
Test status
Simulation time 4804777635 ps
CPU time 5.33 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 224736 kb
Host smart-b7754d69-df3f-43f0-8529-cc9abe720b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682677612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3682677612
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3402896947
Short name T717
Test name
Test status
Simulation time 18144142 ps
CPU time 0.76 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 206564 kb
Host smart-de1057a9-357e-4749-bdee-79246ef30430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402896947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3402896947
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1647014581
Short name T440
Test name
Test status
Simulation time 29501352333 ps
CPU time 161.67 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:21:26 PM PDT 24
Peak memory 257520 kb
Host smart-5f63cec4-f780-4f67-a9e2-37e94c55406a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647014581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1647014581
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3508131545
Short name T942
Test name
Test status
Simulation time 4916987169 ps
CPU time 45.52 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:19:34 PM PDT 24
Peak memory 223104 kb
Host smart-88bfcd19-ef4a-4bae-9986-949dde1dd6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508131545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3508131545
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.250188796
Short name T956
Test name
Test status
Simulation time 7629336117 ps
CPU time 116.88 seconds
Started Aug 17 06:18:49 PM PDT 24
Finished Aug 17 06:20:46 PM PDT 24
Peak memory 250348 kb
Host smart-95eb8af3-1386-45f9-a8d0-1bfbde86c4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250188796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.250188796
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1762593794
Short name T283
Test name
Test status
Simulation time 453452436 ps
CPU time 5.14 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 224644 kb
Host smart-f2388708-001b-41c4-8d83-f71494f53b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762593794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1762593794
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3644057075
Short name T893
Test name
Test status
Simulation time 4652035442 ps
CPU time 15.71 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:19:04 PM PDT 24
Peak memory 238020 kb
Host smart-48ce6182-8ecf-4069-8c38-6597aa0f9c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644057075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3644057075
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1284657581
Short name T1010
Test name
Test status
Simulation time 133251821 ps
CPU time 4.42 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 224656 kb
Host smart-ca6ad0a4-2bb7-41fe-b08a-6872619ccd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284657581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1284657581
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2791089062
Short name T506
Test name
Test status
Simulation time 482051406 ps
CPU time 12.81 seconds
Started Aug 17 06:18:42 PM PDT 24
Finished Aug 17 06:18:55 PM PDT 24
Peak memory 237632 kb
Host smart-e39c8f34-6a79-48f4-84c6-58766455ca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791089062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2791089062
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3927670916
Short name T471
Test name
Test status
Simulation time 1199268589 ps
CPU time 3.43 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:48 PM PDT 24
Peak memory 224676 kb
Host smart-0d7df1e1-ed1a-42bf-9bca-7af00f7f5fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927670916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3927670916
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.674930730
Short name T457
Test name
Test status
Simulation time 1020235841 ps
CPU time 2.64 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 224588 kb
Host smart-d490888e-00a4-47e3-a269-38dabc0ec3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674930730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.674930730
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.382361592
Short name T913
Test name
Test status
Simulation time 255747288 ps
CPU time 4.13 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 223272 kb
Host smart-4dcf6fb1-0fd4-4b45-bd21-f2cc09539b26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=382361592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.382361592
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.676083185
Short name T209
Test name
Test status
Simulation time 1527174169 ps
CPU time 19.03 seconds
Started Aug 17 06:18:53 PM PDT 24
Finished Aug 17 06:19:12 PM PDT 24
Peak memory 249332 kb
Host smart-883e359e-e141-4488-9cae-9a6cea175d01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676083185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.676083185
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2406530460
Short name T1000
Test name
Test status
Simulation time 12972438687 ps
CPU time 21.66 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:19:08 PM PDT 24
Peak memory 216564 kb
Host smart-4cf2239a-b5ff-483c-80e5-3087c14b7405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406530460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2406530460
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3237252998
Short name T706
Test name
Test status
Simulation time 35103103321 ps
CPU time 19.21 seconds
Started Aug 17 06:18:43 PM PDT 24
Finished Aug 17 06:19:02 PM PDT 24
Peak memory 216516 kb
Host smart-3ed0f58f-5344-4f61-8a35-187c355d1fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237252998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3237252998
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2140427979
Short name T597
Test name
Test status
Simulation time 17467444 ps
CPU time 0.81 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 206108 kb
Host smart-37cf3ca8-9861-43cf-9508-b2a9b5d1b74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140427979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2140427979
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2770645428
Short name T707
Test name
Test status
Simulation time 93944381 ps
CPU time 0.83 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 206132 kb
Host smart-a9bde97f-c651-467c-abb6-b3d4768d5e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770645428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2770645428
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.546564186
Short name T195
Test name
Test status
Simulation time 605757762 ps
CPU time 8.94 seconds
Started Aug 17 06:18:51 PM PDT 24
Finished Aug 17 06:19:00 PM PDT 24
Peak memory 232828 kb
Host smart-500a5938-be05-48c2-98fe-1e18b0997573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546564186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.546564186
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3538671763
Short name T629
Test name
Test status
Simulation time 11036604 ps
CPU time 0.7 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 205480 kb
Host smart-672013fa-6c55-42c5-a1ba-becfc1aea9c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538671763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3538671763
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.204216433
Short name T220
Test name
Test status
Simulation time 1589299351 ps
CPU time 13.41 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:19:02 PM PDT 24
Peak memory 232836 kb
Host smart-d053df1f-af95-4c2c-a1e7-412576101039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204216433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.204216433
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2037753
Short name T703
Test name
Test status
Simulation time 15336358 ps
CPU time 0.76 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:18:48 PM PDT 24
Peak memory 206920 kb
Host smart-8912af0d-6358-4ab5-a96f-168f98e51fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2037753
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1958134784
Short name T972
Test name
Test status
Simulation time 330114234977 ps
CPU time 356.41 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:24:44 PM PDT 24
Peak memory 253452 kb
Host smart-d6edb972-d38f-4d18-8dfc-0660c4109baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958134784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1958134784
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1537511509
Short name T198
Test name
Test status
Simulation time 33589004630 ps
CPU time 318.53 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:24:03 PM PDT 24
Peak memory 255540 kb
Host smart-9ef2541a-9bd0-4970-a1aa-0e9f6ef73721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537511509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1537511509
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3560445098
Short name T938
Test name
Test status
Simulation time 35005448672 ps
CPU time 27.28 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:19:13 PM PDT 24
Peak memory 226704 kb
Host smart-cbe346a7-a27d-406d-bc4b-7485f3b7300c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560445098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3560445098
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2831941563
Short name T173
Test name
Test status
Simulation time 44131374237 ps
CPU time 113.51 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:20:40 PM PDT 24
Peak memory 252596 kb
Host smart-e5a6fbc3-d204-489a-9feb-81936322a42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831941563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2831941563
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4286744270
Short name T204
Test name
Test status
Simulation time 1163794943 ps
CPU time 4.76 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 224684 kb
Host smart-c68c91fc-e171-4fbe-8bd3-92c915831fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286744270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4286744270
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2727465017
Short name T1011
Test name
Test status
Simulation time 28024683475 ps
CPU time 59.69 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:19:45 PM PDT 24
Peak memory 232964 kb
Host smart-2b5c8db2-d94a-4884-9fdc-b9a071705d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727465017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2727465017
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1327382308
Short name T862
Test name
Test status
Simulation time 4114000919 ps
CPU time 8.33 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:54 PM PDT 24
Peak memory 232912 kb
Host smart-fdc270e6-ae7a-4ed4-89b0-7ed4b671d796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327382308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1327382308
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1271666132
Short name T234
Test name
Test status
Simulation time 434875313 ps
CPU time 3.24 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 224676 kb
Host smart-f3398c7f-1a6b-46e7-8a34-a94f0906f6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271666132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1271666132
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1891109950
Short name T781
Test name
Test status
Simulation time 331501361 ps
CPU time 6.37 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:18:55 PM PDT 24
Peak memory 222700 kb
Host smart-cac5ed3d-d9ec-4cd1-bd7d-a4c535c11121
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1891109950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1891109950
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1799554650
Short name T489
Test name
Test status
Simulation time 217610193 ps
CPU time 1.03 seconds
Started Aug 17 06:18:50 PM PDT 24
Finished Aug 17 06:18:51 PM PDT 24
Peak memory 206632 kb
Host smart-d27b3b8b-f3da-4ec4-a32f-77eba0ba1d0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799554650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1799554650
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1855143036
Short name T766
Test name
Test status
Simulation time 1738824184 ps
CPU time 8.91 seconds
Started Aug 17 06:18:42 PM PDT 24
Finished Aug 17 06:18:51 PM PDT 24
Peak memory 216516 kb
Host smart-dc1241d6-3693-4165-8ea8-40315ac0ae7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855143036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1855143036
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3243416206
Short name T452
Test name
Test status
Simulation time 16943240349 ps
CPU time 12.13 seconds
Started Aug 17 06:18:49 PM PDT 24
Finished Aug 17 06:19:01 PM PDT 24
Peak memory 216608 kb
Host smart-cc294e2b-bb2a-41b8-be00-b4862be877a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243416206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3243416206
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3957491433
Short name T919
Test name
Test status
Simulation time 186055075 ps
CPU time 1.46 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 216448 kb
Host smart-e2a6da24-6945-4444-be5a-030cc239d2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957491433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3957491433
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2704461264
Short name T984
Test name
Test status
Simulation time 86152504 ps
CPU time 1.03 seconds
Started Aug 17 06:18:49 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 206100 kb
Host smart-87242d22-d48f-4936-9d35-a3b49d9966c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704461264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2704461264
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3054883883
Short name T633
Test name
Test status
Simulation time 564637575 ps
CPU time 4 seconds
Started Aug 17 06:18:52 PM PDT 24
Finished Aug 17 06:18:56 PM PDT 24
Peak memory 224628 kb
Host smart-20f0ca8c-b3b1-4921-a3f5-81e10e3f4cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054883883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3054883883
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.945609490
Short name T968
Test name
Test status
Simulation time 38204882 ps
CPU time 0.76 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:18:45 PM PDT 24
Peak memory 204868 kb
Host smart-92c925b8-b865-499f-b341-0239e5cb0321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945609490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.945609490
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3983548562
Short name T878
Test name
Test status
Simulation time 1028770560 ps
CPU time 12.8 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:19:01 PM PDT 24
Peak memory 232888 kb
Host smart-4dff09a4-8d60-4e53-a2d4-b3a2472456cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983548562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3983548562
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1408171474
Short name T882
Test name
Test status
Simulation time 14599603 ps
CPU time 0.8 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 206588 kb
Host smart-dad24b93-d456-48e2-9db6-f36598e8f7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408171474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1408171474
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2294168426
Short name T537
Test name
Test status
Simulation time 18474094100 ps
CPU time 33.02 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:19:19 PM PDT 24
Peak memory 224804 kb
Host smart-e33d20f4-633f-441f-a23e-6a0555ef8f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294168426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2294168426
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.986206749
Short name T682
Test name
Test status
Simulation time 31257540130 ps
CPU time 282.06 seconds
Started Aug 17 06:18:40 PM PDT 24
Finished Aug 17 06:23:22 PM PDT 24
Peak memory 266512 kb
Host smart-956d36a3-f246-4261-aedd-61ca04ae4f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986206749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.986206749
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2212092914
Short name T285
Test name
Test status
Simulation time 113475453 ps
CPU time 3.8 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:18:51 PM PDT 24
Peak memory 224632 kb
Host smart-a426fef7-52c7-4f65-b610-1c83696ea2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212092914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2212092914
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.922343208
Short name T971
Test name
Test status
Simulation time 48114658194 ps
CPU time 177.31 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:21:45 PM PDT 24
Peak memory 249376 kb
Host smart-0f65c258-cd82-4d29-83b4-a418ff862463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922343208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.922343208
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2881836271
Short name T981
Test name
Test status
Simulation time 265948875 ps
CPU time 2.56 seconds
Started Aug 17 06:18:50 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 232896 kb
Host smart-ac454c54-b3bd-4433-8b66-672a6095b60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881836271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2881836271
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2631549180
Short name T242
Test name
Test status
Simulation time 160112896 ps
CPU time 3.07 seconds
Started Aug 17 06:18:53 PM PDT 24
Finished Aug 17 06:18:56 PM PDT 24
Peak memory 232848 kb
Host smart-0f401daa-6b0c-41bf-b2fb-5d1441492e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631549180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2631549180
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2584704575
Short name T642
Test name
Test status
Simulation time 113524933 ps
CPU time 3.18 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 232896 kb
Host smart-05d47b6b-b376-4b99-adff-bd09940e5307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584704575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2584704575
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1405386817
Short name T873
Test name
Test status
Simulation time 443050614 ps
CPU time 3.36 seconds
Started Aug 17 06:18:54 PM PDT 24
Finished Aug 17 06:18:57 PM PDT 24
Peak memory 224616 kb
Host smart-bb66407c-09e4-49b5-a039-234e64de18cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405386817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1405386817
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1425992978
Short name T770
Test name
Test status
Simulation time 2854091657 ps
CPU time 5.78 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 219060 kb
Host smart-b9377bf3-204a-4466-ae16-b8dd7364d158
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1425992978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1425992978
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.128881356
Short name T658
Test name
Test status
Simulation time 47115286693 ps
CPU time 190.31 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:21:54 PM PDT 24
Peak memory 265832 kb
Host smart-6b9a9ccc-5fe0-4937-b319-c880c663779c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128881356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.128881356
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.998702295
Short name T820
Test name
Test status
Simulation time 1295758266 ps
CPU time 6.68 seconds
Started Aug 17 06:18:45 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 216844 kb
Host smart-be52b7fd-6d59-4166-a729-da986a98e996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998702295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.998702295
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1620113773
Short name T60
Test name
Test status
Simulation time 15780285298 ps
CPU time 14.72 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:19:02 PM PDT 24
Peak memory 216168 kb
Host smart-d21af52f-499f-4ac9-90fa-0d4fcb3e799f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620113773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1620113773
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3875970073
Short name T660
Test name
Test status
Simulation time 119519327 ps
CPU time 1.78 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 216488 kb
Host smart-7571b33a-6607-460b-b890-b32d334bdc4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875970073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3875970073
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3447071509
Short name T332
Test name
Test status
Simulation time 68670150 ps
CPU time 0.94 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:48 PM PDT 24
Peak memory 206148 kb
Host smart-48d067c0-351e-4480-b751-c02e7934a1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447071509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3447071509
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3334556774
Short name T701
Test name
Test status
Simulation time 7911552740 ps
CPU time 14.81 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:18:59 PM PDT 24
Peak memory 224636 kb
Host smart-283076d2-d397-4317-9025-e43f60752a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334556774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3334556774
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2994391016
Short name T908
Test name
Test status
Simulation time 11787983 ps
CPU time 0.71 seconds
Started Aug 17 06:18:55 PM PDT 24
Finished Aug 17 06:18:56 PM PDT 24
Peak memory 205552 kb
Host smart-f2191efd-aaa5-4244-90c1-b0a5869b8ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994391016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2994391016
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2425224717
Short name T761
Test name
Test status
Simulation time 441592953 ps
CPU time 3.93 seconds
Started Aug 17 06:18:51 PM PDT 24
Finished Aug 17 06:18:56 PM PDT 24
Peak memory 232744 kb
Host smart-43e2d45f-65db-4343-9c18-87430eaf9574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425224717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2425224717
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3504071067
Short name T734
Test name
Test status
Simulation time 16680570 ps
CPU time 0.8 seconds
Started Aug 17 06:18:51 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 206528 kb
Host smart-8052d991-9b20-4891-8837-f20247a2e028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504071067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3504071067
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2763678810
Short name T755
Test name
Test status
Simulation time 7972731832 ps
CPU time 27.99 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:19:15 PM PDT 24
Peak memory 237276 kb
Host smart-3ef5b142-6276-4787-8913-91751a956b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763678810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2763678810
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4215483957
Short name T865
Test name
Test status
Simulation time 3562787225 ps
CPU time 46.4 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:19:33 PM PDT 24
Peak memory 249536 kb
Host smart-0a635740-e58d-43fc-aee5-49d6c9758f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215483957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4215483957
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.177357835
Short name T278
Test name
Test status
Simulation time 124469006 ps
CPU time 4.43 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 224624 kb
Host smart-2a6ad04c-2c5e-46d9-beaf-9406f62fd85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177357835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.177357835
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3033095072
Short name T922
Test name
Test status
Simulation time 2721940497 ps
CPU time 17.52 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:19:05 PM PDT 24
Peak memory 236464 kb
Host smart-27fa78ec-36ae-41a3-b01b-4845d0c75c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033095072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3033095072
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2754594346
Short name T763
Test name
Test status
Simulation time 394278495 ps
CPU time 3.4 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 224624 kb
Host smart-52ad90cb-ba3f-4532-8481-185fd9e868e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754594346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2754594346
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.607739327
Short name T205
Test name
Test status
Simulation time 123335617 ps
CPU time 4 seconds
Started Aug 17 06:18:54 PM PDT 24
Finished Aug 17 06:18:58 PM PDT 24
Peak memory 232796 kb
Host smart-7047a247-a52c-4674-8d5f-13f9b4e85176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607739327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.607739327
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.217659202
Short name T277
Test name
Test status
Simulation time 407199749 ps
CPU time 7.58 seconds
Started Aug 17 06:18:51 PM PDT 24
Finished Aug 17 06:18:58 PM PDT 24
Peak memory 233752 kb
Host smart-2d9fcb09-71ac-4e28-8473-a3681d904ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217659202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.217659202
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3169529314
Short name T416
Test name
Test status
Simulation time 22860204730 ps
CPU time 29.75 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:19:18 PM PDT 24
Peak memory 223660 kb
Host smart-6f232905-970f-4429-b004-9181c2b0bbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169529314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3169529314
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2093033513
Short name T615
Test name
Test status
Simulation time 1751037089 ps
CPU time 5.72 seconds
Started Aug 17 06:18:51 PM PDT 24
Finished Aug 17 06:18:57 PM PDT 24
Peak memory 220408 kb
Host smart-0a1f188d-f456-461c-9b7b-bdaa0de9313a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2093033513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2093033513
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1051684296
Short name T186
Test name
Test status
Simulation time 5076591531 ps
CPU time 111.68 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:20:39 PM PDT 24
Peak memory 272464 kb
Host smart-24a0506b-8fcc-44ca-bdfa-d8f124c1afe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051684296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1051684296
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3765105834
Short name T536
Test name
Test status
Simulation time 9148104188 ps
CPU time 46.38 seconds
Started Aug 17 06:18:47 PM PDT 24
Finished Aug 17 06:19:34 PM PDT 24
Peak memory 215440 kb
Host smart-47eaff59-7639-43cb-b7f8-6759a154cad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765105834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3765105834
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3049854060
Short name T345
Test name
Test status
Simulation time 4303994585 ps
CPU time 12.53 seconds
Started Aug 17 06:19:32 PM PDT 24
Finished Aug 17 06:19:44 PM PDT 24
Peak memory 216296 kb
Host smart-98b79889-57c7-4817-b137-29b2bd4c12fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049854060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3049854060
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.708615495
Short name T975
Test name
Test status
Simulation time 38641882 ps
CPU time 0.74 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 206108 kb
Host smart-7d06b289-02d5-4ae7-b315-566cd129a8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708615495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.708615495
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.316175821
Short name T573
Test name
Test status
Simulation time 222513152 ps
CPU time 0.73 seconds
Started Aug 17 06:18:49 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 206128 kb
Host smart-70a5d5dc-9419-4878-a507-154522342463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316175821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.316175821
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.688040509
Short name T594
Test name
Test status
Simulation time 72056917 ps
CPU time 2.35 seconds
Started Aug 17 06:18:44 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 232840 kb
Host smart-1505bd92-5fbb-4b6d-b1ab-6359da58a972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688040509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.688040509
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1037286535
Short name T3
Test name
Test status
Simulation time 188054509 ps
CPU time 0.74 seconds
Started Aug 17 06:18:54 PM PDT 24
Finished Aug 17 06:19:00 PM PDT 24
Peak memory 205556 kb
Host smart-ce3f60ce-453c-4b3d-9133-32d9d6d29d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037286535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1037286535
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2452980108
Short name T127
Test name
Test status
Simulation time 244090309 ps
CPU time 5.85 seconds
Started Aug 17 06:18:58 PM PDT 24
Finished Aug 17 06:19:04 PM PDT 24
Peak memory 232828 kb
Host smart-938f0882-eb3b-4bc1-bb80-d33d18d9a5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452980108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2452980108
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3841782326
Short name T344
Test name
Test status
Simulation time 36451539 ps
CPU time 0.81 seconds
Started Aug 17 06:18:50 PM PDT 24
Finished Aug 17 06:18:51 PM PDT 24
Peak memory 206600 kb
Host smart-e2bd1c74-1c70-42a6-8a22-2b903852a2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841782326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3841782326
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.810931596
Short name T210
Test name
Test status
Simulation time 104563147381 ps
CPU time 214.32 seconds
Started Aug 17 06:18:56 PM PDT 24
Finished Aug 17 06:22:30 PM PDT 24
Peak memory 263620 kb
Host smart-18730e0b-c923-4e2c-9329-89e60d846d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810931596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.810931596
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.150041582
Short name T291
Test name
Test status
Simulation time 84451137472 ps
CPU time 59.93 seconds
Started Aug 17 06:18:55 PM PDT 24
Finished Aug 17 06:19:55 PM PDT 24
Peak memory 239056 kb
Host smart-1c70d732-d218-4904-99d7-af3ca7d86b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150041582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.150041582
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3658977531
Short name T530
Test name
Test status
Simulation time 24503472154 ps
CPU time 50.19 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:19:38 PM PDT 24
Peak memory 249448 kb
Host smart-d168978c-9713-480f-8c53-20518e5e6476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658977531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3658977531
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.743284417
Short name T389
Test name
Test status
Simulation time 2837433607 ps
CPU time 12.45 seconds
Started Aug 17 06:18:49 PM PDT 24
Finished Aug 17 06:19:02 PM PDT 24
Peak memory 235172 kb
Host smart-3a6ffcb8-f853-4b91-8838-bf2ac4e419d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743284417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.743284417
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1216453107
Short name T880
Test name
Test status
Simulation time 701061493 ps
CPU time 5.45 seconds
Started Aug 17 06:18:55 PM PDT 24
Finished Aug 17 06:19:00 PM PDT 24
Peak memory 224708 kb
Host smart-5eff13b3-c36b-4060-af43-4b23f7dfc446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216453107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1216453107
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.323124266
Short name T849
Test name
Test status
Simulation time 113789919 ps
CPU time 2.17 seconds
Started Aug 17 06:18:52 PM PDT 24
Finished Aug 17 06:18:54 PM PDT 24
Peak memory 224032 kb
Host smart-5ba063e0-a6ce-4369-8011-c1645b15ff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323124266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.323124266
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2637575811
Short name T1014
Test name
Test status
Simulation time 913566148 ps
CPU time 9.02 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:18:57 PM PDT 24
Peak memory 232868 kb
Host smart-aaf441fb-63af-43e1-ba94-bf49dcf6e447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637575811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2637575811
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2849038289
Short name T240
Test name
Test status
Simulation time 3112948601 ps
CPU time 12.65 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:19:01 PM PDT 24
Peak memory 224680 kb
Host smart-38d61643-ddc3-4b1d-a849-49749f4ea362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849038289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2849038289
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1273633687
Short name T997
Test name
Test status
Simulation time 337674932 ps
CPU time 3.59 seconds
Started Aug 17 06:18:49 PM PDT 24
Finished Aug 17 06:18:52 PM PDT 24
Peak memory 232872 kb
Host smart-6ad73fa5-eba4-4d2d-977a-11448e5ad4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273633687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1273633687
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3001506311
Short name T142
Test name
Test status
Simulation time 783711103 ps
CPU time 4.95 seconds
Started Aug 17 06:18:51 PM PDT 24
Finished Aug 17 06:18:56 PM PDT 24
Peak memory 223144 kb
Host smart-781d0e2f-8712-4973-a3ed-d02bde40db42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3001506311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3001506311
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.158294957
Short name T869
Test name
Test status
Simulation time 174315000995 ps
CPU time 395.44 seconds
Started Aug 17 06:18:53 PM PDT 24
Finished Aug 17 06:25:28 PM PDT 24
Peak memory 265800 kb
Host smart-c9e8ac13-d888-4648-9c91-d8e678977095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158294957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.158294957
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1658886237
Short name T1004
Test name
Test status
Simulation time 28118608685 ps
CPU time 21.86 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:19:10 PM PDT 24
Peak memory 216672 kb
Host smart-d3061479-386c-4585-b4e6-083bb9e5aff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658886237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1658886237
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.240393264
Short name T923
Test name
Test status
Simulation time 1030432527 ps
CPU time 2.06 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:18:50 PM PDT 24
Peak memory 216468 kb
Host smart-b77c2c04-e202-4f68-816d-d849f8ee4780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240393264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.240393264
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2136479445
Short name T1016
Test name
Test status
Simulation time 188978016 ps
CPU time 2.75 seconds
Started Aug 17 06:18:52 PM PDT 24
Finished Aug 17 06:18:55 PM PDT 24
Peak memory 216528 kb
Host smart-df1c78a9-6bc5-4c72-829f-b5d94d5df39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136479445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2136479445
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3603590296
Short name T569
Test name
Test status
Simulation time 109180713 ps
CPU time 0.88 seconds
Started Aug 17 06:18:54 PM PDT 24
Finished Aug 17 06:18:55 PM PDT 24
Peak memory 207160 kb
Host smart-4a1ced6b-3652-43a7-bb27-951c1560c284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603590296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3603590296
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1045534493
Short name T606
Test name
Test status
Simulation time 516890836 ps
CPU time 7.8 seconds
Started Aug 17 06:18:49 PM PDT 24
Finished Aug 17 06:18:57 PM PDT 24
Peak memory 224692 kb
Host smart-ee711655-73dc-470a-ab7c-e34e0b8c8e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045534493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1045534493
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1964089387
Short name T918
Test name
Test status
Simulation time 24145318 ps
CPU time 0.74 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:19:00 PM PDT 24
Peak memory 204916 kb
Host smart-1bf62522-0db8-4f2c-b42f-254d4b113a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964089387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1964089387
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2767640114
Short name T958
Test name
Test status
Simulation time 1170928282 ps
CPU time 6.55 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:19:07 PM PDT 24
Peak memory 224580 kb
Host smart-007d7565-4892-4673-8e0e-0eae5313a3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767640114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2767640114
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3294452199
Short name T782
Test name
Test status
Simulation time 13106924 ps
CPU time 0.74 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:47 PM PDT 24
Peak memory 206948 kb
Host smart-97a27664-9339-432e-8f42-238297ec39aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294452199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3294452199
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3727668040
Short name T698
Test name
Test status
Simulation time 11332120 ps
CPU time 0.76 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:19:01 PM PDT 24
Peak memory 215880 kb
Host smart-a1e9750b-6d19-4492-8993-0c3076db4ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727668040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3727668040
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1357351223
Short name T172
Test name
Test status
Simulation time 25053642266 ps
CPU time 264.9 seconds
Started Aug 17 06:18:55 PM PDT 24
Finished Aug 17 06:23:20 PM PDT 24
Peak memory 253956 kb
Host smart-8c41f271-5ccf-4a50-92cb-7c485f0e4427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357351223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1357351223
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.214803050
Short name T595
Test name
Test status
Simulation time 185700310 ps
CPU time 4.89 seconds
Started Aug 17 06:18:56 PM PDT 24
Finished Aug 17 06:19:01 PM PDT 24
Peak memory 235020 kb
Host smart-77cdd110-838c-4485-8ec3-e4f3217bf644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214803050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.214803050
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.532707331
Short name T749
Test name
Test status
Simulation time 8160221404 ps
CPU time 13.44 seconds
Started Aug 17 06:18:57 PM PDT 24
Finished Aug 17 06:19:10 PM PDT 24
Peak memory 241152 kb
Host smart-28193a43-306c-49f5-8b6a-d6d0c677dcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532707331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.532707331
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2187304988
Short name T590
Test name
Test status
Simulation time 20930563436 ps
CPU time 115.21 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:20:55 PM PDT 24
Peak memory 249372 kb
Host smart-605bf782-ef38-4623-887e-ad3f1a3e05d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187304988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2187304988
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1650785649
Short name T514
Test name
Test status
Simulation time 2350741309 ps
CPU time 10.82 seconds
Started Aug 17 06:18:53 PM PDT 24
Finished Aug 17 06:19:04 PM PDT 24
Peak memory 224664 kb
Host smart-70ed2177-81be-4371-9a07-0f2a22107eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650785649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1650785649
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4190712210
Short name T196
Test name
Test status
Simulation time 68875650949 ps
CPU time 92.94 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:20:21 PM PDT 24
Peak memory 232980 kb
Host smart-56c11924-780f-40c0-b710-bff5cbf66546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190712210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4190712210
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1334935158
Short name T801
Test name
Test status
Simulation time 1846428620 ps
CPU time 7.11 seconds
Started Aug 17 06:18:51 PM PDT 24
Finished Aug 17 06:18:58 PM PDT 24
Peak memory 224592 kb
Host smart-63cc8f5c-61f6-4017-ac9e-ca3e155d6975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334935158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1334935158
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2755388581
Short name T783
Test name
Test status
Simulation time 1324071123 ps
CPU time 5.44 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:18:51 PM PDT 24
Peak memory 224640 kb
Host smart-517cefe5-f7dd-4b92-97a0-83108b7b1f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755388581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2755388581
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3919275772
Short name T459
Test name
Test status
Simulation time 2092659768 ps
CPU time 6.86 seconds
Started Aug 17 06:19:02 PM PDT 24
Finished Aug 17 06:19:09 PM PDT 24
Peak memory 219064 kb
Host smart-46c5425c-08b0-46f6-a3cf-09dd19aaccb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3919275772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3919275772
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3407805789
Short name T31
Test name
Test status
Simulation time 58268175 ps
CPU time 1.08 seconds
Started Aug 17 06:18:57 PM PDT 24
Finished Aug 17 06:18:59 PM PDT 24
Peak memory 207616 kb
Host smart-017372e1-327f-47c7-a1b1-70367b328adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407805789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3407805789
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.284584132
Short name T290
Test name
Test status
Simulation time 7880665643 ps
CPU time 49.02 seconds
Started Aug 17 06:18:51 PM PDT 24
Finished Aug 17 06:19:40 PM PDT 24
Peak memory 216576 kb
Host smart-1fe512fb-6c77-41f3-a81a-ddf51a5cd3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284584132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.284584132
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3206075128
Short name T526
Test name
Test status
Simulation time 1484286859 ps
CPU time 3.93 seconds
Started Aug 17 06:18:49 PM PDT 24
Finished Aug 17 06:18:54 PM PDT 24
Peak memory 216436 kb
Host smart-1fff4970-29dc-4cde-8b50-19d33540395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206075128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3206075128
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3532429833
Short name T493
Test name
Test status
Simulation time 25925563 ps
CPU time 0.79 seconds
Started Aug 17 06:18:50 PM PDT 24
Finished Aug 17 06:18:51 PM PDT 24
Peak memory 206588 kb
Host smart-f5337ba6-104d-4648-844d-f17cd6561399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532429833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3532429833
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.384676051
Short name T423
Test name
Test status
Simulation time 12228470 ps
CPU time 0.73 seconds
Started Aug 17 06:18:48 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 205608 kb
Host smart-4c03a8aa-b16f-45fa-b0da-2c98baaed6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384676051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.384676051
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3010089464
Short name T565
Test name
Test status
Simulation time 6136591721 ps
CPU time 19.61 seconds
Started Aug 17 06:18:46 PM PDT 24
Finished Aug 17 06:19:06 PM PDT 24
Peak memory 232948 kb
Host smart-f1e3e5f2-6dd6-4ab4-8747-daac7d5c4ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010089464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3010089464
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4145098865
Short name T331
Test name
Test status
Simulation time 23813348 ps
CPU time 0.7 seconds
Started Aug 17 06:18:57 PM PDT 24
Finished Aug 17 06:18:58 PM PDT 24
Peak memory 204952 kb
Host smart-a528fdfe-53b4-4d6a-b2d9-ccc844960928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145098865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4145098865
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1116627950
Short name T668
Test name
Test status
Simulation time 4203012815 ps
CPU time 9.28 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:19:08 PM PDT 24
Peak memory 232908 kb
Host smart-36ff6649-f3ea-4f49-b7a1-6cce84d41fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116627950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1116627950
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2932443271
Short name T496
Test name
Test status
Simulation time 20876956 ps
CPU time 0.81 seconds
Started Aug 17 06:19:01 PM PDT 24
Finished Aug 17 06:19:02 PM PDT 24
Peak memory 207004 kb
Host smart-3f9ef98a-880d-42b5-abbe-9ee0941ac01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932443271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2932443271
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2315285291
Short name T261
Test name
Test status
Simulation time 295029439732 ps
CPU time 514.12 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:27:34 PM PDT 24
Peak memory 249376 kb
Host smart-83ef2cb7-9baf-45fd-924c-26ecbae6963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315285291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2315285291
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2292517639
Short name T217
Test name
Test status
Simulation time 67099852842 ps
CPU time 321.79 seconds
Started Aug 17 06:18:57 PM PDT 24
Finished Aug 17 06:24:19 PM PDT 24
Peak memory 268284 kb
Host smart-8afdef75-7dcb-4cc3-aa20-1d07201f3f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292517639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2292517639
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2251809449
Short name T343
Test name
Test status
Simulation time 8940705327 ps
CPU time 12.92 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:19:12 PM PDT 24
Peak memory 224780 kb
Host smart-fa2eeb53-f42a-45b0-b7c5-b82e757f0ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251809449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2251809449
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1064233991
Short name T603
Test name
Test status
Simulation time 3511875878 ps
CPU time 26.54 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:19:25 PM PDT 24
Peak memory 235728 kb
Host smart-044ed6c3-9ffb-4ac0-b1c6-9a74481ff382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064233991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1064233991
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1202687157
Short name T372
Test name
Test status
Simulation time 299732313 ps
CPU time 3.92 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:19:03 PM PDT 24
Peak memory 232892 kb
Host smart-8406adec-0ea9-4c07-bce5-d359a2fbe505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202687157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1202687157
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3405695745
Short name T909
Test name
Test status
Simulation time 15562649511 ps
CPU time 36.43 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:19:36 PM PDT 24
Peak memory 230956 kb
Host smart-f964e64b-7da9-4e7f-b8f9-ef17b1220a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405695745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3405695745
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1426973333
Short name T964
Test name
Test status
Simulation time 5495839560 ps
CPU time 10.59 seconds
Started Aug 17 06:18:57 PM PDT 24
Finished Aug 17 06:19:08 PM PDT 24
Peak memory 232968 kb
Host smart-5d5019e3-fbd2-45ae-97db-5f22d55479c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426973333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1426973333
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3138544728
Short name T967
Test name
Test status
Simulation time 430987233 ps
CPU time 2.62 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:19:02 PM PDT 24
Peak memory 224664 kb
Host smart-5a219ad6-4907-47da-9df7-3be83ab0decd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138544728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3138544728
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3183218872
Short name T364
Test name
Test status
Simulation time 439460753 ps
CPU time 4.59 seconds
Started Aug 17 06:19:03 PM PDT 24
Finished Aug 17 06:19:07 PM PDT 24
Peak memory 223132 kb
Host smart-cfbd1191-5862-465a-8b86-2dcb0a7ac890
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3183218872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3183218872
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.4103623234
Short name T983
Test name
Test status
Simulation time 141284539709 ps
CPU time 196.27 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:22:15 PM PDT 24
Peak memory 264180 kb
Host smart-721b95fa-a21f-47ac-adad-91c59173a5a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103623234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.4103623234
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2656685286
Short name T670
Test name
Test status
Simulation time 11664406413 ps
CPU time 18.5 seconds
Started Aug 17 06:18:56 PM PDT 24
Finished Aug 17 06:19:15 PM PDT 24
Peak memory 216612 kb
Host smart-90c9e79d-e284-4f7e-8545-8cf038d73930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656685286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2656685286
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2904776706
Short name T912
Test name
Test status
Simulation time 12629898 ps
CPU time 0.71 seconds
Started Aug 17 06:18:57 PM PDT 24
Finished Aug 17 06:18:58 PM PDT 24
Peak memory 205644 kb
Host smart-a7cf31e8-5146-461d-a1dd-fba5e97f8740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904776706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2904776706
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.545700365
Short name T811
Test name
Test status
Simulation time 259974480 ps
CPU time 1.34 seconds
Started Aug 17 06:19:01 PM PDT 24
Finished Aug 17 06:19:03 PM PDT 24
Peak memory 216572 kb
Host smart-de8b12c3-98cc-4f70-9b61-b730563520b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545700365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.545700365
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2774149535
Short name T382
Test name
Test status
Simulation time 51040219 ps
CPU time 0.91 seconds
Started Aug 17 06:19:02 PM PDT 24
Finished Aug 17 06:19:03 PM PDT 24
Peak memory 207092 kb
Host smart-89a83cdf-a318-417d-bcaf-8959a5561a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774149535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2774149535
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2295578285
Short name T417
Test name
Test status
Simulation time 66348194 ps
CPU time 2.52 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:19:02 PM PDT 24
Peak memory 232480 kb
Host smart-d87dc4ae-55ef-4980-b37c-e1484633565b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295578285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2295578285
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.100754351
Short name T363
Test name
Test status
Simulation time 34493103 ps
CPU time 0.75 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:19:00 PM PDT 24
Peak memory 205548 kb
Host smart-7bc3c679-de41-4e6d-88cc-d9945aeac500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100754351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.100754351
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.986299794
Short name T630
Test name
Test status
Simulation time 619186707 ps
CPU time 3.84 seconds
Started Aug 17 06:18:57 PM PDT 24
Finished Aug 17 06:19:01 PM PDT 24
Peak memory 224632 kb
Host smart-955ce035-83c9-4b3f-8324-4c10738632e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986299794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.986299794
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1063219086
Short name T76
Test name
Test status
Simulation time 47579271 ps
CPU time 0.74 seconds
Started Aug 17 06:19:04 PM PDT 24
Finished Aug 17 06:19:04 PM PDT 24
Peak memory 205536 kb
Host smart-3e0b3130-2ab0-40ed-a623-de32b54bd4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063219086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1063219086
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1050816710
Short name T208
Test name
Test status
Simulation time 19749782650 ps
CPU time 148.53 seconds
Started Aug 17 06:19:04 PM PDT 24
Finished Aug 17 06:21:33 PM PDT 24
Peak memory 255604 kb
Host smart-18780fe4-9a46-467a-bbbc-c072fb66e825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050816710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1050816710
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.4108577905
Short name T130
Test name
Test status
Simulation time 25662923993 ps
CPU time 218.6 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:22:38 PM PDT 24
Peak memory 254184 kb
Host smart-229aadda-5410-42f3-82c2-0c1156cffbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108577905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.4108577905
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2193693485
Short name T400
Test name
Test status
Simulation time 17725834736 ps
CPU time 67.57 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:20:06 PM PDT 24
Peak memory 232984 kb
Host smart-b61a9cdb-623d-4574-9a74-8bbfcc20075a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193693485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2193693485
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1237197167
Short name T50
Test name
Test status
Simulation time 1264311704 ps
CPU time 16.39 seconds
Started Aug 17 06:19:04 PM PDT 24
Finished Aug 17 06:19:20 PM PDT 24
Peak memory 239772 kb
Host smart-28952727-3b48-4fb3-b3a9-f4e5fb14a741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237197167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1237197167
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1296358148
Short name T813
Test name
Test status
Simulation time 2754367594 ps
CPU time 23.86 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:19:24 PM PDT 24
Peak memory 224732 kb
Host smart-8c50ce44-6a60-467b-9b98-eed22a4d1da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296358148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1296358148
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3776824559
Short name T758
Test name
Test status
Simulation time 7139037519 ps
CPU time 17.93 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:19:18 PM PDT 24
Peak memory 232992 kb
Host smart-c365578e-fc09-4581-94c3-1ea425304257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776824559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3776824559
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3327261413
Short name T959
Test name
Test status
Simulation time 2559412032 ps
CPU time 5.2 seconds
Started Aug 17 06:18:56 PM PDT 24
Finished Aug 17 06:19:01 PM PDT 24
Peak memory 224716 kb
Host smart-f51b90b7-fa26-41b0-bac2-3b0ae2f874be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327261413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3327261413
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.615535834
Short name T963
Test name
Test status
Simulation time 2227033055 ps
CPU time 11.23 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:19:10 PM PDT 24
Peak memory 248876 kb
Host smart-4b8f7d0d-3d11-469f-8ff0-411029a49a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615535834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.615535834
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3442085776
Short name T730
Test name
Test status
Simulation time 470399109 ps
CPU time 4.09 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:19:04 PM PDT 24
Peak memory 223212 kb
Host smart-8819f26a-080a-485d-8c60-5e5985ef1264
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3442085776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3442085776
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2028743730
Short name T148
Test name
Test status
Simulation time 189758803 ps
CPU time 1.03 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:19:01 PM PDT 24
Peak memory 207792 kb
Host smart-eb785c16-89a9-434c-b304-546ecb229a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028743730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2028743730
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1340722143
Short name T812
Test name
Test status
Simulation time 3552219206 ps
CPU time 10.31 seconds
Started Aug 17 06:18:59 PM PDT 24
Finished Aug 17 06:19:09 PM PDT 24
Peak memory 216516 kb
Host smart-dfd8b9a2-83f3-46a8-814f-03687b333952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340722143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1340722143
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3808125626
Short name T355
Test name
Test status
Simulation time 19599181783 ps
CPU time 18.28 seconds
Started Aug 17 06:18:57 PM PDT 24
Finished Aug 17 06:19:15 PM PDT 24
Peak memory 216568 kb
Host smart-c3622b01-2223-4437-834b-93d025a2a223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808125626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3808125626
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1887185161
Short name T936
Test name
Test status
Simulation time 51240295 ps
CPU time 1 seconds
Started Aug 17 06:19:03 PM PDT 24
Finished Aug 17 06:19:04 PM PDT 24
Peak memory 208108 kb
Host smart-0b83eee9-3650-4539-ab92-5b0019ccbd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887185161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1887185161
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1374261256
Short name T796
Test name
Test status
Simulation time 120017730 ps
CPU time 1.01 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:19:01 PM PDT 24
Peak memory 206144 kb
Host smart-c0471920-04e0-41d7-bf9e-575fe2ccfdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374261256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1374261256
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3494058371
Short name T191
Test name
Test status
Simulation time 28519049884 ps
CPU time 22.89 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:19:23 PM PDT 24
Peak memory 241068 kb
Host smart-bdabb4aa-3ed6-4bbc-887d-8181823f5758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494058371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3494058371
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1305847626
Short name T551
Test name
Test status
Simulation time 13702108 ps
CPU time 0.71 seconds
Started Aug 17 06:19:11 PM PDT 24
Finished Aug 17 06:19:11 PM PDT 24
Peak memory 205460 kb
Host smart-96978587-be05-4125-9a71-e4336dbb50cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305847626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1305847626
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.845375479
Short name T697
Test name
Test status
Simulation time 307167224 ps
CPU time 2.2 seconds
Started Aug 17 06:19:04 PM PDT 24
Finished Aug 17 06:19:06 PM PDT 24
Peak memory 224640 kb
Host smart-bacda254-ba52-47e0-a053-dfd9ade4a4b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845375479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.845375479
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1436675226
Short name T659
Test name
Test status
Simulation time 52397338 ps
CPU time 0.73 seconds
Started Aug 17 06:19:00 PM PDT 24
Finished Aug 17 06:19:00 PM PDT 24
Peak memory 206960 kb
Host smart-2a32d616-2cb8-4ccb-afd6-9c3342e9c53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436675226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1436675226
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.4195364591
Short name T871
Test name
Test status
Simulation time 38117272039 ps
CPU time 92 seconds
Started Aug 17 06:19:04 PM PDT 24
Finished Aug 17 06:20:36 PM PDT 24
Peak memory 249356 kb
Host smart-e6b14b77-ffff-4448-a445-b4c3e6ef0429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195364591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4195364591
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2666434880
Short name T61
Test name
Test status
Simulation time 107048694867 ps
CPU time 256.41 seconds
Started Aug 17 06:19:04 PM PDT 24
Finished Aug 17 06:23:21 PM PDT 24
Peak memory 241180 kb
Host smart-a143193b-461f-4cab-a83e-a1e6c2e01334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666434880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2666434880
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.473940573
Short name T621
Test name
Test status
Simulation time 255270722390 ps
CPU time 189.92 seconds
Started Aug 17 06:19:04 PM PDT 24
Finished Aug 17 06:22:14 PM PDT 24
Peak memory 234148 kb
Host smart-86073575-99a7-48c0-87d3-402d9126fb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473940573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.473940573
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3508046012
Short name T284
Test name
Test status
Simulation time 130639989 ps
CPU time 3.87 seconds
Started Aug 17 06:19:05 PM PDT 24
Finished Aug 17 06:19:09 PM PDT 24
Peak memory 224560 kb
Host smart-3bd0d5be-80f3-4dcd-9164-a4b81c40c7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508046012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3508046012
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1217987931
Short name T838
Test name
Test status
Simulation time 2745772790 ps
CPU time 46.94 seconds
Started Aug 17 06:19:05 PM PDT 24
Finished Aug 17 06:19:52 PM PDT 24
Peak memory 254188 kb
Host smart-03cae8ae-a2b2-47ae-a458-08e07c8e9a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217987931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1217987931
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1553340803
Short name T1007
Test name
Test status
Simulation time 164450803 ps
CPU time 3.49 seconds
Started Aug 17 06:19:07 PM PDT 24
Finished Aug 17 06:19:10 PM PDT 24
Peak memory 232888 kb
Host smart-23f4b639-4faf-4963-9b72-a9e63f175b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553340803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1553340803
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2336108491
Short name T219
Test name
Test status
Simulation time 6884783693 ps
CPU time 26.63 seconds
Started Aug 17 06:19:04 PM PDT 24
Finished Aug 17 06:19:31 PM PDT 24
Peak memory 240048 kb
Host smart-cb77c9c3-fc90-47ce-9e50-e3367c322375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336108491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2336108491
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3877793068
Short name T852
Test name
Test status
Simulation time 1657424341 ps
CPU time 6.42 seconds
Started Aug 17 06:19:06 PM PDT 24
Finished Aug 17 06:19:13 PM PDT 24
Peak memory 232820 kb
Host smart-3a64a931-04e6-487f-977d-0d8d58e8f05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877793068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3877793068
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2398443720
Short name T247
Test name
Test status
Simulation time 8014083092 ps
CPU time 28.28 seconds
Started Aug 17 06:19:07 PM PDT 24
Finished Aug 17 06:19:35 PM PDT 24
Peak memory 236572 kb
Host smart-27110837-ae31-43ca-a056-c7c374fb29cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398443720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2398443720
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2007482524
Short name T337
Test name
Test status
Simulation time 1955979642 ps
CPU time 5.57 seconds
Started Aug 17 06:19:07 PM PDT 24
Finished Aug 17 06:19:13 PM PDT 24
Peak memory 222296 kb
Host smart-daf194fb-5b3e-4574-9a91-9f2bfe816c66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2007482524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2007482524
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1593346692
Short name T152
Test name
Test status
Simulation time 150250335322 ps
CPU time 115.23 seconds
Started Aug 17 06:19:05 PM PDT 24
Finished Aug 17 06:21:01 PM PDT 24
Peak memory 251940 kb
Host smart-7937b876-2e06-4f9b-abd5-1f632b09e512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593346692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1593346692
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3089513851
Short name T297
Test name
Test status
Simulation time 29744914704 ps
CPU time 48.57 seconds
Started Aug 17 06:19:03 PM PDT 24
Finished Aug 17 06:19:52 PM PDT 24
Peak memory 216572 kb
Host smart-ced7d7b5-56c4-4e11-9168-95214bd5c7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089513851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3089513851
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2959927078
Short name T567
Test name
Test status
Simulation time 2638126219 ps
CPU time 5.68 seconds
Started Aug 17 06:19:04 PM PDT 24
Finished Aug 17 06:19:10 PM PDT 24
Peak memory 216464 kb
Host smart-fadba9fd-2977-4539-be19-9c991c922b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959927078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2959927078
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1121783878
Short name T966
Test name
Test status
Simulation time 185957381 ps
CPU time 2.29 seconds
Started Aug 17 06:19:10 PM PDT 24
Finished Aug 17 06:19:12 PM PDT 24
Peak memory 216516 kb
Host smart-b9205c3b-53e3-4f72-9e79-78f6c5415017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121783878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1121783878
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.174532345
Short name T406
Test name
Test status
Simulation time 55416422 ps
CPU time 0.98 seconds
Started Aug 17 06:19:04 PM PDT 24
Finished Aug 17 06:19:05 PM PDT 24
Peak memory 206128 kb
Host smart-90781d1e-4660-41fe-85e8-7f6067238c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174532345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.174532345
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2460950083
Short name T233
Test name
Test status
Simulation time 19670399358 ps
CPU time 14.42 seconds
Started Aug 17 06:19:07 PM PDT 24
Finished Aug 17 06:19:21 PM PDT 24
Peak memory 232968 kb
Host smart-9b062b55-33e8-4ecc-826b-3db6485e250b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460950083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2460950083
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2007594423
Short name T351
Test name
Test status
Simulation time 11511085 ps
CPU time 0.72 seconds
Started Aug 17 06:17:25 PM PDT 24
Finished Aug 17 06:17:26 PM PDT 24
Peak memory 204960 kb
Host smart-8e45e4b7-9594-415c-83a6-5489f1a430af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007594423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
007594423
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4228247427
Short name T973
Test name
Test status
Simulation time 1608059067 ps
CPU time 17.21 seconds
Started Aug 17 06:17:17 PM PDT 24
Finished Aug 17 06:17:34 PM PDT 24
Peak memory 232928 kb
Host smart-fb796296-80c2-4b4a-957e-32e86d5c140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228247427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4228247427
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2889235581
Short name T347
Test name
Test status
Simulation time 14803039 ps
CPU time 0.76 seconds
Started Aug 17 06:17:06 PM PDT 24
Finished Aug 17 06:17:07 PM PDT 24
Peak memory 206584 kb
Host smart-f071745a-c5fb-4e21-b442-62e7e1b547c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889235581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2889235581
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2701899254
Short name T41
Test name
Test status
Simulation time 5103218223 ps
CPU time 92.81 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:18:49 PM PDT 24
Peak memory 265744 kb
Host smart-73a68363-4b75-4f0c-a3ac-a961fea2d42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701899254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2701899254
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3719417176
Short name T773
Test name
Test status
Simulation time 5487364206 ps
CPU time 38.02 seconds
Started Aug 17 06:17:19 PM PDT 24
Finished Aug 17 06:17:57 PM PDT 24
Peak memory 224800 kb
Host smart-ccd458ab-65f0-4396-9588-be8ad1b862f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719417176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3719417176
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.434211391
Short name T155
Test name
Test status
Simulation time 34419513251 ps
CPU time 254.7 seconds
Started Aug 17 06:17:13 PM PDT 24
Finished Aug 17 06:21:28 PM PDT 24
Peak memory 252172 kb
Host smart-571c31ea-f3a8-4c67-9f90-23d59eb7f463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434211391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
434211391
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.841941251
Short name T141
Test name
Test status
Simulation time 234531178 ps
CPU time 5.91 seconds
Started Aug 17 06:17:02 PM PDT 24
Finished Aug 17 06:17:08 PM PDT 24
Peak memory 224712 kb
Host smart-824340b1-be75-4693-9d1c-5baadfd4faa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841941251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.841941251
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1052938391
Short name T803
Test name
Test status
Simulation time 2548312625 ps
CPU time 35.09 seconds
Started Aug 17 06:16:59 PM PDT 24
Finished Aug 17 06:17:39 PM PDT 24
Peak memory 249300 kb
Host smart-5a8ae48d-05ea-4629-9d7c-17f6a1a37ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052938391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1052938391
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1566992714
Short name T91
Test name
Test status
Simulation time 1644138701 ps
CPU time 4.55 seconds
Started Aug 17 06:17:01 PM PDT 24
Finished Aug 17 06:17:06 PM PDT 24
Peak memory 232916 kb
Host smart-5e75e8de-5156-4525-a3bf-1716b75c2d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566992714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1566992714
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2033851895
Short name T422
Test name
Test status
Simulation time 393658614 ps
CPU time 5.6 seconds
Started Aug 17 06:17:25 PM PDT 24
Finished Aug 17 06:17:31 PM PDT 24
Peak memory 224692 kb
Host smart-8f7bcbf6-cfcc-4d6d-82ac-8f6b0bb92d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033851895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2033851895
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3743628219
Short name T899
Test name
Test status
Simulation time 15649166 ps
CPU time 0.98 seconds
Started Aug 17 06:17:35 PM PDT 24
Finished Aug 17 06:17:36 PM PDT 24
Peak memory 218048 kb
Host smart-eb6ef8cf-4e48-4cd9-9a82-b816a709da3b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743628219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3743628219
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.4166979435
Short name T650
Test name
Test status
Simulation time 57288891 ps
CPU time 2.03 seconds
Started Aug 17 06:17:12 PM PDT 24
Finished Aug 17 06:17:14 PM PDT 24
Peak memory 232484 kb
Host smart-0467bc15-f8f5-4d1f-a4e2-12f3d8abab65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166979435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.4166979435
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2646065270
Short name T444
Test name
Test status
Simulation time 150254079 ps
CPU time 3.18 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:17:20 PM PDT 24
Peak memory 232908 kb
Host smart-d30ab0ab-1acd-42ce-b2de-aa17a25bb9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646065270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2646065270
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3256165069
Short name T43
Test name
Test status
Simulation time 1325623557 ps
CPU time 15.61 seconds
Started Aug 17 06:17:25 PM PDT 24
Finished Aug 17 06:17:40 PM PDT 24
Peak memory 222140 kb
Host smart-efab167b-a8cf-4e4f-9cf4-ac9643e62b43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3256165069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3256165069
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.46645359
Short name T752
Test name
Test status
Simulation time 7162481517 ps
CPU time 9.16 seconds
Started Aug 17 06:17:20 PM PDT 24
Finished Aug 17 06:17:29 PM PDT 24
Peak memory 216560 kb
Host smart-4c25128e-8a44-4b00-921a-803e6cf65da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46645359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.46645359
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3358232359
Short name T889
Test name
Test status
Simulation time 4250283342 ps
CPU time 11.44 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:32 PM PDT 24
Peak memory 216508 kb
Host smart-a8bece72-278e-41bb-9b2b-edf3c842c199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358232359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3358232359
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.421704378
Short name T330
Test name
Test status
Simulation time 61508235 ps
CPU time 0.84 seconds
Started Aug 17 06:16:59 PM PDT 24
Finished Aug 17 06:17:00 PM PDT 24
Peak memory 207160 kb
Host smart-b08a48e4-b06a-4fcb-966c-ec4eaf5778c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421704378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.421704378
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3177484297
Short name T747
Test name
Test status
Simulation time 39485649 ps
CPU time 0.74 seconds
Started Aug 17 06:16:58 PM PDT 24
Finished Aug 17 06:16:58 PM PDT 24
Peak memory 206108 kb
Host smart-4d08f544-d886-4f3e-a94a-a25d4b914de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177484297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3177484297
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2703017086
Short name T636
Test name
Test status
Simulation time 6163618597 ps
CPU time 12.75 seconds
Started Aug 17 06:17:17 PM PDT 24
Finished Aug 17 06:17:30 PM PDT 24
Peak memory 241100 kb
Host smart-109c1615-08ae-41ee-96e7-8446e6530400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703017086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2703017086
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.4091259800
Short name T742
Test name
Test status
Simulation time 42855737 ps
CPU time 0.74 seconds
Started Aug 17 06:17:01 PM PDT 24
Finished Aug 17 06:17:02 PM PDT 24
Peak memory 205512 kb
Host smart-21f3e2cc-ef0e-488c-9ecd-d243c8f33d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091259800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.4
091259800
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1659300366
Short name T461
Test name
Test status
Simulation time 1317720192 ps
CPU time 5.96 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:17:27 PM PDT 24
Peak memory 232832 kb
Host smart-61371898-c300-4872-9148-57b4352ec388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659300366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1659300366
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1244035247
Short name T418
Test name
Test status
Simulation time 45823366 ps
CPU time 0.82 seconds
Started Aug 17 06:16:55 PM PDT 24
Finished Aug 17 06:16:56 PM PDT 24
Peak memory 206976 kb
Host smart-f9709115-d1e1-48a3-a14d-d673b00c986d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244035247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1244035247
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3449894140
Short name T1021
Test name
Test status
Simulation time 8530296421 ps
CPU time 34.5 seconds
Started Aug 17 06:17:05 PM PDT 24
Finished Aug 17 06:17:39 PM PDT 24
Peak memory 250380 kb
Host smart-42c3aae5-b6fc-412b-a652-a82d8ed39b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449894140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3449894140
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1229542558
Short name T428
Test name
Test status
Simulation time 423900053422 ps
CPU time 314.55 seconds
Started Aug 17 06:17:20 PM PDT 24
Finished Aug 17 06:22:35 PM PDT 24
Peak memory 257604 kb
Host smart-831ea477-20ca-4776-a3a6-5f007c4903ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229542558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1229542558
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1507964314
Short name T466
Test name
Test status
Simulation time 1073526226 ps
CPU time 6.33 seconds
Started Aug 17 06:17:14 PM PDT 24
Finished Aug 17 06:17:20 PM PDT 24
Peak memory 224680 kb
Host smart-5ae5401c-4e82-452b-874f-cdd0296b32d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507964314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1507964314
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1355815047
Short name T167
Test name
Test status
Simulation time 11782792635 ps
CPU time 74.03 seconds
Started Aug 17 06:17:08 PM PDT 24
Finished Aug 17 06:18:22 PM PDT 24
Peak memory 254852 kb
Host smart-a2617577-4fa5-44e2-a498-cb391e2e3ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355815047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1355815047
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.186845716
Short name T441
Test name
Test status
Simulation time 1448742334 ps
CPU time 4.23 seconds
Started Aug 17 06:17:02 PM PDT 24
Finished Aug 17 06:17:07 PM PDT 24
Peak memory 232908 kb
Host smart-0d816408-ddbf-4b7d-8418-6f5ec5178917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186845716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.186845716
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1755083173
Short name T223
Test name
Test status
Simulation time 2632548454 ps
CPU time 5.27 seconds
Started Aug 17 06:17:13 PM PDT 24
Finished Aug 17 06:17:19 PM PDT 24
Peak memory 224700 kb
Host smart-e8a24d44-d200-4b73-a1e3-f362766a9b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755083173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1755083173
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2058517739
Short name T336
Test name
Test status
Simulation time 102351164 ps
CPU time 1.03 seconds
Started Aug 17 06:17:02 PM PDT 24
Finished Aug 17 06:17:03 PM PDT 24
Peak memory 218020 kb
Host smart-23e58858-1f47-48d3-92af-a2d4867296fb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058517739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2058517739
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2353412935
Short name T468
Test name
Test status
Simulation time 10190648222 ps
CPU time 17.54 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:17:34 PM PDT 24
Peak memory 240752 kb
Host smart-184ebba2-24e4-42b1-b68a-a22e9061095e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353412935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2353412935
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2994022085
Short name T902
Test name
Test status
Simulation time 2467430787 ps
CPU time 8.4 seconds
Started Aug 17 06:17:02 PM PDT 24
Finished Aug 17 06:17:11 PM PDT 24
Peak memory 224748 kb
Host smart-b2281fc0-d15c-4817-aa0d-066cbe9216e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994022085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2994022085
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.446093396
Short name T692
Test name
Test status
Simulation time 1810001496 ps
CPU time 5.65 seconds
Started Aug 17 06:17:02 PM PDT 24
Finished Aug 17 06:17:08 PM PDT 24
Peak memory 222556 kb
Host smart-9ee29930-61f2-4631-b5bf-7de62a8cf610
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=446093396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.446093396
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.451302029
Short name T841
Test name
Test status
Simulation time 215912445689 ps
CPU time 319.48 seconds
Started Aug 17 06:16:59 PM PDT 24
Finished Aug 17 06:22:19 PM PDT 24
Peak memory 269568 kb
Host smart-69264be7-4411-4e59-9608-b391895ed882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451302029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.451302029
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.324147218
Short name T856
Test name
Test status
Simulation time 8751167047 ps
CPU time 12.04 seconds
Started Aug 17 06:17:14 PM PDT 24
Finished Aug 17 06:17:26 PM PDT 24
Peak memory 216504 kb
Host smart-7c5282d8-4350-45c4-a188-2091a78ceb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324147218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.324147218
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2298119492
Short name T1017
Test name
Test status
Simulation time 8008937362 ps
CPU time 21.47 seconds
Started Aug 17 06:17:07 PM PDT 24
Finished Aug 17 06:17:29 PM PDT 24
Peak memory 216584 kb
Host smart-1b9a2da4-e697-4945-9a5c-1bda5decc2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298119492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2298119492
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.415409996
Short name T819
Test name
Test status
Simulation time 38307932 ps
CPU time 0.89 seconds
Started Aug 17 06:17:15 PM PDT 24
Finished Aug 17 06:17:17 PM PDT 24
Peak memory 206828 kb
Host smart-c716603f-3694-4b9f-8ec2-dffdeaea419e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415409996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.415409996
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2537087114
Short name T431
Test name
Test status
Simulation time 107227577 ps
CPU time 0.89 seconds
Started Aug 17 06:17:05 PM PDT 24
Finished Aug 17 06:17:06 PM PDT 24
Peak memory 206056 kb
Host smart-dccceaaf-b0f1-4f48-9cf9-c30b39dba354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537087114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2537087114
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1008236466
Short name T847
Test name
Test status
Simulation time 3177000412 ps
CPU time 9.36 seconds
Started Aug 17 06:17:07 PM PDT 24
Finished Aug 17 06:17:17 PM PDT 24
Peak memory 224692 kb
Host smart-7efec6c2-8fbb-4b39-94ce-e7ce0fce1643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008236466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1008236466
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1729834613
Short name T424
Test name
Test status
Simulation time 13317667 ps
CPU time 0.73 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:17:22 PM PDT 24
Peak memory 205552 kb
Host smart-8d617bcd-9ad5-4fdf-929a-5c8ebb44b16b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729834613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
729834613
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1699308608
Short name T77
Test name
Test status
Simulation time 99187929 ps
CPU time 3.5 seconds
Started Aug 17 06:17:04 PM PDT 24
Finished Aug 17 06:17:08 PM PDT 24
Peak memory 224692 kb
Host smart-443dad71-5988-4d6b-8d87-118526230b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699308608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1699308608
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2808268902
Short name T791
Test name
Test status
Simulation time 16499487 ps
CPU time 0.8 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:17:17 PM PDT 24
Peak memory 206536 kb
Host smart-03ac15e0-e955-464c-803a-9d6c574a6517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808268902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2808268902
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2042715080
Short name T39
Test name
Test status
Simulation time 69043221050 ps
CPU time 265.1 seconds
Started Aug 17 06:17:34 PM PDT 24
Finished Aug 17 06:21:59 PM PDT 24
Peak memory 256856 kb
Host smart-932b4ec3-fb1e-4de2-a84d-4125813bdba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042715080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2042715080
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2406261559
Short name T854
Test name
Test status
Simulation time 5184146876 ps
CPU time 22.21 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:43 PM PDT 24
Peak memory 222760 kb
Host smart-14695862-17b3-4414-90e1-3ab1e9fc5e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406261559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2406261559
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1507854907
Short name T715
Test name
Test status
Simulation time 2241575118 ps
CPU time 9.97 seconds
Started Aug 17 06:17:00 PM PDT 24
Finished Aug 17 06:17:10 PM PDT 24
Peak memory 224464 kb
Host smart-f92af6a2-eda7-40fd-b6cb-02b85dd2c3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507854907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1507854907
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2127308007
Short name T676
Test name
Test status
Simulation time 1036030041 ps
CPU time 4.47 seconds
Started Aug 17 06:17:06 PM PDT 24
Finished Aug 17 06:17:10 PM PDT 24
Peak memory 224632 kb
Host smart-8fdc59ad-1913-45ed-a331-71cf047c3e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127308007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2127308007
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1873673346
Short name T961
Test name
Test status
Simulation time 1823642418 ps
CPU time 24.41 seconds
Started Aug 17 06:16:59 PM PDT 24
Finished Aug 17 06:17:23 PM PDT 24
Peak memory 249260 kb
Host smart-f51ab54c-7a04-43e9-b269-6c739f289983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873673346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1873673346
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2530782728
Short name T229
Test name
Test status
Simulation time 84652041 ps
CPU time 2.25 seconds
Started Aug 17 06:17:01 PM PDT 24
Finished Aug 17 06:17:03 PM PDT 24
Peak memory 224728 kb
Host smart-a66b508e-616e-4eab-add7-bf7bc28696b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530782728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2530782728
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.191554148
Short name T607
Test name
Test status
Simulation time 108822940 ps
CPU time 2.48 seconds
Started Aug 17 06:16:56 PM PDT 24
Finished Aug 17 06:16:59 PM PDT 24
Peak memory 232440 kb
Host smart-1f58fa22-6b2f-4a97-853c-6e74b4d159ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191554148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.191554148
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1224810578
Short name T36
Test name
Test status
Simulation time 28528118 ps
CPU time 1.18 seconds
Started Aug 17 06:17:14 PM PDT 24
Finished Aug 17 06:17:16 PM PDT 24
Peak memory 217960 kb
Host smart-751d5457-f3cf-4dcc-a781-b32001ba05ca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224810578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1224810578
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4251131730
Short name T864
Test name
Test status
Simulation time 8560664917 ps
CPU time 10.97 seconds
Started Aug 17 06:17:07 PM PDT 24
Finished Aug 17 06:17:18 PM PDT 24
Peak memory 256568 kb
Host smart-4d66e323-2ea8-415a-87f1-1219a968c95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251131730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4251131730
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2928759584
Short name T712
Test name
Test status
Simulation time 13319450642 ps
CPU time 5.25 seconds
Started Aug 17 06:17:18 PM PDT 24
Finished Aug 17 06:17:23 PM PDT 24
Peak memory 232960 kb
Host smart-44035616-2761-402a-9500-001c8d2fbfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928759584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2928759584
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3949108795
Short name T327
Test name
Test status
Simulation time 362986152 ps
CPU time 4.87 seconds
Started Aug 17 06:16:54 PM PDT 24
Finished Aug 17 06:16:59 PM PDT 24
Peak memory 223044 kb
Host smart-d5f5a7e8-3e87-4477-8614-96d914b867e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3949108795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3949108795
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2952713864
Short name T271
Test name
Test status
Simulation time 87663459183 ps
CPU time 283.3 seconds
Started Aug 17 06:17:17 PM PDT 24
Finished Aug 17 06:22:01 PM PDT 24
Peak memory 257432 kb
Host smart-ee71734a-d65d-4726-8d0b-e6623af1ee43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952713864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2952713864
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1688212779
Short name T574
Test name
Test status
Simulation time 167130665 ps
CPU time 3.13 seconds
Started Aug 17 06:17:13 PM PDT 24
Finished Aug 17 06:17:16 PM PDT 24
Peak memory 216536 kb
Host smart-0f502224-4bde-4adc-b7bb-86d38f19c6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688212779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1688212779
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2584515184
Short name T685
Test name
Test status
Simulation time 26374932990 ps
CPU time 21.49 seconds
Started Aug 17 06:17:08 PM PDT 24
Finished Aug 17 06:17:30 PM PDT 24
Peak memory 216556 kb
Host smart-844734a9-2261-453e-af70-af50d0c9bea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584515184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2584515184
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1511151216
Short name T741
Test name
Test status
Simulation time 25734098 ps
CPU time 0.78 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:22 PM PDT 24
Peak memory 206556 kb
Host smart-e62cb0c8-6990-4ec1-bc14-fa933014b9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511151216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1511151216
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2177961789
Short name T25
Test name
Test status
Simulation time 49180268 ps
CPU time 0.67 seconds
Started Aug 17 06:17:08 PM PDT 24
Finished Aug 17 06:17:09 PM PDT 24
Peak memory 205664 kb
Host smart-64e6ad6e-0c97-41b9-bae1-88c98f3f2648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177961789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2177961789
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1941987419
Short name T816
Test name
Test status
Simulation time 81162144 ps
CPU time 3.23 seconds
Started Aug 17 06:17:20 PM PDT 24
Finished Aug 17 06:17:23 PM PDT 24
Peak memory 232868 kb
Host smart-56959edd-d409-44b0-9c8f-ce91bb51da44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941987419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1941987419
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1830310629
Short name T933
Test name
Test status
Simulation time 61572117 ps
CPU time 0.7 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:17:25 PM PDT 24
Peak memory 204960 kb
Host smart-a71922c2-4c75-4712-9c4c-de9147b603fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830310629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
830310629
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2646094032
Short name T350
Test name
Test status
Simulation time 163855855 ps
CPU time 2.52 seconds
Started Aug 17 06:17:10 PM PDT 24
Finished Aug 17 06:17:13 PM PDT 24
Peak memory 224628 kb
Host smart-1040c0b0-491c-435c-9d15-e9b40b18a14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646094032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2646094032
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2518845817
Short name T719
Test name
Test status
Simulation time 64203376 ps
CPU time 0.76 seconds
Started Aug 17 06:17:25 PM PDT 24
Finished Aug 17 06:17:26 PM PDT 24
Peak memory 205584 kb
Host smart-476d7842-f253-4f3e-8e33-64b1f21ea11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518845817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2518845817
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2835830316
Short name T56
Test name
Test status
Simulation time 16463223382 ps
CPU time 147.2 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:19:48 PM PDT 24
Peak memory 254148 kb
Host smart-70a4d954-ddb5-46a1-a2b7-5c880add8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835830316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2835830316
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.4240338465
Short name T58
Test name
Test status
Simulation time 5054715585 ps
CPU time 57.07 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:18:18 PM PDT 24
Peak memory 249260 kb
Host smart-58e0bd20-891c-43d0-80a7-93f3585492d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240338465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.4240338465
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2660338161
Short name T353
Test name
Test status
Simulation time 650366442 ps
CPU time 12.35 seconds
Started Aug 17 06:17:15 PM PDT 24
Finished Aug 17 06:17:27 PM PDT 24
Peak memory 224644 kb
Host smart-e2b2dd4d-8d9a-4029-99a4-f2f15115e0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660338161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2660338161
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3250327273
Short name T40
Test name
Test status
Simulation time 1466960927 ps
CPU time 26.33 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:17:43 PM PDT 24
Peak memory 239132 kb
Host smart-ef962e96-9fe0-4eac-be7b-6aa43ab10489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250327273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3250327273
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.916339264
Short name T502
Test name
Test status
Simulation time 3511430411 ps
CPU time 9.64 seconds
Started Aug 17 06:17:20 PM PDT 24
Finished Aug 17 06:17:30 PM PDT 24
Peak memory 224732 kb
Host smart-60eb8a1a-f5ba-4bd4-8d7d-911b06a55c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916339264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.916339264
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1932080825
Short name T544
Test name
Test status
Simulation time 28272843 ps
CPU time 2.09 seconds
Started Aug 17 06:17:18 PM PDT 24
Finished Aug 17 06:17:20 PM PDT 24
Peak memory 223940 kb
Host smart-27d5451c-ab09-4ae7-bc89-df8f13e96e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932080825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1932080825
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3837714582
Short name T425
Test name
Test status
Simulation time 65300108 ps
CPU time 1.08 seconds
Started Aug 17 06:17:03 PM PDT 24
Finished Aug 17 06:17:04 PM PDT 24
Peak memory 216688 kb
Host smart-981b6d23-1e39-47fd-ba6d-e635c27f1d95
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837714582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3837714582
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.40069837
Short name T82
Test name
Test status
Simulation time 2677656857 ps
CPU time 6.39 seconds
Started Aug 17 06:17:23 PM PDT 24
Finished Aug 17 06:17:30 PM PDT 24
Peak memory 232896 kb
Host smart-8374e40c-8a53-43af-b74e-339b1de22269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40069837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.40069837
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1840308836
Short name T214
Test name
Test status
Simulation time 183632438 ps
CPU time 2.2 seconds
Started Aug 17 06:17:17 PM PDT 24
Finished Aug 17 06:17:19 PM PDT 24
Peak memory 232892 kb
Host smart-1a076b99-9a26-4d6e-a60a-4ec7b1275acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840308836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1840308836
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2089274688
Short name T825
Test name
Test status
Simulation time 5118845359 ps
CPU time 12.78 seconds
Started Aug 17 06:17:23 PM PDT 24
Finished Aug 17 06:17:36 PM PDT 24
Peak memory 222284 kb
Host smart-6f09e8be-815b-4fe9-a062-5f2187a0c054
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2089274688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2089274688
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3344038573
Short name T21
Test name
Test status
Simulation time 33559052102 ps
CPU time 138.46 seconds
Started Aug 17 06:17:17 PM PDT 24
Finished Aug 17 06:19:35 PM PDT 24
Peak memory 251864 kb
Host smart-e07a2124-f70e-4800-9399-4c7c0561c3b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344038573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3344038573
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3366060516
Short name T289
Test name
Test status
Simulation time 2696000722 ps
CPU time 9.47 seconds
Started Aug 17 06:17:15 PM PDT 24
Finished Aug 17 06:17:25 PM PDT 24
Peak memory 216536 kb
Host smart-c59dc04e-6c87-469e-a1c4-64dbbac97033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366060516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3366060516
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.341009988
Short name T413
Test name
Test status
Simulation time 1565520266 ps
CPU time 5.05 seconds
Started Aug 17 06:17:18 PM PDT 24
Finished Aug 17 06:17:23 PM PDT 24
Peak memory 216400 kb
Host smart-595a2c82-7fce-4ecb-a164-f5b6e9c4059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341009988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.341009988
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2926644019
Short name T358
Test name
Test status
Simulation time 148461564 ps
CPU time 2.46 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:17:25 PM PDT 24
Peak memory 216500 kb
Host smart-051d8244-4c22-4710-b6d4-3abe9b2a3dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926644019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2926644019
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.947461268
Short name T683
Test name
Test status
Simulation time 69172820 ps
CPU time 0.89 seconds
Started Aug 17 06:17:08 PM PDT 24
Finished Aug 17 06:17:09 PM PDT 24
Peak memory 206040 kb
Host smart-d61a4630-738c-46d7-a7eb-cf6c9a79b3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947461268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.947461268
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2020712585
Short name T510
Test name
Test status
Simulation time 530357448 ps
CPU time 3.42 seconds
Started Aug 17 06:17:17 PM PDT 24
Finished Aug 17 06:17:20 PM PDT 24
Peak memory 224692 kb
Host smart-2b2c4cd5-2536-4995-b07d-7f610543ee3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020712585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2020712585
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4201319028
Short name T311
Test name
Test status
Simulation time 12709726 ps
CPU time 0.74 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:17:22 PM PDT 24
Peak memory 204964 kb
Host smart-4ee3e991-0e3b-431f-84e2-bd4ed9ca52a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201319028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
201319028
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2909465730
Short name T168
Test name
Test status
Simulation time 117420311 ps
CPU time 2.43 seconds
Started Aug 17 06:17:29 PM PDT 24
Finished Aug 17 06:17:31 PM PDT 24
Peak memory 232804 kb
Host smart-9745f8d9-8445-43ed-9555-70ccdea0b90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909465730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2909465730
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2396157509
Short name T601
Test name
Test status
Simulation time 22071546 ps
CPU time 0.77 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:21 PM PDT 24
Peak memory 206924 kb
Host smart-b9673aef-9f78-40bf-83fb-c9bb4656e815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396157509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2396157509
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2158115532
Short name T228
Test name
Test status
Simulation time 4281956664 ps
CPU time 46.27 seconds
Started Aug 17 06:17:17 PM PDT 24
Finished Aug 17 06:18:03 PM PDT 24
Peak memory 224792 kb
Host smart-444f8be6-9674-4e9c-ad2e-9f028b5531a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158115532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2158115532
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3659653160
Short name T177
Test name
Test status
Simulation time 9075837157 ps
CPU time 89.58 seconds
Started Aug 17 06:17:24 PM PDT 24
Finished Aug 17 06:18:53 PM PDT 24
Peak memory 249372 kb
Host smart-b0f824bb-46a6-44b9-97b1-72bc31c48192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659653160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3659653160
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1328488384
Short name T736
Test name
Test status
Simulation time 283501116 ps
CPU time 4.95 seconds
Started Aug 17 06:17:23 PM PDT 24
Finished Aug 17 06:17:28 PM PDT 24
Peak memory 224672 kb
Host smart-da99dcc0-fa92-4ce9-ab89-5158688e25a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328488384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1328488384
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3843549433
Short name T45
Test name
Test status
Simulation time 7298063600 ps
CPU time 44.47 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:18:07 PM PDT 24
Peak memory 254560 kb
Host smart-321d2342-f1ad-4540-9f1e-8ca065a73204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843549433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3843549433
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.980176722
Short name T632
Test name
Test status
Simulation time 241324221 ps
CPU time 3.84 seconds
Started Aug 17 06:17:22 PM PDT 24
Finished Aug 17 06:17:26 PM PDT 24
Peak memory 232876 kb
Host smart-6601e61a-bd43-4ff3-8504-944262b76042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980176722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.980176722
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4082683906
Short name T586
Test name
Test status
Simulation time 59566632 ps
CPU time 2.36 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:17:19 PM PDT 24
Peak memory 232920 kb
Host smart-7e832e09-3177-4a61-abb3-3f9a06379018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082683906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4082683906
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3516276606
Short name T951
Test name
Test status
Simulation time 41065312 ps
CPU time 1 seconds
Started Aug 17 06:17:21 PM PDT 24
Finished Aug 17 06:17:22 PM PDT 24
Peak memory 217956 kb
Host smart-4d6b857e-d645-4bd7-be12-14e230c84fde
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516276606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3516276606
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.260164568
Short name T361
Test name
Test status
Simulation time 4836146252 ps
CPU time 10.34 seconds
Started Aug 17 06:17:20 PM PDT 24
Finished Aug 17 06:17:30 PM PDT 24
Peak memory 249120 kb
Host smart-72680e10-25dc-46b2-86c6-248b20f8faa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260164568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
260164568
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2488838372
Short name T644
Test name
Test status
Simulation time 1695761795 ps
CPU time 5.45 seconds
Started Aug 17 06:17:18 PM PDT 24
Finished Aug 17 06:17:24 PM PDT 24
Peak memory 232880 kb
Host smart-91595642-39c1-4fb1-8620-bf24889b0ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488838372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2488838372
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3899092569
Short name T977
Test name
Test status
Simulation time 1215711987 ps
CPU time 4.9 seconds
Started Aug 17 06:17:15 PM PDT 24
Finished Aug 17 06:17:20 PM PDT 24
Peak memory 222320 kb
Host smart-655d54db-db7a-4403-b8d3-bd9f4704fc20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3899092569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3899092569
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.997873565
Short name T771
Test name
Test status
Simulation time 36758531875 ps
CPU time 358.76 seconds
Started Aug 17 06:17:31 PM PDT 24
Finished Aug 17 06:23:30 PM PDT 24
Peak memory 257520 kb
Host smart-a182788c-acfd-4d9b-96c7-0b6497478343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997873565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.997873565
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3331206064
Short name T588
Test name
Test status
Simulation time 5132157940 ps
CPU time 19.5 seconds
Started Aug 17 06:17:23 PM PDT 24
Finished Aug 17 06:17:42 PM PDT 24
Peak memory 216648 kb
Host smart-4df22b81-e098-43fd-b63f-19bcb8f14cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331206064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3331206064
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2253644834
Short name T907
Test name
Test status
Simulation time 969459185 ps
CPU time 4.86 seconds
Started Aug 17 06:17:16 PM PDT 24
Finished Aug 17 06:17:21 PM PDT 24
Peak memory 216524 kb
Host smart-ce7b1b14-53a0-43eb-9725-f1479864a9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253644834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2253644834
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2140555176
Short name T661
Test name
Test status
Simulation time 81456223 ps
CPU time 1.03 seconds
Started Aug 17 06:17:31 PM PDT 24
Finished Aug 17 06:17:32 PM PDT 24
Peak memory 207428 kb
Host smart-3a315ed4-20ec-40a2-8057-81fd12b7f809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140555176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2140555176
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1722759781
Short name T334
Test name
Test status
Simulation time 39318872 ps
CPU time 0.75 seconds
Started Aug 17 06:17:30 PM PDT 24
Finished Aug 17 06:17:31 PM PDT 24
Peak memory 206052 kb
Host smart-c54344cc-6404-410d-8166-afb932abef99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722759781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1722759781
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2905565229
Short name T663
Test name
Test status
Simulation time 24856231912 ps
CPU time 18.89 seconds
Started Aug 17 06:17:23 PM PDT 24
Finished Aug 17 06:17:42 PM PDT 24
Peak memory 232824 kb
Host smart-0500f227-3d55-4d71-bd6b-eb49cd4184e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905565229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2905565229
Directory /workspace/9.spi_device_upload/latest
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