Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2677824	1			T2	1		T3	1		T5	54
all_values[1]	2677824	1			T2	1		T3	1		T5	54
all_values[2]	2677824	1			T2	1		T3	1		T5	54
all_values[3]	2677824	1			T2	1		T3	1		T5	54
all_values[4]	2677824	1			T2	1		T3	1		T5	54
all_values[5]	2677824	1			T2	1		T3	1		T5	54
all_values[6]	2677824	1			T2	1		T3	1		T5	54
all_values[7]	2677824	1			T2	1		T3	1		T5	54

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20337511

1

T2

8

T3

8

T5

432

auto[1]

1085081

1

T8

110

T9

18248

T17

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21394962

1

T2

8

T3

8

T5

432

auto[1]

27630

1

T8

420

T9

298

T11

595

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2547008	1			T2	1		T3	1		T5	54
all_values[0]	auto[0]	auto[1]	12841	1			T8	236		T9	119		T11	310
all_values[0]	auto[1]	auto[0]	117281	1			T8	10		T9	10		T17	1
all_values[0]	auto[1]	auto[1]	694	1			T8	9		T9	2		T17	3
all_values[1]	auto[0]	auto[0]	2530551	1			T2	1		T3	1		T5	54
all_values[1]	auto[0]	auto[1]	8084	1			T8	107		T11	196		T27	223
all_values[1]	auto[1]	auto[0]	138530	1			T8	8		T9	5967		T17	6
all_values[1]	auto[1]	auto[1]	659	1			T8	8		T9	99		T17	1
all_values[2]	auto[0]	auto[0]	2640145	1			T2	1		T3	1		T5	54
all_values[2]	auto[0]	auto[1]	3308	1			T8	11		T9	23		T11	89
all_values[2]	auto[1]	auto[0]	34181	1			T8	10		T9	8		T17	2
all_values[2]	auto[1]	auto[1]	190	1			T8	4		T9	6		T17	2
all_values[3]	auto[0]	auto[0]	2617702	1			T2	1		T3	1		T5	54
all_values[3]	auto[0]	auto[1]	204	1			T8	6		T9	7		T17	2
all_values[3]	auto[1]	auto[0]	59736	1			T8	4		T9	9		T18	1
all_values[3]	auto[1]	auto[1]	182	1			T8	6		T9	5		T17	3
all_values[4]	auto[0]	auto[0]	2444942	1			T2	1		T3	1		T5	54
all_values[4]	auto[0]	auto[1]	188	1			T8	5		T9	1		T17	1
all_values[4]	auto[1]	auto[0]	232496	1			T8	6		T9	6058		T17	3
all_values[4]	auto[1]	auto[1]	198	1			T8	5		T9	5		T17	6
all_values[5]	auto[0]	auto[0]	2440734	1			T2	1		T3	1		T5	54
all_values[5]	auto[0]	auto[1]	174	1			T8	3		T9	4		T17	1
all_values[5]	auto[1]	auto[0]	236754	1			T8	13		T9	11		T17	4
all_values[5]	auto[1]	auto[1]	162	1			T8	5		T9	2		T17	1
all_values[6]	auto[0]	auto[0]	2537044	1			T2	1		T3	1		T5	54
all_values[6]	auto[0]	auto[1]	172	1			T8	2		T9	8		T17	2
all_values[6]	auto[1]	auto[0]	140428	1			T8	6		T9	3		T17	4
all_values[6]	auto[1]	auto[1]	180	1			T8	3		T9	4		T18	1
all_values[7]	auto[0]	auto[0]	2554221	1			T2	1		T3	1		T5	54
all_values[7]	auto[0]	auto[1]	193	1			T8	3		T9	6		T17	1
all_values[7]	auto[1]	auto[0]	123209	1			T8	6		T9	6052		T17	8
all_values[7]	auto[1]	auto[1]	201	1			T8	7		T9	7		T17	1