Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34904	1			T3	6		T5	38		T6	476
auto[SpiFlashAddrCfg]	7854	1			T5	2		T6	47		T8	62
auto[SpiFlashAddr3b]	9604	1			T5	2		T6	42		T8	93
auto[SpiFlashAddr4b]	7883	1			T5	4		T6	57		T8	71

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34390

1

T3

6

T5

46

T6

457

auto[1]

25855

1

T6

165

T8

311

T9

57

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32390

1

T3

6

T5

4

T6

405

auto[1]

27855

1

T5

42

T6

217

T8

341

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39763	1			T3	6		T5	40		T6	511
values[1]	1133	1			T6	3		T8	7		T9	2
values[2]	1506	1			T6	6		T8	10		T9	8
values[3]	1535	1			T5	2		T6	3		T8	9
values[4]	1448	1			T6	7		T8	12		T9	5
values[5]	1511	1			T6	3		T8	22		T9	13
values[6]	1496	1			T6	17		T8	10		T9	5
values[7]	1564	1			T6	16		T8	16		T9	4
values[8]	10289	1			T5	4		T6	56		T8	104

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28857

1

T3

6

T5

46

T6

622

auto[1]

31388

1

T8

245

T10

1

T11

260

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56969

1

T3

6

T5

46

T6

598

write

3276

1

T6

24

T8

26

T9

11

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20300

1

T3

6

T5

8

T6

122

valids[0x1]

39945

1

T5

38

T6

500

T8

380

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1693	1			T6	12		T8	11		T9	6
internal_process_ops[0x5a]	1636	1			T6	5		T8	21		T9	6
internal_process_ops[0x05]	20362	1			T5	38		T6	387		T8	208
internal_process_ops[0x35]	1614	1			T6	9		T8	15		T9	5
internal_process_ops[0x15]	1612	1			T6	6		T8	14		T9	5
internal_process_ops[0x03]	1018	1			T6	8		T8	9		T9	2
internal_process_ops[0x0b]	997	1			T6	8		T8	8		T9	5
internal_process_ops[0x3b]	1095	1			T6	7		T8	13		T9	9
internal_process_ops[0x6b]	1082	1			T6	12		T8	5		T9	5
internal_process_ops[0xbb]	1085	1			T6	12		T8	14		T9	6
internal_process_ops[0xeb]	1110	1			T5	2		T6	5		T8	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58598

1

T3

6

T5

46

T6

609

auto[1]

1647

1

T6

13

T8

14

T9

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57879

1

T3

6

T5

44

T6

600

auto[1]

2366

1

T5

2

T6

22

T8

26

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10074

1

T3

6

T5

38

T6

374

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5143

1

T6

97

T8

146

T9

23

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1920

1

T5

2

T6

20

T8

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1812

1

T6

21

T8

14

T9

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2490

1

T5

2

T6

22

T8

18

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2153

1

T6

16

T8

22

T9

14

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2029

1

T5

4

T6

28

T8

13

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1721

1

T6

20

T8

18

T9

9

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

93

1

T6

2

T9

2

T11

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

91

1

T6

2

T8

3

T27

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

83

1

T8

1

T37

3

T16

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

73

1

T6

1

T27

1

T35

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

88

1

T6

2

T8

2

T9

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

89

1

T11

6

T27

3

T28

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

99

1

T6

1

T8

3

T35

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T6

3

T11

1

T27

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

106

1

T9

2

T27

3

T41

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

115

1

T6

1

T8

1

T11

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

77

1

T6

2

T11

1

T79

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

118

1

T6

1

T11

3

T27

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

104

1

T6

4

T9

4

T11

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

89

1

T6

2

T8

2

T11

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

89

1

T27

2

T16

2

T71

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

98

1

T6

3

T9

1

T11

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10704

1

T8

65

T11

92

T36

85

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8189

1

T8

46

T11

33

T36

33

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1622

1

T8

16

T11

19

T36

21

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1642

1

T8

18

T11

10

T36

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2133

1

T8

31

T11

20

T39

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1989

1

T8

19

T11

24

T36

29

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1747

1

T8

21

T10

1

T11

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1601

1

T8

15

T11

19

T36

17

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

100

1

T36

8

T16

2

T70

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

128

1

T8

3

T11

1

T36

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

106

1

T8

3

T36

1

T18

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

120

1

T8

3

T11

3

T75

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

123

1

T36

4

T18

1

T143

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

113

1

T36

1

T75

1

T18

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

140

1

T11

2

T36

2

T70

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T8

1

T11

2

T36

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

114

1

T8

1

T11

4

T70

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

105

1

T11

1

T36

2

T16

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

107

1

T8

1

T11

3

T70

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

97

1

T11

3

T36

2

T70

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

111

1

T11

3

T36

2

T18

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

102

1

T8

1

T11

3

T36

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

89

1

T8

1

T11

1

T36

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

103

1

T36

1

T75

3

T70

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3909	1			T3	6		T5	2		T6	56
auto[0]	values[0]	valids[0x1]	14151	1			T5	38		T6	455		T8	209
auto[0]	values[1]	valids[0x1]	533	1			T6	3		T8	4		T9	2
auto[0]	values[2]	valids[0x0]	499	1			T6	4		T8	2		T9	7
auto[0]	values[2]	valids[0x1]	302	1			T6	2		T8	3		T9	1
auto[0]	values[3]	valids[0x0]	547	1			T5	2		T6	3		T8	6
auto[0]	values[3]	valids[0x1]	254	1			T11	3		T28	3		T35	4
auto[0]	values[4]	valids[0x0]	524	1			T6	2		T8	3		T9	5
auto[0]	values[4]	valids[0x1]	265	1			T6	5		T8	5		T11	5
auto[0]	values[5]	valids[0x0]	553	1			T6	1		T8	7		T9	8
auto[0]	values[5]	valids[0x1]	282	1			T6	2		T8	2		T9	5
auto[0]	values[6]	valids[0x0]	496	1			T6	11		T8	4		T9	3
auto[0]	values[6]	valids[0x1]	281	1			T6	6		T8	2		T9	2
auto[0]	values[7]	valids[0x0]	566	1			T6	10		T8	3		T9	3
auto[0]	values[7]	valids[0x1]	270	1			T6	6		T8	2		T9	1
auto[0]	values[8]	valids[0x0]	3477	1			T5	4		T6	35		T8	18
auto[0]	values[8]	valids[0x1]	1948	1			T6	21		T8	23		T9	14
auto[1]	values[0]	valids[0x0]	4378	1			T8	54		T11	49		T36	54
auto[1]	values[0]	valids[0x1]	17325	1			T8	85		T11	110		T36	101
auto[1]	values[1]	valids[0x1]	600	1			T8	3		T11	9		T36	4
auto[1]	values[2]	valids[0x0]	409	1			T8	2		T11	5		T36	8
auto[1]	values[2]	valids[0x1]	296	1			T8	3		T11	1		T36	3
auto[1]	values[3]	valids[0x0]	432	1			T8	1		T11	10		T36	6
auto[1]	values[3]	valids[0x1]	302	1			T8	2		T11	3		T36	3
auto[1]	values[4]	valids[0x0]	379	1			T8	4		T11	3		T36	10
auto[1]	values[4]	valids[0x1]	280	1			T11	3		T36	1		T70	8
auto[1]	values[5]	valids[0x0]	389	1			T8	9		T11	1		T36	3
auto[1]	values[5]	valids[0x1]	287	1			T8	4		T11	3		T36	3
auto[1]	values[6]	valids[0x0]	428	1			T8	4		T11	10		T39	1
auto[1]	values[6]	valids[0x1]	291	1			T11	2		T36	4		T16	1
auto[1]	values[7]	valids[0x0]	426	1			T8	4		T11	1		T36	3
auto[1]	values[7]	valids[0x1]	302	1			T8	7		T11	11		T39	2
auto[1]	values[8]	valids[0x0]	2888	1			T8	37		T10	1		T11	23
auto[1]	values[8]	valids[0x1]	1976	1			T8	26		T11	16		T36	28