Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3395718

1

T3

166

T5

5

T6

6422

auto[1]

30195

1

T5

38

T6

382

T8

196

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006130

1

T3

166

T5

5

T6

96

auto[1]

2419783

1

T5

38

T6

6708

T8

31353

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	610053	1			T3	2		T5	43		T6	901
auto[524288:1048575]	445429	1			T3	1		T6	3636		T8	12544
auto[1048576:1572863]	383927	1			T6	1480		T8	619		T9	572
auto[1572864:2097151]	409147	1			T6	2		T8	2497		T9	1163
auto[2097152:2621439]	354689	1			T3	81		T6	180		T8	273
auto[2621440:3145727]	438289	1			T3	82		T6	551		T8	5149
auto[3145728:3670015]	391127	1			T6	12		T8	11		T11	2468
auto[3670016:4194303]	393252	1			T6	42		T8	7101		T9	1034

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2455025

1

T3

11

T5

41

T6

6787

auto[1]

970888

1

T3

155

T5

2

T6

17

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2959714

1

T3

164

T5

43

T6

6283

auto[1]

466199

1

T3

2

T6

521

T8

13490

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	209930	1			T3	2		T5	3		T6	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	341447	1			T5	2		T6	896		T8	3245
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	122506	1			T3	1		T6	23		T8	11
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	253487	1			T6	3128		T8	6667		T9	128
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	114031	1			T6	15		T8	4		T9	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	219951	1			T6	1157		T8	514		T9	571
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	117276	1			T6	1		T8	7		T9	4
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	229886	1			T8	2466		T9	641		T11	840
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	84995	1			T3	79		T6	12		T8	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	218247	1			T6	131		T8	258		T11	2972
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	107281	1			T3	82		T6	6		T8	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	266694	1			T6	513		T9	2727		T11	7534
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	114261	1			T6	2		T8	5		T11	10
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	220144	1			T6	5		T8	4		T11	1427
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	111432	1			T6	5		T8	11		T9	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	202575	1			T6	2		T8	4606		T9	1029
auto[0]	auto[1]	auto[0:524287]	auto[0]	4836	1			T8	1		T9	1		T11	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	49227	1			T11	3		T36	135		T75	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	826	1			T6	2		T8	7		T9	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	64221	1			T6	256		T8	5813		T27	7
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	832	1			T6	2		T8	2		T27	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	45588	1			T6	260		T8	1		T27	3121
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	3850	1			T6	1		T8	6		T9	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	54125	1			T8	1		T9	512		T27	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	5810	1			T3	2		T8	1		T9	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	41830	1			T8	6		T9	2		T11	770
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1459	1			T8	7		T9	1		T11	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	59870	1			T8	5131		T11	1624		T27	515
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2079	1			T11	2		T35	1		T38	28
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	50936	1			T11	1024		T38	2729		T70	1025
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	700	1			T11	5		T27	3		T36	9
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	75386	1			T8	2471		T11	514		T18	5
auto[1]	auto[0]	auto[0:524287]	auto[0]	500	1			T5	2		T8	5		T11	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3154	1			T5	36		T8	2		T27	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	452	1			T6	10		T8	4		T11	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3658	1			T6	217		T8	42		T27	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	356	1			T6	5		T8	2		T11	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2409	1			T6	41		T8	76		T11	12
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	395	1			T8	4		T9	1		T11	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2880	1			T8	1		T9	2		T11	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	387	1			T6	3		T8	2		T11	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2727	1			T6	34		T11	9		T27	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	351	1			T6	1		T9	7		T11	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2259	1			T6	31		T9	23		T11	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	460	1			T6	1		T8	1		T11	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2918	1			T6	4		T8	1		T11	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	428	1			T6	2		T8	2		T9	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2237	1			T6	33		T8	11		T11	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	71	1			T36	4		T75	1		T79	9
auto[1]	auto[1]	auto[0:524287]	auto[1]	888	1			T36	231		T79	256		T143	6
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	77	1			T27	1		T30	1		T37	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	202	1			T37	14		T71	10		T21	23
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	91	1			T8	1		T28	1		T18	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	669	1			T8	19		T18	7		T20	30
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	126	1			T8	1		T27	1		T35	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	609	1			T8	11		T35	104		T205	31
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	93	1			T8	1		T9	1		T11	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	600	1			T8	1		T9	19		T11	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	59	1			T8	3		T27	3		T35	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	316	1			T8	6		T27	2		T35	63
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	60	1			T70	1		T180	2		T20	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	269	1			T70	6		T180	6		T20	25
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	120	1			T11	2		T36	5		T196	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	374	1			T11	3		T196	25		T19	11

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1978726	1			T3	9		T5	3		T6	5890
auto[0]	auto[0]	auto[1]	955417	1			T3	155		T5	2		T6	11
auto[0]	auto[1]	auto[0]	446739	1			T3	2		T6	521		T8	13447
auto[0]	auto[1]	auto[1]	14836	1			T35	1		T18	1		T71	2
auto[1]	auto[0]	auto[0]	25054	1			T5	38		T6	376		T8	151
auto[1]	auto[0]	auto[1]	517	1			T6	6		T8	2		T9	1
auto[1]	auto[1]	auto[0]	4506	1			T8	42		T9	20		T11	7
auto[1]	auto[1]	auto[1]	118	1			T8	1		T11	1		T37	1