Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2677824	1			T2	1		T3	1		T5	54
all_pins[1]	2677824	1			T2	1		T3	1		T5	54
all_pins[2]	2677824	1			T2	1		T3	1		T5	54
all_pins[3]	2677824	1			T2	1		T3	1		T5	54
all_pins[4]	2677824	1			T2	1		T3	1		T5	54
all_pins[5]	2677824	1			T2	1		T3	1		T5	54
all_pins[6]	2677824	1			T2	1		T3	1		T5	54
all_pins[7]	2677824	1			T2	1		T3	1		T5	54

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21279748	1			T2	8		T3	8		T5	432
values[0x1]	142844	1			T8	47		T9	136		T17	17
transitions[0x0=>0x1]	140931	1			T8	34		T9	127		T17	12
transitions[0x1=>0x0]	140938	1			T8	34		T9	127		T17	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2677070	1			T2	1		T3	1		T5	54
all_pins[0]	values[0x1]	754	1			T8	9		T9	2		T17	3
all_pins[0]	transitions[0x0=>0x1]	528	1			T8	5		T9	2		T17	2
all_pins[0]	transitions[0x1=>0x0]	475	1			T8	4		T9	105		T19	5
all_pins[1]	values[0x0]	2677123	1			T2	1		T3	1		T5	54
all_pins[1]	values[0x1]	701	1			T8	8		T9	105		T17	1
all_pins[1]	transitions[0x0=>0x1]	650	1			T8	7		T9	103		T17	1
all_pins[1]	transitions[0x1=>0x0]	143	1			T8	3		T9	4		T17	2
all_pins[2]	values[0x0]	2677630	1			T2	1		T3	1		T5	54
all_pins[2]	values[0x1]	194	1			T8	4		T9	6		T17	2
all_pins[2]	transitions[0x0=>0x1]	140	1			T8	3		T9	3		T17	2
all_pins[2]	transitions[0x1=>0x0]	128	1			T8	5		T9	2		T17	3
all_pins[3]	values[0x0]	2677642	1			T2	1		T3	1		T5	54
all_pins[3]	values[0x1]	182	1			T8	6		T9	5		T17	3
all_pins[3]	transitions[0x0=>0x1]	130	1			T8	5		T9	3		T17	1
all_pins[3]	transitions[0x1=>0x0]	146	1			T8	4		T9	3		T17	4
all_pins[4]	values[0x0]	2677626	1			T2	1		T3	1		T5	54
all_pins[4]	values[0x1]	198	1			T8	5		T9	5		T17	6
all_pins[4]	transitions[0x0=>0x1]	153	1			T8	4		T9	5		T17	5
all_pins[4]	transitions[0x1=>0x0]	2773	1			T8	4		T9	2		T19	1
all_pins[5]	values[0x0]	2675006	1			T2	1		T3	1		T5	54
all_pins[5]	values[0x1]	2818	1			T8	5		T9	2		T17	1
all_pins[5]	transitions[0x0=>0x1]	1446	1			T8	5		T9	2		T17	1
all_pins[5]	transitions[0x1=>0x0]	136424	1			T8	3		T9	4		T18	1
all_pins[6]	values[0x0]	2540028	1			T2	1		T3	1		T5	54
all_pins[6]	values[0x1]	137796	1			T8	3		T9	4		T18	1
all_pins[6]	transitions[0x0=>0x1]	137743	1			T8	1		T9	2		T19	1
all_pins[6]	transitions[0x1=>0x0]	148	1			T8	5		T9	5		T17	1
all_pins[7]	values[0x0]	2677623	1			T2	1		T3	1		T5	54
all_pins[7]	values[0x1]	201	1			T8	7		T9	7		T17	1
all_pins[7]	transitions[0x0=>0x1]	141	1			T8	4		T9	7		T18	1
all_pins[7]	transitions[0x1=>0x0]	701	1			T8	6		T9	2		T17	3