Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17288

1

T3

6

T5

46

T6

457

auto[1]

11569

1

T6

165

T8

204

T9

57

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3729	1			T3	6		T9	40		T27	53
values[1]	3767	1			T6	95		T8	123		T9	20
values[2]	4046	1			T5	46		T6	312		T8	30
values[3]	3020	1			T6	105		T11	42		T28	45
values[4]	3481	1			T6	48		T9	24		T12	20
values[5]	3699	1			T6	62		T9	26		T11	44
values[6]	3734	1			T8	156		T11	45		T27	48
values[7]	3381	1			T8	22		T9	20		T35	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3859	1			T6	170		T9	26		T11	45
values[1]	3917	1			T6	75		T8	32		T9	20
values[2]	3778	1			T6	20		T9	44		T11	23
values[3]	3475	1			T3	6		T8	30		T12	20
values[4]	3163	1			T6	69		T8	20		T9	44
values[5]	3649	1			T5	46		T6	20		T8	227
values[6]	3564	1			T6	223		T8	22		T11	41
values[7]	3452	1			T6	45		T11	44		T27	23

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	320	1			T71	7		T206	4		T179	41
auto[0]	values[0]	values[1]	520	1			T27	13		T71	12		T186	13
auto[0]	values[0]	values[2]	167	1			T16	9		T159	14		T20	10
auto[0]	values[0]	values[3]	308	1			T3	6		T79	12		T207	6
auto[0]	values[0]	values[4]	337	1			T27	15		T35	11		T71	25
auto[0]	values[0]	values[5]	168	1			T9	35		T35	12		T30	11
auto[0]	values[0]	values[6]	173	1			T28	25		T180	9		T20	11
auto[0]	values[0]	values[7]	285	1			T35	15		T37	27		T180	10
auto[0]	values[1]	values[0]	158	1			T76	6		T208	12		T47	24
auto[0]	values[1]	values[1]	370	1			T6	59		T8	11		T9	14
auto[0]	values[1]	values[2]	156	1			T27	7		T16	13		T209	4
auto[0]	values[1]	values[3]	289	1			T28	18		T159	12		T20	5
auto[0]	values[1]	values[4]	118	1			T186	12		T182	15		T158	33
auto[0]	values[1]	values[5]	281	1			T8	60		T161	17		T179	5
auto[0]	values[1]	values[6]	426	1			T11	20		T25	8		T35	114
auto[0]	values[1]	values[7]	187	1			T6	13		T183	12		T210	9
auto[0]	values[2]	values[0]	228	1			T11	21		T28	13		T190	12
auto[0]	values[2]	values[1]	395	1			T27	16		T41	93		T79	12
auto[0]	values[2]	values[2]	293	1			T6	14		T21	9		T182	10
auto[0]	values[2]	values[3]	394	1			T8	26		T35	8		T79	14
auto[0]	values[2]	values[4]	268	1			T6	56		T9	34		T11	14
auto[0]	values[2]	values[5]	377	1			T5	46		T9	11		T11	13
auto[0]	values[2]	values[6]	357	1			T6	214		T16	24		T211	6
auto[0]	values[2]	values[7]	254	1			T27	14		T21	14		T45	14
auto[0]	values[3]	values[0]	293	1			T6	25		T11	15		T79	13
auto[0]	values[3]	values[1]	262	1			T40	27		T159	9		T20	22
auto[0]	values[3]	values[2]	258	1			T35	7		T21	13		T194	22
auto[0]	values[3]	values[3]	167	1			T182	13		T160	6		T212	7
auto[0]	values[3]	values[4]	221	1			T213	8		T214	18		T182	10
auto[0]	values[3]	values[5]	146	1			T35	15		T38	17		T175	14
auto[0]	values[3]	values[6]	182	1			T28	16		T79	8		T180	13
auto[0]	values[3]	values[7]	271	1			T6	10		T11	14		T28	12
auto[0]	values[4]	values[0]	337	1			T6	40		T37	58		T215	40
auto[0]	values[4]	values[1]	134	1			T27	12		T51	4		T182	5
auto[0]	values[4]	values[2]	377	1			T9	13		T27	15		T28	12
auto[0]	values[4]	values[3]	196	1			T12	20		T28	10		T38	12
auto[0]	values[4]	values[4]	126	1			T71	16		T20	9		T215	7
auto[0]	values[4]	values[5]	242	1			T20	11		T216	52		T217	11
auto[0]	values[4]	values[6]	254	1			T38	10		T79	13		T21	17
auto[0]	values[4]	values[7]	426	1			T37	13		T188	18		T218	4
auto[0]	values[5]	values[0]	344	1			T6	16		T9	15		T35	12
auto[0]	values[5]	values[1]	286	1			T20	170		T174	14		T52	8
auto[0]	values[5]	values[2]	434	1			T28	14		T16	9		T20	7
auto[0]	values[5]	values[3]	198	1			T219	2		T79	8		T21	37
auto[0]	values[5]	values[4]	124	1			T20	8		T21	7		T220	18
auto[0]	values[5]	values[5]	293	1			T6	10		T11	19		T16	10
auto[0]	values[5]	values[6]	182	1			T27	12		T221	13		T222	10
auto[0]	values[5]	values[7]	259	1			T11	15		T79	13		T21	11
auto[0]	values[6]	values[0]	379	1			T186	14		T178	14		T223	2
auto[0]	values[6]	values[1]	304	1			T27	16		T180	28		T21	14
auto[0]	values[6]	values[2]	318	1			T11	15		T71	11		T224	8
auto[0]	values[6]	values[3]	270	1			T28	17		T80	2		T20	14
auto[0]	values[6]	values[4]	296	1			T8	12		T186	14		T161	13
auto[0]	values[6]	values[5]	328	1			T8	6		T11	16		T35	101
auto[0]	values[6]	values[6]	317	1			T27	13		T16	18		T225	4
auto[0]	values[6]	values[7]	141	1			T28	9		T16	27		T226	16
auto[0]	values[7]	values[0]	293	1			T20	14		T161	25		T190	11
auto[0]	values[7]	values[1]	235	1			T227	29		T20	15		T189	4
auto[0]	values[7]	values[2]	404	1			T9	15		T35	12		T79	11
auto[0]	values[7]	values[3]	192	1			T79	10		T71	8		T21	20
auto[0]	values[7]	values[4]	211	1			T177	6		T190	25		T194	11
auto[0]	values[7]	values[5]	200	1			T21	8		T161	17		T228	14
auto[0]	values[7]	values[6]	330	1			T8	12		T30	13		T229	12
auto[0]	values[7]	values[7]	229	1			T230	6		T79	11		T231	16
auto[1]	values[0]	values[0]	130	1			T71	17		T179	8		T194	8
auto[1]	values[0]	values[1]	213	1			T27	7		T71	19		T186	7
auto[1]	values[0]	values[2]	134	1			T16	11		T159	6		T20	10
auto[1]	values[0]	values[3]	160	1			T79	8		T161	7		T221	7
auto[1]	values[0]	values[4]	305	1			T27	18		T35	9		T71	11
auto[1]	values[0]	values[5]	167	1			T9	5		T35	8		T30	19
auto[1]	values[0]	values[6]	88	1			T28	6		T180	11		T20	9
auto[1]	values[0]	values[7]	254	1			T35	69		T37	9		T180	10
auto[1]	values[1]	values[0]	146	1			T114	10		T194	15		T232	78
auto[1]	values[1]	values[1]	215	1			T6	16		T8	21		T9	6
auto[1]	values[1]	values[2]	143	1			T27	13		T16	7		T20	12
auto[1]	values[1]	values[3]	253	1			T28	5		T159	8		T20	50
auto[1]	values[1]	values[4]	211	1			T186	8		T182	28		T158	27
auto[1]	values[1]	values[5]	390	1			T8	31		T161	9		T179	132
auto[1]	values[1]	values[6]	263	1			T11	21		T35	12		T16	4
auto[1]	values[1]	values[7]	161	1			T6	7		T183	8		T233	18
auto[1]	values[2]	values[0]	99	1			T11	4		T28	7		T190	8
auto[1]	values[2]	values[1]	141	1			T27	9		T79	8		T21	20
auto[1]	values[2]	values[2]	179	1			T6	6		T21	11		T182	10
auto[1]	values[2]	values[3]	315	1			T8	4		T35	47		T79	6
auto[1]	values[2]	values[4]	179	1			T6	13		T9	10		T11	6
auto[1]	values[2]	values[5]	176	1			T9	9		T11	7		T35	26
auto[1]	values[2]	values[6]	269	1			T6	9		T16	140		T186	12
auto[1]	values[2]	values[7]	122	1			T27	9		T21	11		T160	6
auto[1]	values[3]	values[0]	260	1			T6	55		T11	5		T79	7
auto[1]	values[3]	values[1]	161	1			T40	14		T234	12		T159	11
auto[1]	values[3]	values[2]	110	1			T35	13		T21	7		T194	5
auto[1]	values[3]	values[3]	129	1			T182	7		T160	14		T212	13
auto[1]	values[3]	values[4]	107	1			T182	31		T173	6		T222	10
auto[1]	values[3]	values[5]	128	1			T35	5		T38	3		T160	8
auto[1]	values[3]	values[6]	148	1			T28	9		T79	12		T180	11
auto[1]	values[3]	values[7]	177	1			T6	15		T11	8		T28	8
auto[1]	values[4]	values[0]	277	1			T6	8		T37	127		T215	28
auto[1]	values[4]	values[1]	163	1			T27	9		T182	17		T200	9
auto[1]	values[4]	values[2]	180	1			T9	11		T27	6		T28	8
auto[1]	values[4]	values[3]	159	1			T28	10		T38	8		T71	11
auto[1]	values[4]	values[4]	151	1			T71	12		T20	75		T215	13
auto[1]	values[4]	values[5]	89	1			T20	9		T216	3		T217	10
auto[1]	values[4]	values[6]	117	1			T235	14		T38	10		T79	7
auto[1]	values[4]	values[7]	253	1			T37	7		T178	8		T221	5
auto[1]	values[5]	values[0]	322	1			T6	26		T9	11		T35	105
auto[1]	values[5]	values[1]	84	1			T20	12		T160	19		T236	8
auto[1]	values[5]	values[2]	333	1			T28	7		T16	11		T20	35
auto[1]	values[5]	values[3]	124	1			T79	12		T21	11		T114	14
auto[1]	values[5]	values[4]	137	1			T192	14		T20	14		T21	15
auto[1]	values[5]	values[5]	302	1			T6	10		T11	3		T16	11
auto[1]	values[5]	values[6]	90	1			T27	8		T221	7		T222	10
auto[1]	values[5]	values[7]	187	1			T11	7		T79	7		T21	11
auto[1]	values[6]	values[0]	131	1			T186	6		T178	7		T179	5
auto[1]	values[6]	values[1]	218	1			T27	11		T180	5		T21	10
auto[1]	values[6]	values[2]	162	1			T11	8		T71	9		T161	5
auto[1]	values[6]	values[3]	155	1			T28	10		T20	6		T186	12
auto[1]	values[6]	values[4]	203	1			T8	8		T186	6		T161	7
auto[1]	values[6]	values[5]	243	1			T8	130		T11	6		T35	4
auto[1]	values[6]	values[6]	155	1			T27	8		T16	2		T20	7
auto[1]	values[6]	values[7]	114	1			T28	11		T16	43		T177	11
auto[1]	values[7]	values[0]	142	1			T20	6		T161	17		T190	9
auto[1]	values[7]	values[1]	216	1			T227	12		T20	34		T194	13
auto[1]	values[7]	values[2]	130	1			T9	5		T35	8		T79	9
auto[1]	values[7]	values[3]	166	1			T79	10		T71	12		T21	4
auto[1]	values[7]	values[4]	169	1			T237	20		T177	14		T190	8
auto[1]	values[7]	values[5]	119	1			T21	25		T161	16		T158	6
auto[1]	values[7]	values[6]	213	1			T8	10		T30	9		T21	7
auto[1]	values[7]	values[7]	132	1			T79	9		T194	13		T232	32