Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	429	1			T6	8		T8	2		T9	1
auto[ReadAddrCrossIntoMailbox]	268	1			T6	6		T8	4		T9	2
auto[ReadAddrCrossOutOfMailbox]	270	1			T6	2		T8	3		T9	2
auto[ReadAddrCrossAllMailbox]	185	1			T6	4		T8	3		T9	3
auto[ReadAddrOutsideMailbox]	3526	1			T5	2		T6	32		T8	22

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2298

1

T5

1

T6

25

T8

16

auto[1]

2380

1

T5

1

T6

27

T8

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	743	1			T6	8		T8	6		T9	2
read_ops[0x0b]	745	1			T6	8		T8	4		T9	5
read_ops[0x3b]	803	1			T6	7		T8	9		T9	9
read_ops[0x6b]	785	1			T6	12		T8	2		T9	5
read_ops[0xbb]	798	1			T6	12		T8	11		T9	6
read_ops[0xeb]	804	1			T5	2		T6	5		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T8	1		T28	1		T35	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T6	2		T27	1		T35	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T71	1		T21	3		T238	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T11	1		T27	2		T35	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T37	1		T207	1		T184	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T11	2		T27	1		T30	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T8	1		T11	1		T37	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T35	1		T20	1		T114	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	275	1			T6	2		T8	3		T11	5
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T6	4		T8	1		T9	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T9	1		T16	1		T186	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T6	1		T8	1		T21	3
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T16	2		T38	1		T194	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T6	1		T37	1		T114	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T30	1		T182	1		T194	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T8	1		T28	1		T37	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T9	1		T79	1		T207	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T6	2		T11	1		T37	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	273	1			T6	3		T8	2		T9	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	272	1			T6	1		T9	2		T11	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T11	1		T30	2		T71	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T6	1		T28	1		T71	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T8	2		T27	1		T21	3
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T8	2		T9	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T9	2		T35	1		T16	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T8	2		T35	1		T21	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T9	1		T186	1		T158	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T35	1		T79	1		T217	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	315	1			T6	5		T8	1		T11	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T6	1		T8	2		T9	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T6	2		T11	1		T25	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T25	1		T35	1		T37	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T6	2		T27	1		T28	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T9	1		T79	1		T20	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T35	1		T194	1		T222	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T16	1		T20	1		T21	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T6	1		T21	2		T239	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T11	2		T215	1		T238	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T6	5		T9	2		T11	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T6	2		T8	2		T9	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T6	1		T37	1		T159	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T35	2		T79	1		T20	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T6	3		T28	1		T38	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T35	1		T180	1		T207	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T71	2		T21	2		T158	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T6	1		T37	1		T38	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T8	1		T159	1		T178	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T6	1		T8	1		T35	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T8	3		T9	3		T11	7
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T6	6		T8	6		T9	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T71	1		T188	1		T20	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T6	1		T71	2		T188	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T35	1		T159	1		T20	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T71	1		T186	2		T114	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T27	3		T28	1		T180	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T6	1		T37	1		T16	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T238	2		T194	2		T210	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T9	1		T16	1		T21	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	293	1			T5	1		T6	1		T8	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	315	1			T5	1		T6	2		T9	2