Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3187	1			T6	117		T8	207		T9	20
values[1]	3869	1			T6	97		T11	20		T28	20
values[2]	3263	1			T5	46		T6	51		T27	20
values[3]	3740	1			T6	252		T9	40		T11	40
values[4]	4231	1			T6	40		T8	72		T9	20
values[5]	3955	1			T3	6		T6	45		T8	32
values[6]	3444	1			T6	20		T11	22		T27	41
values[7]	3168	1			T8	20		T9	90		T11	47

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3208	1			T6	94		T11	45		T27	61
values[1]	3450	1			T6	42		T8	188		T9	40
values[2]	3225	1			T6	20		T9	20		T11	42
values[3]	3603	1			T6	278		T11	22		T12	20
values[4]	3613	1			T3	6		T8	40		T9	26
values[5]	4058	1			T6	49		T8	32		T9	20
values[6]	4113	1			T6	91		T8	20		T9	68
values[7]	3587	1			T5	46		T6	48		T8	51

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28081

1

T3

6

T5

46

T6

609

auto[1]

776

1

T6

13

T8

6

T9

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	375	1			T6	69		T27	19		T20	20
auto[0]	values[0]	values[1]	588	1			T8	136		T37	135		T181	6
auto[0]	values[0]	values[2]	250	1			T9	20		T178	17		T240	18
auto[0]	values[0]	values[3]	371	1			T11	22		T12	20		T79	20
auto[0]	values[0]	values[4]	238	1			T71	19		T184	20		T173	19
auto[0]	values[0]	values[5]	476	1			T79	20		T225	4		T20	62
auto[0]	values[0]	values[6]	277	1			T8	20		T47	24		T184	20
auto[0]	values[0]	values[7]	511	1			T6	46		T8	48		T27	22
auto[0]	values[1]	values[0]	402	1			T235	14		T198	20		T194	30
auto[0]	values[1]	values[1]	556	1			T6	42		T16	86		T20	132
auto[0]	values[1]	values[2]	371	1			T11	16		T218	4		T182	22
auto[0]	values[1]	values[3]	690	1			T6	53		T227	20		T20	20
auto[0]	values[1]	values[4]	554	1			T35	144		T30	20		T37	49
auto[0]	values[1]	values[5]	353	1			T28	20		T230	6		T219	2
auto[0]	values[1]	values[6]	317	1			T241	2		T211	6		T195	14
auto[0]	values[1]	values[7]	528	1			T188	18		T21	20		T223	2
auto[0]	values[2]	values[0]	379	1			T27	16		T37	20		T237	14
auto[0]	values[2]	values[1]	285	1			T38	15		T192	14		T20	65
auto[0]	values[2]	values[2]	493	1			T177	25		T184	44		T173	20
auto[0]	values[2]	values[3]	429	1			T28	31		T20	40		T161	21
auto[0]	values[2]	values[4]	471	1			T16	20		T79	19		T227	38
auto[0]	values[2]	values[5]	282	1			T242	14		T182	41		T158	20
auto[0]	values[2]	values[6]	569	1			T6	51		T28	20		T16	119
auto[0]	values[2]	values[7]	265	1			T5	46		T20	44		T186	20
auto[0]	values[3]	values[0]	358	1			T234	12		T226	16		T243	16
auto[0]	values[3]	values[1]	453	1			T9	40		T28	39		T79	18
auto[0]	values[3]	values[2]	514	1			T159	20		T21	19		T221	107
auto[0]	values[3]	values[3]	585	1			T6	219		T79	20		T71	20
auto[0]	values[3]	values[4]	281	1			T11	19		T162	2		T212	17
auto[0]	values[3]	values[5]	403	1			T6	29		T27	28		T79	19
auto[0]	values[3]	values[6]	488	1			T16	20		T207	6		T224	8
auto[0]	values[3]	values[7]	549	1			T11	19		T28	20		T35	116
auto[0]	values[4]	values[0]	582	1			T11	19		T79	20		T21	20
auto[0]	values[4]	values[1]	487	1			T8	51		T17	22		T79	16
auto[0]	values[4]	values[2]	328	1			T71	30		T173	20		T189	4
auto[0]	values[4]	values[3]	425	1			T28	25		T20	20		T21	23
auto[0]	values[4]	values[4]	611	1			T8	19		T25	8		T35	105
auto[0]	values[4]	values[5]	632	1			T6	20		T9	20		T11	20
auto[0]	values[4]	values[6]	606	1			T6	20		T16	39		T229	12
auto[0]	values[4]	values[7]	433	1			T71	32		T20	28		T45	14
auto[0]	values[5]	values[0]	458	1			T6	23		T35	53		T30	30
auto[0]	values[5]	values[1]	279	1			T27	22		T35	19		T244	2
auto[0]	values[5]	values[2]	365	1			T6	20		T16	20		T38	20
auto[0]	values[5]	values[3]	283	1			T28	16		T79	19		T215	20
auto[0]	values[5]	values[4]	625	1			T3	6		T11	21		T16	20
auto[0]	values[5]	values[5]	685	1			T8	32		T11	21		T27	40
auto[0]	values[5]	values[6]	853	1			T9	24		T35	20		T20	179
auto[0]	values[5]	values[7]	320	1			T81	10		T79	20		T161	19
auto[0]	values[6]	values[0]	294	1			T27	19		T21	20		T245	12
auto[0]	values[6]	values[1]	380	1			T27	20		T161	25		T114	24
auto[0]	values[6]	values[2]	362	1			T21	24		T178	18		T173	40
auto[0]	values[6]	values[3]	378	1			T80	2		T180	24		T178	23
auto[0]	values[6]	values[4]	467	1			T202	8		T246	12		T247	12
auto[0]	values[6]	values[5]	597	1			T16	143		T38	20		T71	16
auto[0]	values[6]	values[6]	447	1			T6	17		T79	20		T159	20
auto[0]	values[6]	values[7]	450	1			T11	21		T180	33		T21	40
auto[0]	values[7]	values[0]	250	1			T11	23		T206	4		T160	38
auto[0]	values[7]	values[1]	330	1			T27	20		T41	93		T16	70
auto[0]	values[7]	values[2]	453	1			T11	21		T248	6		T182	20
auto[0]	values[7]	values[3]	336	1			T21	25		T186	20		T177	46
auto[0]	values[7]	values[4]	283	1			T8	19		T9	26		T220	18
auto[0]	values[7]	values[5]	519	1			T27	24		T28	25		T159	19
auto[0]	values[7]	values[6]	459	1			T9	43		T71	28		T20	18
auto[0]	values[7]	values[7]	443	1			T9	20		T35	58		T16	20
auto[1]	values[0]	values[0]	10	1			T27	1		T236	2		T249	3
auto[1]	values[0]	values[1]	4	1			T173	1		T119	1		T122	2
auto[1]	values[0]	values[2]	19	1			T178	4		T250	4		T139	1
auto[1]	values[0]	values[3]	18	1			T21	1		T194	3		T217	2
auto[1]	values[0]	values[4]	4	1			T71	1		T173	1		T185	1
auto[1]	values[0]	values[5]	15	1			T20	4		T114	1		T198	3
auto[1]	values[0]	values[6]	8	1			T217	1		T138	1		T251	3
auto[1]	values[0]	values[7]	23	1			T6	2		T8	3		T27	3
auto[1]	values[1]	values[0]	7	1			T194	2		T252	2		T253	1
auto[1]	values[1]	values[1]	13	1			T16	2		T20	1		T210	4
auto[1]	values[1]	values[2]	16	1			T11	4		T254	3		T255	4
auto[1]	values[1]	values[3]	25	1			T6	2		T177	2		T184	4
auto[1]	values[1]	values[4]	13	1			T35	2		T30	2		T37	1
auto[1]	values[1]	values[5]	10	1			T232	1		T256	1		T185	1
auto[1]	values[1]	values[6]	2	1			T118	1		T121	1		-	-
auto[1]	values[1]	values[7]	12	1			T179	3		T173	3		T257	1
auto[1]	values[2]	values[0]	23	1			T27	4		T237	6		T186	1
auto[1]	values[2]	values[1]	7	1			T38	5		T20	1		T258	1
auto[1]	values[2]	values[2]	10	1			T177	3		T200	1		T258	1
auto[1]	values[2]	values[3]	11	1			T161	1		T194	2		T232	1
auto[1]	values[2]	values[4]	9	1			T79	1		T227	3		T194	1
auto[1]	values[2]	values[5]	10	1			T173	1		T115	1		T259	2
auto[1]	values[2]	values[6]	15	1			T28	3		T21	1		T136	1
auto[1]	values[2]	values[7]	5	1			T20	2		T210	1		T260	1
auto[1]	values[3]	values[0]	18	1			T239	4		T261	2		T217	1
auto[1]	values[3]	values[1]	19	1			T28	2		T79	2		T71	1
auto[1]	values[3]	values[2]	11	1			T21	1		T221	2		T177	1
auto[1]	values[3]	values[3]	12	1			T6	4		T114	2		T251	1
auto[1]	values[3]	values[4]	7	1			T11	1		T212	3		T173	1
auto[1]	values[3]	values[5]	16	1			T27	5		T79	1		T212	2
auto[1]	values[3]	values[6]	11	1			T198	1		T179	3		T194	1
auto[1]	values[3]	values[7]	15	1			T11	1		T35	1		T71	4
auto[1]	values[4]	values[0]	21	1			T11	1		T21	2		T160	1
auto[1]	values[4]	values[1]	13	1			T8	1		T79	4		T186	1
auto[1]	values[4]	values[2]	8	1			T71	1		T194	1		T262	1
auto[1]	values[4]	values[3]	17	1			T28	2		T21	1		T263	2
auto[1]	values[4]	values[4]	16	1			T8	1		T71	2		T198	1
auto[1]	values[4]	values[5]	21	1			T11	2		T37	2		T40	1
auto[1]	values[4]	values[6]	15	1			T16	1		T194	5		T232	2
auto[1]	values[4]	values[7]	16	1			T71	3		T20	1		T160	4
auto[1]	values[5]	values[0]	11	1			T6	2		T35	2		T38	1
auto[1]	values[5]	values[1]	23	1			T27	1		T35	1		T244	2
auto[1]	values[5]	values[2]	3	1			T16	1		T264	2		-	-
auto[1]	values[5]	values[3]	6	1			T28	4		T79	1		T262	1
auto[1]	values[5]	values[4]	14	1			T11	2		T161	1		T217	2
auto[1]	values[5]	values[5]	10	1			T27	1		T20	1		T232	3
auto[1]	values[5]	values[6]	16	1			T20	3		T177	1		T179	1
auto[1]	values[5]	values[7]	4	1			T161	1		T262	1		T265	1
auto[1]	values[6]	values[0]	6	1			T27	2		T258	4		-	-
auto[1]	values[6]	values[1]	11	1			T136	1		T254	2		T119	3
auto[1]	values[6]	values[2]	11	1			T21	4		T178	4		T266	1
auto[1]	values[6]	values[3]	6	1			T139	1		T265	1		T32	3
auto[1]	values[6]	values[4]	8	1			T177	1		T260	1		T267	3
auto[1]	values[6]	values[5]	16	1			T16	1		T71	4		T20	1
auto[1]	values[6]	values[6]	6	1			T6	3		T20	1		T173	1
auto[1]	values[6]	values[7]	5	1			T11	1		T114	1		T236	1
auto[1]	values[7]	values[0]	14	1			T11	2		T160	2		T114	3
auto[1]	values[7]	values[1]	2	1			T27	1		T21	1		-	-
auto[1]	values[7]	values[2]	11	1			T11	1		T173	2		T194	1
auto[1]	values[7]	values[3]	11	1			T177	4		T262	1		T268	1
auto[1]	values[7]	values[4]	12	1			T8	1		T176	1		T232	2
auto[1]	values[7]	values[5]	13	1			T27	3		T159	1		T186	1
auto[1]	values[7]	values[6]	24	1			T9	1		T71	1		T20	2
auto[1]	values[7]	values[7]	8	1			T21	5		T185	2		T269	1