Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	784	1			T8	21		T9	21		T17	8
all_values[1]	784	1			T8	21		T9	21		T17	8
all_values[2]	784	1			T8	21		T9	21		T17	8
all_values[3]	784	1			T8	21		T9	21		T17	8
all_values[4]	784	1			T8	21		T9	21		T17	8
all_values[5]	784	1			T8	21		T9	21		T17	8
all_values[6]	784	1			T8	21		T9	21		T17	8
all_values[7]	784	1			T8	21		T9	21		T17	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3310

1

T8

80

T9

85

T17

35

auto[1]

2962

1

T8

88

T9

83

T17

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2453

1

T8

70

T9

71

T17

31

auto[1]

3819

1

T8

98

T9

97

T17

33

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3554

1

T8

98

T9

106

T17

43

auto[1]

2718

1

T8

70

T9

62

T17

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	154	1			T8	1		T9	8		T18	2
all_values[0]	auto[0]	auto[0]	auto[1]	74	1			T8	1		T9	1		T17	2
all_values[0]	auto[0]	auto[1]	auto[0]	109	1			T8	4		T9	4		T17	1
all_values[0]	auto[0]	auto[1]	auto[1]	87	1			T8	5		T9	2		T141	3
all_values[0]	auto[1]	auto[0]	auto[1]	176	1			T8	2		T9	3		T17	3
all_values[0]	auto[1]	auto[1]	auto[1]	184	1			T8	8		T9	3		T17	2
all_values[1]	auto[0]	auto[0]	auto[0]	154	1			T8	2		T9	5		T17	3
all_values[1]	auto[0]	auto[0]	auto[1]	66	1			T18	1		T141	3		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	145	1			T8	6		T9	5		T17	2
all_values[1]	auto[0]	auto[1]	auto[1]	86	1			T8	4		T9	3		T19	5
all_values[1]	auto[1]	auto[0]	auto[1]	163	1			T8	3		T9	1		T17	1
all_values[1]	auto[1]	auto[1]	auto[1]	170	1			T8	6		T9	7		T17	2
all_values[2]	auto[0]	auto[0]	auto[0]	161	1			T8	7		T9	1		T17	4
all_values[2]	auto[0]	auto[0]	auto[1]	80	1			T8	1		T9	2		T19	1
all_values[2]	auto[0]	auto[1]	auto[0]	136	1			T8	3		T9	3		T18	2
all_values[2]	auto[0]	auto[1]	auto[1]	72	1			T8	2		T9	3		T17	1
all_values[2]	auto[1]	auto[0]	auto[1]	186	1			T8	6		T9	4		T17	2
all_values[2]	auto[1]	auto[1]	auto[1]	149	1			T8	2		T9	8		T17	1
all_values[3]	auto[0]	auto[0]	auto[0]	154	1			T8	5		T9	1		T17	2
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T8	4		T9	3		T17	2
all_values[3]	auto[0]	auto[1]	auto[0]	124	1			T8	2		T9	5		T141	3
all_values[3]	auto[0]	auto[1]	auto[1]	79	1			T8	3		T9	3		T17	1
all_values[3]	auto[1]	auto[0]	auto[1]	195	1			T8	6		T9	5		T17	2
all_values[3]	auto[1]	auto[1]	auto[1]	145	1			T8	1		T9	4		T17	1
all_values[4]	auto[0]	auto[0]	auto[0]	152	1			T8	5		T9	2		T17	1
all_values[4]	auto[0]	auto[0]	auto[1]	69	1			T8	2		T141	1		T142	2
all_values[4]	auto[0]	auto[1]	auto[0]	119	1			T8	2		T9	9		T18	2
all_values[4]	auto[0]	auto[1]	auto[1]	89	1			T8	3		T9	3		T17	4
all_values[4]	auto[1]	auto[0]	auto[1]	194	1			T8	4		T9	6		T17	2
all_values[4]	auto[1]	auto[1]	auto[1]	161	1			T8	5		T9	1		T17	1
all_values[5]	auto[0]	auto[0]	auto[0]	222	1			T8	6		T9	6		T17	4
all_values[5]	auto[0]	auto[1]	auto[0]	226	1			T8	7		T9	9		T17	2
all_values[5]	auto[1]	auto[0]	auto[1]	185	1			T8	3		T9	4		T19	2
all_values[5]	auto[1]	auto[1]	auto[1]	151	1			T8	5		T9	2		T17	2
all_values[6]	auto[0]	auto[0]	auto[0]	176	1			T8	10		T9	6		T17	3
all_values[6]	auto[0]	auto[0]	auto[1]	67	1			T9	4		T17	1		T114	1
all_values[6]	auto[0]	auto[1]	auto[0]	136	1			T8	5		T9	1		T17	3
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T9	2		T19	1		T141	2
all_values[6]	auto[1]	auto[0]	auto[1]	178	1			T8	3		T9	7		T17	1
all_values[6]	auto[1]	auto[1]	auto[1]	146	1			T8	3		T9	1		T19	2
all_values[7]	auto[0]	auto[0]	auto[0]	159	1			T8	4		T9	5		T17	1
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T8	1		T9	6		T141	1
all_values[7]	auto[0]	auto[1]	auto[0]	126	1			T8	1		T9	1		T17	5
all_values[7]	auto[0]	auto[1]	auto[1]	85	1			T8	2		T9	3		T17	1
all_values[7]	auto[1]	auto[0]	auto[1]	179	1			T8	4		T9	5		T17	1
all_values[7]	auto[1]	auto[1]	auto[1]	156	1			T8	9		T9	1		T18	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal