Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1935

1

T2

8

T8

10

T9

10

auto[1]

1872

1

T2

5

T8

11

T9

3

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2173

1

T8

15

T9

9

T11

31

auto[1]

1634

1

T2

13

T8

6

T9

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2983

1

T2

13

T8

17

T9

10

auto[1]

824

1

T8

4

T9

3

T11

15

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	766	1			T2	3		T8	3		T9	2
valid[1]	763	1			T2	4		T8	1		T9	3
valid[2]	729	1			T2	2		T8	6		T9	1
valid[3]	763	1			T2	2		T8	4		T9	2
valid[4]	786	1			T2	2		T8	7		T9	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	163	1			T8	1		T9	1		T11	2
auto[0]	auto[0]	valid[0]	auto[1]	160	1			T2	2		T9	1		T11	1
auto[0]	auto[0]	valid[1]	auto[0]	146	1			T27	1		T28	1		T18	3
auto[0]	auto[0]	valid[1]	auto[1]	176	1			T2	3		T11	1		T26	4
auto[0]	auto[0]	valid[2]	auto[0]	120	1			T8	1		T9	1		T11	3
auto[0]	auto[0]	valid[2]	auto[1]	143	1			T8	2		T11	1		T26	2
auto[0]	auto[0]	valid[3]	auto[0]	140	1			T8	3		T11	1		T27	2
auto[0]	auto[0]	valid[3]	auto[1]	172	1			T2	1		T11	1		T26	2
auto[0]	auto[0]	valid[4]	auto[0]	138	1			T9	3		T11	3		T27	1
auto[0]	auto[0]	valid[4]	auto[1]	161	1			T2	2		T8	2		T9	1
auto[0]	auto[1]	valid[0]	auto[0]	126	1			T11	1		T27	1		T18	1
auto[0]	auto[1]	valid[0]	auto[1]	166	1			T2	1		T11	1		T26	1
auto[0]	auto[1]	valid[1]	auto[0]	128	1			T8	1		T11	2		T27	1
auto[0]	auto[1]	valid[1]	auto[1]	147	1			T2	1		T9	2		T26	2
auto[0]	auto[1]	valid[2]	auto[0]	124	1			T8	2		T11	1		T28	2
auto[0]	auto[1]	valid[2]	auto[1]	169	1			T2	2		T26	5		T75	1
auto[0]	auto[1]	valid[3]	auto[0]	143	1			T9	1		T11	2		T27	2
auto[0]	auto[1]	valid[3]	auto[1]	150	1			T2	1		T11	1		T26	1
auto[0]	auto[1]	valid[4]	auto[0]	121	1			T8	3		T11	1		T27	2
auto[0]	auto[1]	valid[4]	auto[1]	190	1			T8	2		T11	4		T26	2
auto[1]	auto[0]	valid[0]	auto[0]	86	1			T11	3		T28	2		T29	1
auto[1]	auto[0]	valid[1]	auto[0]	80	1			T9	1		T11	2		T40	1
auto[1]	auto[0]	valid[2]	auto[0]	78	1			T11	1		T27	3		T28	1
auto[1]	auto[0]	valid[3]	auto[0]	82	1			T8	1		T9	1		T11	1
auto[1]	auto[0]	valid[4]	auto[0]	90	1			T9	1		T11	2		T28	1
auto[1]	auto[1]	valid[0]	auto[0]	65	1			T8	2		T11	2		T18	2
auto[1]	auto[1]	valid[1]	auto[0]	86	1			T11	2		T28	1		T75	1
auto[1]	auto[1]	valid[2]	auto[0]	95	1			T8	1		T11	1		T27	2
auto[1]	auto[1]	valid[3]	auto[0]	76	1			T11	1		T27	1		T40	1
auto[1]	auto[1]	valid[4]	auto[0]	86	1			T28	2		T29	1		T40	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal