Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56575

1

T8

507

T9

266

T11

798

auto[1]

17739

1

T2

136

T8

83

T9

76

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53561

1

T2

136

T8

408

T9

230

auto[1]

20753

1

T8

182

T9

112

T11

291

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	38256	1			T2	80		T8	289		T9	176
others[1]	6255	1			T2	8		T8	62		T9	26
others[2]	6336	1			T2	13		T8	55		T9	28
others[3]	7113	1			T2	6		T8	69		T9	31
interest[1]	4033	1			T2	8		T8	20		T9	21
interest[4]	24824	1			T2	41		T8	189		T9	121
interest[64]	12321	1			T2	21		T8	95		T9	60

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	18457	1			T8	168		T9	78		T11	253
auto[0]	auto[0]	others[1]	3051	1			T8	34		T9	14		T11	42
auto[0]	auto[0]	others[2]	2993	1			T8	32		T9	14		T11	55
auto[0]	auto[0]	others[3]	3393	1			T8	29		T9	13		T11	49
auto[0]	auto[0]	interest[1]	2009	1			T8	10		T9	9		T11	31
auto[0]	auto[0]	interest[4]	12030	1			T8	112		T9	56		T11	176
auto[0]	auto[0]	interest[64]	5919	1			T8	52		T9	26		T11	77
auto[0]	auto[1]	others[0]	9228	1			T2	80		T8	40		T9	36
auto[0]	auto[1]	others[1]	1502	1			T2	8		T8	7		T9	4
auto[0]	auto[1]	others[2]	1555	1			T2	13		T8	10		T9	8
auto[0]	auto[1]	others[3]	1649	1			T2	6		T8	8		T9	13
auto[0]	auto[1]	interest[1]	901	1			T2	8		T8	1		T9	4
auto[0]	auto[1]	interest[4]	6017	1			T2	41		T8	26		T9	30
auto[0]	auto[1]	interest[64]	2904	1			T2	21		T8	17		T9	11
auto[1]	auto[0]	others[0]	10571	1			T8	81		T9	62		T11	155
auto[1]	auto[0]	others[1]	1702	1			T8	21		T9	8		T11	10
auto[1]	auto[0]	others[2]	1788	1			T8	13		T9	6		T11	22
auto[1]	auto[0]	others[3]	2071	1			T8	32		T9	5		T11	33
auto[1]	auto[0]	interest[1]	1123	1			T8	9		T9	8		T11	16
auto[1]	auto[0]	interest[4]	6777	1			T8	51		T9	35		T11	102
auto[1]	auto[0]	interest[64]	3498	1			T8	26		T9	23		T11	55

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal