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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T130 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.694050682 Aug 18 04:45:15 PM PDT 24 Aug 18 04:45:18 PM PDT 24 1937210060 ps
T1040 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.792030359 Aug 18 04:44:54 PM PDT 24 Aug 18 04:44:57 PM PDT 24 81101867 ps
T92 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1259269724 Aug 18 04:45:08 PM PDT 24 Aug 18 04:45:10 PM PDT 24 240634914 ps
T131 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.527587504 Aug 18 04:44:53 PM PDT 24 Aug 18 04:44:57 PM PDT 24 185796285 ps
T1041 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3101257061 Aug 18 04:45:04 PM PDT 24 Aug 18 04:45:05 PM PDT 24 61987381 ps
T132 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2061091307 Aug 18 04:44:53 PM PDT 24 Aug 18 04:44:56 PM PDT 24 110163299 ps
T104 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2122384402 Aug 18 04:44:51 PM PDT 24 Aug 18 04:44:59 PM PDT 24 356617863 ps
T87 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1816645687 Aug 18 04:45:05 PM PDT 24 Aug 18 04:45:13 PM PDT 24 284283883 ps
T94 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3661487755 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:55 PM PDT 24 86647680 ps
T144 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3859618048 Aug 18 04:44:56 PM PDT 24 Aug 18 04:45:10 PM PDT 24 596256295 ps
T1042 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1754724560 Aug 18 04:45:10 PM PDT 24 Aug 18 04:45:11 PM PDT 24 27693452 ps
T105 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.288980007 Aug 18 04:44:56 PM PDT 24 Aug 18 04:44:59 PM PDT 24 330843138 ps
T111 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2780094558 Aug 18 04:44:41 PM PDT 24 Aug 18 04:44:53 PM PDT 24 365172120 ps
T1043 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.681154444 Aug 18 04:44:56 PM PDT 24 Aug 18 04:44:58 PM PDT 24 56908293 ps
T93 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.948633904 Aug 18 04:44:57 PM PDT 24 Aug 18 04:45:01 PM PDT 24 850903343 ps
T153 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2934288325 Aug 18 04:44:55 PM PDT 24 Aug 18 04:45:10 PM PDT 24 223544283 ps
T1044 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1577841265 Aug 18 04:45:09 PM PDT 24 Aug 18 04:45:10 PM PDT 24 16273156 ps
T133 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.456756432 Aug 18 04:44:48 PM PDT 24 Aug 18 04:44:50 PM PDT 24 269419073 ps
T106 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1348148019 Aug 18 04:45:01 PM PDT 24 Aug 18 04:45:18 PM PDT 24 640144843 ps
T107 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.642280355 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:54 PM PDT 24 28520914 ps
T150 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1902649485 Aug 18 04:44:57 PM PDT 24 Aug 18 04:45:11 PM PDT 24 2167036983 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.388512824 Aug 18 04:44:48 PM PDT 24 Aug 18 04:44:52 PM PDT 24 2411058464 ps
T108 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4055294096 Aug 18 04:44:53 PM PDT 24 Aug 18 04:45:14 PM PDT 24 734815375 ps
T89 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2318654996 Aug 18 04:44:56 PM PDT 24 Aug 18 04:44:58 PM PDT 24 159698271 ps
T134 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.219972740 Aug 18 04:45:12 PM PDT 24 Aug 18 04:45:19 PM PDT 24 318983135 ps
T1046 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1914051819 Aug 18 04:45:04 PM PDT 24 Aug 18 04:45:05 PM PDT 24 48978964 ps
T135 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3244479961 Aug 18 04:45:14 PM PDT 24 Aug 18 04:45:16 PM PDT 24 390832215 ps
T1047 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3217603266 Aug 18 04:45:04 PM PDT 24 Aug 18 04:45:08 PM PDT 24 162393297 ps
T1048 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3258490566 Aug 18 04:45:01 PM PDT 24 Aug 18 04:45:02 PM PDT 24 22303840 ps
T147 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2288800906 Aug 18 04:45:18 PM PDT 24 Aug 18 04:45:26 PM PDT 24 1135313988 ps
T1049 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4278871475 Aug 18 04:44:58 PM PDT 24 Aug 18 04:44:59 PM PDT 24 60744407 ps
T1050 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3742193509 Aug 18 04:44:51 PM PDT 24 Aug 18 04:44:52 PM PDT 24 19386818 ps
T1051 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4056189621 Aug 18 04:44:57 PM PDT 24 Aug 18 04:44:58 PM PDT 24 43402378 ps
T1052 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2632474532 Aug 18 04:45:09 PM PDT 24 Aug 18 04:45:10 PM PDT 24 14893285 ps
T90 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4056919737 Aug 18 04:45:05 PM PDT 24 Aug 18 04:45:09 PM PDT 24 113496613 ps
T72 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1133990059 Aug 18 04:45:00 PM PDT 24 Aug 18 04:45:01 PM PDT 24 55518325 ps
T109 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2488679420 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:54 PM PDT 24 31078312 ps
T1053 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1537451985 Aug 18 04:45:14 PM PDT 24 Aug 18 04:45:15 PM PDT 24 14599184 ps
T1054 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1787379419 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:53 PM PDT 24 23182794 ps
T98 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3070066539 Aug 18 04:44:54 PM PDT 24 Aug 18 04:45:03 PM PDT 24 163712281 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2689284605 Aug 18 04:44:49 PM PDT 24 Aug 18 04:44:50 PM PDT 24 60049775 ps
T1056 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.204671451 Aug 18 04:45:05 PM PDT 24 Aug 18 04:45:06 PM PDT 24 185607873 ps
T1057 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.541401031 Aug 18 04:44:59 PM PDT 24 Aug 18 04:45:00 PM PDT 24 17504200 ps
T1058 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2996344753 Aug 18 04:45:21 PM PDT 24 Aug 18 04:45:22 PM PDT 24 82285400 ps
T1059 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.722365469 Aug 18 04:45:17 PM PDT 24 Aug 18 04:45:17 PM PDT 24 14571568 ps
T110 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3269554845 Aug 18 04:45:08 PM PDT 24 Aug 18 04:45:11 PM PDT 24 191730813 ps
T1060 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.310995584 Aug 18 04:45:03 PM PDT 24 Aug 18 04:45:04 PM PDT 24 32927839 ps
T112 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3148660719 Aug 18 04:45:13 PM PDT 24 Aug 18 04:45:15 PM PDT 24 27999444 ps
T1061 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3528519497 Aug 18 04:45:14 PM PDT 24 Aug 18 04:45:15 PM PDT 24 15411674 ps
T73 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2966456167 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:53 PM PDT 24 27045535 ps
T1062 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3700273672 Aug 18 04:45:03 PM PDT 24 Aug 18 04:45:04 PM PDT 24 19130876 ps
T1063 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4164072715 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:55 PM PDT 24 81229901 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1843408024 Aug 18 04:44:48 PM PDT 24 Aug 18 04:44:50 PM PDT 24 61960736 ps
T1065 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2099505414 Aug 18 04:44:59 PM PDT 24 Aug 18 04:45:02 PM PDT 24 88715405 ps
T1066 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2056534769 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:53 PM PDT 24 12119163 ps
T1067 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2736089633 Aug 18 04:45:14 PM PDT 24 Aug 18 04:45:17 PM PDT 24 151107175 ps
T1068 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1307240965 Aug 18 04:45:03 PM PDT 24 Aug 18 04:45:06 PM PDT 24 239209318 ps
T1069 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4145337838 Aug 18 04:45:10 PM PDT 24 Aug 18 04:45:11 PM PDT 24 11658694 ps
T1070 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3514594 Aug 18 04:45:07 PM PDT 24 Aug 18 04:45:08 PM PDT 24 27732997 ps
T74 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3007187201 Aug 18 04:45:01 PM PDT 24 Aug 18 04:45:02 PM PDT 24 25649210 ps
T1071 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1771863327 Aug 18 04:45:04 PM PDT 24 Aug 18 04:45:08 PM PDT 24 207116030 ps
T1072 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.888891638 Aug 18 04:45:01 PM PDT 24 Aug 18 04:45:03 PM PDT 24 29871760 ps
T1073 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2707401868 Aug 18 04:45:14 PM PDT 24 Aug 18 04:45:15 PM PDT 24 29773659 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3345686572 Aug 18 04:44:53 PM PDT 24 Aug 18 04:44:58 PM PDT 24 115441712 ps
T1075 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.634608098 Aug 18 04:44:59 PM PDT 24 Aug 18 04:45:03 PM PDT 24 919705313 ps
T1076 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4165234629 Aug 18 04:44:55 PM PDT 24 Aug 18 04:44:56 PM PDT 24 40740214 ps
T95 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2776814659 Aug 18 04:44:59 PM PDT 24 Aug 18 04:45:04 PM PDT 24 255640170 ps
T1077 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2753935650 Aug 18 04:44:59 PM PDT 24 Aug 18 04:45:01 PM PDT 24 186552912 ps
T1078 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.632257561 Aug 18 04:44:53 PM PDT 24 Aug 18 04:44:56 PM PDT 24 654658488 ps
T1079 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3719518690 Aug 18 04:45:11 PM PDT 24 Aug 18 04:45:36 PM PDT 24 1806082851 ps
T1080 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2793768802 Aug 18 04:44:55 PM PDT 24 Aug 18 04:44:59 PM PDT 24 191447492 ps
T145 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1130229315 Aug 18 04:45:07 PM PDT 24 Aug 18 04:45:26 PM PDT 24 454001998 ps
T1081 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.174744172 Aug 18 04:44:56 PM PDT 24 Aug 18 04:44:56 PM PDT 24 11233028 ps
T1082 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3768860367 Aug 18 04:45:18 PM PDT 24 Aug 18 04:45:21 PM PDT 24 209837237 ps
T1083 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1822130029 Aug 18 04:44:56 PM PDT 24 Aug 18 04:44:56 PM PDT 24 12620889 ps
T1084 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3972739490 Aug 18 04:45:21 PM PDT 24 Aug 18 04:45:22 PM PDT 24 41699411 ps
T1085 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1810381045 Aug 18 04:45:11 PM PDT 24 Aug 18 04:45:14 PM PDT 24 513747855 ps
T1086 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3962369730 Aug 18 04:44:55 PM PDT 24 Aug 18 04:44:59 PM PDT 24 156272751 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.66166455 Aug 18 04:44:59 PM PDT 24 Aug 18 04:45:02 PM PDT 24 95078693 ps
T1088 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2907568875 Aug 18 04:44:55 PM PDT 24 Aug 18 04:44:59 PM PDT 24 327353779 ps
T1089 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3007309764 Aug 18 04:44:57 PM PDT 24 Aug 18 04:45:00 PM PDT 24 122630240 ps
T1090 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1580542055 Aug 18 04:45:13 PM PDT 24 Aug 18 04:45:14 PM PDT 24 104242965 ps
T1091 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2936009957 Aug 18 04:45:15 PM PDT 24 Aug 18 04:45:16 PM PDT 24 16278859 ps
T1092 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1810658999 Aug 18 04:45:12 PM PDT 24 Aug 18 04:45:13 PM PDT 24 14492973 ps
T1093 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2531388133 Aug 18 04:44:53 PM PDT 24 Aug 18 04:44:56 PM PDT 24 106170571 ps
T1094 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.530241388 Aug 18 04:45:01 PM PDT 24 Aug 18 04:45:04 PM PDT 24 1010649894 ps
T1095 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1137967087 Aug 18 04:44:50 PM PDT 24 Aug 18 04:44:51 PM PDT 24 200989554 ps
T1096 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3911286097 Aug 18 04:44:42 PM PDT 24 Aug 18 04:44:51 PM PDT 24 1284036216 ps
T1097 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1411037403 Aug 18 04:45:10 PM PDT 24 Aug 18 04:45:14 PM PDT 24 219440829 ps
T1098 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3541377075 Aug 18 04:45:07 PM PDT 24 Aug 18 04:45:10 PM PDT 24 34407743 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3774325480 Aug 18 04:45:09 PM PDT 24 Aug 18 04:45:11 PM PDT 24 168933793 ps
T1100 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2050453681 Aug 18 04:45:10 PM PDT 24 Aug 18 04:45:14 PM PDT 24 643592970 ps
T1101 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.550911531 Aug 18 04:45:00 PM PDT 24 Aug 18 04:45:04 PM PDT 24 59909760 ps
T1102 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2670686769 Aug 18 04:45:09 PM PDT 24 Aug 18 04:45:14 PM PDT 24 17846345 ps
T1103 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.654629675 Aug 18 04:44:55 PM PDT 24 Aug 18 04:44:58 PM PDT 24 458819687 ps
T146 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.15559000 Aug 18 04:44:52 PM PDT 24 Aug 18 04:45:07 PM PDT 24 2640628634 ps
T1104 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3683627101 Aug 18 04:45:05 PM PDT 24 Aug 18 04:45:12 PM PDT 24 433171213 ps
T1105 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3558864048 Aug 18 04:44:58 PM PDT 24 Aug 18 04:44:58 PM PDT 24 15662573 ps
T1106 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3575317980 Aug 18 04:44:59 PM PDT 24 Aug 18 04:45:00 PM PDT 24 42799964 ps
T1107 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.108327243 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:54 PM PDT 24 643020162 ps
T1108 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3769219027 Aug 18 04:44:51 PM PDT 24 Aug 18 04:45:17 PM PDT 24 1883869349 ps
T1109 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2275077467 Aug 18 04:45:10 PM PDT 24 Aug 18 04:45:11 PM PDT 24 38467894 ps
T1110 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1746629487 Aug 18 04:44:53 PM PDT 24 Aug 18 04:44:55 PM PDT 24 554620553 ps
T1111 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1523020731 Aug 18 04:45:01 PM PDT 24 Aug 18 04:45:03 PM PDT 24 29998567 ps
T1112 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4213411786 Aug 18 04:45:12 PM PDT 24 Aug 18 04:45:15 PM PDT 24 325829978 ps
T1113 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.757232447 Aug 18 04:45:00 PM PDT 24 Aug 18 04:45:02 PM PDT 24 46686261 ps
T1114 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2863584772 Aug 18 04:45:08 PM PDT 24 Aug 18 04:45:09 PM PDT 24 38488518 ps
T148 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.387278608 Aug 18 04:44:58 PM PDT 24 Aug 18 04:45:20 PM PDT 24 4068451831 ps
T1115 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1957449163 Aug 18 04:45:17 PM PDT 24 Aug 18 04:45:17 PM PDT 24 29728111 ps
T1116 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2234179257 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:53 PM PDT 24 15116160 ps
T1117 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1423863749 Aug 18 04:44:56 PM PDT 24 Aug 18 04:45:24 PM PDT 24 1805907268 ps
T1118 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1537149805 Aug 18 04:45:21 PM PDT 24 Aug 18 04:45:22 PM PDT 24 14548774 ps
T1119 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4175235401 Aug 18 04:44:58 PM PDT 24 Aug 18 04:44:58 PM PDT 24 13947272 ps
T1120 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.330282360 Aug 18 04:44:55 PM PDT 24 Aug 18 04:44:56 PM PDT 24 48189147 ps
T1121 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.292157291 Aug 18 04:45:00 PM PDT 24 Aug 18 04:45:03 PM PDT 24 445325123 ps
T154 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2396784951 Aug 18 04:44:56 PM PDT 24 Aug 18 04:45:03 PM PDT 24 639908608 ps
T1122 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2794164278 Aug 18 04:44:51 PM PDT 24 Aug 18 04:44:52 PM PDT 24 13318819 ps
T151 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.797353017 Aug 18 04:45:11 PM PDT 24 Aug 18 04:45:23 PM PDT 24 768865643 ps
T1123 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3234738003 Aug 18 04:44:45 PM PDT 24 Aug 18 04:44:47 PM PDT 24 114947025 ps
T1124 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2517938775 Aug 18 04:45:08 PM PDT 24 Aug 18 04:45:11 PM PDT 24 104728664 ps
T1125 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.428921210 Aug 18 04:45:11 PM PDT 24 Aug 18 04:45:15 PM PDT 24 126172146 ps
T1126 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.502681323 Aug 18 04:44:48 PM PDT 24 Aug 18 04:44:52 PM PDT 24 204646303 ps
T152 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1333526527 Aug 18 04:45:09 PM PDT 24 Aug 18 04:45:24 PM PDT 24 8926000600 ps
T1127 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.888989450 Aug 18 04:44:56 PM PDT 24 Aug 18 04:44:59 PM PDT 24 91694305 ps
T149 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1559347703 Aug 18 04:44:54 PM PDT 24 Aug 18 04:45:17 PM PDT 24 11374792449 ps
T1128 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1909735817 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:56 PM PDT 24 222026358 ps
T1129 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1800115993 Aug 18 04:45:11 PM PDT 24 Aug 18 04:45:13 PM PDT 24 216079175 ps
T1130 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3229155508 Aug 18 04:45:10 PM PDT 24 Aug 18 04:45:11 PM PDT 24 15375683 ps
T1131 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1902023414 Aug 18 04:45:07 PM PDT 24 Aug 18 04:45:08 PM PDT 24 39848874 ps
T1132 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1663851270 Aug 18 04:44:53 PM PDT 24 Aug 18 04:44:57 PM PDT 24 477467614 ps
T1133 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3622415585 Aug 18 04:44:51 PM PDT 24 Aug 18 04:44:53 PM PDT 24 155826504 ps
T1134 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3635166127 Aug 18 04:45:08 PM PDT 24 Aug 18 04:45:10 PM PDT 24 78781681 ps
T1135 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.285142791 Aug 18 04:44:49 PM PDT 24 Aug 18 04:45:05 PM PDT 24 2948395504 ps
T1136 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.708340815 Aug 18 04:44:51 PM PDT 24 Aug 18 04:45:07 PM PDT 24 2419733112 ps
T1137 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3723297671 Aug 18 04:44:51 PM PDT 24 Aug 18 04:44:52 PM PDT 24 72795182 ps
T1138 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3920673747 Aug 18 04:45:04 PM PDT 24 Aug 18 04:45:05 PM PDT 24 37035736 ps
T1139 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2375614090 Aug 18 04:45:03 PM PDT 24 Aug 18 04:45:05 PM PDT 24 24162077 ps
T1140 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.791837387 Aug 18 04:44:52 PM PDT 24 Aug 18 04:44:53 PM PDT 24 13454010 ps
T1141 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2469056253 Aug 18 04:44:56 PM PDT 24 Aug 18 04:44:58 PM PDT 24 104207315 ps
T1142 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.869714900 Aug 18 04:44:54 PM PDT 24 Aug 18 04:44:56 PM PDT 24 173968760 ps
T1143 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.468118270 Aug 18 04:44:51 PM PDT 24 Aug 18 04:44:52 PM PDT 24 48947386 ps
T1144 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1856975157 Aug 18 04:44:55 PM PDT 24 Aug 18 04:44:59 PM PDT 24 169644143 ps
T155 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2665359067 Aug 18 04:45:12 PM PDT 24 Aug 18 04:45:34 PM PDT 24 2129418226 ps
T156 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.927897882 Aug 18 04:45:01 PM PDT 24 Aug 18 04:45:19 PM PDT 24 1522125519 ps
T1145 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.744395644 Aug 18 04:44:53 PM PDT 24 Aug 18 04:44:55 PM PDT 24 25579542 ps
T1146 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3569347482 Aug 18 04:45:13 PM PDT 24 Aug 18 04:45:14 PM PDT 24 14342933 ps
T1147 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1608123330 Aug 18 04:45:00 PM PDT 24 Aug 18 04:45:24 PM PDT 24 4263519017 ps
T1148 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.46209395 Aug 18 04:44:48 PM PDT 24 Aug 18 04:44:49 PM PDT 24 12780905 ps
T1149 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3891526 Aug 18 04:45:18 PM PDT 24 Aug 18 04:45:19 PM PDT 24 24951679 ps
T1150 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4226857926 Aug 18 04:45:15 PM PDT 24 Aug 18 04:45:17 PM PDT 24 87407895 ps
T1151 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1634601181 Aug 18 04:44:58 PM PDT 24 Aug 18 04:44:59 PM PDT 24 23398536 ps

Test location /workspace/coverage/default/15.spi_device_stress_all.2141593102
Short name T8
Test name
Test status
Simulation time 136779570979 ps
CPU time 370.19 seconds
Started Aug 18 05:49:39 PM PDT 24
Finished Aug 18 05:55:49 PM PDT 24
Peak memory 269060 kb
Host smart-b8db5531-c633-42fb-bcdf-b91f6a2635a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141593102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2141593102
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2749521550
Short name T21
Test name
Test status
Simulation time 137960180490 ps
CPU time 1239.51 seconds
Started Aug 18 05:50:19 PM PDT 24
Finished Aug 18 06:10:58 PM PDT 24
Peak memory 287420 kb
Host smart-4c99dd09-49eb-463a-8374-8af6bc2bbed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749521550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2749521550
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.857072580
Short name T99
Test name
Test status
Simulation time 208622042 ps
CPU time 1.72 seconds
Started Aug 18 04:45:19 PM PDT 24
Finished Aug 18 04:45:21 PM PDT 24
Peak memory 217116 kb
Host smart-134cf76e-4c07-4475-8ffc-89ca7a7be0a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857072580 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.857072580
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3841117498
Short name T11
Test name
Test status
Simulation time 148204378559 ps
CPU time 739.49 seconds
Started Aug 18 05:51:16 PM PDT 24
Finished Aug 18 06:03:36 PM PDT 24
Peak memory 282140 kb
Host smart-e09763b2-38b0-40c8-aca2-49f093aaba4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841117498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3841117498
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2135072887
Short name T55
Test name
Test status
Simulation time 25384589 ps
CPU time 0.71 seconds
Started Aug 18 05:48:55 PM PDT 24
Finished Aug 18 05:48:56 PM PDT 24
Peak memory 216212 kb
Host smart-2dda3185-d485-46a4-86e6-344de085bd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135072887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2135072887
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.341232760
Short name T20
Test name
Test status
Simulation time 33572152531 ps
CPU time 216.85 seconds
Started Aug 18 05:51:17 PM PDT 24
Finished Aug 18 05:54:54 PM PDT 24
Peak memory 272104 kb
Host smart-deb7185a-2f4b-4f35-827e-17b3f2fa935b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341232760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.341232760
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4061245858
Short name T194
Test name
Test status
Simulation time 66080766845 ps
CPU time 772.65 seconds
Started Aug 18 05:49:39 PM PDT 24
Finished Aug 18 06:02:31 PM PDT 24
Peak memory 301296 kb
Host smart-7ecf313d-a693-4c65-ad02-4355672f8a4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061245858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4061245858
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.288980007
Short name T105
Test name
Test status
Simulation time 330843138 ps
CPU time 2.15 seconds
Started Aug 18 04:44:56 PM PDT 24
Finished Aug 18 04:44:59 PM PDT 24
Peak memory 215948 kb
Host smart-7f978a50-df4b-4907-b667-37926532ff4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288980007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.288980007
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1615534733
Short name T27
Test name
Test status
Simulation time 254383024087 ps
CPU time 364.23 seconds
Started Aug 18 05:50:20 PM PDT 24
Finished Aug 18 05:56:24 PM PDT 24
Peak memory 267508 kb
Host smart-75f76842-33a5-46ea-959e-007b1af452de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615534733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1615534733
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3859618048
Short name T144
Test name
Test status
Simulation time 596256295 ps
CPU time 14.2 seconds
Started Aug 18 04:44:56 PM PDT 24
Finished Aug 18 04:45:10 PM PDT 24
Peak memory 215944 kb
Host smart-de28db18-f7b8-4000-8302-5fea18d9a564
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859618048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3859618048
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3651012868
Short name T39
Test name
Test status
Simulation time 3069508726 ps
CPU time 24.65 seconds
Started Aug 18 05:51:07 PM PDT 24
Finished Aug 18 05:51:32 PM PDT 24
Peak memory 234016 kb
Host smart-e946ba8c-7fa3-45d8-8887-3a35c1f31d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651012868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3651012868
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3599133927
Short name T317
Test name
Test status
Simulation time 21299082 ps
CPU time 0.72 seconds
Started Aug 18 05:49:23 PM PDT 24
Finished Aug 18 05:49:24 PM PDT 24
Peak memory 205532 kb
Host smart-b9a6903a-f74a-40ba-8dd1-636b642394d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599133927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3599133927
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1797595530
Short name T79
Test name
Test status
Simulation time 5932894819 ps
CPU time 104.86 seconds
Started Aug 18 05:49:47 PM PDT 24
Finished Aug 18 05:51:32 PM PDT 24
Peak memory 256384 kb
Host smart-99c260b0-2045-47c9-8a5a-12ed14e68ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797595530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1797595530
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.948633904
Short name T93
Test name
Test status
Simulation time 850903343 ps
CPU time 4.79 seconds
Started Aug 18 04:44:57 PM PDT 24
Finished Aug 18 04:45:01 PM PDT 24
Peak memory 216148 kb
Host smart-b7c51a32-b064-4c38-873a-4f62a8ca0986
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948633904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.948633904
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1550118325
Short name T184
Test name
Test status
Simulation time 35831385069 ps
CPU time 236.91 seconds
Started Aug 18 05:49:01 PM PDT 24
Finished Aug 18 05:52:58 PM PDT 24
Peak memory 255412 kb
Host smart-a96b860b-82b3-4388-b5aa-7f5c498eeebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550118325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1550118325
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1391005685
Short name T71
Test name
Test status
Simulation time 67748090009 ps
CPU time 282.55 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:55:50 PM PDT 24
Peak memory 261992 kb
Host smart-31c1408d-6b51-47da-971a-0c83e5548eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391005685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1391005685
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2380704190
Short name T502
Test name
Test status
Simulation time 101871761 ps
CPU time 1 seconds
Started Aug 18 05:48:55 PM PDT 24
Finished Aug 18 05:48:56 PM PDT 24
Peak memory 217872 kb
Host smart-4500b910-14b3-4c73-a989-ce9bee3d38e8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380704190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2380704190
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1066854476
Short name T251
Test name
Test status
Simulation time 313212589911 ps
CPU time 716.5 seconds
Started Aug 18 05:49:02 PM PDT 24
Finished Aug 18 06:00:58 PM PDT 24
Peak memory 272784 kb
Host smart-976aea63-253b-4b99-afcd-f867c73d8755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066854476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1066854476
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3837151748
Short name T58
Test name
Test status
Simulation time 168522852 ps
CPU time 1.17 seconds
Started Aug 18 05:48:53 PM PDT 24
Finished Aug 18 05:48:55 PM PDT 24
Peak memory 236628 kb
Host smart-eb9e021f-0493-4d78-8e11-bd65169a32ff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837151748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3837151748
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2439764591
Short name T22
Test name
Test status
Simulation time 22631915005 ps
CPU time 101.43 seconds
Started Aug 18 05:49:09 PM PDT 24
Finished Aug 18 05:50:50 PM PDT 24
Peak memory 273928 kb
Host smart-00a836c2-011e-4730-ba36-a13ed66fe3ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439764591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2439764591
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.4051560895
Short name T265
Test name
Test status
Simulation time 56837111882 ps
CPU time 253.98 seconds
Started Aug 18 05:49:28 PM PDT 24
Finished Aug 18 05:53:42 PM PDT 24
Peak memory 254756 kb
Host smart-1550d1f0-f816-48e3-b274-813c7a7f26cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051560895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.4051560895
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2212354162
Short name T160
Test name
Test status
Simulation time 85484705253 ps
CPU time 294.75 seconds
Started Aug 18 05:48:59 PM PDT 24
Finished Aug 18 05:53:54 PM PDT 24
Peak memory 255988 kb
Host smart-1fced7e5-46ae-4ce2-9c0c-e27c13d481c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212354162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2212354162
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.238847422
Short name T32
Test name
Test status
Simulation time 89297956149 ps
CPU time 848.56 seconds
Started Aug 18 05:50:53 PM PDT 24
Finished Aug 18 06:05:02 PM PDT 24
Peak memory 289520 kb
Host smart-1c9ca47c-394c-46c1-ab10-86f1e9cedcb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238847422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.238847422
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1166944808
Short name T217
Test name
Test status
Simulation time 104867016101 ps
CPU time 522.64 seconds
Started Aug 18 05:48:54 PM PDT 24
Finished Aug 18 05:57:37 PM PDT 24
Peak memory 264692 kb
Host smart-9202f6ea-da77-48d9-aef7-b6862ff9048c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166944808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1166944808
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.927897882
Short name T156
Test name
Test status
Simulation time 1522125519 ps
CPU time 17.73 seconds
Started Aug 18 04:45:01 PM PDT 24
Finished Aug 18 04:45:19 PM PDT 24
Peak memory 216716 kb
Host smart-500c87e7-f6c8-4005-b3fd-abb6e2357fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927897882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.927897882
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.4193055240
Short name T198
Test name
Test status
Simulation time 8373922924 ps
CPU time 108.64 seconds
Started Aug 18 05:49:22 PM PDT 24
Finished Aug 18 05:51:11 PM PDT 24
Peak memory 254376 kb
Host smart-a0c8b499-08eb-4ab5-9b92-19170d675d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193055240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.4193055240
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3070066539
Short name T98
Test name
Test status
Simulation time 163712281 ps
CPU time 3.88 seconds
Started Aug 18 04:44:54 PM PDT 24
Finished Aug 18 04:45:03 PM PDT 24
Peak memory 215996 kb
Host smart-6e40688b-7b7a-4fae-9f1c-f6f1c2faf432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070066539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
070066539
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.68837113
Short name T273
Test name
Test status
Simulation time 1231914817 ps
CPU time 20.52 seconds
Started Aug 18 05:49:06 PM PDT 24
Finished Aug 18 05:49:27 PM PDT 24
Peak memory 224660 kb
Host smart-96468274-0604-4e98-a534-6868a5bd165e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68837113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.68837113
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.893022818
Short name T178
Test name
Test status
Simulation time 23995657079 ps
CPU time 211.03 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:54:19 PM PDT 24
Peak memory 254936 kb
Host smart-689e8888-c595-4701-9fdf-d124d099c11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893022818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.893022818
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.312417316
Short name T249
Test name
Test status
Simulation time 200072088619 ps
CPU time 166.95 seconds
Started Aug 18 05:48:55 PM PDT 24
Finished Aug 18 05:51:42 PM PDT 24
Peak memory 254840 kb
Host smart-f285e533-df61-4641-a200-650f597a589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312417316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.312417316
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4200240125
Short name T283
Test name
Test status
Simulation time 9450783012 ps
CPU time 19.55 seconds
Started Aug 18 05:48:53 PM PDT 24
Finished Aug 18 05:49:12 PM PDT 24
Peak memory 216512 kb
Host smart-049d3963-18da-4f78-b767-2c5c21d28388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200240125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4200240125
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.596219849
Short name T121
Test name
Test status
Simulation time 37969412531 ps
CPU time 151.43 seconds
Started Aug 18 05:49:27 PM PDT 24
Finished Aug 18 05:51:58 PM PDT 24
Peak memory 265764 kb
Host smart-96f3c086-a4fc-4a9e-8831-0b14265d152b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596219849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.596219849
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.757545792
Short name T35
Test name
Test status
Simulation time 4027245400 ps
CPU time 83.3 seconds
Started Aug 18 05:49:35 PM PDT 24
Finished Aug 18 05:50:58 PM PDT 24
Peak memory 255780 kb
Host smart-3f8d3698-4793-4bb1-8889-bc48c0511a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757545792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.757545792
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3462592232
Short name T264
Test name
Test status
Simulation time 126051096068 ps
CPU time 1110.69 seconds
Started Aug 18 05:50:27 PM PDT 24
Finished Aug 18 06:08:58 PM PDT 24
Peak memory 283896 kb
Host smart-26787cdb-8c70-47ff-a418-b4d778eb215e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462592232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3462592232
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.277417745
Short name T257
Test name
Test status
Simulation time 188632709938 ps
CPU time 312.9 seconds
Started Aug 18 05:50:49 PM PDT 24
Finished Aug 18 05:56:02 PM PDT 24
Peak memory 255888 kb
Host smart-6ec923d2-a7b0-4b46-a0f2-64cae5e23472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277417745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.277417745
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1450934242
Short name T253
Test name
Test status
Simulation time 252176030040 ps
CPU time 660.37 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 06:02:29 PM PDT 24
Peak memory 278988 kb
Host smart-8951d56f-8a57-439d-bc78-f132c5e605a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450934242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1450934242
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.801607822
Short name T86
Test name
Test status
Simulation time 204727576 ps
CPU time 7.42 seconds
Started Aug 18 04:45:03 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 215900 kb
Host smart-c7e9c841-6fc2-4f4f-a8bd-0dbe10d6b09e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801607822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.801607822
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.219972740
Short name T134
Test name
Test status
Simulation time 318983135 ps
CPU time 7.05 seconds
Started Aug 18 04:45:12 PM PDT 24
Finished Aug 18 04:45:19 PM PDT 24
Peak memory 216596 kb
Host smart-871788a1-708f-4f29-8751-b33a63a99bef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219972740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.219972740
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2743483107
Short name T122
Test name
Test status
Simulation time 12960560906 ps
CPU time 99.96 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 260948 kb
Host smart-c5f6fa17-3876-41e9-a2fc-a3cbb59d76ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743483107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2743483107
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1175233924
Short name T301
Test name
Test status
Simulation time 203312436 ps
CPU time 0.72 seconds
Started Aug 18 05:49:28 PM PDT 24
Finished Aug 18 05:49:28 PM PDT 24
Peak memory 206092 kb
Host smart-6ca634ec-cad3-4ed8-b0cf-dfcc19fed0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175233924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1175233924
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.704276243
Short name T917
Test name
Test status
Simulation time 3080312099 ps
CPU time 39.64 seconds
Started Aug 18 05:49:57 PM PDT 24
Finished Aug 18 05:50:37 PM PDT 24
Peak memory 241104 kb
Host smart-e257ef26-a2f1-44b0-b0c3-3b9cce150d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704276243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.704276243
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4238609774
Short name T276
Test name
Test status
Simulation time 735461323 ps
CPU time 7.65 seconds
Started Aug 18 05:51:15 PM PDT 24
Finished Aug 18 05:51:23 PM PDT 24
Peak memory 249224 kb
Host smart-4de2c4cd-d063-476f-a30f-64bbc2532c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238609774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4238609774
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1054679792
Short name T480
Test name
Test status
Simulation time 73594237905 ps
CPU time 106.29 seconds
Started Aug 18 05:49:56 PM PDT 24
Finished Aug 18 05:51:42 PM PDT 24
Peak memory 255104 kb
Host smart-31451142-b7be-4fbb-8d78-80cfc91c5231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054679792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1054679792
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3260498920
Short name T188
Test name
Test status
Simulation time 7430086942 ps
CPU time 10.58 seconds
Started Aug 18 05:49:32 PM PDT 24
Finished Aug 18 05:49:43 PM PDT 24
Peak memory 224640 kb
Host smart-f6192b52-a605-46c9-84c3-f4f7ab538f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260498920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3260498920
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1133990059
Short name T72
Test name
Test status
Simulation time 55518325 ps
CPU time 0.93 seconds
Started Aug 18 04:45:00 PM PDT 24
Finished Aug 18 04:45:01 PM PDT 24
Peak memory 207416 kb
Host smart-159646b3-19f6-49a4-87f5-1db40c41f3f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133990059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1133990059
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3007309764
Short name T1089
Test name
Test status
Simulation time 122630240 ps
CPU time 2.38 seconds
Started Aug 18 04:44:57 PM PDT 24
Finished Aug 18 04:45:00 PM PDT 24
Peak memory 216064 kb
Host smart-8565a1b4-554a-45bb-b8b1-9fa680b9d5a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007309764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3007309764
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.708340815
Short name T1136
Test name
Test status
Simulation time 2419733112 ps
CPU time 15.93 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:45:07 PM PDT 24
Peak memory 216000 kb
Host smart-9328f954-d4db-44d0-8bef-06a793fe989c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708340815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.708340815
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4055294096
Short name T108
Test name
Test status
Simulation time 734815375 ps
CPU time 20.3 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:45:14 PM PDT 24
Peak memory 215888 kb
Host smart-58a3f793-075c-44b2-b0c5-d40839015337
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055294096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.4055294096
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1137967087
Short name T1095
Test name
Test status
Simulation time 200989554 ps
CPU time 1.41 seconds
Started Aug 18 04:44:50 PM PDT 24
Finished Aug 18 04:44:51 PM PDT 24
Peak memory 216908 kb
Host smart-3d22ea33-cd8f-40eb-a7af-d0fe849d7514
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137967087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1137967087
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.388512824
Short name T1045
Test name
Test status
Simulation time 2411058464 ps
CPU time 3.3 seconds
Started Aug 18 04:44:48 PM PDT 24
Finished Aug 18 04:44:52 PM PDT 24
Peak memory 218724 kb
Host smart-77708993-e5a8-40c2-b279-a4c3a6d0a6d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388512824 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.388512824
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4165234629
Short name T1076
Test name
Test status
Simulation time 40740214 ps
CPU time 1.25 seconds
Started Aug 18 04:44:55 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 207800 kb
Host smart-3e5163ae-2aeb-4bc3-af9c-83733f461bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165234629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
165234629
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2689284605
Short name T1055
Test name
Test status
Simulation time 60049775 ps
CPU time 0.72 seconds
Started Aug 18 04:44:49 PM PDT 24
Finished Aug 18 04:44:50 PM PDT 24
Peak memory 204228 kb
Host smart-8f944987-a321-452f-b41f-7314e05a0ce2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689284605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
689284605
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.744395644
Short name T1145
Test name
Test status
Simulation time 25579542 ps
CPU time 1.61 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:55 PM PDT 24
Peak memory 215856 kb
Host smart-0ef8647b-5384-4be2-8e1e-3ffbe844cdcc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744395644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.744395644
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3742193509
Short name T1050
Test name
Test status
Simulation time 19386818 ps
CPU time 0.65 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:52 PM PDT 24
Peak memory 204208 kb
Host smart-8a1872d6-f093-40f3-9bf0-c7276e6ef606
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742193509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3742193509
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.456756432
Short name T133
Test name
Test status
Simulation time 269419073 ps
CPU time 1.76 seconds
Started Aug 18 04:44:48 PM PDT 24
Finished Aug 18 04:44:50 PM PDT 24
Peak memory 216396 kb
Host smart-4132cd11-6769-474d-b02f-18c469a24b19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456756432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.456756432
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.869714900
Short name T1142
Test name
Test status
Simulation time 173968760 ps
CPU time 2.64 seconds
Started Aug 18 04:44:54 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 216032 kb
Host smart-b9729e43-a3c6-46fe-913b-35249900d4c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869714900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.869714900
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3911286097
Short name T1096
Test name
Test status
Simulation time 1284036216 ps
CPU time 8.05 seconds
Started Aug 18 04:44:42 PM PDT 24
Finished Aug 18 04:44:51 PM PDT 24
Peak memory 216432 kb
Host smart-c42ee9f2-2e20-4ff6-89a6-4d53292cf533
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911286097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3911286097
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.285142791
Short name T1135
Test name
Test status
Simulation time 2948395504 ps
CPU time 16.01 seconds
Started Aug 18 04:44:49 PM PDT 24
Finished Aug 18 04:45:05 PM PDT 24
Peak memory 215952 kb
Host smart-56282db0-d3eb-4594-9549-e824f36cc85d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285142791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.285142791
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2780094558
Short name T111
Test name
Test status
Simulation time 365172120 ps
CPU time 11.83 seconds
Started Aug 18 04:44:41 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 207736 kb
Host smart-e943831f-cc3c-46e5-9c36-3854dbe1f018
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780094558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2780094558
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3622415585
Short name T1133
Test name
Test status
Simulation time 155826504 ps
CPU time 2.65 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 217428 kb
Host smart-dc6fa889-3627-45f0-9455-3768d8bfc420
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622415585 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3622415585
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1843408024
Short name T1064
Test name
Test status
Simulation time 61960736 ps
CPU time 2.13 seconds
Started Aug 18 04:44:48 PM PDT 24
Finished Aug 18 04:44:50 PM PDT 24
Peak memory 215900 kb
Host smart-8eaecfb3-9f0e-4e8d-8455-351573babd7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843408024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
843408024
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1822130029
Short name T1083
Test name
Test status
Simulation time 12620889 ps
CPU time 0.7 seconds
Started Aug 18 04:44:56 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 204256 kb
Host smart-a2544b65-42e1-4f91-b39b-d58dc6ae413c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822130029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
822130029
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3234738003
Short name T1123
Test name
Test status
Simulation time 114947025 ps
CPU time 1.38 seconds
Started Aug 18 04:44:45 PM PDT 24
Finished Aug 18 04:44:47 PM PDT 24
Peak memory 215868 kb
Host smart-d5a0e06a-296e-4e6c-9490-329527dddf14
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234738003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3234738003
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.791837387
Short name T1140
Test name
Test status
Simulation time 13454010 ps
CPU time 0.66 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 204340 kb
Host smart-25396e8e-1506-4cd8-8d22-26e640368933
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791837387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.791837387
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3345686572
Short name T1074
Test name
Test status
Simulation time 115441712 ps
CPU time 3.99 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:58 PM PDT 24
Peak memory 215924 kb
Host smart-95f132d8-346a-495f-8586-a15eff182330
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345686572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3345686572
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3661487755
Short name T94
Test name
Test status
Simulation time 86647680 ps
CPU time 2.44 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:55 PM PDT 24
Peak memory 216024 kb
Host smart-f0b55ffd-e772-43e2-94c9-16fe3cd807a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661487755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
661487755
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2503447990
Short name T85
Test name
Test status
Simulation time 3219855032 ps
CPU time 11.46 seconds
Started Aug 18 04:44:59 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 215976 kb
Host smart-25392067-a3c9-44cf-a1c8-676f650487b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503447990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2503447990
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1909735817
Short name T1128
Test name
Test status
Simulation time 222026358 ps
CPU time 3.99 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 218364 kb
Host smart-f8e82577-b10c-4089-8810-0494f9095cb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909735817 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1909735817
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3148660719
Short name T112
Test name
Test status
Simulation time 27999444 ps
CPU time 1.76 seconds
Started Aug 18 04:45:13 PM PDT 24
Finished Aug 18 04:45:15 PM PDT 24
Peak memory 216032 kb
Host smart-172f6b85-3334-4e54-99f3-971aeca89168
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148660719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3148660719
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.310995584
Short name T1060
Test name
Test status
Simulation time 32927839 ps
CPU time 0.77 seconds
Started Aug 18 04:45:03 PM PDT 24
Finished Aug 18 04:45:04 PM PDT 24
Peak memory 204632 kb
Host smart-b50413a9-8883-4947-bc36-f76f2428a8b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310995584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.310995584
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3217603266
Short name T1047
Test name
Test status
Simulation time 162393297 ps
CPU time 4.2 seconds
Started Aug 18 04:45:04 PM PDT 24
Finished Aug 18 04:45:08 PM PDT 24
Peak memory 215988 kb
Host smart-c3d80806-7deb-4861-b25d-15b10aefef9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217603266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3217603266
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1771863327
Short name T1071
Test name
Test status
Simulation time 207116030 ps
CPU time 3.68 seconds
Started Aug 18 04:45:04 PM PDT 24
Finished Aug 18 04:45:08 PM PDT 24
Peak memory 216112 kb
Host smart-ef926569-32c2-4b76-b4b5-499da0d1ff5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771863327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1771863327
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4164072715
Short name T1063
Test name
Test status
Simulation time 81229901 ps
CPU time 2.73 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:55 PM PDT 24
Peak memory 217208 kb
Host smart-e8908afa-b064-42b3-9310-e63b538b6a54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164072715 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4164072715
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.108327243
Short name T1107
Test name
Test status
Simulation time 643020162 ps
CPU time 2.54 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:54 PM PDT 24
Peak memory 215900 kb
Host smart-73e73e13-64d3-4fe5-b444-fba515b89cc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108327243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.108327243
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3575317980
Short name T1106
Test name
Test status
Simulation time 42799964 ps
CPU time 0.74 seconds
Started Aug 18 04:44:59 PM PDT 24
Finished Aug 18 04:45:00 PM PDT 24
Peak memory 204372 kb
Host smart-21b3e961-9a79-4c84-a3b7-cb73f0fe4e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575317980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3575317980
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2793768802
Short name T1080
Test name
Test status
Simulation time 191447492 ps
CPU time 4.11 seconds
Started Aug 18 04:44:55 PM PDT 24
Finished Aug 18 04:44:59 PM PDT 24
Peak memory 215848 kb
Host smart-cf17e316-8362-4081-93c8-700e40da61f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793768802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2793768802
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3962369730
Short name T1086
Test name
Test status
Simulation time 156272751 ps
CPU time 3.52 seconds
Started Aug 18 04:44:55 PM PDT 24
Finished Aug 18 04:44:59 PM PDT 24
Peak memory 217972 kb
Host smart-344ef667-9314-40c0-9e24-a0da84c84ace
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962369730 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3962369730
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.654629675
Short name T1103
Test name
Test status
Simulation time 458819687 ps
CPU time 2.11 seconds
Started Aug 18 04:44:55 PM PDT 24
Finished Aug 18 04:44:58 PM PDT 24
Peak memory 207796 kb
Host smart-7274984a-aca2-4178-a728-79ed0701bad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654629675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.654629675
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.330282360
Short name T1120
Test name
Test status
Simulation time 48189147 ps
CPU time 0.77 seconds
Started Aug 18 04:44:55 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 204360 kb
Host smart-267a2e11-d107-4fde-86ce-d7bd5dcb7b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330282360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.330282360
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.292157291
Short name T1121
Test name
Test status
Simulation time 445325123 ps
CPU time 3.07 seconds
Started Aug 18 04:45:00 PM PDT 24
Finished Aug 18 04:45:03 PM PDT 24
Peak memory 215820 kb
Host smart-c9b05cc9-138b-4e05-adaf-d9aaf37d86cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292157291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.292157291
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2907568875
Short name T1088
Test name
Test status
Simulation time 327353779 ps
CPU time 4.11 seconds
Started Aug 18 04:44:55 PM PDT 24
Finished Aug 18 04:44:59 PM PDT 24
Peak memory 216148 kb
Host smart-4450a194-9cbb-41a4-a756-8d99b9cedc6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907568875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2907568875
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.634608098
Short name T1075
Test name
Test status
Simulation time 919705313 ps
CPU time 3.84 seconds
Started Aug 18 04:44:59 PM PDT 24
Finished Aug 18 04:45:03 PM PDT 24
Peak memory 217808 kb
Host smart-c1b9f0f0-877d-4936-9634-9c3dc94f6e70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634608098 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.634608098
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3410947418
Short name T101
Test name
Test status
Simulation time 95021716 ps
CPU time 1.71 seconds
Started Aug 18 04:45:19 PM PDT 24
Finished Aug 18 04:45:21 PM PDT 24
Peak memory 220468 kb
Host smart-bff878f6-18be-4526-9340-e09192b7b34d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410947418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3410947418
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3920673747
Short name T1138
Test name
Test status
Simulation time 37035736 ps
CPU time 0.76 seconds
Started Aug 18 04:45:04 PM PDT 24
Finished Aug 18 04:45:05 PM PDT 24
Peak memory 204320 kb
Host smart-bde9e34c-2605-4f12-b337-2d91a2fc2498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920673747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3920673747
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2099505414
Short name T1065
Test name
Test status
Simulation time 88715405 ps
CPU time 2.83 seconds
Started Aug 18 04:44:59 PM PDT 24
Finished Aug 18 04:45:02 PM PDT 24
Peak memory 215760 kb
Host smart-477f5731-dcbe-48d1-8368-1565b3dbb2b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099505414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2099505414
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4226857926
Short name T1150
Test name
Test status
Simulation time 87407895 ps
CPU time 1.78 seconds
Started Aug 18 04:45:15 PM PDT 24
Finished Aug 18 04:45:17 PM PDT 24
Peak memory 216272 kb
Host smart-46151d16-cb6d-447a-a1dc-9eafc5055a84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226857926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4226857926
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1816645687
Short name T87
Test name
Test status
Simulation time 284283883 ps
CPU time 7.83 seconds
Started Aug 18 04:45:05 PM PDT 24
Finished Aug 18 04:45:13 PM PDT 24
Peak memory 216016 kb
Host smart-8e7e2438-0a03-40d8-b266-ac050349c52d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816645687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1816645687
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3244479961
Short name T135
Test name
Test status
Simulation time 390832215 ps
CPU time 1.96 seconds
Started Aug 18 04:45:14 PM PDT 24
Finished Aug 18 04:45:16 PM PDT 24
Peak memory 215996 kb
Host smart-8aafee8b-70b4-4eeb-aaf7-ceccca372c1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244479961 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3244479961
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1307240965
Short name T1068
Test name
Test status
Simulation time 239209318 ps
CPU time 2.76 seconds
Started Aug 18 04:45:03 PM PDT 24
Finished Aug 18 04:45:06 PM PDT 24
Peak memory 215916 kb
Host smart-eda15263-ef83-4507-8b43-a1f1fdb3b640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307240965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1307240965
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3972739490
Short name T1084
Test name
Test status
Simulation time 41699411 ps
CPU time 0.71 seconds
Started Aug 18 04:45:21 PM PDT 24
Finished Aug 18 04:45:22 PM PDT 24
Peak memory 204232 kb
Host smart-5fd1df5b-ccac-41b4-a6a8-f5e62558cd06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972739490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3972739490
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3768860367
Short name T1082
Test name
Test status
Simulation time 209837237 ps
CPU time 2.93 seconds
Started Aug 18 04:45:18 PM PDT 24
Finished Aug 18 04:45:21 PM PDT 24
Peak memory 215860 kb
Host smart-b342a951-fd2d-4586-a0e1-f207818a52bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768860367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3768860367
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2517938775
Short name T1124
Test name
Test status
Simulation time 104728664 ps
CPU time 2.98 seconds
Started Aug 18 04:45:08 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 216052 kb
Host smart-628615cb-1c06-4120-8606-026069bf67a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517938775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2517938775
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1130229315
Short name T145
Test name
Test status
Simulation time 454001998 ps
CPU time 18.44 seconds
Started Aug 18 04:45:07 PM PDT 24
Finished Aug 18 04:45:26 PM PDT 24
Peak memory 216308 kb
Host smart-c9714acb-e9c0-4570-8591-eaded848a31c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130229315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1130229315
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2050453681
Short name T1100
Test name
Test status
Simulation time 643592970 ps
CPU time 3.82 seconds
Started Aug 18 04:45:10 PM PDT 24
Finished Aug 18 04:45:14 PM PDT 24
Peak memory 217864 kb
Host smart-ff5cddb5-a9b8-48c5-abb4-ebaa7c20e86f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050453681 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2050453681
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1537149805
Short name T1118
Test name
Test status
Simulation time 14548774 ps
CPU time 0.72 seconds
Started Aug 18 04:45:21 PM PDT 24
Finished Aug 18 04:45:22 PM PDT 24
Peak memory 204236 kb
Host smart-f79fa7b8-3631-4a22-99b8-4df525456e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537149805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1537149805
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3864084271
Short name T129
Test name
Test status
Simulation time 665309255 ps
CPU time 3.81 seconds
Started Aug 18 04:45:09 PM PDT 24
Finished Aug 18 04:45:13 PM PDT 24
Peak memory 215824 kb
Host smart-83bc29d8-00fd-4c67-858a-da3a78034707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864084271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3864084271
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2697904842
Short name T84
Test name
Test status
Simulation time 709564131 ps
CPU time 3.92 seconds
Started Aug 18 04:45:07 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 216164 kb
Host smart-a35eeec0-bc63-4cf4-a3e7-dde3328a48f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697904842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2697904842
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1608123330
Short name T1147
Test name
Test status
Simulation time 4263519017 ps
CPU time 23.23 seconds
Started Aug 18 04:45:00 PM PDT 24
Finished Aug 18 04:45:24 PM PDT 24
Peak memory 217684 kb
Host smart-b6077a49-4738-47f0-b2f1-e742791a88a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608123330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1608123330
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1445646039
Short name T97
Test name
Test status
Simulation time 501308545 ps
CPU time 3.93 seconds
Started Aug 18 04:45:16 PM PDT 24
Finished Aug 18 04:45:20 PM PDT 24
Peak memory 218248 kb
Host smart-9da54872-da02-4994-8ca1-215ca942a74b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445646039 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1445646039
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3603533108
Short name T1033
Test name
Test status
Simulation time 23889366 ps
CPU time 1.38 seconds
Started Aug 18 04:45:23 PM PDT 24
Finished Aug 18 04:45:24 PM PDT 24
Peak memory 207700 kb
Host smart-3c625cad-21c6-41d9-8c33-71b438cf8c78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603533108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3603533108
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3528519497
Short name T1061
Test name
Test status
Simulation time 15411674 ps
CPU time 0.69 seconds
Started Aug 18 04:45:14 PM PDT 24
Finished Aug 18 04:45:15 PM PDT 24
Peak memory 204344 kb
Host smart-9bafeb7a-5954-4f25-89d1-3c4a1ac96e01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528519497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3528519497
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.694050682
Short name T130
Test name
Test status
Simulation time 1937210060 ps
CPU time 3.16 seconds
Started Aug 18 04:45:15 PM PDT 24
Finished Aug 18 04:45:18 PM PDT 24
Peak memory 215820 kb
Host smart-ede1b09b-aebc-488f-9edd-0f667cfe0c43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694050682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.694050682
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.530241388
Short name T1094
Test name
Test status
Simulation time 1010649894 ps
CPU time 2.82 seconds
Started Aug 18 04:45:01 PM PDT 24
Finished Aug 18 04:45:04 PM PDT 24
Peak memory 216148 kb
Host smart-acde43ca-fcf6-4d4c-b028-43ed5fa6a7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530241388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.530241388
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3541377075
Short name T1098
Test name
Test status
Simulation time 34407743 ps
CPU time 2.39 seconds
Started Aug 18 04:45:07 PM PDT 24
Finished Aug 18 04:45:10 PM PDT 24
Peak memory 217384 kb
Host smart-10607b6a-a0f5-43cb-b693-24e735a6169d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541377075 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3541377075
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.247657062
Short name T103
Test name
Test status
Simulation time 37341313 ps
CPU time 2.55 seconds
Started Aug 18 04:45:16 PM PDT 24
Finished Aug 18 04:45:19 PM PDT 24
Peak memory 215808 kb
Host smart-bf533d88-1095-45ab-8e9d-7aabb7aa989e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247657062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.247657062
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2772882918
Short name T1031
Test name
Test status
Simulation time 27026385 ps
CPU time 0.72 seconds
Started Aug 18 04:45:00 PM PDT 24
Finished Aug 18 04:45:00 PM PDT 24
Peak memory 204264 kb
Host smart-45defbca-1024-42cb-b6a6-09061674e9a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772882918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2772882918
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1810381045
Short name T1085
Test name
Test status
Simulation time 513747855 ps
CPU time 2.91 seconds
Started Aug 18 04:45:11 PM PDT 24
Finished Aug 18 04:45:14 PM PDT 24
Peak memory 215848 kb
Host smart-e3c69488-2700-4d30-905e-18a4c1200f4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810381045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1810381045
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3683627101
Short name T1104
Test name
Test status
Simulation time 433171213 ps
CPU time 6.54 seconds
Started Aug 18 04:45:05 PM PDT 24
Finished Aug 18 04:45:12 PM PDT 24
Peak memory 215908 kb
Host smart-3d2a34fb-df63-489b-9689-e1df5bdcef70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683627101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3683627101
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3188526265
Short name T96
Test name
Test status
Simulation time 50151080 ps
CPU time 1.67 seconds
Started Aug 18 04:45:05 PM PDT 24
Finished Aug 18 04:45:07 PM PDT 24
Peak memory 216068 kb
Host smart-0f53f222-ee9c-455c-b6e7-e34fd0d50349
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188526265 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3188526265
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3381632687
Short name T1038
Test name
Test status
Simulation time 68204888 ps
CPU time 1.13 seconds
Started Aug 18 04:45:09 PM PDT 24
Finished Aug 18 04:45:10 PM PDT 24
Peak memory 215904 kb
Host smart-c9e2bad9-a463-4564-9d9e-be8c344194af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381632687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3381632687
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1537451985
Short name T1053
Test name
Test status
Simulation time 14599184 ps
CPU time 0.74 seconds
Started Aug 18 04:45:14 PM PDT 24
Finished Aug 18 04:45:15 PM PDT 24
Peak memory 204244 kb
Host smart-aa04bfa5-f8da-410d-a84c-57c8078c673a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537451985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1537451985
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4213411786
Short name T1112
Test name
Test status
Simulation time 325829978 ps
CPU time 3.13 seconds
Started Aug 18 04:45:12 PM PDT 24
Finished Aug 18 04:45:15 PM PDT 24
Peak memory 215804 kb
Host smart-23327a1d-5bdd-48bd-a139-e32ed0747e3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213411786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4213411786
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.274865700
Short name T82
Test name
Test status
Simulation time 158130490 ps
CPU time 4.24 seconds
Started Aug 18 04:45:04 PM PDT 24
Finished Aug 18 04:45:09 PM PDT 24
Peak memory 216008 kb
Host smart-b6efc7e9-83e4-423b-858e-fa8d69496f92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274865700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.274865700
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2288800906
Short name T147
Test name
Test status
Simulation time 1135313988 ps
CPU time 8 seconds
Started Aug 18 04:45:18 PM PDT 24
Finished Aug 18 04:45:26 PM PDT 24
Peak memory 215956 kb
Host smart-830991ae-4258-41a1-b87a-e59751ae66de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288800906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2288800906
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2736089633
Short name T1067
Test name
Test status
Simulation time 151107175 ps
CPU time 2.14 seconds
Started Aug 18 04:45:14 PM PDT 24
Finished Aug 18 04:45:17 PM PDT 24
Peak memory 215988 kb
Host smart-1b64eeac-10a1-4e9e-a8a3-ab19aba9ab1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736089633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2736089633
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.722365469
Short name T1059
Test name
Test status
Simulation time 14571568 ps
CPU time 0.72 seconds
Started Aug 18 04:45:17 PM PDT 24
Finished Aug 18 04:45:17 PM PDT 24
Peak memory 204652 kb
Host smart-a5e53edf-8882-47f6-94bf-18182f8dfea0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722365469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.722365469
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3086700829
Short name T1030
Test name
Test status
Simulation time 103035289 ps
CPU time 2.79 seconds
Started Aug 18 04:45:11 PM PDT 24
Finished Aug 18 04:45:14 PM PDT 24
Peak memory 215860 kb
Host smart-f05b8e80-8a40-4f5b-af60-2297e17e3d74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086700829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3086700829
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2776814659
Short name T95
Test name
Test status
Simulation time 255640170 ps
CPU time 5.26 seconds
Started Aug 18 04:44:59 PM PDT 24
Finished Aug 18 04:45:04 PM PDT 24
Peak memory 217792 kb
Host smart-1c8ba6c0-e610-4020-aa37-ec8a143af7ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776814659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2776814659
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.797353017
Short name T151
Test name
Test status
Simulation time 768865643 ps
CPU time 11.51 seconds
Started Aug 18 04:45:11 PM PDT 24
Finished Aug 18 04:45:23 PM PDT 24
Peak memory 215928 kb
Host smart-872e2805-5f9d-4549-8235-03299850eca5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797353017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.797353017
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2122384402
Short name T104
Test name
Test status
Simulation time 356617863 ps
CPU time 7.66 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:59 PM PDT 24
Peak memory 207788 kb
Host smart-b371e11b-dde3-4f0c-9b69-66e325496a65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122384402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2122384402
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1423863749
Short name T1117
Test name
Test status
Simulation time 1805907268 ps
CPU time 28.39 seconds
Started Aug 18 04:44:56 PM PDT 24
Finished Aug 18 04:45:24 PM PDT 24
Peak memory 207720 kb
Host smart-75435d8c-e0c2-4045-b8ad-beed423f1ef7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423863749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1423863749
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3007187201
Short name T74
Test name
Test status
Simulation time 25649210 ps
CPU time 1.01 seconds
Started Aug 18 04:45:01 PM PDT 24
Finished Aug 18 04:45:02 PM PDT 24
Peak memory 207388 kb
Host smart-3acb3cea-2ced-4431-a840-1fb11f08a515
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007187201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3007187201
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.66166455
Short name T1087
Test name
Test status
Simulation time 95078693 ps
CPU time 2.92 seconds
Started Aug 18 04:44:59 PM PDT 24
Finished Aug 18 04:45:02 PM PDT 24
Peak memory 218464 kb
Host smart-52e15cc4-dc8e-4097-9ce9-bceb4e5feba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66166455 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.66166455
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1523020731
Short name T1111
Test name
Test status
Simulation time 29998567 ps
CPU time 1.83 seconds
Started Aug 18 04:45:01 PM PDT 24
Finished Aug 18 04:45:03 PM PDT 24
Peak memory 215812 kb
Host smart-f6a7bf45-55a7-421a-8634-80478573e5b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523020731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
523020731
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3723297671
Short name T1137
Test name
Test status
Simulation time 72795182 ps
CPU time 0.66 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:52 PM PDT 24
Peak memory 204356 kb
Host smart-59c98c23-fa98-4368-99b6-d7804f0f3162
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723297671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
723297671
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2488679420
Short name T109
Test name
Test status
Simulation time 31078312 ps
CPU time 1.25 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:54 PM PDT 24
Peak memory 215916 kb
Host smart-cc227301-c113-4c4e-afca-596cc7debed4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488679420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2488679420
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2056534769
Short name T1066
Test name
Test status
Simulation time 12119163 ps
CPU time 0.65 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 204528 kb
Host smart-871ac079-f59d-4d32-b043-4e13be6bbc23
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056534769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2056534769
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2753935650
Short name T1077
Test name
Test status
Simulation time 186552912 ps
CPU time 1.81 seconds
Started Aug 18 04:44:59 PM PDT 24
Finished Aug 18 04:45:01 PM PDT 24
Peak memory 215840 kb
Host smart-0e124df8-c5f6-41e9-9cf6-cd977a9c3dd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753935650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2753935650
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.502681323
Short name T1126
Test name
Test status
Simulation time 204646303 ps
CPU time 3.44 seconds
Started Aug 18 04:44:48 PM PDT 24
Finished Aug 18 04:44:52 PM PDT 24
Peak memory 216140 kb
Host smart-ce135baa-d612-4129-8145-ac69c898d395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502681323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.502681323
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2934288325
Short name T153
Test name
Test status
Simulation time 223544283 ps
CPU time 14.63 seconds
Started Aug 18 04:44:55 PM PDT 24
Finished Aug 18 04:45:10 PM PDT 24
Peak memory 215928 kb
Host smart-1d5e06f6-b5b8-484e-b81c-b8d464713060
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934288325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2934288325
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1754724560
Short name T1042
Test name
Test status
Simulation time 27693452 ps
CPU time 0.78 seconds
Started Aug 18 04:45:10 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 204660 kb
Host smart-f68f7766-c256-417b-a85c-b29cd44f881e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754724560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1754724560
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3558864048
Short name T1105
Test name
Test status
Simulation time 15662573 ps
CPU time 0.68 seconds
Started Aug 18 04:44:58 PM PDT 24
Finished Aug 18 04:44:58 PM PDT 24
Peak memory 204264 kb
Host smart-b6364195-73f1-46ae-9463-16ef1c5bbc61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558864048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3558864048
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3258490566
Short name T1048
Test name
Test status
Simulation time 22303840 ps
CPU time 0.72 seconds
Started Aug 18 04:45:01 PM PDT 24
Finished Aug 18 04:45:02 PM PDT 24
Peak memory 204352 kb
Host smart-30a92b56-33e5-4a8d-9b5f-fdcfbf19ee62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258490566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3258490566
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.174744172
Short name T1081
Test name
Test status
Simulation time 11233028 ps
CPU time 0.69 seconds
Started Aug 18 04:44:56 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 204356 kb
Host smart-3dff534a-a6af-4454-b3c2-030a8f484974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174744172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.174744172
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3411927712
Short name T1034
Test name
Test status
Simulation time 51891336 ps
CPU time 0.83 seconds
Started Aug 18 04:44:59 PM PDT 24
Finished Aug 18 04:45:00 PM PDT 24
Peak memory 204264 kb
Host smart-617f0c3f-38b5-42db-903e-efd50f330ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411927712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3411927712
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3514594
Short name T1070
Test name
Test status
Simulation time 27732997 ps
CPU time 0.83 seconds
Started Aug 18 04:45:07 PM PDT 24
Finished Aug 18 04:45:08 PM PDT 24
Peak memory 204320 kb
Host smart-9e48d94a-c174-4be6-ab60-3b4ce2ad2bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.3514594
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1580542055
Short name T1090
Test name
Test status
Simulation time 104242965 ps
CPU time 0.72 seconds
Started Aug 18 04:45:13 PM PDT 24
Finished Aug 18 04:45:14 PM PDT 24
Peak memory 204684 kb
Host smart-bae01a98-8f81-4805-bd71-b16d8541943a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580542055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1580542055
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2275077467
Short name T1109
Test name
Test status
Simulation time 38467894 ps
CPU time 0.74 seconds
Started Aug 18 04:45:10 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 204288 kb
Host smart-b47aca03-3215-47bb-84b3-56691e3e8204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275077467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2275077467
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3891526
Short name T1149
Test name
Test status
Simulation time 24951679 ps
CPU time 0.7 seconds
Started Aug 18 04:45:18 PM PDT 24
Finished Aug 18 04:45:19 PM PDT 24
Peak memory 204236 kb
Host smart-a466665a-947e-4b24-9a93-cce71d65c550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.3891526
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2996344753
Short name T1058
Test name
Test status
Simulation time 82285400 ps
CPU time 0.77 seconds
Started Aug 18 04:45:21 PM PDT 24
Finished Aug 18 04:45:22 PM PDT 24
Peak memory 204244 kb
Host smart-af02fe5d-7514-4ed7-8815-f8a3162886d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996344753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2996344753
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.844568206
Short name T102
Test name
Test status
Simulation time 617643782 ps
CPU time 7.73 seconds
Started Aug 18 04:45:00 PM PDT 24
Finished Aug 18 04:45:08 PM PDT 24
Peak memory 215888 kb
Host smart-5a6ccd59-f253-4033-8ce5-c38f06a5a5d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844568206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.844568206
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3769219027
Short name T1108
Test name
Test status
Simulation time 1883869349 ps
CPU time 25.91 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:45:17 PM PDT 24
Peak memory 207656 kb
Host smart-8a241fd1-dba7-45a6-879c-37fcdb00f46f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769219027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3769219027
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2966456167
Short name T73
Test name
Test status
Simulation time 27045535 ps
CPU time 0.96 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 207412 kb
Host smart-5af30fde-dd7d-4d64-b3e0-d439e4ebdb57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966456167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2966456167
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3774325480
Short name T1099
Test name
Test status
Simulation time 168933793 ps
CPU time 1.69 seconds
Started Aug 18 04:45:09 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 215984 kb
Host smart-45dc3226-71c9-4020-b9c7-2f38790511cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774325480 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3774325480
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.681154444
Short name T1043
Test name
Test status
Simulation time 56908293 ps
CPU time 1.9 seconds
Started Aug 18 04:44:56 PM PDT 24
Finished Aug 18 04:44:58 PM PDT 24
Peak memory 215904 kb
Host smart-2b2956b5-c749-4e15-bf34-e49c654c0d05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681154444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.681154444
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.46209395
Short name T1148
Test name
Test status
Simulation time 12780905 ps
CPU time 0.72 seconds
Started Aug 18 04:44:48 PM PDT 24
Finished Aug 18 04:44:49 PM PDT 24
Peak memory 204216 kb
Host smart-950eabc7-c473-43e3-9a98-5aa181f441c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46209395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.46209395
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.757232447
Short name T1113
Test name
Test status
Simulation time 46686261 ps
CPU time 1.84 seconds
Started Aug 18 04:45:00 PM PDT 24
Finished Aug 18 04:45:02 PM PDT 24
Peak memory 215868 kb
Host smart-0e713947-c98d-402a-b38b-4a38f98db245
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757232447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.757232447
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.541401031
Short name T1057
Test name
Test status
Simulation time 17504200 ps
CPU time 0.65 seconds
Started Aug 18 04:44:59 PM PDT 24
Finished Aug 18 04:45:00 PM PDT 24
Peak memory 204204 kb
Host smart-e88b1363-3feb-4c86-8cb4-4380a6ba21bc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541401031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.541401031
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1856975157
Short name T1144
Test name
Test status
Simulation time 169644143 ps
CPU time 4 seconds
Started Aug 18 04:44:55 PM PDT 24
Finished Aug 18 04:44:59 PM PDT 24
Peak memory 215796 kb
Host smart-d5fd77db-a9a7-4086-81b0-586681044b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856975157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1856975157
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.233157269
Short name T91
Test name
Test status
Simulation time 49871646 ps
CPU time 3.05 seconds
Started Aug 18 04:45:05 PM PDT 24
Finished Aug 18 04:45:08 PM PDT 24
Peak memory 216052 kb
Host smart-0829fb64-0f77-47d1-927a-71ed3e53713b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233157269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.233157269
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1559347703
Short name T149
Test name
Test status
Simulation time 11374792449 ps
CPU time 23.28 seconds
Started Aug 18 04:44:54 PM PDT 24
Finished Aug 18 04:45:17 PM PDT 24
Peak memory 216492 kb
Host smart-83a0a5e1-2cef-4483-bd4f-0b780befa4af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559347703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1559347703
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4145337838
Short name T1069
Test name
Test status
Simulation time 11658694 ps
CPU time 0.77 seconds
Started Aug 18 04:45:10 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 204304 kb
Host smart-cf28e1a2-645d-4713-b5b7-c6c36fa5afdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145337838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4145337838
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3229155508
Short name T1130
Test name
Test status
Simulation time 15375683 ps
CPU time 0.78 seconds
Started Aug 18 04:45:10 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 204284 kb
Host smart-6f7cdb13-81d2-4f54-804b-f3338ce69855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229155508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3229155508
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1137858235
Short name T1039
Test name
Test status
Simulation time 159936908 ps
CPU time 0.73 seconds
Started Aug 18 04:45:12 PM PDT 24
Finished Aug 18 04:45:13 PM PDT 24
Peak memory 204252 kb
Host smart-39f57e14-a05c-4a05-a175-4c402bc49854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137858235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1137858235
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4175235401
Short name T1119
Test name
Test status
Simulation time 13947272 ps
CPU time 0.68 seconds
Started Aug 18 04:44:58 PM PDT 24
Finished Aug 18 04:44:58 PM PDT 24
Peak memory 204264 kb
Host smart-980306cc-ce82-493d-8ef4-fcaab2583d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175235401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4175235401
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3569347482
Short name T1146
Test name
Test status
Simulation time 14342933 ps
CPU time 0.76 seconds
Started Aug 18 04:45:13 PM PDT 24
Finished Aug 18 04:45:14 PM PDT 24
Peak memory 204240 kb
Host smart-80557b88-0225-41db-96b1-07aa1c33b399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569347482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3569347482
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2632474532
Short name T1052
Test name
Test status
Simulation time 14893285 ps
CPU time 0.73 seconds
Started Aug 18 04:45:09 PM PDT 24
Finished Aug 18 04:45:10 PM PDT 24
Peak memory 204200 kb
Host smart-7383d192-d204-4250-b10e-8aa91b1287f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632474532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2632474532
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2670686769
Short name T1102
Test name
Test status
Simulation time 17846345 ps
CPU time 0.7 seconds
Started Aug 18 04:45:09 PM PDT 24
Finished Aug 18 04:45:14 PM PDT 24
Peak memory 204572 kb
Host smart-a602eccc-2815-4591-bc25-40cd313ac1da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670686769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2670686769
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1914051819
Short name T1046
Test name
Test status
Simulation time 48978964 ps
CPU time 0.77 seconds
Started Aug 18 04:45:04 PM PDT 24
Finished Aug 18 04:45:05 PM PDT 24
Peak memory 204268 kb
Host smart-409749c2-7bac-45bf-9783-3eb6c1ecab09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914051819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1914051819
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1577841265
Short name T1044
Test name
Test status
Simulation time 16273156 ps
CPU time 0.74 seconds
Started Aug 18 04:45:09 PM PDT 24
Finished Aug 18 04:45:10 PM PDT 24
Peak memory 204248 kb
Host smart-5842cb4c-e6f1-40b3-8461-9fbf0da2a75d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577841265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1577841265
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2863584772
Short name T1114
Test name
Test status
Simulation time 38488518 ps
CPU time 0.7 seconds
Started Aug 18 04:45:08 PM PDT 24
Finished Aug 18 04:45:09 PM PDT 24
Peak memory 204580 kb
Host smart-afb37404-6fe6-47f0-ae85-a66621970a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863584772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2863584772
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1348148019
Short name T106
Test name
Test status
Simulation time 640144843 ps
CPU time 16.16 seconds
Started Aug 18 04:45:01 PM PDT 24
Finished Aug 18 04:45:18 PM PDT 24
Peak memory 215772 kb
Host smart-d8c2c72a-b89b-434b-b6df-a2ed551e271f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348148019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1348148019
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3719518690
Short name T1079
Test name
Test status
Simulation time 1806082851 ps
CPU time 25.46 seconds
Started Aug 18 04:45:11 PM PDT 24
Finished Aug 18 04:45:36 PM PDT 24
Peak memory 207768 kb
Host smart-4300e014-189c-44b9-8e24-ced099062ba2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719518690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3719518690
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2375614090
Short name T1139
Test name
Test status
Simulation time 24162077 ps
CPU time 1.33 seconds
Started Aug 18 04:45:03 PM PDT 24
Finished Aug 18 04:45:05 PM PDT 24
Peak memory 207764 kb
Host smart-d1a6f22f-491d-421d-b659-e5cf7771e51b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375614090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2375614090
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1663851270
Short name T1132
Test name
Test status
Simulation time 477467614 ps
CPU time 3.53 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:57 PM PDT 24
Peak memory 218620 kb
Host smart-5492866d-9678-4469-bd57-4aff0c5d0ec5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663851270 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1663851270
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4278871475
Short name T1049
Test name
Test status
Simulation time 60744407 ps
CPU time 1.25 seconds
Started Aug 18 04:44:58 PM PDT 24
Finished Aug 18 04:44:59 PM PDT 24
Peak memory 207664 kb
Host smart-49618469-6750-4833-b3cf-97a6c58745bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278871475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
278871475
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.468118270
Short name T1143
Test name
Test status
Simulation time 48947386 ps
CPU time 0.76 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:52 PM PDT 24
Peak memory 204272 kb
Host smart-3c89fe8b-81b8-4595-ac0f-c7a2028dd81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468118270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.468118270
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1800115993
Short name T1129
Test name
Test status
Simulation time 216079175 ps
CPU time 2.07 seconds
Started Aug 18 04:45:11 PM PDT 24
Finished Aug 18 04:45:13 PM PDT 24
Peak memory 215916 kb
Host smart-4f959e06-ea93-47fc-8a21-f0894c238504
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800115993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1800115993
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2794164278
Short name T1122
Test name
Test status
Simulation time 13318819 ps
CPU time 0.7 seconds
Started Aug 18 04:44:51 PM PDT 24
Finished Aug 18 04:44:52 PM PDT 24
Peak memory 204296 kb
Host smart-040add48-c42b-4df2-b298-bab11031f0c4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794164278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2794164278
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2469056253
Short name T1141
Test name
Test status
Simulation time 104207315 ps
CPU time 2.24 seconds
Started Aug 18 04:44:56 PM PDT 24
Finished Aug 18 04:44:58 PM PDT 24
Peak memory 215876 kb
Host smart-855a60b4-0840-417a-b577-0f7511d6a7ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469056253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2469056253
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3755800061
Short name T88
Test name
Test status
Simulation time 178362977 ps
CPU time 3.6 seconds
Started Aug 18 04:45:16 PM PDT 24
Finished Aug 18 04:45:25 PM PDT 24
Peak memory 216204 kb
Host smart-5cdbeb33-9e55-4604-9068-cb19d99c09e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755800061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
755800061
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2396784951
Short name T154
Test name
Test status
Simulation time 639908608 ps
CPU time 7.07 seconds
Started Aug 18 04:44:56 PM PDT 24
Finished Aug 18 04:45:03 PM PDT 24
Peak memory 215772 kb
Host smart-086343b1-566e-4762-a299-5343d3f72aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396784951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2396784951
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3700273672
Short name T1062
Test name
Test status
Simulation time 19130876 ps
CPU time 0.78 seconds
Started Aug 18 04:45:03 PM PDT 24
Finished Aug 18 04:45:04 PM PDT 24
Peak memory 204228 kb
Host smart-e483ed50-0b31-47ce-84f7-e49b8e6d5bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700273672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3700273672
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1810658999
Short name T1092
Test name
Test status
Simulation time 14492973 ps
CPU time 0.71 seconds
Started Aug 18 04:45:12 PM PDT 24
Finished Aug 18 04:45:13 PM PDT 24
Peak memory 204352 kb
Host smart-3344e64a-979a-4152-8c45-fba1d79345e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810658999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1810658999
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.126196696
Short name T1036
Test name
Test status
Simulation time 48574279 ps
CPU time 0.7 seconds
Started Aug 18 04:45:16 PM PDT 24
Finished Aug 18 04:45:17 PM PDT 24
Peak memory 204316 kb
Host smart-e4750345-ecab-421c-846d-38298e43bed2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126196696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.126196696
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3101257061
Short name T1041
Test name
Test status
Simulation time 61987381 ps
CPU time 0.73 seconds
Started Aug 18 04:45:04 PM PDT 24
Finished Aug 18 04:45:05 PM PDT 24
Peak memory 204348 kb
Host smart-28e69ec1-d55d-4b96-9d8e-74578be8070a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101257061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3101257061
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1957449163
Short name T1115
Test name
Test status
Simulation time 29728111 ps
CPU time 0.69 seconds
Started Aug 18 04:45:17 PM PDT 24
Finished Aug 18 04:45:17 PM PDT 24
Peak memory 204268 kb
Host smart-78db2cee-6113-479d-b388-58c67f309fe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957449163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1957449163
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2936009957
Short name T1091
Test name
Test status
Simulation time 16278859 ps
CPU time 0.79 seconds
Started Aug 18 04:45:15 PM PDT 24
Finished Aug 18 04:45:16 PM PDT 24
Peak memory 204336 kb
Host smart-d6ea8718-ad00-427f-be8a-0673b3bcdc0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936009957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2936009957
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1902023414
Short name T1131
Test name
Test status
Simulation time 39848874 ps
CPU time 0.69 seconds
Started Aug 18 04:45:07 PM PDT 24
Finished Aug 18 04:45:08 PM PDT 24
Peak memory 204276 kb
Host smart-8c8778db-242e-45e3-b2a8-58ef1e9ce538
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902023414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1902023414
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4056189621
Short name T1051
Test name
Test status
Simulation time 43402378 ps
CPU time 0.74 seconds
Started Aug 18 04:44:57 PM PDT 24
Finished Aug 18 04:44:58 PM PDT 24
Peak memory 204200 kb
Host smart-b92908d6-093b-46af-af93-cc34298fd6e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056189621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4056189621
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2707401868
Short name T1073
Test name
Test status
Simulation time 29773659 ps
CPU time 0.69 seconds
Started Aug 18 04:45:14 PM PDT 24
Finished Aug 18 04:45:15 PM PDT 24
Peak memory 204304 kb
Host smart-2cf52a31-d05e-472b-ba2f-774383dea016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707401868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2707401868
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.932460538
Short name T1035
Test name
Test status
Simulation time 30340052 ps
CPU time 0.74 seconds
Started Aug 18 04:45:01 PM PDT 24
Finished Aug 18 04:45:02 PM PDT 24
Peak memory 204400 kb
Host smart-8817eebe-c788-45a0-9e07-2822ba784dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932460538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.932460538
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.632257561
Short name T1078
Test name
Test status
Simulation time 654658488 ps
CPU time 2.77 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 218632 kb
Host smart-eb821740-0719-439f-a8d8-1241ecd75394
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632257561 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.632257561
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1746629487
Short name T1110
Test name
Test status
Simulation time 554620553 ps
CPU time 1.93 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:55 PM PDT 24
Peak memory 215988 kb
Host smart-198945da-881e-4c03-8a1b-7ec0b6eb7dd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746629487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
746629487
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1177344142
Short name T1037
Test name
Test status
Simulation time 140206102 ps
CPU time 0.72 seconds
Started Aug 18 04:44:54 PM PDT 24
Finished Aug 18 04:44:55 PM PDT 24
Peak memory 204328 kb
Host smart-504d1c38-f5fd-4f3a-a4ec-97de853c18b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177344142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
177344142
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.792030359
Short name T1040
Test name
Test status
Simulation time 81101867 ps
CPU time 2.72 seconds
Started Aug 18 04:44:54 PM PDT 24
Finished Aug 18 04:44:57 PM PDT 24
Peak memory 216240 kb
Host smart-dc87942a-1636-4faa-bd5b-4f2cbcb8ab7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792030359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.792030359
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2318654996
Short name T89
Test name
Test status
Simulation time 159698271 ps
CPU time 1.95 seconds
Started Aug 18 04:44:56 PM PDT 24
Finished Aug 18 04:44:58 PM PDT 24
Peak memory 215996 kb
Host smart-c9fe01ea-d126-4387-8236-7b58b1ca8541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318654996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
318654996
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2665359067
Short name T155
Test name
Test status
Simulation time 2129418226 ps
CPU time 21.85 seconds
Started Aug 18 04:45:12 PM PDT 24
Finished Aug 18 04:45:34 PM PDT 24
Peak memory 215888 kb
Host smart-355e6460-6125-4d1e-a3ac-521793be8b18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665359067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2665359067
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.204671451
Short name T1056
Test name
Test status
Simulation time 185607873 ps
CPU time 1.69 seconds
Started Aug 18 04:45:05 PM PDT 24
Finished Aug 18 04:45:06 PM PDT 24
Peak memory 216988 kb
Host smart-2459c1ed-026c-47dc-b238-f59e20cf4f44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204671451 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.204671451
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.642280355
Short name T107
Test name
Test status
Simulation time 28520914 ps
CPU time 1.71 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:54 PM PDT 24
Peak memory 215880 kb
Host smart-d0b54aa9-02ff-42ca-9ffa-611e2ff1853e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642280355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.642280355
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1787379419
Short name T1054
Test name
Test status
Simulation time 23182794 ps
CPU time 0.78 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 204156 kb
Host smart-8a2c792b-25b9-4034-aaab-4c058b472604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787379419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
787379419
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.428921210
Short name T1125
Test name
Test status
Simulation time 126172146 ps
CPU time 3.09 seconds
Started Aug 18 04:45:11 PM PDT 24
Finished Aug 18 04:45:15 PM PDT 24
Peak memory 215836 kb
Host smart-3cc4eddd-e88e-4e09-8f72-131f152dc202
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428921210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.428921210
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4056919737
Short name T90
Test name
Test status
Simulation time 113496613 ps
CPU time 3.79 seconds
Started Aug 18 04:45:05 PM PDT 24
Finished Aug 18 04:45:09 PM PDT 24
Peak memory 216032 kb
Host smart-02042e22-46b7-4c28-a69d-288170a59469
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056919737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
056919737
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.387278608
Short name T148
Test name
Test status
Simulation time 4068451831 ps
CPU time 21.92 seconds
Started Aug 18 04:44:58 PM PDT 24
Finished Aug 18 04:45:20 PM PDT 24
Peak memory 216368 kb
Host smart-a358e43b-53bf-48e8-b3c0-209f48f7d36b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387278608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.387278608
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2061091307
Short name T132
Test name
Test status
Simulation time 110163299 ps
CPU time 2.73 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 217704 kb
Host smart-9e80789e-b086-4bf4-87d6-b29cf5ebaae3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061091307 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2061091307
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3635166127
Short name T1134
Test name
Test status
Simulation time 78781681 ps
CPU time 1.94 seconds
Started Aug 18 04:45:08 PM PDT 24
Finished Aug 18 04:45:10 PM PDT 24
Peak memory 207680 kb
Host smart-86e63f80-7650-4d57-9390-2cc2f3396ad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635166127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
635166127
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1634601181
Short name T1151
Test name
Test status
Simulation time 23398536 ps
CPU time 0.78 seconds
Started Aug 18 04:44:58 PM PDT 24
Finished Aug 18 04:44:59 PM PDT 24
Peak memory 204572 kb
Host smart-dbbaf18d-ba4e-4fa2-bff2-80f8c6547e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634601181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
634601181
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.550911531
Short name T1101
Test name
Test status
Simulation time 59909760 ps
CPU time 3.63 seconds
Started Aug 18 04:45:00 PM PDT 24
Finished Aug 18 04:45:04 PM PDT 24
Peak memory 215892 kb
Host smart-5d0aa7cd-a1b0-4f8c-9a9a-116ebc27ad9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550911531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.550911531
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.888989450
Short name T1127
Test name
Test status
Simulation time 91694305 ps
CPU time 2.42 seconds
Started Aug 18 04:44:56 PM PDT 24
Finished Aug 18 04:44:59 PM PDT 24
Peak memory 216084 kb
Host smart-1c030ee5-3df4-4be6-b894-52e9b090100f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888989450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.888989450
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1333526527
Short name T152
Test name
Test status
Simulation time 8926000600 ps
CPU time 15.38 seconds
Started Aug 18 04:45:09 PM PDT 24
Finished Aug 18 04:45:24 PM PDT 24
Peak memory 216256 kb
Host smart-e09d71e1-dc2e-4b5f-9516-9d9cf2552469
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333526527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1333526527
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3309662455
Short name T83
Test name
Test status
Simulation time 182320444 ps
CPU time 1.57 seconds
Started Aug 18 04:45:09 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 216004 kb
Host smart-d95c3333-6ab4-42f4-bb09-051e9f74b95d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309662455 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3309662455
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3269554845
Short name T110
Test name
Test status
Simulation time 191730813 ps
CPU time 2.14 seconds
Started Aug 18 04:45:08 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 207664 kb
Host smart-30086854-12a1-4c9b-8457-de5248a004be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269554845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
269554845
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2234179257
Short name T1116
Test name
Test status
Simulation time 15116160 ps
CPU time 0.76 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:44:53 PM PDT 24
Peak memory 204248 kb
Host smart-0d5a520f-cf00-44a5-b47d-5e69049f443b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234179257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
234179257
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.527587504
Short name T131
Test name
Test status
Simulation time 185796285 ps
CPU time 3.97 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:57 PM PDT 24
Peak memory 215868 kb
Host smart-9ddd3514-9f23-46c1-94b9-e2d56981349a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527587504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.527587504
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1259269724
Short name T92
Test name
Test status
Simulation time 240634914 ps
CPU time 1.79 seconds
Started Aug 18 04:45:08 PM PDT 24
Finished Aug 18 04:45:10 PM PDT 24
Peak memory 215928 kb
Host smart-ea5230f3-97e6-4cb8-b2ca-222af9206b61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259269724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
259269724
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1902649485
Short name T150
Test name
Test status
Simulation time 2167036983 ps
CPU time 14.19 seconds
Started Aug 18 04:44:57 PM PDT 24
Finished Aug 18 04:45:11 PM PDT 24
Peak memory 216212 kb
Host smart-12d8460c-4fcf-4983-aba1-7664c0f9917e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902649485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1902649485
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1411037403
Short name T1097
Test name
Test status
Simulation time 219440829 ps
CPU time 3.57 seconds
Started Aug 18 04:45:10 PM PDT 24
Finished Aug 18 04:45:14 PM PDT 24
Peak memory 218172 kb
Host smart-c4507f66-507e-4453-94d5-5c10af8638e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411037403 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1411037403
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.888891638
Short name T1072
Test name
Test status
Simulation time 29871760 ps
CPU time 2 seconds
Started Aug 18 04:45:01 PM PDT 24
Finished Aug 18 04:45:03 PM PDT 24
Peak memory 215792 kb
Host smart-14f1ca05-f7f9-4b2f-9901-6db8e465a1da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888891638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.888891638
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.446088612
Short name T1032
Test name
Test status
Simulation time 67030199 ps
CPU time 0.74 seconds
Started Aug 18 04:44:54 PM PDT 24
Finished Aug 18 04:44:54 PM PDT 24
Peak memory 204232 kb
Host smart-067fc1e0-28dc-473b-9980-d851cce5a09c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446088612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.446088612
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2531388133
Short name T1093
Test name
Test status
Simulation time 106170571 ps
CPU time 2.99 seconds
Started Aug 18 04:44:53 PM PDT 24
Finished Aug 18 04:44:56 PM PDT 24
Peak memory 215936 kb
Host smart-5727e168-824a-4b7d-9f42-ef7e7a28b45b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531388133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2531388133
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.15559000
Short name T146
Test name
Test status
Simulation time 2640628634 ps
CPU time 14.44 seconds
Started Aug 18 04:44:52 PM PDT 24
Finished Aug 18 04:45:07 PM PDT 24
Peak memory 217576 kb
Host smart-999482e0-6a13-4a28-b241-429fa229a60b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15559000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_t
l_intg_err.15559000
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.296661205
Short name T438
Test name
Test status
Simulation time 35475346 ps
CPU time 0.73 seconds
Started Aug 18 05:48:56 PM PDT 24
Finished Aug 18 05:48:57 PM PDT 24
Peak memory 205404 kb
Host smart-c46ec2f7-928c-4e11-a24f-8bf79868b659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296661205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.296661205
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2159771165
Short name T46
Test name
Test status
Simulation time 113256596 ps
CPU time 2.28 seconds
Started Aug 18 05:48:57 PM PDT 24
Finished Aug 18 05:49:00 PM PDT 24
Peak memory 224552 kb
Host smart-d90cda20-6989-4273-8a3f-f5786681d67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159771165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2159771165
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.401527084
Short name T339
Test name
Test status
Simulation time 70532065 ps
CPU time 0.76 seconds
Started Aug 18 05:48:57 PM PDT 24
Finished Aug 18 05:48:58 PM PDT 24
Peak memory 206920 kb
Host smart-caf4513d-900e-4900-b9e0-c0efe330fce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401527084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.401527084
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2467651531
Short name T269
Test name
Test status
Simulation time 16122112900 ps
CPU time 146.88 seconds
Started Aug 18 05:48:52 PM PDT 24
Finished Aug 18 05:51:19 PM PDT 24
Peak memory 240256 kb
Host smart-b8a154a0-8c2b-47d4-9f5e-e792990b291e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467651531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2467651531
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.5100898
Short name T1010
Test name
Test status
Simulation time 70237779209 ps
CPU time 170.59 seconds
Started Aug 18 05:48:52 PM PDT 24
Finished Aug 18 05:51:42 PM PDT 24
Peak memory 257236 kb
Host smart-f6acc3ce-190c-4502-a87d-4799b5eeb902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5100898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.5100898
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.105161215
Short name T639
Test name
Test status
Simulation time 514597775 ps
CPU time 9.18 seconds
Started Aug 18 05:48:55 PM PDT 24
Finished Aug 18 05:49:04 PM PDT 24
Peak memory 224676 kb
Host smart-9c882261-bb74-4859-8961-eb2d51ddf217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105161215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.105161215
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2935377975
Short name T442
Test name
Test status
Simulation time 7529071813 ps
CPU time 30.58 seconds
Started Aug 18 05:48:57 PM PDT 24
Finished Aug 18 05:49:28 PM PDT 24
Peak memory 249324 kb
Host smart-cc18d6ac-98bb-410d-96f8-16bc40979cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935377975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2935377975
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4255880221
Short name T974
Test name
Test status
Simulation time 159175741 ps
CPU time 4.17 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:09 PM PDT 24
Peak memory 224616 kb
Host smart-21703bb9-419f-412b-b001-4fece23a08a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255880221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4255880221
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2741410940
Short name T516
Test name
Test status
Simulation time 7261480163 ps
CPU time 23.92 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:28 PM PDT 24
Peak memory 224728 kb
Host smart-bd2b3804-36c4-4d61-8e90-8e9a7656351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741410940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2741410940
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4037468538
Short name T67
Test name
Test status
Simulation time 1190707573 ps
CPU time 2.58 seconds
Started Aug 18 05:48:56 PM PDT 24
Finished Aug 18 05:48:59 PM PDT 24
Peak memory 232784 kb
Host smart-0f12622a-e86d-47ba-9612-0a8fb30d9d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037468538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4037468538
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4091429467
Short name T667
Test name
Test status
Simulation time 2701793136 ps
CPU time 9 seconds
Started Aug 18 05:48:54 PM PDT 24
Finished Aug 18 05:49:03 PM PDT 24
Peak memory 232912 kb
Host smart-d593a547-0aa0-48a6-959b-a325961688cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091429467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4091429467
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1050896547
Short name T676
Test name
Test status
Simulation time 4681288033 ps
CPU time 9.92 seconds
Started Aug 18 05:49:05 PM PDT 24
Finished Aug 18 05:49:15 PM PDT 24
Peak memory 222120 kb
Host smart-c6f540b5-1f85-4e86-b1b7-3e3832797a60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1050896547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1050896547
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4226522980
Short name T348
Test name
Test status
Simulation time 1343258474 ps
CPU time 19.69 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:24 PM PDT 24
Peak memory 219468 kb
Host smart-79377f92-825b-4569-893c-25eebedfb683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226522980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4226522980
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3822547560
Short name T537
Test name
Test status
Simulation time 13927856901 ps
CPU time 11.06 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:49:15 PM PDT 24
Peak memory 216528 kb
Host smart-6eaf0e0b-b6dd-4055-bfd9-d498ad1d9bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822547560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3822547560
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3147285427
Short name T1019
Test name
Test status
Simulation time 268521184 ps
CPU time 2.45 seconds
Started Aug 18 05:48:52 PM PDT 24
Finished Aug 18 05:48:55 PM PDT 24
Peak memory 216432 kb
Host smart-9c6240df-c934-472c-916b-751cc213aaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147285427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3147285427
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2263103606
Short name T613
Test name
Test status
Simulation time 53605562 ps
CPU time 0.83 seconds
Started Aug 18 05:48:55 PM PDT 24
Finished Aug 18 05:48:56 PM PDT 24
Peak memory 206060 kb
Host smart-68a4655b-af0e-45f4-b7b6-d35bb5b46a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263103606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2263103606
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2876723074
Short name T425
Test name
Test status
Simulation time 34908514 ps
CPU time 2.1 seconds
Started Aug 18 05:48:53 PM PDT 24
Finished Aug 18 05:48:55 PM PDT 24
Peak memory 234116 kb
Host smart-6e9c5c0a-c6ce-4ac8-bade-2bed4678c768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876723074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2876723074
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3629460424
Short name T918
Test name
Test status
Simulation time 41397724 ps
CPU time 0.7 seconds
Started Aug 18 05:49:01 PM PDT 24
Finished Aug 18 05:49:02 PM PDT 24
Peak memory 205852 kb
Host smart-c796f55b-8c3a-4dda-9148-296bbbee2e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629460424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
629460424
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1844260684
Short name T374
Test name
Test status
Simulation time 1863447539 ps
CPU time 7.2 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:49:10 PM PDT 24
Peak memory 224608 kb
Host smart-78779c22-620f-47ce-b5fd-848f36eec8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844260684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1844260684
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2735325685
Short name T308
Test name
Test status
Simulation time 21923322 ps
CPU time 0.82 seconds
Started Aug 18 05:48:56 PM PDT 24
Finished Aug 18 05:48:57 PM PDT 24
Peak memory 206576 kb
Host smart-ef47390c-981e-4499-b317-2de550ceba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735325685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2735325685
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1251386948
Short name T313
Test name
Test status
Simulation time 5718948861 ps
CPU time 22.57 seconds
Started Aug 18 05:48:58 PM PDT 24
Finished Aug 18 05:49:21 PM PDT 24
Peak memory 232892 kb
Host smart-252a3a8a-2a84-4eca-8c47-8ff124f98093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251386948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1251386948
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.171492717
Short name T205
Test name
Test status
Simulation time 14568471368 ps
CPU time 135.26 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:51:18 PM PDT 24
Peak memory 253540 kb
Host smart-34f0e7c8-80c9-4636-859a-5157307e2ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171492717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.171492717
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2652434255
Short name T984
Test name
Test status
Simulation time 41605743387 ps
CPU time 85.59 seconds
Started Aug 18 05:49:02 PM PDT 24
Finished Aug 18 05:50:28 PM PDT 24
Peak memory 236344 kb
Host smart-373e41ca-1036-40f3-80c6-133b24c98766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652434255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2652434255
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1321537082
Short name T603
Test name
Test status
Simulation time 74729935 ps
CPU time 2.68 seconds
Started Aug 18 05:48:58 PM PDT 24
Finished Aug 18 05:49:00 PM PDT 24
Peak memory 224616 kb
Host smart-c1d3b735-c6d6-429d-ad5d-4f6094703eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321537082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1321537082
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1658035199
Short name T262
Test name
Test status
Simulation time 7513884453 ps
CPU time 75.95 seconds
Started Aug 18 05:49:01 PM PDT 24
Finished Aug 18 05:50:18 PM PDT 24
Peak memory 256872 kb
Host smart-e5daf626-ed8a-4747-9748-a625712acaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658035199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1658035199
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2292821551
Short name T519
Test name
Test status
Simulation time 754354471 ps
CPU time 5.59 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:49:09 PM PDT 24
Peak memory 232828 kb
Host smart-88c3f9db-43c2-4991-8c24-6442f1abd4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292821551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2292821551
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1064941037
Short name T324
Test name
Test status
Simulation time 5995195400 ps
CPU time 15.89 seconds
Started Aug 18 05:49:10 PM PDT 24
Finished Aug 18 05:49:26 PM PDT 24
Peak memory 232944 kb
Host smart-6042ce46-d584-421d-8dd3-7fabd39d702c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064941037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1064941037
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3667040792
Short name T854
Test name
Test status
Simulation time 99757539 ps
CPU time 1 seconds
Started Aug 18 05:48:54 PM PDT 24
Finished Aug 18 05:48:55 PM PDT 24
Peak memory 217968 kb
Host smart-4947f906-4bf7-4a53-a274-0c2a8479beae
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667040792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3667040792
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1353314473
Short name T924
Test name
Test status
Simulation time 1246768309 ps
CPU time 3.88 seconds
Started Aug 18 05:49:00 PM PDT 24
Finished Aug 18 05:49:04 PM PDT 24
Peak memory 224576 kb
Host smart-724185cd-4133-4766-8d91-20b8a27d834c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353314473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1353314473
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1088538842
Short name T730
Test name
Test status
Simulation time 1335616895 ps
CPU time 4.42 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:09 PM PDT 24
Peak memory 224620 kb
Host smart-61ac572f-26a9-40b2-bfa9-7f0530480c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088538842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1088538842
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.820422331
Short name T626
Test name
Test status
Simulation time 5643444838 ps
CPU time 6.85 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:11 PM PDT 24
Peak memory 220212 kb
Host smart-56aa5c83-44e3-4520-8762-8a92724dde6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=820422331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.820422331
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.4154925412
Short name T57
Test name
Test status
Simulation time 37682839 ps
CPU time 0.95 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 235580 kb
Host smart-c9e65986-4ec9-4daa-8fc5-04a964dec8be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154925412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.4154925412
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3950500394
Short name T872
Test name
Test status
Simulation time 29962167988 ps
CPU time 72.94 seconds
Started Aug 18 05:49:00 PM PDT 24
Finished Aug 18 05:50:13 PM PDT 24
Peak memory 249328 kb
Host smart-1f71a6e0-fb7e-46a4-8ada-ab5312fa51ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950500394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3950500394
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.762983472
Short name T342
Test name
Test status
Simulation time 463180276 ps
CPU time 3.37 seconds
Started Aug 18 05:48:56 PM PDT 24
Finished Aug 18 05:48:59 PM PDT 24
Peak memory 216460 kb
Host smart-4091da2f-6a7f-43fb-8520-a5eb20248be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762983472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.762983472
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2733465904
Short name T399
Test name
Test status
Simulation time 31228142 ps
CPU time 1.44 seconds
Started Aug 18 05:48:52 PM PDT 24
Finished Aug 18 05:48:54 PM PDT 24
Peak memory 216460 kb
Host smart-f7605ddf-31fe-4a37-8961-c6b2553184d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733465904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2733465904
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1484691453
Short name T647
Test name
Test status
Simulation time 470974322 ps
CPU time 1.01 seconds
Started Aug 18 05:48:52 PM PDT 24
Finished Aug 18 05:48:53 PM PDT 24
Peak memory 207116 kb
Host smart-d8e4568e-7767-431e-b015-5cbc1da196f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484691453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1484691453
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.4193208802
Short name T100
Test name
Test status
Simulation time 1028961788 ps
CPU time 2.36 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 223428 kb
Host smart-6197bc89-8821-4a0e-8826-d20482e72a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193208802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4193208802
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.602528883
Short name T887
Test name
Test status
Simulation time 12032092 ps
CPU time 0.71 seconds
Started Aug 18 05:49:37 PM PDT 24
Finished Aug 18 05:49:38 PM PDT 24
Peak memory 205796 kb
Host smart-e63532db-0a9a-4bdb-8255-7390b9083baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602528883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.602528883
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3246102003
Short name T407
Test name
Test status
Simulation time 405046802 ps
CPU time 3.27 seconds
Started Aug 18 05:49:23 PM PDT 24
Finished Aug 18 05:49:26 PM PDT 24
Peak memory 232768 kb
Host smart-93c3f114-511e-4c51-b3fd-7f32d0aa6122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246102003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3246102003
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4197362363
Short name T457
Test name
Test status
Simulation time 96916371 ps
CPU time 0.74 seconds
Started Aug 18 05:49:27 PM PDT 24
Finished Aug 18 05:49:28 PM PDT 24
Peak memory 206920 kb
Host smart-cbc911f3-ab6e-4e6c-8281-08bd42be2e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197362363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4197362363
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1168337232
Short name T221
Test name
Test status
Simulation time 1223702733 ps
CPU time 17.55 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 249252 kb
Host smart-493ab71f-965a-499d-a924-595f87cecbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168337232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1168337232
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2571860266
Short name T609
Test name
Test status
Simulation time 7572531529 ps
CPU time 38.83 seconds
Started Aug 18 05:49:27 PM PDT 24
Finished Aug 18 05:50:06 PM PDT 24
Peak memory 250344 kb
Host smart-bad33a59-3879-47af-8a2c-a546664b7445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571860266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2571860266
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.291260164
Short name T493
Test name
Test status
Simulation time 360782728 ps
CPU time 6.03 seconds
Started Aug 18 05:49:32 PM PDT 24
Finished Aug 18 05:49:38 PM PDT 24
Peak memory 232852 kb
Host smart-c10f93ba-3c56-4738-a8f4-532a41094017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291260164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.291260164
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1241836586
Short name T682
Test name
Test status
Simulation time 4027006122 ps
CPU time 8.48 seconds
Started Aug 18 05:49:30 PM PDT 24
Finished Aug 18 05:49:39 PM PDT 24
Peak memory 232896 kb
Host smart-edc6af27-15b8-402b-950c-7893ba9d17b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241836586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1241836586
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.265123837
Short name T747
Test name
Test status
Simulation time 2012118635 ps
CPU time 9.37 seconds
Started Aug 18 05:49:21 PM PDT 24
Finished Aug 18 05:49:31 PM PDT 24
Peak memory 224656 kb
Host smart-5a499c0a-508a-492d-a672-0e360787bf13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265123837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.265123837
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3091397024
Short name T33
Test name
Test status
Simulation time 32979032 ps
CPU time 1.15 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:49:36 PM PDT 24
Peak memory 216696 kb
Host smart-eb2190d7-080b-476d-960e-13c8311566c8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091397024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3091397024
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3742808037
Short name T250
Test name
Test status
Simulation time 1889964973 ps
CPU time 6.71 seconds
Started Aug 18 05:49:26 PM PDT 24
Finished Aug 18 05:49:33 PM PDT 24
Peak memory 232788 kb
Host smart-1e9e7faf-b685-4f68-8322-9720c2f13d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742808037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3742808037
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.568366754
Short name T63
Test name
Test status
Simulation time 450735932 ps
CPU time 2.47 seconds
Started Aug 18 05:49:35 PM PDT 24
Finished Aug 18 05:49:37 PM PDT 24
Peak memory 224600 kb
Host smart-5b0fa5c9-557a-400d-9ee1-774110053bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568366754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.568366754
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.176400073
Short name T805
Test name
Test status
Simulation time 532580934 ps
CPU time 5.73 seconds
Started Aug 18 05:49:24 PM PDT 24
Finished Aug 18 05:49:29 PM PDT 24
Peak memory 220488 kb
Host smart-118f76f3-8030-4fdb-9933-d48b00896eb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=176400073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.176400073
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1225036988
Short name T552
Test name
Test status
Simulation time 46493043824 ps
CPU time 142.97 seconds
Started Aug 18 05:49:30 PM PDT 24
Finished Aug 18 05:51:53 PM PDT 24
Peak memory 255224 kb
Host smart-89473638-302c-4cd9-8d74-3566a2573b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225036988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1225036988
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.42460230
Short name T758
Test name
Test status
Simulation time 5347206387 ps
CPU time 19.7 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:49:53 PM PDT 24
Peak memory 216488 kb
Host smart-70bcab45-c1a9-4b7e-b267-31e270a8662f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42460230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.42460230
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1431896797
Short name T740
Test name
Test status
Simulation time 21012129800 ps
CPU time 7.03 seconds
Started Aug 18 05:49:29 PM PDT 24
Finished Aug 18 05:49:36 PM PDT 24
Peak memory 216564 kb
Host smart-0722465f-ee55-45b0-8413-f0b73ac26988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431896797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1431896797
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1566900624
Short name T414
Test name
Test status
Simulation time 16854957 ps
CPU time 0.83 seconds
Started Aug 18 05:49:27 PM PDT 24
Finished Aug 18 05:49:28 PM PDT 24
Peak memory 206056 kb
Host smart-f9f2680c-4d6f-4668-b80f-94b9cef7510f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566900624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1566900624
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1177296179
Short name T540
Test name
Test status
Simulation time 115728832 ps
CPU time 0.88 seconds
Started Aug 18 05:49:25 PM PDT 24
Finished Aug 18 05:49:26 PM PDT 24
Peak memory 206076 kb
Host smart-641cab1a-2f2a-4e75-a405-d45fe19b7245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177296179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1177296179
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2697003201
Short name T823
Test name
Test status
Simulation time 1749319762 ps
CPU time 4.02 seconds
Started Aug 18 05:49:32 PM PDT 24
Finished Aug 18 05:49:36 PM PDT 24
Peak memory 224600 kb
Host smart-1d7418b0-7da9-4bc5-8c67-eb51a210211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697003201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2697003201
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3336374510
Short name T163
Test name
Test status
Simulation time 53706759 ps
CPU time 2.13 seconds
Started Aug 18 05:49:25 PM PDT 24
Finished Aug 18 05:49:28 PM PDT 24
Peak memory 223632 kb
Host smart-8a672c88-76ca-4392-b009-900e985bb045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336374510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3336374510
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.270272807
Short name T352
Test name
Test status
Simulation time 53988667 ps
CPU time 0.75 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:49:35 PM PDT 24
Peak memory 205892 kb
Host smart-fdcfd289-39f2-4bd9-a0be-3357384f0840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270272807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.270272807
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1362990829
Short name T599
Test name
Test status
Simulation time 9716050406 ps
CPU time 17.13 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:49:50 PM PDT 24
Peak memory 241108 kb
Host smart-a73daaa4-737d-495a-b3c8-86ddcaca95ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362990829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1362990829
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1592027636
Short name T835
Test name
Test status
Simulation time 31840837305 ps
CPU time 121.28 seconds
Started Aug 18 05:49:38 PM PDT 24
Finished Aug 18 05:51:40 PM PDT 24
Peak memory 253784 kb
Host smart-9da69e76-7803-4ca7-a4f5-9a25be536331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592027636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1592027636
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1996675093
Short name T42
Test name
Test status
Simulation time 7339996945 ps
CPU time 93.18 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:51:07 PM PDT 24
Peak memory 249360 kb
Host smart-1ddd7607-fff1-483d-93a0-0310a932e815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996675093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1996675093
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.260777771
Short name T789
Test name
Test status
Simulation time 3615987933 ps
CPU time 52.64 seconds
Started Aug 18 05:49:27 PM PDT 24
Finished Aug 18 05:50:20 PM PDT 24
Peak memory 232944 kb
Host smart-7f06aa00-783b-452a-8f78-18004b1034a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260777771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.260777771
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2660546082
Short name T665
Test name
Test status
Simulation time 789581231 ps
CPU time 12.55 seconds
Started Aug 18 05:49:24 PM PDT 24
Finished Aug 18 05:49:37 PM PDT 24
Peak memory 224688 kb
Host smart-c7f9ceb5-71b5-4130-a417-00ca7df3b27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660546082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2660546082
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.234358533
Short name T207
Test name
Test status
Simulation time 23699779719 ps
CPU time 22.69 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:49:56 PM PDT 24
Peak memory 224744 kb
Host smart-a932c813-618f-48ae-a85f-92824d065189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234358533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.234358533
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.608567765
Short name T429
Test name
Test status
Simulation time 24074655 ps
CPU time 0.96 seconds
Started Aug 18 05:49:23 PM PDT 24
Finished Aug 18 05:49:24 PM PDT 24
Peak memory 217940 kb
Host smart-c6a33588-4421-4ccb-b7bf-6b4e27dd7f5f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608567765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.608567765
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1637367193
Short name T1018
Test name
Test status
Simulation time 532207564 ps
CPU time 5.38 seconds
Started Aug 18 05:49:23 PM PDT 24
Finished Aug 18 05:49:28 PM PDT 24
Peak memory 232812 kb
Host smart-9b3f0f78-fd1c-4c66-b00b-be6c8896d3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637367193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1637367193
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3964693345
Short name T1026
Test name
Test status
Simulation time 962229502 ps
CPU time 5.01 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:49:38 PM PDT 24
Peak memory 232864 kb
Host smart-8999f6ab-451a-4225-bffc-e405ba041086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964693345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3964693345
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1742961819
Short name T686
Test name
Test status
Simulation time 782083912 ps
CPU time 3.44 seconds
Started Aug 18 05:49:23 PM PDT 24
Finished Aug 18 05:49:27 PM PDT 24
Peak memory 223192 kb
Host smart-b6107fcf-510e-4684-ade2-642a766ae81f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1742961819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1742961819
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1049684401
Short name T375
Test name
Test status
Simulation time 15755142478 ps
CPU time 22.32 seconds
Started Aug 18 05:49:32 PM PDT 24
Finished Aug 18 05:49:54 PM PDT 24
Peak memory 220032 kb
Host smart-ab4dd899-ff80-4d97-9a88-112130715200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049684401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1049684401
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3038318926
Short name T1025
Test name
Test status
Simulation time 5688108281 ps
CPU time 8.02 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:49:42 PM PDT 24
Peak memory 216544 kb
Host smart-fe99da73-e132-48bf-a8c1-42bd3e32be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038318926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3038318926
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1022835948
Short name T68
Test name
Test status
Simulation time 249885386 ps
CPU time 1.49 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:49:36 PM PDT 24
Peak memory 216480 kb
Host smart-1a82ee45-45f6-4a34-a562-a05a30e43512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022835948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1022835948
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_upload.1584772941
Short name T961
Test name
Test status
Simulation time 142251395 ps
CPU time 2.59 seconds
Started Aug 18 05:49:29 PM PDT 24
Finished Aug 18 05:49:32 PM PDT 24
Peak memory 224696 kb
Host smart-d6022221-4368-44cb-a21a-2f17b649e121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584772941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1584772941
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4156314395
Short name T727
Test name
Test status
Simulation time 14785843 ps
CPU time 0.7 seconds
Started Aug 18 05:49:37 PM PDT 24
Finished Aug 18 05:49:38 PM PDT 24
Peak memory 205508 kb
Host smart-c8c3e864-ba33-4080-a0d9-c235147068b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156314395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4156314395
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3033845440
Short name T229
Test name
Test status
Simulation time 1314312190 ps
CPU time 8.28 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:49:42 PM PDT 24
Peak memory 232812 kb
Host smart-1e753792-72c9-48b3-b0c8-4dc0049e16aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033845440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3033845440
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3389350527
Short name T671
Test name
Test status
Simulation time 60323027 ps
CPU time 0.75 seconds
Started Aug 18 05:49:25 PM PDT 24
Finished Aug 18 05:49:26 PM PDT 24
Peak memory 206864 kb
Host smart-53c0a013-d3fb-4620-ac39-dccab7ae53c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389350527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3389350527
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2558202712
Short name T282
Test name
Test status
Simulation time 8309771204 ps
CPU time 36.85 seconds
Started Aug 18 05:49:32 PM PDT 24
Finished Aug 18 05:50:09 PM PDT 24
Peak memory 237696 kb
Host smart-e42009d7-664c-464b-bb1a-377b50450598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558202712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2558202712
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3873644047
Short name T1013
Test name
Test status
Simulation time 48045757585 ps
CPU time 154.79 seconds
Started Aug 18 05:49:38 PM PDT 24
Finished Aug 18 05:52:13 PM PDT 24
Peak memory 253536 kb
Host smart-5ef9c78e-5577-46c6-b971-f277c6dc3258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873644047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3873644047
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2664920650
Short name T464
Test name
Test status
Simulation time 429147188 ps
CPU time 8.98 seconds
Started Aug 18 05:49:37 PM PDT 24
Finished Aug 18 05:49:46 PM PDT 24
Peak memory 249276 kb
Host smart-396275cb-c352-4bd6-a7e4-3abb288830f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664920650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2664920650
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.863889539
Short name T568
Test name
Test status
Simulation time 21363260776 ps
CPU time 113.38 seconds
Started Aug 18 05:49:36 PM PDT 24
Finished Aug 18 05:51:29 PM PDT 24
Peak memory 254364 kb
Host smart-9d05a3a7-e77f-4aa5-8c57-9ebd6181e779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863889539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.863889539
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2170964096
Short name T555
Test name
Test status
Simulation time 529599182 ps
CPU time 3.29 seconds
Started Aug 18 05:49:37 PM PDT 24
Finished Aug 18 05:49:40 PM PDT 24
Peak memory 232892 kb
Host smart-93b483f0-24a6-4abd-a24c-c104a59053ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170964096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2170964096
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2163064435
Short name T673
Test name
Test status
Simulation time 113979968541 ps
CPU time 59.17 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:50:33 PM PDT 24
Peak memory 241000 kb
Host smart-35feae0f-4394-4da4-9f45-b44162032199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163064435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2163064435
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1486210277
Short name T452
Test name
Test status
Simulation time 15687920 ps
CPU time 1.03 seconds
Started Aug 18 05:49:27 PM PDT 24
Finished Aug 18 05:49:28 PM PDT 24
Peak memory 215716 kb
Host smart-39cef88b-fbbe-4fcb-9684-16fd712eef70
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486210277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1486210277
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.516672101
Short name T576
Test name
Test status
Simulation time 47059260 ps
CPU time 2.29 seconds
Started Aug 18 05:49:38 PM PDT 24
Finished Aug 18 05:49:41 PM PDT 24
Peak memory 232784 kb
Host smart-e24d182c-e92d-462e-b2bc-e056d0558edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516672101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.516672101
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2988063160
Short name T653
Test name
Test status
Simulation time 478692582 ps
CPU time 6.01 seconds
Started Aug 18 05:49:36 PM PDT 24
Finished Aug 18 05:49:42 PM PDT 24
Peak memory 232880 kb
Host smart-7827cab5-f7d1-4ada-8ed6-3a03f63bf07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988063160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2988063160
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4138442521
Short name T828
Test name
Test status
Simulation time 5188620416 ps
CPU time 10.39 seconds
Started Aug 18 05:49:35 PM PDT 24
Finished Aug 18 05:49:46 PM PDT 24
Peak memory 218936 kb
Host smart-18301bad-04bc-442d-b677-f4d0d0236127
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4138442521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4138442521
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3530679929
Short name T584
Test name
Test status
Simulation time 46015708 ps
CPU time 1.03 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:49:35 PM PDT 24
Peak memory 206968 kb
Host smart-f73d7e53-273f-4b62-a072-2a4cc8859d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530679929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3530679929
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1413966683
Short name T615
Test name
Test status
Simulation time 2159820818 ps
CPU time 32.86 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:50:06 PM PDT 24
Peak memory 216548 kb
Host smart-5ab173ba-e05d-4987-9df3-9bcd353b41bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413966683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1413966683
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2663379743
Short name T304
Test name
Test status
Simulation time 1150526997 ps
CPU time 6.61 seconds
Started Aug 18 05:49:38 PM PDT 24
Finished Aug 18 05:49:45 PM PDT 24
Peak memory 216612 kb
Host smart-46973158-a102-4c86-b39b-6e57bb40e188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663379743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2663379743
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2913677364
Short name T814
Test name
Test status
Simulation time 61433287 ps
CPU time 1.12 seconds
Started Aug 18 05:49:36 PM PDT 24
Finished Aug 18 05:49:37 PM PDT 24
Peak memory 208236 kb
Host smart-11ab4380-0d91-4e3e-9a73-d39b3c532a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913677364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2913677364
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3206591380
Short name T507
Test name
Test status
Simulation time 333516453 ps
CPU time 0.83 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:49:34 PM PDT 24
Peak memory 206028 kb
Host smart-d81d131e-6a69-48b9-993a-775d44d6666d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206591380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3206591380
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1791624934
Short name T788
Test name
Test status
Simulation time 2504005635 ps
CPU time 10.34 seconds
Started Aug 18 05:49:37 PM PDT 24
Finished Aug 18 05:49:48 PM PDT 24
Peak memory 232908 kb
Host smart-77753e35-00e2-4774-bd52-709c76f77b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791624934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1791624934
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2780309701
Short name T945
Test name
Test status
Simulation time 13971755 ps
CPU time 0.7 seconds
Started Aug 18 05:49:40 PM PDT 24
Finished Aug 18 05:49:41 PM PDT 24
Peak memory 205872 kb
Host smart-fdf3bea2-7d4f-40f2-ac68-05fead9911bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780309701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2780309701
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3404151101
Short name T495
Test name
Test status
Simulation time 9287427992 ps
CPU time 19.53 seconds
Started Aug 18 05:49:38 PM PDT 24
Finished Aug 18 05:49:58 PM PDT 24
Peak memory 224664 kb
Host smart-558df2cf-f638-4f1e-bb1f-f39e5931c68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404151101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3404151101
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1840254397
Short name T638
Test name
Test status
Simulation time 13964642 ps
CPU time 0.79 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:49:34 PM PDT 24
Peak memory 206568 kb
Host smart-89a1e7ef-6980-4ec6-b14f-0930c33be3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840254397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1840254397
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2055192872
Short name T177
Test name
Test status
Simulation time 32708209196 ps
CPU time 253.13 seconds
Started Aug 18 05:49:37 PM PDT 24
Finished Aug 18 05:53:51 PM PDT 24
Peak memory 269496 kb
Host smart-3465a9ef-dc58-4fce-afb7-a268426d52ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055192872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2055192872
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1068114264
Short name T743
Test name
Test status
Simulation time 79418884531 ps
CPU time 259.37 seconds
Started Aug 18 05:49:37 PM PDT 24
Finished Aug 18 05:53:56 PM PDT 24
Peak memory 261924 kb
Host smart-ac6c37bc-6cfd-4b24-b180-bca59752a555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068114264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1068114264
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.522627291
Short name T28
Test name
Test status
Simulation time 56425631783 ps
CPU time 215.25 seconds
Started Aug 18 05:49:32 PM PDT 24
Finished Aug 18 05:53:08 PM PDT 24
Peak memory 262044 kb
Host smart-61131f03-50b8-4747-a361-1a1d074d17a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522627291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.522627291
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3557632783
Short name T302
Test name
Test status
Simulation time 299585264 ps
CPU time 3.7 seconds
Started Aug 18 05:49:40 PM PDT 24
Finished Aug 18 05:49:44 PM PDT 24
Peak memory 232724 kb
Host smart-76bf6e3c-a25c-42a9-9b1c-7b7b1b9958fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557632783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3557632783
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2932968079
Short name T817
Test name
Test status
Simulation time 1467843965 ps
CPU time 37.97 seconds
Started Aug 18 05:49:36 PM PDT 24
Finished Aug 18 05:50:15 PM PDT 24
Peak memory 249240 kb
Host smart-1a24a25a-6c5d-486b-8686-5f840f67e2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932968079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2932968079
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2702609421
Short name T812
Test name
Test status
Simulation time 18289348635 ps
CPU time 41.09 seconds
Started Aug 18 05:49:37 PM PDT 24
Finished Aug 18 05:50:18 PM PDT 24
Peak memory 232868 kb
Host smart-3404716e-73f6-4f6b-8e82-cd37a29ba360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702609421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2702609421
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.656306093
Short name T912
Test name
Test status
Simulation time 119972793 ps
CPU time 1.04 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:49:34 PM PDT 24
Peak memory 216684 kb
Host smart-96aea9f0-8b13-48d9-b85e-3c1764812162
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656306093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.656306093
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.4225351620
Short name T494
Test name
Test status
Simulation time 141673735 ps
CPU time 2.5 seconds
Started Aug 18 05:49:30 PM PDT 24
Finished Aug 18 05:49:33 PM PDT 24
Peak memory 232784 kb
Host smart-445bd809-e173-46e4-a73d-2207b8363e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225351620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.4225351620
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1503344754
Short name T485
Test name
Test status
Simulation time 72606926 ps
CPU time 2.48 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:49:37 PM PDT 24
Peak memory 224568 kb
Host smart-cee4f515-7175-4f51-a9fd-9fee510fc2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503344754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1503344754
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4216145146
Short name T915
Test name
Test status
Simulation time 601238778 ps
CPU time 7.44 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:49:42 PM PDT 24
Peak memory 220632 kb
Host smart-13a0671f-6494-41e5-8f27-ba2617929fdc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4216145146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4216145146
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2901850068
Short name T736
Test name
Test status
Simulation time 9329781295 ps
CPU time 63.21 seconds
Started Aug 18 05:49:39 PM PDT 24
Finished Aug 18 05:50:42 PM PDT 24
Peak memory 257492 kb
Host smart-ab81ed3e-a101-45a1-889c-811b639760a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901850068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2901850068
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.105709622
Short name T1002
Test name
Test status
Simulation time 3164994664 ps
CPU time 29.99 seconds
Started Aug 18 05:49:37 PM PDT 24
Finished Aug 18 05:50:07 PM PDT 24
Peak memory 216492 kb
Host smart-5c5fa3c3-4a2a-474b-8ada-39a044883f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105709622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.105709622
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1867342390
Short name T550
Test name
Test status
Simulation time 362371075 ps
CPU time 2.29 seconds
Started Aug 18 05:49:38 PM PDT 24
Finished Aug 18 05:49:40 PM PDT 24
Peak memory 216216 kb
Host smart-5a90afd3-8bd4-4932-9dcd-7ab0c81c924d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867342390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1867342390
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3998263003
Short name T662
Test name
Test status
Simulation time 67162663 ps
CPU time 1 seconds
Started Aug 18 05:49:37 PM PDT 24
Finished Aug 18 05:49:39 PM PDT 24
Peak memory 207332 kb
Host smart-fbb10b54-a51d-4008-ad4f-f2a1bdc8b46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998263003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3998263003
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2193228514
Short name T946
Test name
Test status
Simulation time 108172024 ps
CPU time 1.05 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:49:34 PM PDT 24
Peak memory 207032 kb
Host smart-cb2e820f-33f9-4016-8037-a057261e3b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193228514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2193228514
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3007331475
Short name T794
Test name
Test status
Simulation time 910036070 ps
CPU time 8.63 seconds
Started Aug 18 05:49:39 PM PDT 24
Finished Aug 18 05:49:48 PM PDT 24
Peak memory 232808 kb
Host smart-c5c39d45-215e-44a5-a249-c84cbe1cf24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007331475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3007331475
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.65135579
Short name T1023
Test name
Test status
Simulation time 24216472 ps
CPU time 0.74 seconds
Started Aug 18 05:49:40 PM PDT 24
Finished Aug 18 05:49:41 PM PDT 24
Peak memory 205408 kb
Host smart-0c7420f1-c9df-4047-8cf4-6373c7b606da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65135579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.65135579
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1240382102
Short name T298
Test name
Test status
Simulation time 32365979 ps
CPU time 2.14 seconds
Started Aug 18 05:49:51 PM PDT 24
Finished Aug 18 05:49:53 PM PDT 24
Peak memory 232492 kb
Host smart-8c8182fe-b593-4397-9c4a-53d561f55c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240382102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1240382102
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.73399653
Short name T614
Test name
Test status
Simulation time 43547971 ps
CPU time 0.74 seconds
Started Aug 18 05:49:43 PM PDT 24
Finished Aug 18 05:49:44 PM PDT 24
Peak memory 206900 kb
Host smart-78521dc6-afcb-4d17-a1f1-79954821a0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73399653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.73399653
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2468373644
Short name T215
Test name
Test status
Simulation time 89506927237 ps
CPU time 187.99 seconds
Started Aug 18 05:49:38 PM PDT 24
Finished Aug 18 05:52:46 PM PDT 24
Peak memory 255788 kb
Host smart-7c0395c4-dad7-4ac1-812a-0b71b1826b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468373644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2468373644
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2794791949
Short name T439
Test name
Test status
Simulation time 51337182697 ps
CPU time 96.93 seconds
Started Aug 18 05:49:37 PM PDT 24
Finished Aug 18 05:51:15 PM PDT 24
Peak memory 250824 kb
Host smart-ab1cef4e-98e9-4a3d-9db9-dc03ca71da0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794791949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2794791949
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1137735941
Short name T30
Test name
Test status
Simulation time 45321095674 ps
CPU time 100.82 seconds
Started Aug 18 05:49:42 PM PDT 24
Finished Aug 18 05:51:23 PM PDT 24
Peak memory 256308 kb
Host smart-38deeec8-0a02-4b99-be50-50200864e9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137735941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1137735941
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4085172999
Short name T270
Test name
Test status
Simulation time 6474151219 ps
CPU time 28.47 seconds
Started Aug 18 05:49:39 PM PDT 24
Finished Aug 18 05:50:08 PM PDT 24
Peak memory 232848 kb
Host smart-5ae3c2ea-d0bd-4799-94f5-253ee9a0fdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085172999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4085172999
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2206986361
Short name T866
Test name
Test status
Simulation time 14562809111 ps
CPU time 131.64 seconds
Started Aug 18 05:49:47 PM PDT 24
Finished Aug 18 05:51:58 PM PDT 24
Peak memory 251784 kb
Host smart-759b2a38-81be-4d94-a6f6-f29b238d6ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206986361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2206986361
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3592362769
Short name T808
Test name
Test status
Simulation time 2650281236 ps
CPU time 5.12 seconds
Started Aug 18 05:49:46 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 232840 kb
Host smart-0eb7d5ee-99cf-4eb6-9e59-8771ad04016c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592362769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3592362769
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4200632618
Short name T456
Test name
Test status
Simulation time 138682160 ps
CPU time 5.2 seconds
Started Aug 18 05:49:41 PM PDT 24
Finished Aug 18 05:49:46 PM PDT 24
Peak memory 233020 kb
Host smart-8cd07154-78ea-4176-bb9d-c3b27a0060ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200632618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4200632618
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1377662289
Short name T890
Test name
Test status
Simulation time 29161898 ps
CPU time 1 seconds
Started Aug 18 05:49:44 PM PDT 24
Finished Aug 18 05:49:45 PM PDT 24
Peak memory 216688 kb
Host smart-7285cc4b-a5c4-4078-997c-aea18c405290
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377662289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1377662289
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4287566416
Short name T949
Test name
Test status
Simulation time 1309678446 ps
CPU time 4.73 seconds
Started Aug 18 05:49:38 PM PDT 24
Finished Aug 18 05:49:43 PM PDT 24
Peak memory 224628 kb
Host smart-56f435b0-31dc-46a1-b385-f64700e774bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287566416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4287566416
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.963041622
Short name T174
Test name
Test status
Simulation time 48693281929 ps
CPU time 10.98 seconds
Started Aug 18 05:49:40 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 224684 kb
Host smart-5430f780-ba6c-4e97-b5de-95aea8335bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963041622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.963041622
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2464140940
Short name T547
Test name
Test status
Simulation time 3128726097 ps
CPU time 13.31 seconds
Started Aug 18 05:49:50 PM PDT 24
Finished Aug 18 05:50:03 PM PDT 24
Peak memory 223180 kb
Host smart-ca87bdf1-9428-4a73-baf2-749b91128ced
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2464140940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2464140940
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.188171469
Short name T617
Test name
Test status
Simulation time 6386802569 ps
CPU time 11.35 seconds
Started Aug 18 05:49:38 PM PDT 24
Finished Aug 18 05:49:50 PM PDT 24
Peak memory 216448 kb
Host smart-340acd1b-fd95-43b7-a398-4015e235d495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188171469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.188171469
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1223603732
Short name T820
Test name
Test status
Simulation time 4317995459 ps
CPU time 8.83 seconds
Started Aug 18 05:49:39 PM PDT 24
Finished Aug 18 05:49:48 PM PDT 24
Peak memory 216488 kb
Host smart-dfa3775a-233a-48c6-be75-b94e564d1297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223603732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1223603732
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1369628957
Short name T774
Test name
Test status
Simulation time 49221360 ps
CPU time 0.83 seconds
Started Aug 18 05:49:40 PM PDT 24
Finished Aug 18 05:49:41 PM PDT 24
Peak memory 206864 kb
Host smart-e9c938e7-b3c8-407c-ab3f-3622ea8410ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369628957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1369628957
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.351937287
Short name T990
Test name
Test status
Simulation time 25335797 ps
CPU time 0.78 seconds
Started Aug 18 05:49:52 PM PDT 24
Finished Aug 18 05:49:53 PM PDT 24
Peak memory 206088 kb
Host smart-05c7fe52-ff85-49b9-8dac-557d086cda21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351937287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.351937287
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3459719763
Short name T704
Test name
Test status
Simulation time 1168380175 ps
CPU time 6.54 seconds
Started Aug 18 05:49:44 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 232900 kb
Host smart-79cab518-bbe7-474d-885e-24aa482b0deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459719763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3459719763
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1792407038
Short name T589
Test name
Test status
Simulation time 92117287 ps
CPU time 0.75 seconds
Started Aug 18 05:49:40 PM PDT 24
Finished Aug 18 05:49:41 PM PDT 24
Peak memory 204952 kb
Host smart-aee399cc-386c-40af-ae93-54bd56e8a03e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792407038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1792407038
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4125075541
Short name T958
Test name
Test status
Simulation time 799824962 ps
CPU time 5.86 seconds
Started Aug 18 05:49:45 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 232728 kb
Host smart-671a8e73-9957-4304-9a73-b6d1c6ca7945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125075541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4125075541
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3922336304
Short name T514
Test name
Test status
Simulation time 28951695 ps
CPU time 0.72 seconds
Started Aug 18 05:49:40 PM PDT 24
Finished Aug 18 05:49:41 PM PDT 24
Peak memory 205532 kb
Host smart-e2506731-fb21-4574-a4dd-469a04d4c620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922336304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3922336304
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2555367276
Short name T886
Test name
Test status
Simulation time 7062887363 ps
CPU time 30.88 seconds
Started Aug 18 05:49:45 PM PDT 24
Finished Aug 18 05:50:16 PM PDT 24
Peak memory 241188 kb
Host smart-86d2e669-efb6-478f-96b1-874dd714c20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555367276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2555367276
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.4112557675
Short name T260
Test name
Test status
Simulation time 108677137316 ps
CPU time 214.75 seconds
Started Aug 18 05:49:47 PM PDT 24
Finished Aug 18 05:53:22 PM PDT 24
Peak memory 251992 kb
Host smart-de4540f6-eda7-458c-bab4-abcd22fcf19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112557675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.4112557675
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2870216068
Short name T212
Test name
Test status
Simulation time 232975250852 ps
CPU time 185.23 seconds
Started Aug 18 05:49:47 PM PDT 24
Finished Aug 18 05:52:52 PM PDT 24
Peak memory 250704 kb
Host smart-f4da284f-8977-4541-aca8-b88e10e3fdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870216068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2870216068
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1645606738
Short name T837
Test name
Test status
Simulation time 20294332358 ps
CPU time 44.42 seconds
Started Aug 18 05:49:44 PM PDT 24
Finished Aug 18 05:50:29 PM PDT 24
Peak memory 249320 kb
Host smart-887227c3-90f9-47af-bc73-249b557cf7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645606738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1645606738
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3244566587
Short name T611
Test name
Test status
Simulation time 986073030 ps
CPU time 9.37 seconds
Started Aug 18 05:49:50 PM PDT 24
Finished Aug 18 05:50:00 PM PDT 24
Peak memory 224672 kb
Host smart-62617769-7f64-4222-8bdb-9df5f67eb8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244566587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3244566587
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3673680236
Short name T600
Test name
Test status
Simulation time 4073992772 ps
CPU time 12.23 seconds
Started Aug 18 05:49:39 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 232868 kb
Host smart-8f5185f0-c248-44ff-b286-c811d0d161e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673680236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3673680236
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2421608819
Short name T748
Test name
Test status
Simulation time 399865688 ps
CPU time 3.68 seconds
Started Aug 18 05:49:39 PM PDT 24
Finished Aug 18 05:49:43 PM PDT 24
Peak memory 232808 kb
Host smart-0827fd2a-c90b-40d4-bf03-9590f91d3f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421608819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2421608819
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3364119164
Short name T821
Test name
Test status
Simulation time 528271920 ps
CPU time 1.03 seconds
Started Aug 18 05:49:41 PM PDT 24
Finished Aug 18 05:49:42 PM PDT 24
Peak memory 216712 kb
Host smart-e3e37b42-ea1e-410c-93ac-aa111f193196
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364119164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3364119164
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.103861843
Short name T777
Test name
Test status
Simulation time 5917032580 ps
CPU time 7.95 seconds
Started Aug 18 05:49:41 PM PDT 24
Finished Aug 18 05:49:50 PM PDT 24
Peak memory 224704 kb
Host smart-98390880-8ed0-4470-b757-31c9d5af7cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103861843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.103861843
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1366929396
Short name T503
Test name
Test status
Simulation time 31269294 ps
CPU time 2.2 seconds
Started Aug 18 05:49:57 PM PDT 24
Finished Aug 18 05:50:00 PM PDT 24
Peak memory 232504 kb
Host smart-42865b52-49f3-4df1-ab38-e8331fc39e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366929396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1366929396
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3014370698
Short name T325
Test name
Test status
Simulation time 751390934 ps
CPU time 5.3 seconds
Started Aug 18 05:49:39 PM PDT 24
Finished Aug 18 05:49:44 PM PDT 24
Peak memory 220668 kb
Host smart-7bf1695d-29df-437a-a743-a924ccbb5e32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3014370698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3014370698
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1546447127
Short name T316
Test name
Test status
Simulation time 1132956486 ps
CPU time 7.28 seconds
Started Aug 18 05:49:47 PM PDT 24
Finished Aug 18 05:49:54 PM PDT 24
Peak memory 216420 kb
Host smart-681d9823-e44f-4935-9636-88e8abbabe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546447127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1546447127
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.575279657
Short name T688
Test name
Test status
Simulation time 4867510746 ps
CPU time 16.2 seconds
Started Aug 18 05:49:46 PM PDT 24
Finished Aug 18 05:50:02 PM PDT 24
Peak memory 216436 kb
Host smart-58caa045-e05d-46cb-bb70-4d6f86805267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575279657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.575279657
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2215842789
Short name T560
Test name
Test status
Simulation time 54011436 ps
CPU time 1.08 seconds
Started Aug 18 05:49:40 PM PDT 24
Finished Aug 18 05:49:42 PM PDT 24
Peak memory 207756 kb
Host smart-3333e057-3177-4948-8d34-b14b2ee0df5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215842789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2215842789
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.825362557
Short name T763
Test name
Test status
Simulation time 16517074 ps
CPU time 0.72 seconds
Started Aug 18 05:49:40 PM PDT 24
Finished Aug 18 05:49:41 PM PDT 24
Peak memory 206056 kb
Host smart-bf50e85f-7180-47b5-a357-0c0fbc84a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825362557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.825362557
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3814963308
Short name T51
Test name
Test status
Simulation time 480707444 ps
CPU time 3.88 seconds
Started Aug 18 05:49:41 PM PDT 24
Finished Aug 18 05:49:45 PM PDT 24
Peak memory 232836 kb
Host smart-5f43d217-7e22-40e9-b7b0-343c69b2e0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814963308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3814963308
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3254023712
Short name T942
Test name
Test status
Simulation time 14412608 ps
CPU time 0.74 seconds
Started Aug 18 05:49:49 PM PDT 24
Finished Aug 18 05:49:50 PM PDT 24
Peak memory 204880 kb
Host smart-da5a28f1-8c43-4fbe-acf9-75f093401297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254023712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3254023712
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.142084690
Short name T368
Test name
Test status
Simulation time 170279264 ps
CPU time 3.31 seconds
Started Aug 18 05:49:49 PM PDT 24
Finished Aug 18 05:49:53 PM PDT 24
Peak memory 224648 kb
Host smart-83cf58f0-b99f-46e2-b885-7ae17a5adb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142084690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.142084690
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3062087763
Short name T571
Test name
Test status
Simulation time 17036643 ps
CPU time 0.74 seconds
Started Aug 18 05:49:42 PM PDT 24
Finished Aug 18 05:49:43 PM PDT 24
Peak memory 206580 kb
Host smart-81443f3e-f145-4dc6-bdcd-f80386db6927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062087763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3062087763
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.743918683
Short name T675
Test name
Test status
Simulation time 115753442770 ps
CPU time 208.19 seconds
Started Aug 18 05:49:53 PM PDT 24
Finished Aug 18 05:53:21 PM PDT 24
Peak memory 252132 kb
Host smart-f806f99d-5b5c-4f4a-9ba5-9f10f320211f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743918683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.743918683
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2986933942
Short name T171
Test name
Test status
Simulation time 51571660587 ps
CPU time 347.58 seconds
Started Aug 18 05:49:47 PM PDT 24
Finished Aug 18 05:55:34 PM PDT 24
Peak memory 257512 kb
Host smart-1d5b9622-8388-44e7-9a38-90e8f7a6efa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986933942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2986933942
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2843673729
Short name T499
Test name
Test status
Simulation time 20514588294 ps
CPU time 171.13 seconds
Started Aug 18 05:49:50 PM PDT 24
Finished Aug 18 05:52:41 PM PDT 24
Peak memory 251540 kb
Host smart-24e7bb47-af99-458a-90d8-64ef5b71790c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843673729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2843673729
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1816185135
Short name T333
Test name
Test status
Simulation time 77891378 ps
CPU time 3.47 seconds
Started Aug 18 05:49:48 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 232812 kb
Host smart-19ed0d26-ea69-4494-a485-7cbe19aa7e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816185135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1816185135
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2292743999
Short name T418
Test name
Test status
Simulation time 9438450278 ps
CPU time 86.44 seconds
Started Aug 18 05:49:48 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 241120 kb
Host smart-4ba38dca-ce32-4305-9ee3-900eaa3c972c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292743999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2292743999
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2918769952
Short name T334
Test name
Test status
Simulation time 190488307 ps
CPU time 5.18 seconds
Started Aug 18 05:49:47 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 232836 kb
Host smart-12d399d8-035d-4007-93ac-b96c7e154509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918769952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2918769952
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2691272040
Short name T903
Test name
Test status
Simulation time 4098396891 ps
CPU time 28.91 seconds
Started Aug 18 05:49:52 PM PDT 24
Finished Aug 18 05:50:21 PM PDT 24
Peak memory 232844 kb
Host smart-cca232ba-024b-4a8a-ab57-42cdd1afc603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691272040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2691272040
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3875587882
Short name T929
Test name
Test status
Simulation time 56470737 ps
CPU time 1.02 seconds
Started Aug 18 05:49:39 PM PDT 24
Finished Aug 18 05:49:40 PM PDT 24
Peak memory 217916 kb
Host smart-17d64bd4-4f8a-44d7-bba8-25f9cc98ddf7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875587882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3875587882
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1829911109
Short name T234
Test name
Test status
Simulation time 9210096000 ps
CPU time 9.08 seconds
Started Aug 18 05:49:51 PM PDT 24
Finished Aug 18 05:50:00 PM PDT 24
Peak memory 224728 kb
Host smart-d2e11173-8001-4c90-b247-e36213432823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829911109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1829911109
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2576469079
Short name T651
Test name
Test status
Simulation time 123602241 ps
CPU time 4.95 seconds
Started Aug 18 05:49:45 PM PDT 24
Finished Aug 18 05:49:50 PM PDT 24
Peak memory 232888 kb
Host smart-ea4a5f08-def3-4b06-a277-41b1a41e9e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576469079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2576469079
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1038418642
Short name T927
Test name
Test status
Simulation time 2797555238 ps
CPU time 9.23 seconds
Started Aug 18 05:49:49 PM PDT 24
Finished Aug 18 05:49:59 PM PDT 24
Peak memory 223268 kb
Host smart-ff493675-9f67-4921-9afb-08ffb17f8f97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1038418642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1038418642
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.753056731
Short name T142
Test name
Test status
Simulation time 36598220 ps
CPU time 0.9 seconds
Started Aug 18 05:49:50 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 206580 kb
Host smart-98a4b4b1-277f-42cc-ba00-bdfb499cadfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753056731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.753056731
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1577947767
Short name T666
Test name
Test status
Simulation time 3701884008 ps
CPU time 11.98 seconds
Started Aug 18 05:49:51 PM PDT 24
Finished Aug 18 05:50:03 PM PDT 24
Peak memory 216528 kb
Host smart-9d5e5f2f-fa66-4eaf-86e7-13a097aaa010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577947767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1577947767
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1479943835
Short name T795
Test name
Test status
Simulation time 2420673018 ps
CPU time 7.24 seconds
Started Aug 18 05:49:40 PM PDT 24
Finished Aug 18 05:49:47 PM PDT 24
Peak memory 216484 kb
Host smart-835c801c-3508-4314-b2f3-e0735bd6608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479943835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1479943835
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3707492863
Short name T288
Test name
Test status
Simulation time 662288339 ps
CPU time 11.52 seconds
Started Aug 18 05:49:51 PM PDT 24
Finished Aug 18 05:50:03 PM PDT 24
Peak memory 216412 kb
Host smart-a49fa03b-3458-40bd-b09e-75156f17f6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707492863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3707492863
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1576331168
Short name T749
Test name
Test status
Simulation time 61465457 ps
CPU time 0.9 seconds
Started Aug 18 05:49:44 PM PDT 24
Finished Aug 18 05:49:45 PM PDT 24
Peak memory 206012 kb
Host smart-2d898f77-6ca4-4d7b-a518-75793b652b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576331168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1576331168
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1370317443
Short name T209
Test name
Test status
Simulation time 164295946 ps
CPU time 2.45 seconds
Started Aug 18 05:49:40 PM PDT 24
Finished Aug 18 05:49:42 PM PDT 24
Peak memory 224608 kb
Host smart-70c1ff9b-5017-4cad-b6ae-d63eef4b9d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370317443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1370317443
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.669141036
Short name T66
Test name
Test status
Simulation time 19876423 ps
CPU time 0.7 seconds
Started Aug 18 05:49:50 PM PDT 24
Finished Aug 18 05:49:50 PM PDT 24
Peak memory 204920 kb
Host smart-9564a973-c340-43ce-83db-597ed69db3f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669141036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.669141036
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2302263423
Short name T700
Test name
Test status
Simulation time 549157506 ps
CPU time 2.35 seconds
Started Aug 18 05:49:49 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 224620 kb
Host smart-76abc83e-8391-498d-a87b-615eae9dfebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302263423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2302263423
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2108763046
Short name T113
Test name
Test status
Simulation time 19678078 ps
CPU time 0.8 seconds
Started Aug 18 05:49:46 PM PDT 24
Finished Aug 18 05:49:47 PM PDT 24
Peak memory 206868 kb
Host smart-487c8ada-aee8-4aff-92b6-680b98b074e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108763046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2108763046
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1828092602
Short name T216
Test name
Test status
Simulation time 58550096076 ps
CPU time 110.29 seconds
Started Aug 18 05:49:52 PM PDT 24
Finished Aug 18 05:51:42 PM PDT 24
Peak memory 252972 kb
Host smart-6ee766d9-f444-49b6-83aa-84917b42afd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828092602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1828092602
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1612661644
Short name T798
Test name
Test status
Simulation time 4702502328 ps
CPU time 68.41 seconds
Started Aug 18 05:49:52 PM PDT 24
Finished Aug 18 05:51:01 PM PDT 24
Peak memory 249368 kb
Host smart-e6a14847-2fc2-496f-996e-2b6db6d3d8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612661644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1612661644
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.761708311
Short name T258
Test name
Test status
Simulation time 17221867120 ps
CPU time 119.32 seconds
Started Aug 18 05:49:48 PM PDT 24
Finished Aug 18 05:51:47 PM PDT 24
Peak memory 264520 kb
Host smart-d212fed8-a2e7-47bc-a538-3d654d4fe57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761708311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.761708311
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2522841884
Short name T781
Test name
Test status
Simulation time 105921250 ps
CPU time 2.94 seconds
Started Aug 18 05:49:48 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 232840 kb
Host smart-7a4bcdf3-2070-4dc2-a154-5f8cdba83c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522841884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2522841884
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.256037283
Short name T994
Test name
Test status
Simulation time 565288395 ps
CPU time 4.23 seconds
Started Aug 18 05:49:47 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 224700 kb
Host smart-84f1e6c5-3c5f-48a5-a8f9-f3c557ac64a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256037283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.256037283
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.52895482
Short name T985
Test name
Test status
Simulation time 4931731937 ps
CPU time 18.57 seconds
Started Aug 18 05:49:48 PM PDT 24
Finished Aug 18 05:50:06 PM PDT 24
Peak memory 232924 kb
Host smart-61794018-c60a-4783-9796-f2fa81ff5c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52895482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.52895482
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1007961422
Short name T34
Test name
Test status
Simulation time 17223388 ps
CPU time 1.09 seconds
Started Aug 18 05:49:53 PM PDT 24
Finished Aug 18 05:49:54 PM PDT 24
Peak memory 216692 kb
Host smart-d78521be-1260-497c-a4ac-3f9013af24d5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007961422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1007961422
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1266039820
Short name T515
Test name
Test status
Simulation time 30118060 ps
CPU time 2.55 seconds
Started Aug 18 05:49:49 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 232436 kb
Host smart-65e0bd0f-4bba-4210-9a8d-47c21d834817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266039820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1266039820
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.973096040
Short name T410
Test name
Test status
Simulation time 5522662406 ps
CPU time 5.86 seconds
Started Aug 18 05:49:49 PM PDT 24
Finished Aug 18 05:49:55 PM PDT 24
Peak memory 232876 kb
Host smart-dd24df2d-168e-413c-9323-12beae705ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973096040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.973096040
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1667628333
Short name T564
Test name
Test status
Simulation time 92443799 ps
CPU time 3.81 seconds
Started Aug 18 05:49:48 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 220600 kb
Host smart-651c3e15-a3c0-4a74-85dc-364c7b631902
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1667628333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1667628333
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1898784007
Short name T9
Test name
Test status
Simulation time 22668099175 ps
CPU time 93.11 seconds
Started Aug 18 05:49:48 PM PDT 24
Finished Aug 18 05:51:22 PM PDT 24
Peak memory 251752 kb
Host smart-bd3cc3f0-353d-45b7-8c72-f421d613957a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898784007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1898784007
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4028460458
Short name T332
Test name
Test status
Simulation time 1236943068 ps
CPU time 16.37 seconds
Started Aug 18 05:49:48 PM PDT 24
Finished Aug 18 05:50:05 PM PDT 24
Peak memory 216612 kb
Host smart-572784c6-bfcf-4859-a8b5-47dbf7986ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028460458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4028460458
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2343702910
Short name T959
Test name
Test status
Simulation time 4288465321 ps
CPU time 10.6 seconds
Started Aug 18 05:49:49 PM PDT 24
Finished Aug 18 05:50:00 PM PDT 24
Peak memory 216460 kb
Host smart-b413ddfb-eb37-4676-aa60-18977d35eaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343702910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2343702910
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2939635999
Short name T419
Test name
Test status
Simulation time 779081812 ps
CPU time 2.33 seconds
Started Aug 18 05:49:49 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 216448 kb
Host smart-b668fa22-aab6-40e2-830b-9fbbdf08fcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939635999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2939635999
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4091461866
Short name T385
Test name
Test status
Simulation time 118039395 ps
CPU time 0.82 seconds
Started Aug 18 05:49:49 PM PDT 24
Finished Aug 18 05:49:50 PM PDT 24
Peak memory 206080 kb
Host smart-5a1bfd56-8e29-4ade-bfe8-7fe8740d0653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091461866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4091461866
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4158255293
Short name T41
Test name
Test status
Simulation time 3090521557 ps
CPU time 5.63 seconds
Started Aug 18 05:49:48 PM PDT 24
Finished Aug 18 05:49:54 PM PDT 24
Peak memory 224696 kb
Host smart-c319e830-42a7-4ae3-aed6-7174e9b94b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158255293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4158255293
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.890695472
Short name T367
Test name
Test status
Simulation time 44156089 ps
CPU time 0.7 seconds
Started Aug 18 05:49:55 PM PDT 24
Finished Aug 18 05:49:56 PM PDT 24
Peak memory 204884 kb
Host smart-2dd497cf-c646-4b9a-b62c-a1263fede4af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890695472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.890695472
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2446026718
Short name T351
Test name
Test status
Simulation time 674050243 ps
CPU time 3.48 seconds
Started Aug 18 05:49:47 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 224620 kb
Host smart-0326401f-9bab-4a5e-9619-b7c10507a599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446026718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2446026718
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2476690190
Short name T15
Test name
Test status
Simulation time 16989309 ps
CPU time 0.79 seconds
Started Aug 18 05:49:46 PM PDT 24
Finished Aug 18 05:49:47 PM PDT 24
Peak memory 206580 kb
Host smart-6c0f789b-a03b-437c-aaac-45f94eecd7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476690190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2476690190
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3957734817
Short name T664
Test name
Test status
Simulation time 13736482316 ps
CPU time 127.07 seconds
Started Aug 18 05:49:47 PM PDT 24
Finished Aug 18 05:51:54 PM PDT 24
Peak memory 252684 kb
Host smart-a3fd121b-0328-4726-84cc-30c596b74726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957734817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3957734817
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2321844156
Short name T232
Test name
Test status
Simulation time 3480282911 ps
CPU time 83.89 seconds
Started Aug 18 05:50:02 PM PDT 24
Finished Aug 18 05:51:26 PM PDT 24
Peak memory 264908 kb
Host smart-9f8f7b95-ed86-474d-95a0-4638471d3a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321844156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2321844156
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1528493223
Short name T987
Test name
Test status
Simulation time 26755925855 ps
CPU time 96.51 seconds
Started Aug 18 05:50:01 PM PDT 24
Finished Aug 18 05:51:38 PM PDT 24
Peak memory 255492 kb
Host smart-a6826be7-4aed-4d02-8be2-ef11871f8828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528493223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1528493223
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.388905877
Short name T807
Test name
Test status
Simulation time 1937096672 ps
CPU time 8.11 seconds
Started Aug 18 05:49:50 PM PDT 24
Finished Aug 18 05:49:58 PM PDT 24
Peak memory 224668 kb
Host smart-2dbc2f6d-4dac-4ffa-9470-14536fdbc34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388905877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.388905877
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3645528657
Short name T44
Test name
Test status
Simulation time 2787134878 ps
CPU time 19.38 seconds
Started Aug 18 05:49:50 PM PDT 24
Finished Aug 18 05:50:09 PM PDT 24
Peak memory 241128 kb
Host smart-805f727d-0703-48c3-8d56-52aa6f8a79df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645528657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3645528657
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2847170860
Short name T189
Test name
Test status
Simulation time 98163045 ps
CPU time 3.5 seconds
Started Aug 18 05:49:46 PM PDT 24
Finished Aug 18 05:49:50 PM PDT 24
Peak memory 232796 kb
Host smart-92358967-4fa7-4239-ada5-8d70a8e61af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847170860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2847170860
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2896879419
Short name T921
Test name
Test status
Simulation time 45301907 ps
CPU time 2.68 seconds
Started Aug 18 05:49:49 PM PDT 24
Finished Aug 18 05:49:51 PM PDT 24
Peak memory 232832 kb
Host smart-5aa60e87-58e9-46fd-ac95-d184f6e66db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896879419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2896879419
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3091969580
Short name T449
Test name
Test status
Simulation time 52747635 ps
CPU time 1.02 seconds
Started Aug 18 05:49:51 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 217964 kb
Host smart-a3694f5b-1309-41c3-8514-f54df3135a87
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091969580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3091969580
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.624042749
Short name T1028
Test name
Test status
Simulation time 10816141366 ps
CPU time 10.37 seconds
Started Aug 18 05:49:50 PM PDT 24
Finished Aug 18 05:50:00 PM PDT 24
Peak memory 224608 kb
Host smart-a54a2ac8-e8e7-4501-b49a-69bf636b311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624042749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.624042749
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.711494484
Short name T692
Test name
Test status
Simulation time 1291026034 ps
CPU time 6.05 seconds
Started Aug 18 05:49:47 PM PDT 24
Finished Aug 18 05:49:53 PM PDT 24
Peak memory 232884 kb
Host smart-6fd5e9f8-f684-4e99-80d5-c8d4d4884d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711494484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.711494484
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.4267213325
Short name T13
Test name
Test status
Simulation time 484034852 ps
CPU time 5.52 seconds
Started Aug 18 05:49:50 PM PDT 24
Finished Aug 18 05:49:56 PM PDT 24
Peak memory 220304 kb
Host smart-464ec810-bf1e-48db-a0bc-eb409bf832db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4267213325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.4267213325
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3607128697
Short name T360
Test name
Test status
Simulation time 30195115615 ps
CPU time 90.9 seconds
Started Aug 18 05:49:55 PM PDT 24
Finished Aug 18 05:51:26 PM PDT 24
Peak memory 262888 kb
Host smart-6763268d-3aa0-4ed9-8194-ed2aa74e7ff4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607128697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3607128697
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.597942329
Short name T482
Test name
Test status
Simulation time 1606766466 ps
CPU time 7.79 seconds
Started Aug 18 05:49:50 PM PDT 24
Finished Aug 18 05:49:58 PM PDT 24
Peak memory 216436 kb
Host smart-c7571508-dc3a-4a00-afbe-4e0a20a1b207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597942329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.597942329
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2674653494
Short name T922
Test name
Test status
Simulation time 21810056839 ps
CPU time 12.83 seconds
Started Aug 18 05:49:46 PM PDT 24
Finished Aug 18 05:49:59 PM PDT 24
Peak memory 216532 kb
Host smart-ca6ab724-a91a-4ea3-88a1-6841c6eb702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674653494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2674653494
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1002182746
Short name T357
Test name
Test status
Simulation time 131258924 ps
CPU time 3.59 seconds
Started Aug 18 05:49:50 PM PDT 24
Finished Aug 18 05:49:53 PM PDT 24
Peak memory 216376 kb
Host smart-c88c87f4-c874-443e-a733-96fab18408ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002182746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1002182746
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.225826290
Short name T487
Test name
Test status
Simulation time 21557008 ps
CPU time 0.79 seconds
Started Aug 18 05:49:53 PM PDT 24
Finished Aug 18 05:49:54 PM PDT 24
Peak memory 206104 kb
Host smart-865bc84b-c0fc-4443-a57a-3de0f4399d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225826290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.225826290
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3240872786
Short name T681
Test name
Test status
Simulation time 1149268058 ps
CPU time 7.85 seconds
Started Aug 18 05:49:48 PM PDT 24
Finished Aug 18 05:49:56 PM PDT 24
Peak memory 224636 kb
Host smart-81b7b224-8b22-473a-9425-a15d048894c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240872786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3240872786
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1559819595
Short name T787
Test name
Test status
Simulation time 26514028 ps
CPU time 0.76 seconds
Started Aug 18 05:50:01 PM PDT 24
Finished Aug 18 05:50:02 PM PDT 24
Peak memory 205540 kb
Host smart-b9721fb3-ed1d-446c-8bf7-51649e49c8cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559819595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1559819595
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.201981353
Short name T923
Test name
Test status
Simulation time 47480923 ps
CPU time 2.7 seconds
Started Aug 18 05:49:56 PM PDT 24
Finished Aug 18 05:49:59 PM PDT 24
Peak memory 232868 kb
Host smart-e35200f1-3eb2-4a3f-a228-0e123254284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201981353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.201981353
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.873202317
Short name T991
Test name
Test status
Simulation time 80270554 ps
CPU time 0.73 seconds
Started Aug 18 05:49:55 PM PDT 24
Finished Aug 18 05:49:56 PM PDT 24
Peak memory 205552 kb
Host smart-8bf791ad-e9ff-4388-b5c8-9ad7b5541f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873202317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.873202317
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.429897158
Short name T327
Test name
Test status
Simulation time 68445198250 ps
CPU time 244.99 seconds
Started Aug 18 05:49:58 PM PDT 24
Finished Aug 18 05:54:03 PM PDT 24
Peak memory 255860 kb
Host smart-6d9cf06e-2a98-4e82-a9ec-661e1c58c8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429897158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.429897158
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3826960256
Short name T469
Test name
Test status
Simulation time 5140599834 ps
CPU time 76.49 seconds
Started Aug 18 05:49:55 PM PDT 24
Finished Aug 18 05:51:12 PM PDT 24
Peak memory 253152 kb
Host smart-42b03f9b-0eb9-4469-ada2-8cf1cc2fd655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826960256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3826960256
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.362334839
Short name T1000
Test name
Test status
Simulation time 39092963091 ps
CPU time 106.21 seconds
Started Aug 18 05:49:55 PM PDT 24
Finished Aug 18 05:51:42 PM PDT 24
Peak memory 252156 kb
Host smart-6a205093-edfd-4b68-8fcd-c3a39bdecb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362334839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.362334839
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3850958178
Short name T644
Test name
Test status
Simulation time 153921537596 ps
CPU time 255 seconds
Started Aug 18 05:49:57 PM PDT 24
Finished Aug 18 05:54:12 PM PDT 24
Peak memory 251108 kb
Host smart-6ac204c9-d5ab-45af-bacc-d836286164ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850958178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3850958178
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.737111382
Short name T580
Test name
Test status
Simulation time 600238846 ps
CPU time 4.78 seconds
Started Aug 18 05:49:57 PM PDT 24
Finished Aug 18 05:50:02 PM PDT 24
Peak memory 232868 kb
Host smart-306790c6-1763-4149-b041-8a083fd17ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737111382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.737111382
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2799465902
Short name T471
Test name
Test status
Simulation time 2419192228 ps
CPU time 26.16 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:31 PM PDT 24
Peak memory 224660 kb
Host smart-f4c4eccd-c2ff-4ec5-98bf-a24f0d245059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799465902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2799465902
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3219150327
Short name T944
Test name
Test status
Simulation time 54196192 ps
CPU time 1.01 seconds
Started Aug 18 05:49:59 PM PDT 24
Finished Aug 18 05:50:00 PM PDT 24
Peak memory 216668 kb
Host smart-18148f6c-a658-48f5-87c6-6ff54d9280b7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219150327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3219150327
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1151867387
Short name T454
Test name
Test status
Simulation time 3654305407 ps
CPU time 11.45 seconds
Started Aug 18 05:49:56 PM PDT 24
Finished Aug 18 05:50:08 PM PDT 24
Peak memory 232884 kb
Host smart-39635636-9c6b-4846-ac77-c6d316e2a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151867387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1151867387
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2290115179
Short name T895
Test name
Test status
Simulation time 589008736 ps
CPU time 3.35 seconds
Started Aug 18 05:49:56 PM PDT 24
Finished Aug 18 05:49:59 PM PDT 24
Peak memory 232876 kb
Host smart-d20bea18-85e6-472f-a2d5-38a8ced0fb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290115179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2290115179
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3626526305
Short name T702
Test name
Test status
Simulation time 176573546 ps
CPU time 4.24 seconds
Started Aug 18 05:50:01 PM PDT 24
Finished Aug 18 05:50:05 PM PDT 24
Peak memory 219316 kb
Host smart-51aef78c-a668-47c5-b99a-53796299abb4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3626526305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3626526305
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.375408675
Short name T441
Test name
Test status
Simulation time 45243157 ps
CPU time 0.97 seconds
Started Aug 18 05:49:58 PM PDT 24
Finished Aug 18 05:49:59 PM PDT 24
Peak memory 205528 kb
Host smart-a716712f-b229-4c3e-b62b-923b7693319d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375408675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.375408675
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.768822882
Short name T870
Test name
Test status
Simulation time 2727970093 ps
CPU time 20.69 seconds
Started Aug 18 05:49:59 PM PDT 24
Finished Aug 18 05:50:19 PM PDT 24
Peak memory 216544 kb
Host smart-721dc594-e768-46d4-91d4-0819e06463ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768822882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.768822882
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.775313448
Short name T607
Test name
Test status
Simulation time 7799215537 ps
CPU time 8.42 seconds
Started Aug 18 05:49:59 PM PDT 24
Finished Aug 18 05:50:08 PM PDT 24
Peak memory 216500 kb
Host smart-11911a4a-dac4-4917-85aa-1671babc6107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775313448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.775313448
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2874022920
Short name T715
Test name
Test status
Simulation time 91100629 ps
CPU time 0.9 seconds
Started Aug 18 05:50:02 PM PDT 24
Finished Aug 18 05:50:03 PM PDT 24
Peak memory 207144 kb
Host smart-613db766-e7b3-4a69-a99d-c9d58cbb005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874022920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2874022920
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.887388850
Short name T472
Test name
Test status
Simulation time 11038193 ps
CPU time 0.67 seconds
Started Aug 18 05:49:57 PM PDT 24
Finished Aug 18 05:49:58 PM PDT 24
Peak memory 205572 kb
Host smart-58cca2bc-3748-4ea4-a0aa-a8f63a1eca92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887388850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.887388850
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.674049340
Short name T437
Test name
Test status
Simulation time 61465000 ps
CPU time 2 seconds
Started Aug 18 05:49:55 PM PDT 24
Finished Aug 18 05:49:57 PM PDT 24
Peak memory 224616 kb
Host smart-f6157379-43b6-45f6-8562-58ccc1893ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674049340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.674049340
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.839290661
Short name T378
Test name
Test status
Simulation time 16023325 ps
CPU time 0.71 seconds
Started Aug 18 05:49:01 PM PDT 24
Finished Aug 18 05:49:02 PM PDT 24
Peak memory 205448 kb
Host smart-18d9168d-7ecc-428a-a51c-f69bdd530ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839290661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.839290661
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2737029850
Short name T669
Test name
Test status
Simulation time 418221527 ps
CPU time 5.63 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:49:09 PM PDT 24
Peak memory 232784 kb
Host smart-55f360c9-b9c9-4cb3-a244-6388c5605d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737029850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2737029850
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3152647506
Short name T859
Test name
Test status
Simulation time 12874723 ps
CPU time 0.77 seconds
Started Aug 18 05:49:00 PM PDT 24
Finished Aug 18 05:49:01 PM PDT 24
Peak memory 206580 kb
Host smart-ae7ad923-5331-4267-9e3e-d4d9d8c017ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152647506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3152647506
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1511487869
Short name T227
Test name
Test status
Simulation time 28793582555 ps
CPU time 55.67 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:50:00 PM PDT 24
Peak memory 241068 kb
Host smart-3c047430-c79e-4fb1-94b8-025de05be4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511487869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1511487869
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1715714485
Short name T658
Test name
Test status
Simulation time 4200549960 ps
CPU time 47.09 seconds
Started Aug 18 05:48:59 PM PDT 24
Finished Aug 18 05:49:46 PM PDT 24
Peak memory 232556 kb
Host smart-74094166-a680-4194-8e2b-f44e0580912b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715714485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1715714485
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2283963967
Short name T689
Test name
Test status
Simulation time 1164661566 ps
CPU time 19.58 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:23 PM PDT 24
Peak memory 240928 kb
Host smart-c753358f-9e9c-4017-bef3-84d41b4676d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283963967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2283963967
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2524764794
Short name T822
Test name
Test status
Simulation time 5644889201 ps
CPU time 42.57 seconds
Started Aug 18 05:49:01 PM PDT 24
Finished Aug 18 05:49:44 PM PDT 24
Peak memory 236952 kb
Host smart-e0e73dcc-3bbc-4d87-b19c-a782a955c945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524764794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2524764794
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2034712171
Short name T738
Test name
Test status
Simulation time 466885010 ps
CPU time 6.1 seconds
Started Aug 18 05:48:58 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 224564 kb
Host smart-0ac3a2ff-e370-418f-8a0b-c64490f576ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034712171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2034712171
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2303891436
Short name T206
Test name
Test status
Simulation time 5223253696 ps
CPU time 39.81 seconds
Started Aug 18 05:49:00 PM PDT 24
Finished Aug 18 05:49:40 PM PDT 24
Peak memory 224716 kb
Host smart-3e8a9a2f-6ff6-48fa-945a-a0f28f68ae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303891436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2303891436
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2664430120
Short name T717
Test name
Test status
Simulation time 52148121 ps
CPU time 1.01 seconds
Started Aug 18 05:48:58 PM PDT 24
Finished Aug 18 05:48:59 PM PDT 24
Peak memory 217940 kb
Host smart-043c2dc9-aba5-4107-964e-75a973ca0e26
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664430120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2664430120
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3427188769
Short name T995
Test name
Test status
Simulation time 3417502818 ps
CPU time 6.09 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:10 PM PDT 24
Peak memory 224656 kb
Host smart-4954bf4f-021d-4774-8b2f-c346949798d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427188769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3427188769
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1201219684
Short name T226
Test name
Test status
Simulation time 495182353 ps
CPU time 6.25 seconds
Started Aug 18 05:49:09 PM PDT 24
Finished Aug 18 05:49:15 PM PDT 24
Peak memory 240936 kb
Host smart-65ea7800-eff3-4bdf-ac45-29ee32f3ff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201219684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1201219684
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.130151653
Short name T739
Test name
Test status
Simulation time 180708767 ps
CPU time 4.07 seconds
Started Aug 18 05:49:00 PM PDT 24
Finished Aug 18 05:49:04 PM PDT 24
Peak memory 220688 kb
Host smart-39e64388-7759-40f5-b1a6-719d4323dbf6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=130151653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.130151653
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.294956011
Short name T56
Test name
Test status
Simulation time 106569362 ps
CPU time 0.96 seconds
Started Aug 18 05:49:09 PM PDT 24
Finished Aug 18 05:49:10 PM PDT 24
Peak memory 235560 kb
Host smart-88c12619-f808-4f18-bfa1-96aa1b9ce07c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294956011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.294956011
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.75916244
Short name T377
Test name
Test status
Simulation time 159753592 ps
CPU time 0.98 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 206708 kb
Host smart-bb7ba835-1b1b-4756-88af-8d2365bbcbff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75916244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_
all.75916244
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1320709402
Short name T381
Test name
Test status
Simulation time 2010116029 ps
CPU time 27.65 seconds
Started Aug 18 05:49:09 PM PDT 24
Finished Aug 18 05:49:37 PM PDT 24
Peak memory 219768 kb
Host smart-14d132de-93fe-4009-8611-e762aee3185c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320709402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1320709402
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3531689118
Short name T422
Test name
Test status
Simulation time 4163035960 ps
CPU time 5.42 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:49:08 PM PDT 24
Peak memory 216528 kb
Host smart-a9bfe15f-b05f-4146-8776-0cbc2e39a62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531689118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3531689118
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2860224442
Short name T907
Test name
Test status
Simulation time 22499296 ps
CPU time 0.68 seconds
Started Aug 18 05:48:59 PM PDT 24
Finished Aug 18 05:49:00 PM PDT 24
Peak memory 205612 kb
Host smart-6a5f1021-a1d3-4279-b11b-8fcffed0994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860224442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2860224442
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3501842138
Short name T703
Test name
Test status
Simulation time 11863816 ps
CPU time 0.69 seconds
Started Aug 18 05:49:12 PM PDT 24
Finished Aug 18 05:49:13 PM PDT 24
Peak memory 205608 kb
Host smart-e26dd3b7-2cf8-4859-916d-4a5f13dae03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501842138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3501842138
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1950891361
Short name T434
Test name
Test status
Simulation time 4475937988 ps
CPU time 12.59 seconds
Started Aug 18 05:49:01 PM PDT 24
Finished Aug 18 05:49:14 PM PDT 24
Peak memory 240876 kb
Host smart-a59e8e23-1ff0-4eef-8a27-0eb6655b4d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950891361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1950891361
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1862259309
Short name T356
Test name
Test status
Simulation time 16079610 ps
CPU time 0.65 seconds
Started Aug 18 05:50:02 PM PDT 24
Finished Aug 18 05:50:02 PM PDT 24
Peak memory 205440 kb
Host smart-b4d426ac-b449-4e66-bcda-a7b905bde7d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862259309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1862259309
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.313037298
Short name T376
Test name
Test status
Simulation time 531063712 ps
CPU time 8.01 seconds
Started Aug 18 05:49:58 PM PDT 24
Finished Aug 18 05:50:06 PM PDT 24
Peak memory 232752 kb
Host smart-bbcf2508-1fb9-4c55-ae5f-ea799a69c971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313037298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.313037298
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3858257723
Short name T838
Test name
Test status
Simulation time 21700438 ps
CPU time 0.81 seconds
Started Aug 18 05:49:56 PM PDT 24
Finished Aug 18 05:49:56 PM PDT 24
Peak memory 206548 kb
Host smart-3650670a-6f5d-42ea-bde7-f7d4a1f983ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858257723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3858257723
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.4099086845
Short name T936
Test name
Test status
Simulation time 9264403488 ps
CPU time 87.83 seconds
Started Aug 18 05:49:58 PM PDT 24
Finished Aug 18 05:51:26 PM PDT 24
Peak memory 249864 kb
Host smart-c45db6c0-2676-426c-83c7-28b784ffe77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099086845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.4099086845
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3134956649
Short name T475
Test name
Test status
Simulation time 67985562496 ps
CPU time 160.76 seconds
Started Aug 18 05:49:57 PM PDT 24
Finished Aug 18 05:52:38 PM PDT 24
Peak memory 249388 kb
Host smart-0784dd03-5770-4f53-9425-1cf799b75e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134956649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3134956649
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1470164911
Short name T183
Test name
Test status
Simulation time 11065871222 ps
CPU time 43.03 seconds
Started Aug 18 05:50:05 PM PDT 24
Finished Aug 18 05:50:48 PM PDT 24
Peak memory 224724 kb
Host smart-e67a4176-2a14-4ff8-b921-35f21d5ef268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470164911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1470164911
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1185238231
Short name T428
Test name
Test status
Simulation time 1528947558 ps
CPU time 18.55 seconds
Started Aug 18 05:50:02 PM PDT 24
Finished Aug 18 05:50:20 PM PDT 24
Peak memory 236568 kb
Host smart-3dd54b5a-fcb8-41a3-a607-53f6129111f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185238231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1185238231
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2130653552
Short name T771
Test name
Test status
Simulation time 5486122422 ps
CPU time 18.27 seconds
Started Aug 18 05:49:54 PM PDT 24
Finished Aug 18 05:50:13 PM PDT 24
Peak memory 224640 kb
Host smart-df3b601f-611c-4777-8701-b4fd9e3baab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130653552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2130653552
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.933952633
Short name T12
Test name
Test status
Simulation time 3667414344 ps
CPU time 35.23 seconds
Started Aug 18 05:49:56 PM PDT 24
Finished Aug 18 05:50:32 PM PDT 24
Peak memory 224720 kb
Host smart-927e077f-f5a5-4998-9b1f-c0e69699101e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933952633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.933952633
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1852076290
Short name T259
Test name
Test status
Simulation time 32381749281 ps
CPU time 21.75 seconds
Started Aug 18 05:49:57 PM PDT 24
Finished Aug 18 05:50:19 PM PDT 24
Peak memory 224720 kb
Host smart-c43f25a8-20dc-4d4b-a71e-fbdf5b42010b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852076290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1852076290
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3847352933
Short name T45
Test name
Test status
Simulation time 10998697780 ps
CPU time 14.04 seconds
Started Aug 18 05:49:58 PM PDT 24
Finished Aug 18 05:50:12 PM PDT 24
Peak memory 248980 kb
Host smart-13fe231f-c82a-47a7-b284-511c65cd806e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847352933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3847352933
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3967964572
Short name T598
Test name
Test status
Simulation time 261617266 ps
CPU time 5.07 seconds
Started Aug 18 05:49:58 PM PDT 24
Finished Aug 18 05:50:03 PM PDT 24
Peak memory 223156 kb
Host smart-6a1e5753-b94a-461d-a951-2fc7772e858e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3967964572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3967964572
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2415174926
Short name T190
Test name
Test status
Simulation time 6747416136 ps
CPU time 102.02 seconds
Started Aug 18 05:50:05 PM PDT 24
Finished Aug 18 05:51:47 PM PDT 24
Peak memory 258572 kb
Host smart-76602aed-8037-408c-b901-245b31a0b8c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415174926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2415174926
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2028733464
Short name T496
Test name
Test status
Simulation time 1639747138 ps
CPU time 9.49 seconds
Started Aug 18 05:49:55 PM PDT 24
Finished Aug 18 05:50:05 PM PDT 24
Peak memory 216460 kb
Host smart-8231fb9a-5c55-460a-a13d-52b910c09194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028733464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2028733464
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.46678014
Short name T511
Test name
Test status
Simulation time 17884922011 ps
CPU time 12.95 seconds
Started Aug 18 05:49:59 PM PDT 24
Finished Aug 18 05:50:12 PM PDT 24
Peak memory 216560 kb
Host smart-cd09eb60-6654-47b2-acd2-b9837ea9bf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46678014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.46678014
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1979268751
Short name T1021
Test name
Test status
Simulation time 300930567 ps
CPU time 1.32 seconds
Started Aug 18 05:49:58 PM PDT 24
Finished Aug 18 05:49:59 PM PDT 24
Peak memory 216340 kb
Host smart-b94b4438-fc59-4495-bf9d-d7bb896c1a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979268751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1979268751
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3286981960
Short name T48
Test name
Test status
Simulation time 107961938 ps
CPU time 0.88 seconds
Started Aug 18 05:49:56 PM PDT 24
Finished Aug 18 05:49:57 PM PDT 24
Peak memory 207104 kb
Host smart-8a2ff512-0670-4d5a-81bb-5f751523d6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286981960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3286981960
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1507528615
Short name T369
Test name
Test status
Simulation time 527287254 ps
CPU time 6.42 seconds
Started Aug 18 05:49:56 PM PDT 24
Finished Aug 18 05:50:02 PM PDT 24
Peak memory 234204 kb
Host smart-aa5a7ff1-20a8-43a1-9dd1-c9a67d512d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507528615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1507528615
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1795425035
Short name T400
Test name
Test status
Simulation time 54991359 ps
CPU time 0.73 seconds
Started Aug 18 05:50:11 PM PDT 24
Finished Aug 18 05:50:12 PM PDT 24
Peak memory 205436 kb
Host smart-3d5a61b5-ac19-4cf6-a892-2c9c9c3595a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795425035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1795425035
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1258994387
Short name T3
Test name
Test status
Simulation time 245980778 ps
CPU time 4.1 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:09 PM PDT 24
Peak memory 232796 kb
Host smart-a23ea6d6-1b2e-4e48-a76d-f39de182d049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258994387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1258994387
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3217508979
Short name T586
Test name
Test status
Simulation time 19680951 ps
CPU time 0.72 seconds
Started Aug 18 05:50:01 PM PDT 24
Finished Aug 18 05:50:02 PM PDT 24
Peak memory 205492 kb
Host smart-54d0effe-523f-424f-9bbf-681703936e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217508979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3217508979
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3943086733
Short name T641
Test name
Test status
Simulation time 61188002425 ps
CPU time 226.44 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:53:51 PM PDT 24
Peak memory 249280 kb
Host smart-ff599bac-8579-4374-a6c8-f046df13d69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943086733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3943086733
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2164199699
Short name T1024
Test name
Test status
Simulation time 4628917580 ps
CPU time 23.15 seconds
Started Aug 18 05:50:05 PM PDT 24
Finished Aug 18 05:50:29 PM PDT 24
Peak memory 234940 kb
Host smart-6e3e53e6-1b40-417c-8eb0-492bd5d2a5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164199699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2164199699
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.268600088
Short name T115
Test name
Test status
Simulation time 10907572689 ps
CPU time 47.25 seconds
Started Aug 18 05:50:03 PM PDT 24
Finished Aug 18 05:50:50 PM PDT 24
Peak memory 236392 kb
Host smart-328bea92-eff9-4b46-bc34-c5620c3f9f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268600088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.268600088
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3036927676
Short name T279
Test name
Test status
Simulation time 9333732362 ps
CPU time 37.06 seconds
Started Aug 18 05:50:06 PM PDT 24
Finished Aug 18 05:50:44 PM PDT 24
Peak memory 232896 kb
Host smart-8c41e498-4c6f-44ab-8b24-6951fae4a6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036927676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3036927676
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1240543980
Short name T910
Test name
Test status
Simulation time 13249007833 ps
CPU time 98.03 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:51:43 PM PDT 24
Peak memory 241040 kb
Host smart-27906a8e-c00c-4bb5-bfaf-605f35807e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240543980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1240543980
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.760560380
Short name T501
Test name
Test status
Simulation time 151760709 ps
CPU time 4.9 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:09 PM PDT 24
Peak memory 232844 kb
Host smart-fa72580e-574b-4637-ad86-9e3792d5ccfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760560380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.760560380
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.734833519
Short name T447
Test name
Test status
Simulation time 26593182019 ps
CPU time 51.42 seconds
Started Aug 18 05:50:03 PM PDT 24
Finished Aug 18 05:50:55 PM PDT 24
Peak memory 232888 kb
Host smart-21918d6e-53a5-49e4-9333-0346c44d445e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734833519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.734833519
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.807357749
Short name T431
Test name
Test status
Simulation time 21362484029 ps
CPU time 18.23 seconds
Started Aug 18 05:50:03 PM PDT 24
Finished Aug 18 05:50:21 PM PDT 24
Peak memory 238900 kb
Host smart-12cc16c2-b26b-4a1a-a5c3-274739a96251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807357749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.807357749
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4054987923
Short name T1020
Test name
Test status
Simulation time 740820588 ps
CPU time 4.69 seconds
Started Aug 18 05:50:10 PM PDT 24
Finished Aug 18 05:50:15 PM PDT 24
Peak memory 232780 kb
Host smart-4225270c-a9e4-4341-8e0f-dea16938100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054987923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4054987923
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.916817186
Short name T953
Test name
Test status
Simulation time 1654586300 ps
CPU time 16.45 seconds
Started Aug 18 05:50:03 PM PDT 24
Finished Aug 18 05:50:19 PM PDT 24
Peak memory 220256 kb
Host smart-242afc54-cbff-44ae-a5ce-71c3d130acb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=916817186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.916817186
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1749504353
Short name T114
Test name
Test status
Simulation time 104579954214 ps
CPU time 279.69 seconds
Started Aug 18 05:50:10 PM PDT 24
Finished Aug 18 05:54:50 PM PDT 24
Peak memory 251732 kb
Host smart-5ef8b644-361e-4098-927e-e676ce92f464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749504353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1749504353
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3966985863
Short name T976
Test name
Test status
Simulation time 3934131146 ps
CPU time 6.11 seconds
Started Aug 18 05:50:05 PM PDT 24
Finished Aug 18 05:50:11 PM PDT 24
Peak memory 216712 kb
Host smart-010666ff-2a3c-45f4-98e6-e814c5196fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966985863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3966985863
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3621358705
Short name T578
Test name
Test status
Simulation time 1483724844 ps
CPU time 5.29 seconds
Started Aug 18 05:50:06 PM PDT 24
Finished Aug 18 05:50:12 PM PDT 24
Peak memory 216624 kb
Host smart-0082a20b-213b-4536-9493-da07c7115ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621358705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3621358705
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.626896955
Short name T417
Test name
Test status
Simulation time 130411500 ps
CPU time 3.82 seconds
Started Aug 18 05:50:06 PM PDT 24
Finished Aug 18 05:50:10 PM PDT 24
Peak memory 216500 kb
Host smart-111b52bb-c05b-4eef-967f-17b5a94490b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626896955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.626896955
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.316603531
Short name T629
Test name
Test status
Simulation time 55006292 ps
CPU time 0.71 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:05 PM PDT 24
Peak memory 206016 kb
Host smart-5c213186-f0e4-40b9-a6d3-ec146cee842e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316603531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.316603531
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1110126017
Short name T678
Test name
Test status
Simulation time 463666223 ps
CPU time 5.44 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:10 PM PDT 24
Peak memory 224628 kb
Host smart-8682a8cc-c7e7-42d0-95cb-ef4275624596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110126017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1110126017
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3327586869
Short name T54
Test name
Test status
Simulation time 24589318 ps
CPU time 0.71 seconds
Started Aug 18 05:50:03 PM PDT 24
Finished Aug 18 05:50:04 PM PDT 24
Peak memory 205864 kb
Host smart-cdf9393b-041f-4020-a86f-4e940a38a5ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327586869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3327586869
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2926932318
Short name T402
Test name
Test status
Simulation time 4792485988 ps
CPU time 14.16 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:19 PM PDT 24
Peak memory 224680 kb
Host smart-ac6df5a0-7448-44d2-b5b7-080598ec5451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926932318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2926932318
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.32744422
Short name T947
Test name
Test status
Simulation time 62615263 ps
CPU time 0.78 seconds
Started Aug 18 05:50:07 PM PDT 24
Finished Aug 18 05:50:08 PM PDT 24
Peak memory 206580 kb
Host smart-b0ec132f-b3db-4c7a-8e5a-5bfa689cce04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32744422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.32744422
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2292418563
Short name T143
Test name
Test status
Simulation time 34786489982 ps
CPU time 64.14 seconds
Started Aug 18 05:50:11 PM PDT 24
Finished Aug 18 05:51:15 PM PDT 24
Peak memory 255468 kb
Host smart-5b7436ba-26f9-4165-ac06-19e078079dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292418563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2292418563
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3217057389
Short name T570
Test name
Test status
Simulation time 12693991552 ps
CPU time 41.91 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:46 PM PDT 24
Peak memory 256236 kb
Host smart-4ba7bdb8-5911-4f4d-9568-16c5f78cf5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217057389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3217057389
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1436790995
Short name T705
Test name
Test status
Simulation time 223224310444 ps
CPU time 450.77 seconds
Started Aug 18 05:50:03 PM PDT 24
Finished Aug 18 05:57:34 PM PDT 24
Peak memory 252028 kb
Host smart-0246b838-53be-43f9-b060-c76a87b17232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436790995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1436790995
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3761265260
Short name T490
Test name
Test status
Simulation time 521867430 ps
CPU time 3.26 seconds
Started Aug 18 05:50:03 PM PDT 24
Finished Aug 18 05:50:06 PM PDT 24
Peak memory 232860 kb
Host smart-2ba075df-dcef-4f62-ac83-cb416e03e377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761265260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3761265260
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2422481970
Short name T159
Test name
Test status
Simulation time 12999515295 ps
CPU time 87.06 seconds
Started Aug 18 05:50:03 PM PDT 24
Finished Aug 18 05:51:30 PM PDT 24
Peak memory 236964 kb
Host smart-cb984d51-07de-4035-9788-0646eb058aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422481970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2422481970
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2561607727
Short name T955
Test name
Test status
Simulation time 425351560 ps
CPU time 5.23 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:09 PM PDT 24
Peak memory 224588 kb
Host smart-12a2531f-0a1e-427b-8c2d-5f82a4b20e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561607727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2561607727
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3458557524
Short name T879
Test name
Test status
Simulation time 194946176 ps
CPU time 3.78 seconds
Started Aug 18 05:50:11 PM PDT 24
Finished Aug 18 05:50:15 PM PDT 24
Peak memory 232808 kb
Host smart-a40d16cf-487e-4e29-b5a1-6d0365e10403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458557524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3458557524
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2737229834
Short name T532
Test name
Test status
Simulation time 27091839822 ps
CPU time 7.41 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:11 PM PDT 24
Peak memory 224676 kb
Host smart-3b751c71-1b7d-4c93-993e-30c1a29be333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737229834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2737229834
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3916921953
Short name T243
Test name
Test status
Simulation time 7678831836 ps
CPU time 14.92 seconds
Started Aug 18 05:50:07 PM PDT 24
Finished Aug 18 05:50:22 PM PDT 24
Peak memory 232932 kb
Host smart-b806f671-088b-47ba-ab6c-3e0d49eb4eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916921953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3916921953
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1491626437
Short name T362
Test name
Test status
Simulation time 68013691 ps
CPU time 3.73 seconds
Started Aug 18 05:50:00 PM PDT 24
Finished Aug 18 05:50:04 PM PDT 24
Peak memory 222628 kb
Host smart-8428679b-f2ae-423c-9be4-9d3dd13eb5fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1491626437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1491626437
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3131759306
Short name T573
Test name
Test status
Simulation time 7522400758 ps
CPU time 43.92 seconds
Started Aug 18 05:50:10 PM PDT 24
Finished Aug 18 05:50:54 PM PDT 24
Peak memory 249320 kb
Host smart-35f6329f-d20a-4510-bec5-da2e0aced2ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131759306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3131759306
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.941638871
Short name T529
Test name
Test status
Simulation time 1799712498 ps
CPU time 5.04 seconds
Started Aug 18 05:50:09 PM PDT 24
Finished Aug 18 05:50:14 PM PDT 24
Peak memory 216496 kb
Host smart-e783d11b-c212-4397-aa37-2784822e6390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941638871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.941638871
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.255130463
Short name T26
Test name
Test status
Simulation time 3081181442 ps
CPU time 10.92 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:15 PM PDT 24
Peak memory 216544 kb
Host smart-47d41f12-5006-4bc4-b82d-e5d95fa28ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255130463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.255130463
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1147055702
Short name T335
Test name
Test status
Simulation time 61698950 ps
CPU time 0.9 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:05 PM PDT 24
Peak memory 207100 kb
Host smart-3a9f0d78-35d7-47fc-a9e1-814fb36c523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147055702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1147055702
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1308787068
Short name T588
Test name
Test status
Simulation time 98074166 ps
CPU time 0.99 seconds
Started Aug 18 05:50:02 PM PDT 24
Finished Aug 18 05:50:03 PM PDT 24
Peak memory 207052 kb
Host smart-8c8addf7-5399-4331-8692-772f0d3faaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308787068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1308787068
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.156449429
Short name T204
Test name
Test status
Simulation time 7107521726 ps
CPU time 8.25 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:12 PM PDT 24
Peak memory 232896 kb
Host smart-dbfd16f8-2bc8-4ba3-b4d4-806af70b20e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156449429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.156449429
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2537714763
Short name T853
Test name
Test status
Simulation time 21054581 ps
CPU time 0.68 seconds
Started Aug 18 05:50:11 PM PDT 24
Finished Aug 18 05:50:12 PM PDT 24
Peak memory 205476 kb
Host smart-b6dcb869-4769-4c45-8e1a-fe33efd598ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537714763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2537714763
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1930211411
Short name T855
Test name
Test status
Simulation time 646885420 ps
CPU time 4.35 seconds
Started Aug 18 05:50:05 PM PDT 24
Finished Aug 18 05:50:10 PM PDT 24
Peak memory 224576 kb
Host smart-88cd04a3-6b3f-4805-a0dd-c0db673e119d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930211411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1930211411
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3836959247
Short name T648
Test name
Test status
Simulation time 15454362 ps
CPU time 0.73 seconds
Started Aug 18 05:50:06 PM PDT 24
Finished Aug 18 05:50:07 PM PDT 24
Peak memory 205544 kb
Host smart-a0c1d55a-44da-4d8f-8e59-28607d88f4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836959247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3836959247
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3777261986
Short name T531
Test name
Test status
Simulation time 1419944923 ps
CPU time 32.92 seconds
Started Aug 18 05:50:11 PM PDT 24
Finished Aug 18 05:50:44 PM PDT 24
Peak memory 257408 kb
Host smart-6df29f28-2692-45b0-b608-66088352ed55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777261986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3777261986
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3859039539
Short name T731
Test name
Test status
Simulation time 1933662385 ps
CPU time 44.27 seconds
Started Aug 18 05:50:16 PM PDT 24
Finished Aug 18 05:51:01 PM PDT 24
Peak memory 253592 kb
Host smart-0885c134-4ed9-4149-8237-6abccba224e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859039539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3859039539
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1512962904
Short name T884
Test name
Test status
Simulation time 6352727035 ps
CPU time 46.24 seconds
Started Aug 18 05:50:09 PM PDT 24
Finished Aug 18 05:50:56 PM PDT 24
Peak memory 232996 kb
Host smart-efa4396a-1665-4d5e-b021-62c41323b7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512962904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1512962904
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2581219936
Short name T567
Test name
Test status
Simulation time 879128429 ps
CPU time 3.8 seconds
Started Aug 18 05:50:10 PM PDT 24
Finished Aug 18 05:50:14 PM PDT 24
Peak memory 232892 kb
Host smart-53faaba9-662c-4eb2-af00-99c3563bcb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581219936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2581219936
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3408927413
Short name T77
Test name
Test status
Simulation time 8234805555 ps
CPU time 52.01 seconds
Started Aug 18 05:50:13 PM PDT 24
Finished Aug 18 05:51:05 PM PDT 24
Peak memory 250692 kb
Host smart-16f30912-77dc-4b90-8dde-1628c9c6a683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408927413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3408927413
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3988187613
Short name T631
Test name
Test status
Simulation time 1728424824 ps
CPU time 10.07 seconds
Started Aug 18 05:50:05 PM PDT 24
Finished Aug 18 05:50:16 PM PDT 24
Peak memory 228608 kb
Host smart-8c93a360-afba-4c9d-b216-f76334340dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988187613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3988187613
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.851925666
Short name T792
Test name
Test status
Simulation time 472790140 ps
CPU time 3.93 seconds
Started Aug 18 05:50:05 PM PDT 24
Finished Aug 18 05:50:10 PM PDT 24
Peak memory 232816 kb
Host smart-79a97ef1-1b9a-42c6-947b-968c91e1c7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851925666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.851925666
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1226696143
Short name T834
Test name
Test status
Simulation time 333392536 ps
CPU time 2.79 seconds
Started Aug 18 05:50:06 PM PDT 24
Finished Aug 18 05:50:09 PM PDT 24
Peak memory 224516 kb
Host smart-2c12965e-fd5d-4d59-bb14-a2140a141107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226696143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1226696143
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4058108138
Short name T220
Test name
Test status
Simulation time 8432344699 ps
CPU time 23.09 seconds
Started Aug 18 05:50:04 PM PDT 24
Finished Aug 18 05:50:27 PM PDT 24
Peak memory 232884 kb
Host smart-db9892f6-4c80-4495-aa56-1eb7765a3bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058108138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4058108138
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3211231084
Short name T925
Test name
Test status
Simulation time 312561790 ps
CPU time 4 seconds
Started Aug 18 05:50:16 PM PDT 24
Finished Aug 18 05:50:20 PM PDT 24
Peak memory 223152 kb
Host smart-18cee65c-19f7-405f-9072-7298f5bc762e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3211231084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3211231084
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3524799160
Short name T355
Test name
Test status
Simulation time 8511970466 ps
CPU time 129 seconds
Started Aug 18 05:50:09 PM PDT 24
Finished Aug 18 05:52:18 PM PDT 24
Peak memory 252852 kb
Host smart-856b7025-feda-4504-8aa7-5df137e2cec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524799160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3524799160
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.822425345
Short name T888
Test name
Test status
Simulation time 48624393613 ps
CPU time 33.11 seconds
Started Aug 18 05:50:11 PM PDT 24
Finished Aug 18 05:50:45 PM PDT 24
Peak memory 216508 kb
Host smart-dec9873a-9591-49ed-8a63-9715d351d9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822425345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.822425345
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4108394919
Short name T303
Test name
Test status
Simulation time 662557345 ps
CPU time 4.75 seconds
Started Aug 18 05:50:06 PM PDT 24
Finished Aug 18 05:50:11 PM PDT 24
Peak memory 216428 kb
Host smart-b0d26374-0f51-4b7c-abab-cc9d08d12bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108394919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4108394919
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1773385624
Short name T847
Test name
Test status
Simulation time 24447595 ps
CPU time 0.99 seconds
Started Aug 18 05:50:09 PM PDT 24
Finished Aug 18 05:50:10 PM PDT 24
Peak memory 207144 kb
Host smart-3bc0d9f3-528b-4639-ad8f-5d84c645aec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773385624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1773385624
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.171142497
Short name T973
Test name
Test status
Simulation time 95798299 ps
CPU time 0.86 seconds
Started Aug 18 05:50:03 PM PDT 24
Finished Aug 18 05:50:04 PM PDT 24
Peak memory 206080 kb
Host smart-7fc714cb-de0d-45bc-9a0b-12f2ebbecd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171142497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.171142497
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2666891955
Short name T295
Test name
Test status
Simulation time 337643367 ps
CPU time 3.23 seconds
Started Aug 18 05:50:06 PM PDT 24
Finished Aug 18 05:50:09 PM PDT 24
Peak memory 232872 kb
Host smart-f089de4d-ebad-437e-8a17-1454bb4ee16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666891955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2666891955
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1810500304
Short name T857
Test name
Test status
Simulation time 21079777 ps
CPU time 0.7 seconds
Started Aug 18 05:50:12 PM PDT 24
Finished Aug 18 05:50:13 PM PDT 24
Peak memory 204832 kb
Host smart-bcebd1d5-b515-4044-a907-b4c104dfc8da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810500304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1810500304
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1734060151
Short name T784
Test name
Test status
Simulation time 732796016 ps
CPU time 8.1 seconds
Started Aug 18 05:50:13 PM PDT 24
Finished Aug 18 05:50:21 PM PDT 24
Peak memory 224660 kb
Host smart-4011c8e3-f89f-4ccf-bb3a-f171aff43f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734060151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1734060151
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2221204180
Short name T346
Test name
Test status
Simulation time 18612472 ps
CPU time 0.79 seconds
Started Aug 18 05:50:11 PM PDT 24
Finished Aug 18 05:50:12 PM PDT 24
Peak memory 206552 kb
Host smart-28e6d830-a00f-42ed-93f1-e261b1d7cfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221204180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2221204180
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.4219198305
Short name T196
Test name
Test status
Simulation time 95726359601 ps
CPU time 148.06 seconds
Started Aug 18 05:50:13 PM PDT 24
Finished Aug 18 05:52:41 PM PDT 24
Peak memory 252028 kb
Host smart-09ce3b68-2509-4c2e-a9d4-c84d0370c190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219198305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4219198305
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.612986480
Short name T635
Test name
Test status
Simulation time 6958247362 ps
CPU time 87.31 seconds
Started Aug 18 05:50:16 PM PDT 24
Finished Aug 18 05:51:44 PM PDT 24
Peak memory 249380 kb
Host smart-2cd73c59-799b-48af-af3a-5ab19e39b991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612986480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.612986480
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.572312578
Short name T120
Test name
Test status
Simulation time 8417506410 ps
CPU time 138.1 seconds
Started Aug 18 05:50:10 PM PDT 24
Finished Aug 18 05:52:28 PM PDT 24
Peak memory 266800 kb
Host smart-f2497913-6661-4268-b4dc-0b24930d8d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572312578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.572312578
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1000173130
Short name T124
Test name
Test status
Simulation time 184470366 ps
CPU time 5.68 seconds
Started Aug 18 05:50:09 PM PDT 24
Finished Aug 18 05:50:15 PM PDT 24
Peak memory 232860 kb
Host smart-74f3836e-f4be-4e2b-97dc-1a9831313a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000173130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1000173130
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.940221857
Short name T1022
Test name
Test status
Simulation time 42544707270 ps
CPU time 275.33 seconds
Started Aug 18 05:50:16 PM PDT 24
Finished Aug 18 05:54:52 PM PDT 24
Peak memory 254544 kb
Host smart-635d6b3d-37e2-441a-8695-9014fe434bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940221857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.940221857
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1789362966
Short name T202
Test name
Test status
Simulation time 675575346 ps
CPU time 5.87 seconds
Started Aug 18 05:50:13 PM PDT 24
Finished Aug 18 05:50:19 PM PDT 24
Peak memory 232776 kb
Host smart-b3f08461-ca29-4397-b650-3673c59a7d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789362966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1789362966
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2396020225
Short name T830
Test name
Test status
Simulation time 496526925 ps
CPU time 7.36 seconds
Started Aug 18 05:50:09 PM PDT 24
Finished Aug 18 05:50:17 PM PDT 24
Peak memory 224576 kb
Host smart-06b7378e-3490-4f9f-954d-b29d087b34d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396020225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2396020225
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3729845254
Short name T405
Test name
Test status
Simulation time 584399218 ps
CPU time 3.09 seconds
Started Aug 18 05:50:12 PM PDT 24
Finished Aug 18 05:50:15 PM PDT 24
Peak memory 232852 kb
Host smart-b75fd083-4900-41dc-9ff5-9d25960f7e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729845254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3729845254
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.819592463
Short name T242
Test name
Test status
Simulation time 8677323541 ps
CPU time 8.45 seconds
Started Aug 18 05:50:11 PM PDT 24
Finished Aug 18 05:50:20 PM PDT 24
Peak memory 232908 kb
Host smart-dda8a5b1-bdac-4723-a735-22528264610f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819592463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.819592463
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.112176866
Short name T556
Test name
Test status
Simulation time 105577812 ps
CPU time 4.12 seconds
Started Aug 18 05:50:16 PM PDT 24
Finished Aug 18 05:50:20 PM PDT 24
Peak memory 223152 kb
Host smart-f9d74f6b-d183-4aa7-a58a-ea6d721930ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=112176866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.112176866
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.729925984
Short name T486
Test name
Test status
Simulation time 17281232897 ps
CPU time 144.48 seconds
Started Aug 18 05:50:10 PM PDT 24
Finished Aug 18 05:52:35 PM PDT 24
Peak memory 252720 kb
Host smart-b8d18f8b-3e12-4a20-9507-0739c4870326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729925984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.729925984
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1678699810
Short name T642
Test name
Test status
Simulation time 4119229458 ps
CPU time 23.45 seconds
Started Aug 18 05:50:14 PM PDT 24
Finished Aug 18 05:50:38 PM PDT 24
Peak memory 216524 kb
Host smart-c056e6f0-5bc0-4413-ac7e-3f989c1b22fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678699810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1678699810
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3994551229
Short name T315
Test name
Test status
Simulation time 7996764475 ps
CPU time 12.26 seconds
Started Aug 18 05:50:16 PM PDT 24
Finished Aug 18 05:50:28 PM PDT 24
Peak memory 216548 kb
Host smart-6b5653c1-99ea-4420-af7b-71f05b81beec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994551229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3994551229
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4109547115
Short name T323
Test name
Test status
Simulation time 71367430 ps
CPU time 1.78 seconds
Started Aug 18 05:50:09 PM PDT 24
Finished Aug 18 05:50:11 PM PDT 24
Peak memory 216480 kb
Host smart-a1a1fdfc-2b03-4383-bf3c-95c80774036c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109547115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4109547115
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3134456744
Short name T655
Test name
Test status
Simulation time 214547398 ps
CPU time 0.82 seconds
Started Aug 18 05:50:11 PM PDT 24
Finished Aug 18 05:50:12 PM PDT 24
Peak memory 206096 kb
Host smart-b9326cb9-a766-4a3b-9379-bdfc6b5e162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134456744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3134456744
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1100443590
Short name T460
Test name
Test status
Simulation time 2100670601 ps
CPU time 9.07 seconds
Started Aug 18 05:50:12 PM PDT 24
Finished Aug 18 05:50:21 PM PDT 24
Peak memory 249428 kb
Host smart-07dcf0fc-c95c-4e73-ad8d-5ff0fd60fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100443590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1100443590
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1726936531
Short name T824
Test name
Test status
Simulation time 35839340 ps
CPU time 0.73 seconds
Started Aug 18 05:50:22 PM PDT 24
Finished Aug 18 05:50:23 PM PDT 24
Peak memory 205544 kb
Host smart-1f10a754-b347-408c-8304-9b59146e2156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726936531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1726936531
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.723596947
Short name T297
Test name
Test status
Simulation time 60211603 ps
CPU time 2.1 seconds
Started Aug 18 05:50:19 PM PDT 24
Finished Aug 18 05:50:22 PM PDT 24
Peak memory 224612 kb
Host smart-810fecb8-0ad0-47a4-9b4f-08b58440924c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723596947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.723596947
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4266570029
Short name T566
Test name
Test status
Simulation time 32348113 ps
CPU time 0.72 seconds
Started Aug 18 05:50:17 PM PDT 24
Finished Aug 18 05:50:18 PM PDT 24
Peak memory 206576 kb
Host smart-c984dd44-417f-4e62-8c98-1c3836650380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266570029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4266570029
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1060549645
Short name T37
Test name
Test status
Simulation time 1841227552 ps
CPU time 29.13 seconds
Started Aug 18 05:50:21 PM PDT 24
Finished Aug 18 05:50:50 PM PDT 24
Peak memory 224828 kb
Host smart-7936a568-4049-4a3c-b6f9-8f0a49ccf517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060549645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1060549645
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2238893520
Short name T697
Test name
Test status
Simulation time 17446042545 ps
CPU time 82.7 seconds
Started Aug 18 05:50:23 PM PDT 24
Finished Aug 18 05:51:46 PM PDT 24
Peak memory 256700 kb
Host smart-f4e3efc1-9010-48e5-8cb2-83b330b49fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238893520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2238893520
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2212635349
Short name T775
Test name
Test status
Simulation time 3069608954 ps
CPU time 53.76 seconds
Started Aug 18 05:50:18 PM PDT 24
Finished Aug 18 05:51:11 PM PDT 24
Peak memory 249372 kb
Host smart-698860ec-5040-4c02-a7f4-fc5b683506d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212635349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2212635349
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.445105823
Short name T978
Test name
Test status
Simulation time 1162245272 ps
CPU time 10.49 seconds
Started Aug 18 05:50:21 PM PDT 24
Finished Aug 18 05:50:31 PM PDT 24
Peak memory 224668 kb
Host smart-5773f9d9-825b-4ca2-81fd-1a682c175ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445105823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.445105823
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.26079582
Short name T256
Test name
Test status
Simulation time 6908589814 ps
CPU time 59.13 seconds
Started Aug 18 05:50:19 PM PDT 24
Finished Aug 18 05:51:19 PM PDT 24
Peak memory 249340 kb
Host smart-f082277a-274c-41b0-9c69-33c4e0fe9cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26079582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.26079582
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2226339687
Short name T518
Test name
Test status
Simulation time 155824366 ps
CPU time 4.35 seconds
Started Aug 18 05:50:10 PM PDT 24
Finished Aug 18 05:50:15 PM PDT 24
Peak memory 218996 kb
Host smart-8add0ebd-3421-46fc-b7d9-2dde851e3b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226339687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2226339687
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1858421731
Short name T956
Test name
Test status
Simulation time 56340482188 ps
CPU time 70.61 seconds
Started Aug 18 05:50:12 PM PDT 24
Finished Aug 18 05:51:22 PM PDT 24
Peak memory 232828 kb
Host smart-7cc46fb3-e7d5-4be7-96f5-0f3d7153559a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858421731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1858421731
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1099956458
Short name T930
Test name
Test status
Simulation time 436000498 ps
CPU time 7.64 seconds
Started Aug 18 05:50:12 PM PDT 24
Finished Aug 18 05:50:20 PM PDT 24
Peak memory 241000 kb
Host smart-341e6b05-c1b6-48d7-b2b7-d463ad4e5586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099956458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1099956458
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2515562992
Short name T623
Test name
Test status
Simulation time 181573328 ps
CPU time 2.6 seconds
Started Aug 18 05:50:09 PM PDT 24
Finished Aug 18 05:50:12 PM PDT 24
Peak memory 232820 kb
Host smart-3dae80fb-8cdb-4d7c-a229-db253ccec628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515562992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2515562992
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4102621289
Short name T433
Test name
Test status
Simulation time 996002904 ps
CPU time 10.54 seconds
Started Aug 18 05:50:17 PM PDT 24
Finished Aug 18 05:50:28 PM PDT 24
Peak memory 222232 kb
Host smart-5de62757-e028-4eb4-bccc-f9ceca06594c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4102621289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4102621289
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1372791226
Short name T19
Test name
Test status
Simulation time 16015695175 ps
CPU time 122.05 seconds
Started Aug 18 05:50:18 PM PDT 24
Finished Aug 18 05:52:20 PM PDT 24
Peak memory 257440 kb
Host smart-2e341134-3073-431b-b4e4-767d1e40dde2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372791226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1372791226
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.559184584
Short name T538
Test name
Test status
Simulation time 912378264 ps
CPU time 12.81 seconds
Started Aug 18 05:50:17 PM PDT 24
Finished Aug 18 05:50:29 PM PDT 24
Peak memory 216436 kb
Host smart-24edc841-d324-413f-8ba2-b09e4aef5dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559184584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.559184584
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3760604948
Short name T833
Test name
Test status
Simulation time 11613618 ps
CPU time 0.68 seconds
Started Aug 18 05:50:10 PM PDT 24
Finished Aug 18 05:50:11 PM PDT 24
Peak memory 205700 kb
Host smart-beb5998d-b005-4e83-a880-b3f6eb7e1648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760604948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3760604948
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2407009900
Short name T882
Test name
Test status
Simulation time 12653121 ps
CPU time 0.84 seconds
Started Aug 18 05:50:12 PM PDT 24
Finished Aug 18 05:50:13 PM PDT 24
Peak memory 207036 kb
Host smart-af719dcb-da31-4a5b-b59c-656b7d7f4a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407009900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2407009900
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.844151392
Short name T696
Test name
Test status
Simulation time 47158457 ps
CPU time 0.85 seconds
Started Aug 18 05:50:16 PM PDT 24
Finished Aug 18 05:50:17 PM PDT 24
Peak memory 206076 kb
Host smart-798b9f8d-911a-4094-9439-97f9eb79bae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844151392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.844151392
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2760085576
Short name T349
Test name
Test status
Simulation time 9165379524 ps
CPU time 9.91 seconds
Started Aug 18 05:50:12 PM PDT 24
Finished Aug 18 05:50:23 PM PDT 24
Peak memory 232864 kb
Host smart-782e61ee-553d-4352-97bb-f5e83a04e2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760085576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2760085576
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1164361604
Short name T690
Test name
Test status
Simulation time 45554452 ps
CPU time 0.68 seconds
Started Aug 18 05:50:20 PM PDT 24
Finished Aug 18 05:50:21 PM PDT 24
Peak memory 204884 kb
Host smart-ea1131fb-bbc7-4834-b06c-e59aab43cf6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164361604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1164361604
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1555079279
Short name T1012
Test name
Test status
Simulation time 272385739 ps
CPU time 3.76 seconds
Started Aug 18 05:50:21 PM PDT 24
Finished Aug 18 05:50:24 PM PDT 24
Peak memory 224592 kb
Host smart-caa454f2-54ea-40de-aa4d-1b5eb1dde091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555079279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1555079279
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2420486623
Short name T643
Test name
Test status
Simulation time 63929088 ps
CPU time 0.77 seconds
Started Aug 18 05:50:18 PM PDT 24
Finished Aug 18 05:50:19 PM PDT 24
Peak memory 206512 kb
Host smart-4d0023bc-8762-4c4e-aa51-9ba126b6d301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420486623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2420486623
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3588289183
Short name T726
Test name
Test status
Simulation time 3595407105 ps
CPU time 12.6 seconds
Started Aug 18 05:50:20 PM PDT 24
Finished Aug 18 05:50:33 PM PDT 24
Peak memory 236108 kb
Host smart-9ca8ca29-83dd-43d3-9380-f690ddb45064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588289183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3588289183
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3027417964
Short name T187
Test name
Test status
Simulation time 7215865591 ps
CPU time 30.17 seconds
Started Aug 18 05:50:22 PM PDT 24
Finished Aug 18 05:50:52 PM PDT 24
Peak memory 236200 kb
Host smart-263ef5f9-74ef-47e1-9b3e-7bd751d9f65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027417964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3027417964
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3930866176
Short name T479
Test name
Test status
Simulation time 3788822273 ps
CPU time 18.69 seconds
Started Aug 18 05:50:19 PM PDT 24
Finished Aug 18 05:50:38 PM PDT 24
Peak memory 238624 kb
Host smart-635f42e4-1c22-4301-bff5-b7da2ffcd0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930866176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3930866176
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4222848372
Short name T277
Test name
Test status
Simulation time 174984233 ps
CPU time 8.52 seconds
Started Aug 18 05:50:21 PM PDT 24
Finished Aug 18 05:50:35 PM PDT 24
Peak memory 232844 kb
Host smart-10d1affe-8021-4d1e-b27e-6b1702c341af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222848372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4222848372
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2802442055
Short name T38
Test name
Test status
Simulation time 15260337985 ps
CPU time 99.92 seconds
Started Aug 18 05:50:19 PM PDT 24
Finished Aug 18 05:52:00 PM PDT 24
Peak memory 249300 kb
Host smart-11f59d44-21dd-449e-a732-07296831271a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802442055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2802442055
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4037320788
Short name T25
Test name
Test status
Simulation time 740573693 ps
CPU time 6.93 seconds
Started Aug 18 05:50:19 PM PDT 24
Finished Aug 18 05:50:27 PM PDT 24
Peak memory 224552 kb
Host smart-ce4dd430-4931-467b-bf6b-264d46c03732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037320788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4037320788
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.78128118
Short name T757
Test name
Test status
Simulation time 20341531909 ps
CPU time 14.59 seconds
Started Aug 18 05:50:17 PM PDT 24
Finished Aug 18 05:50:32 PM PDT 24
Peak memory 232852 kb
Host smart-1fefb8d4-dd57-4fd9-a94a-0d3d8d7357b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78128118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.78128118
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3084023655
Short name T827
Test name
Test status
Simulation time 743538230 ps
CPU time 4.29 seconds
Started Aug 18 05:50:21 PM PDT 24
Finished Aug 18 05:50:26 PM PDT 24
Peak memory 224584 kb
Host smart-7f5a3b20-a517-4727-986b-b81ad22b5099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084023655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3084023655
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3656727071
Short name T860
Test name
Test status
Simulation time 3795846104 ps
CPU time 9.3 seconds
Started Aug 18 05:50:19 PM PDT 24
Finished Aug 18 05:50:28 PM PDT 24
Peak memory 224700 kb
Host smart-93d0989d-cb4a-4564-903e-aaf71bfe38fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656727071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3656727071
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1765419782
Short name T128
Test name
Test status
Simulation time 385603143 ps
CPU time 3.86 seconds
Started Aug 18 05:50:25 PM PDT 24
Finished Aug 18 05:50:29 PM PDT 24
Peak memory 219388 kb
Host smart-d7fb106a-7ebd-4ace-ad5b-de5284cff509
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1765419782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1765419782
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3577352662
Short name T387
Test name
Test status
Simulation time 3220242983 ps
CPU time 16.32 seconds
Started Aug 18 05:50:18 PM PDT 24
Finished Aug 18 05:50:34 PM PDT 24
Peak memory 216540 kb
Host smart-9080b89f-4008-44fb-844e-16b2d7d6ddea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577352662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3577352662
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3236928275
Short name T379
Test name
Test status
Simulation time 22612482249 ps
CPU time 13.79 seconds
Started Aug 18 05:50:23 PM PDT 24
Finished Aug 18 05:50:37 PM PDT 24
Peak memory 216488 kb
Host smart-d3d05f93-a9bd-43bf-9cad-6c75b1b74b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236928275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3236928275
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2856704325
Short name T294
Test name
Test status
Simulation time 45492517 ps
CPU time 1.22 seconds
Started Aug 18 05:50:23 PM PDT 24
Finished Aug 18 05:50:24 PM PDT 24
Peak memory 216416 kb
Host smart-9d5808ec-532e-4b55-9529-0c6b837919f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856704325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2856704325
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2713764414
Short name T640
Test name
Test status
Simulation time 60073547 ps
CPU time 0.78 seconds
Started Aug 18 05:50:20 PM PDT 24
Finished Aug 18 05:50:21 PM PDT 24
Peak memory 206112 kb
Host smart-9f7f236f-7a54-4638-ab60-2edce10dcaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713764414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2713764414
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2804942012
Short name T168
Test name
Test status
Simulation time 8852388554 ps
CPU time 8.84 seconds
Started Aug 18 05:50:18 PM PDT 24
Finished Aug 18 05:50:27 PM PDT 24
Peak memory 249028 kb
Host smart-9c4f3b7b-51ff-4d19-92ef-cf888da2561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804942012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2804942012
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.952716627
Short name T474
Test name
Test status
Simulation time 65621300 ps
CPU time 0.72 seconds
Started Aug 18 05:50:21 PM PDT 24
Finished Aug 18 05:50:22 PM PDT 24
Peak memory 204900 kb
Host smart-65911d70-f64c-4060-915d-ae526294cede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952716627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.952716627
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2068815465
Short name T463
Test name
Test status
Simulation time 3230044869 ps
CPU time 9.68 seconds
Started Aug 18 05:50:23 PM PDT 24
Finished Aug 18 05:50:32 PM PDT 24
Peak memory 232960 kb
Host smart-c8f25220-c8ce-4fee-91e9-998d51bfbce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068815465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2068815465
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3952481372
Short name T321
Test name
Test status
Simulation time 143696016 ps
CPU time 0.71 seconds
Started Aug 18 05:50:20 PM PDT 24
Finished Aug 18 05:50:21 PM PDT 24
Peak memory 205548 kb
Host smart-59c380ae-5482-4e78-aa7e-054268e53ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952481372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3952481372
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2982327630
Short name T894
Test name
Test status
Simulation time 66359061068 ps
CPU time 53.48 seconds
Started Aug 18 05:50:19 PM PDT 24
Finished Aug 18 05:51:12 PM PDT 24
Peak memory 249328 kb
Host smart-a286fa1e-14a7-4eb7-990e-d74ed6ba007b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982327630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2982327630
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1944580690
Short name T646
Test name
Test status
Simulation time 4192919715 ps
CPU time 59.77 seconds
Started Aug 18 05:50:17 PM PDT 24
Finished Aug 18 05:51:17 PM PDT 24
Peak memory 249320 kb
Host smart-fd56b859-ebf4-4e7c-91e0-2dfd4369b436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944580690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1944580690
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.670573051
Short name T354
Test name
Test status
Simulation time 7131508868 ps
CPU time 14.96 seconds
Started Aug 18 05:50:19 PM PDT 24
Finished Aug 18 05:50:34 PM PDT 24
Peak memory 249320 kb
Host smart-08b3d45f-72f4-4215-a154-8c9499fa0482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670573051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.670573051
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.741321663
Short name T157
Test name
Test status
Simulation time 4431823561 ps
CPU time 60.87 seconds
Started Aug 18 05:50:16 PM PDT 24
Finished Aug 18 05:51:17 PM PDT 24
Peak memory 256380 kb
Host smart-da2bcfe1-2ee8-49ab-bd58-d0d560edfb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741321663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.741321663
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.759816460
Short name T175
Test name
Test status
Simulation time 4877214516 ps
CPU time 12.97 seconds
Started Aug 18 05:50:20 PM PDT 24
Finished Aug 18 05:50:33 PM PDT 24
Peak memory 232900 kb
Host smart-060288d8-0dd4-49bd-95a5-be2dc12b833f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759816460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.759816460
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.544607744
Short name T851
Test name
Test status
Simulation time 35614308981 ps
CPU time 63.77 seconds
Started Aug 18 05:50:21 PM PDT 24
Finished Aug 18 05:51:25 PM PDT 24
Peak memory 233560 kb
Host smart-66de66e7-fbb2-4bd6-87d2-244607efce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544607744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.544607744
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3451737200
Short name T800
Test name
Test status
Simulation time 4891966801 ps
CPU time 15.05 seconds
Started Aug 18 05:50:18 PM PDT 24
Finished Aug 18 05:50:33 PM PDT 24
Peak memory 232920 kb
Host smart-61bbe2bb-e8f6-489e-ba76-e0ee90602719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451737200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3451737200
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3990509077
Short name T594
Test name
Test status
Simulation time 605256905 ps
CPU time 8.33 seconds
Started Aug 18 05:50:23 PM PDT 24
Finished Aug 18 05:50:31 PM PDT 24
Peak memory 248836 kb
Host smart-13a6c38c-bf39-40eb-a5f3-b1ea54c84624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990509077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3990509077
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2069618480
Short name T338
Test name
Test status
Simulation time 248129946 ps
CPU time 3.67 seconds
Started Aug 18 05:50:17 PM PDT 24
Finished Aug 18 05:50:21 PM PDT 24
Peak memory 219064 kb
Host smart-cba3d4f0-21f9-4584-bec7-86d9e1c839c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2069618480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2069618480
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1637971183
Short name T136
Test name
Test status
Simulation time 204921053455 ps
CPU time 219.64 seconds
Started Aug 18 05:50:19 PM PDT 24
Finished Aug 18 05:53:59 PM PDT 24
Peak memory 268980 kb
Host smart-9099192a-2d4b-4ebb-b312-d4fc3a36c849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637971183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1637971183
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2107742972
Short name T477
Test name
Test status
Simulation time 1656931063 ps
CPU time 24.73 seconds
Started Aug 18 05:50:21 PM PDT 24
Finished Aug 18 05:50:46 PM PDT 24
Peak memory 216456 kb
Host smart-42fd8735-f99f-457c-8dbe-c2a715cb5d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107742972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2107742972
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2890732996
Short name T751
Test name
Test status
Simulation time 740370074 ps
CPU time 4.5 seconds
Started Aug 18 05:50:17 PM PDT 24
Finished Aug 18 05:50:22 PM PDT 24
Peak memory 216448 kb
Host smart-81a4eccb-5aa9-46e3-ba48-75aa6471cfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890732996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2890732996
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2157445636
Short name T633
Test name
Test status
Simulation time 12876301 ps
CPU time 0.87 seconds
Started Aug 18 05:50:21 PM PDT 24
Finished Aug 18 05:50:22 PM PDT 24
Peak memory 206912 kb
Host smart-d8b4f03d-fc0f-4193-8d0c-b94ffe24a353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157445636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2157445636
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.16349739
Short name T846
Test name
Test status
Simulation time 91871351 ps
CPU time 0.71 seconds
Started Aug 18 05:50:20 PM PDT 24
Finished Aug 18 05:50:21 PM PDT 24
Peak memory 206088 kb
Host smart-7294c39f-2990-44b0-8619-9c1d44640cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16349739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.16349739
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2855859172
Short name T246
Test name
Test status
Simulation time 2770610436 ps
CPU time 9.22 seconds
Started Aug 18 05:50:22 PM PDT 24
Finished Aug 18 05:50:31 PM PDT 24
Peak memory 224684 kb
Host smart-0355e860-f5b1-4052-b86d-519b0b6a1450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855859172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2855859172
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2545652830
Short name T398
Test name
Test status
Simulation time 74858777 ps
CPU time 0.69 seconds
Started Aug 18 05:50:27 PM PDT 24
Finished Aug 18 05:50:28 PM PDT 24
Peak memory 204884 kb
Host smart-515244ad-9dd8-4a8c-8077-25818eb645fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545652830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2545652830
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2965277575
Short name T214
Test name
Test status
Simulation time 2364460454 ps
CPU time 29.4 seconds
Started Aug 18 05:50:31 PM PDT 24
Finished Aug 18 05:51:01 PM PDT 24
Peak memory 224656 kb
Host smart-4de837f5-9bf7-4c72-bbfa-f4ccc4465c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965277575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2965277575
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3273121049
Short name T829
Test name
Test status
Simulation time 20770094 ps
CPU time 0.8 seconds
Started Aug 18 05:50:24 PM PDT 24
Finished Aug 18 05:50:24 PM PDT 24
Peak memory 206520 kb
Host smart-c0ed9b19-edfa-4171-8b18-5fa4e193dd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273121049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3273121049
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1769246509
Short name T200
Test name
Test status
Simulation time 83867954224 ps
CPU time 103.5 seconds
Started Aug 18 05:50:32 PM PDT 24
Finished Aug 18 05:52:16 PM PDT 24
Peak memory 233096 kb
Host smart-31b3fcd6-91ec-425b-82c6-63a4122bd946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769246509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1769246509
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4265771140
Short name T654
Test name
Test status
Simulation time 102252499 ps
CPU time 0.85 seconds
Started Aug 18 05:50:35 PM PDT 24
Finished Aug 18 05:50:36 PM PDT 24
Peak memory 217272 kb
Host smart-7e357600-2b2e-478e-ac7d-236fcaf6bfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265771140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4265771140
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2806557572
Short name T489
Test name
Test status
Simulation time 19932685969 ps
CPU time 48.67 seconds
Started Aug 18 05:50:31 PM PDT 24
Finished Aug 18 05:51:19 PM PDT 24
Peak memory 234692 kb
Host smart-2bfb5517-708b-4b70-b913-1d22278fcbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806557572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2806557572
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.243172795
Short name T722
Test name
Test status
Simulation time 61538409 ps
CPU time 3.19 seconds
Started Aug 18 05:50:30 PM PDT 24
Finished Aug 18 05:50:34 PM PDT 24
Peak memory 232560 kb
Host smart-07c112e6-5480-4775-ac28-0543685409fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243172795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.243172795
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.4181848284
Short name T610
Test name
Test status
Simulation time 2071059474 ps
CPU time 35.15 seconds
Started Aug 18 05:50:33 PM PDT 24
Finished Aug 18 05:51:08 PM PDT 24
Peak memory 241060 kb
Host smart-4c4680cb-8f4e-4ca0-bb2b-6e754747fde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181848284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.4181848284
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1261896755
Short name T878
Test name
Test status
Simulation time 82056090 ps
CPU time 2.24 seconds
Started Aug 18 05:50:34 PM PDT 24
Finished Aug 18 05:50:37 PM PDT 24
Peak memory 232392 kb
Host smart-90cceb96-32ea-41f5-af99-0a727c380a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261896755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1261896755
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2966976155
Short name T869
Test name
Test status
Simulation time 52561303551 ps
CPU time 121.24 seconds
Started Aug 18 05:50:32 PM PDT 24
Finished Aug 18 05:52:33 PM PDT 24
Peak memory 232884 kb
Host smart-da1753d5-18e1-4e36-bc49-d7b74ec86f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966976155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2966976155
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1549062018
Short name T261
Test name
Test status
Simulation time 11097181423 ps
CPU time 9.32 seconds
Started Aug 18 05:50:35 PM PDT 24
Finished Aug 18 05:50:45 PM PDT 24
Peak memory 232924 kb
Host smart-e6974889-a6ef-4466-9ed6-b018db3e300b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549062018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1549062018
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.139995642
Short name T880
Test name
Test status
Simulation time 2112783571 ps
CPU time 5.35 seconds
Started Aug 18 05:50:19 PM PDT 24
Finished Aug 18 05:50:25 PM PDT 24
Peak memory 240572 kb
Host smart-522ef5f3-793e-4d7a-aa17-3b3ad47111ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139995642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.139995642
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1142073499
Short name T1
Test name
Test status
Simulation time 5650260380 ps
CPU time 12.07 seconds
Started Aug 18 05:50:39 PM PDT 24
Finished Aug 18 05:50:51 PM PDT 24
Peak memory 222368 kb
Host smart-c9b7acf5-3f22-43de-ac82-85b0cd354f32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1142073499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1142073499
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1749630440
Short name T720
Test name
Test status
Simulation time 7317005574 ps
CPU time 35.41 seconds
Started Aug 18 05:50:20 PM PDT 24
Finished Aug 18 05:50:55 PM PDT 24
Peak memory 216500 kb
Host smart-0bc1a48f-353d-4fce-b5f2-ffc3afdaa031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749630440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1749630440
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3247251136
Short name T865
Test name
Test status
Simulation time 890699561 ps
CPU time 3.09 seconds
Started Aug 18 05:50:22 PM PDT 24
Finished Aug 18 05:50:25 PM PDT 24
Peak memory 208040 kb
Host smart-544bc43a-04fe-4505-a3fd-de57692f7731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247251136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3247251136
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4215321710
Short name T892
Test name
Test status
Simulation time 339350683 ps
CPU time 4.01 seconds
Started Aug 18 05:50:20 PM PDT 24
Finished Aug 18 05:50:24 PM PDT 24
Peak memory 216436 kb
Host smart-736d6986-06e8-49ed-830f-3e179c2d327b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215321710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4215321710
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1001748675
Short name T874
Test name
Test status
Simulation time 74713021 ps
CPU time 0.79 seconds
Started Aug 18 05:50:20 PM PDT 24
Finished Aug 18 05:50:21 PM PDT 24
Peak memory 206064 kb
Host smart-1812a501-9e81-4efa-826f-e83d52568dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001748675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1001748675
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1693393827
Short name T172
Test name
Test status
Simulation time 11648501419 ps
CPU time 9.95 seconds
Started Aug 18 05:50:30 PM PDT 24
Finished Aug 18 05:50:40 PM PDT 24
Peak memory 224708 kb
Host smart-a00e8b39-3e32-465c-a824-4a2d5fde1354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693393827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1693393827
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.734573520
Short name T790
Test name
Test status
Simulation time 107134695 ps
CPU time 0.73 seconds
Started Aug 18 05:50:33 PM PDT 24
Finished Aug 18 05:50:34 PM PDT 24
Peak memory 204952 kb
Host smart-11257b78-a23f-4d39-b04d-7ae64188f1eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734573520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.734573520
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1855387937
Short name T683
Test name
Test status
Simulation time 174831551 ps
CPU time 4.43 seconds
Started Aug 18 05:50:40 PM PDT 24
Finished Aug 18 05:50:44 PM PDT 24
Peak memory 232820 kb
Host smart-c11c4440-1e2d-4dee-98f3-51eb3738650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855387937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1855387937
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1526440095
Short name T616
Test name
Test status
Simulation time 47775150 ps
CPU time 0.75 seconds
Started Aug 18 05:50:30 PM PDT 24
Finished Aug 18 05:50:31 PM PDT 24
Peak memory 206584 kb
Host smart-c11bdb23-4d87-481b-a772-ecf82ba46fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526440095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1526440095
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2908080165
Short name T312
Test name
Test status
Simulation time 485944540 ps
CPU time 4.16 seconds
Started Aug 18 05:50:38 PM PDT 24
Finished Aug 18 05:50:42 PM PDT 24
Peak memory 239828 kb
Host smart-6c9fc76a-4f76-4577-89b3-66f5dccd22df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908080165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2908080165
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.55184553
Short name T353
Test name
Test status
Simulation time 3293979322 ps
CPU time 60.68 seconds
Started Aug 18 05:50:28 PM PDT 24
Finished Aug 18 05:51:28 PM PDT 24
Peak memory 249412 kb
Host smart-17e5b820-4d07-4ae7-9ac4-8ffbd9a6bf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55184553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.55184553
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1509470877
Short name T252
Test name
Test status
Simulation time 46834726739 ps
CPU time 169.84 seconds
Started Aug 18 05:50:27 PM PDT 24
Finished Aug 18 05:53:17 PM PDT 24
Peak memory 254824 kb
Host smart-884a6d18-93ce-468b-b2a1-51a225d3a8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509470877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1509470877
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.250341183
Short name T593
Test name
Test status
Simulation time 263248155 ps
CPU time 7.34 seconds
Started Aug 18 05:50:34 PM PDT 24
Finished Aug 18 05:50:41 PM PDT 24
Peak memory 241036 kb
Host smart-f1adf941-f33c-4fcb-b9c9-434f5d49d52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250341183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.250341183
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.33674455
Short name T158
Test name
Test status
Simulation time 118836419566 ps
CPU time 116.74 seconds
Started Aug 18 05:50:32 PM PDT 24
Finished Aug 18 05:52:29 PM PDT 24
Peak memory 237248 kb
Host smart-9051c43b-9fd7-4b21-ae00-8e0c67dff66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33674455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.33674455
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.718439558
Short name T78
Test name
Test status
Simulation time 280950271 ps
CPU time 4.17 seconds
Started Aug 18 05:50:34 PM PDT 24
Finished Aug 18 05:50:39 PM PDT 24
Peak memory 233072 kb
Host smart-069061f1-715d-4719-9e73-a21899e2bd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718439558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.718439558
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3776431765
Short name T741
Test name
Test status
Simulation time 112390504 ps
CPU time 2.39 seconds
Started Aug 18 05:50:31 PM PDT 24
Finished Aug 18 05:50:34 PM PDT 24
Peak memory 232452 kb
Host smart-ed6cb883-1dd8-4549-9cde-4f64562cd3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776431765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3776431765
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1991488749
Short name T628
Test name
Test status
Simulation time 27600728640 ps
CPU time 20.97 seconds
Started Aug 18 05:50:33 PM PDT 24
Finished Aug 18 05:50:54 PM PDT 24
Peak memory 232880 kb
Host smart-08d8672a-d4ca-4ed4-856a-fb01ae962426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991488749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1991488749
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1985807546
Short name T408
Test name
Test status
Simulation time 205667309 ps
CPU time 3.43 seconds
Started Aug 18 05:50:34 PM PDT 24
Finished Aug 18 05:50:37 PM PDT 24
Peak memory 232852 kb
Host smart-8fedf5eb-2298-489d-bd3d-a7d7f6dc20ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985807546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1985807546
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3639786960
Short name T126
Test name
Test status
Simulation time 4240997944 ps
CPU time 11.93 seconds
Started Aug 18 05:50:31 PM PDT 24
Finished Aug 18 05:50:43 PM PDT 24
Peak memory 220076 kb
Host smart-2ec3aa02-f37a-43ee-b2bb-93ef76f9cc63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3639786960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3639786960
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.895249068
Short name T292
Test name
Test status
Simulation time 34390690994 ps
CPU time 150.98 seconds
Started Aug 18 05:50:33 PM PDT 24
Finished Aug 18 05:53:04 PM PDT 24
Peak memory 240456 kb
Host smart-a5e44072-e542-4bf3-a943-68fe73591a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895249068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.895249068
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.90873802
Short name T937
Test name
Test status
Simulation time 1372662005 ps
CPU time 5.15 seconds
Started Aug 18 05:50:29 PM PDT 24
Finished Aug 18 05:50:34 PM PDT 24
Peak memory 216496 kb
Host smart-d8cb6b4a-a3e7-4857-a676-57302fdfd447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90873802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.90873802
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1494597122
Short name T69
Test name
Test status
Simulation time 4003288144 ps
CPU time 9.16 seconds
Started Aug 18 05:50:36 PM PDT 24
Finished Aug 18 05:50:46 PM PDT 24
Peak memory 216468 kb
Host smart-8c52c460-9b8d-45d5-bf37-c083f78a5a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494597122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1494597122
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.499208653
Short name T318
Test name
Test status
Simulation time 146029830 ps
CPU time 1.67 seconds
Started Aug 18 05:50:29 PM PDT 24
Finished Aug 18 05:50:31 PM PDT 24
Peak memory 216400 kb
Host smart-d7f1a152-4dce-402e-84b4-37849c50f8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499208653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.499208653
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.147363793
Short name T627
Test name
Test status
Simulation time 85819138 ps
CPU time 0.84 seconds
Started Aug 18 05:50:43 PM PDT 24
Finished Aug 18 05:50:43 PM PDT 24
Peak memory 206088 kb
Host smart-dbd872b3-7252-445e-926b-ccd29e0e6257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147363793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.147363793
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.221826577
Short name T248
Test name
Test status
Simulation time 19207350110 ps
CPU time 15.84 seconds
Started Aug 18 05:50:30 PM PDT 24
Finished Aug 18 05:50:46 PM PDT 24
Peak memory 239996 kb
Host smart-18736af4-1490-4b77-9efc-b173ce3b47c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221826577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.221826577
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1175096389
Short name T832
Test name
Test status
Simulation time 12001094 ps
CPU time 0.7 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 204948 kb
Host smart-d53aecf7-d0d4-4d9e-929a-bdeec535601b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175096389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
175096389
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1796494577
Short name T672
Test name
Test status
Simulation time 148089566 ps
CPU time 2.41 seconds
Started Aug 18 05:49:02 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 232976 kb
Host smart-5fbeebc4-94e6-4318-9754-286f664c7e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796494577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1796494577
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3151560940
Short name T684
Test name
Test status
Simulation time 39133037 ps
CPU time 0.76 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:49:04 PM PDT 24
Peak memory 206556 kb
Host smart-de0fb164-c595-4a72-babd-d84509ae3e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151560940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3151560940
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3277512815
Short name T203
Test name
Test status
Simulation time 15650320494 ps
CPU time 57.69 seconds
Started Aug 18 05:49:00 PM PDT 24
Finished Aug 18 05:49:58 PM PDT 24
Peak memory 236988 kb
Host smart-db98556e-fca7-4312-90dc-152541a0a30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277512815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3277512815
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.673538957
Short name T458
Test name
Test status
Simulation time 40423027700 ps
CPU time 386.64 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:55:31 PM PDT 24
Peak memory 249320 kb
Host smart-4eab1464-63fb-4571-b595-eded63dc7a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673538957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.673538957
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.443236918
Short name T569
Test name
Test status
Simulation time 2879512248 ps
CPU time 71.82 seconds
Started Aug 18 05:49:02 PM PDT 24
Finished Aug 18 05:50:14 PM PDT 24
Peak memory 251732 kb
Host smart-7af7beee-606f-4663-876f-40cf90b36f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443236918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
443236918
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3039241763
Short name T170
Test name
Test status
Simulation time 6625976832 ps
CPU time 14.3 seconds
Started Aug 18 05:49:00 PM PDT 24
Finished Aug 18 05:49:15 PM PDT 24
Peak memory 232896 kb
Host smart-d75e152a-31ef-4aa7-b48b-13aea034bb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039241763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3039241763
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3828542397
Short name T427
Test name
Test status
Simulation time 783147436 ps
CPU time 10.1 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:49:13 PM PDT 24
Peak memory 228104 kb
Host smart-9735331b-c8f6-4693-9954-f4932582b64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828542397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3828542397
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1236014613
Short name T24
Test name
Test status
Simulation time 135828574 ps
CPU time 1.12 seconds
Started Aug 18 05:49:06 PM PDT 24
Finished Aug 18 05:49:08 PM PDT 24
Peak memory 216688 kb
Host smart-023b555f-8354-4ee9-88ee-9a5320bb4ef3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236014613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1236014613
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.77694024
Short name T343
Test name
Test status
Simulation time 300835676 ps
CPU time 4.81 seconds
Started Aug 18 05:48:59 PM PDT 24
Finished Aug 18 05:49:04 PM PDT 24
Peak memory 224580 kb
Host smart-a982e2be-5f9b-4fa1-af09-7de7a01e5c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77694024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.77694024
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1699090017
Short name T714
Test name
Test status
Simulation time 266060848 ps
CPU time 3.77 seconds
Started Aug 18 05:49:01 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 232844 kb
Host smart-a8ada6d0-0599-4170-94b4-08b8ada5b9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699090017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1699090017
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1440157836
Short name T411
Test name
Test status
Simulation time 407341652 ps
CPU time 3.39 seconds
Started Aug 18 05:49:02 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 219240 kb
Host smart-352715d9-98fd-41a9-a9f2-ce7f132f4c49
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1440157836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1440157836
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1172854339
Short name T59
Test name
Test status
Simulation time 378284776 ps
CPU time 1.18 seconds
Started Aug 18 05:48:58 PM PDT 24
Finished Aug 18 05:48:59 PM PDT 24
Peak memory 235572 kb
Host smart-73c2da58-5c4b-494a-88c3-65be1a54a72d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172854339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1172854339
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2580070537
Short name T801
Test name
Test status
Simulation time 7578086010 ps
CPU time 36 seconds
Started Aug 18 05:49:01 PM PDT 24
Finished Aug 18 05:49:37 PM PDT 24
Peak memory 216504 kb
Host smart-d5e05f73-761e-40ae-8869-8fc6d22b7f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580070537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2580070537
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4117752849
Short name T300
Test name
Test status
Simulation time 1952303296 ps
CPU time 9.83 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:14 PM PDT 24
Peak memory 216476 kb
Host smart-4db0c40a-1d0f-4929-a662-1de2bdae0ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117752849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4117752849
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3938504081
Short name T596
Test name
Test status
Simulation time 116804117 ps
CPU time 1.98 seconds
Started Aug 18 05:48:59 PM PDT 24
Finished Aug 18 05:49:01 PM PDT 24
Peak memory 216396 kb
Host smart-dbec5537-ae12-4ca0-8080-85c88cd4dd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938504081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3938504081
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1568518010
Short name T403
Test name
Test status
Simulation time 94473138 ps
CPU time 0.69 seconds
Started Aug 18 05:49:10 PM PDT 24
Finished Aug 18 05:49:11 PM PDT 24
Peak memory 206096 kb
Host smart-651cc13c-17f2-4144-9172-498c66457f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568518010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1568518010
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.580017540
Short name T891
Test name
Test status
Simulation time 1022758955 ps
CPU time 7.63 seconds
Started Aug 18 05:49:02 PM PDT 24
Finished Aug 18 05:49:09 PM PDT 24
Peak memory 240624 kb
Host smart-bd0fab86-dfef-4a58-8a9e-4c1e975bea85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580017540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.580017540
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3950034849
Short name T1027
Test name
Test status
Simulation time 39263307 ps
CPU time 0.7 seconds
Started Aug 18 05:50:40 PM PDT 24
Finished Aug 18 05:50:40 PM PDT 24
Peak memory 205536 kb
Host smart-ac765ca5-ef60-4102-92e5-1be6bbcd6a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950034849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3950034849
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1931497082
Short name T563
Test name
Test status
Simulation time 373524573 ps
CPU time 2.48 seconds
Started Aug 18 05:50:31 PM PDT 24
Finished Aug 18 05:50:33 PM PDT 24
Peak memory 224676 kb
Host smart-525ac7fe-166b-482b-a95b-5352b325cd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931497082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1931497082
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2788456811
Short name T293
Test name
Test status
Simulation time 21645192 ps
CPU time 0.81 seconds
Started Aug 18 05:50:36 PM PDT 24
Finished Aug 18 05:50:37 PM PDT 24
Peak memory 206516 kb
Host smart-23fc0e1a-b5c7-4bf2-968e-8d715e6f49e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788456811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2788456811
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3071704144
Short name T534
Test name
Test status
Simulation time 539847079 ps
CPU time 8.12 seconds
Started Aug 18 05:50:27 PM PDT 24
Finished Aug 18 05:50:35 PM PDT 24
Peak memory 232760 kb
Host smart-b9591f03-1894-4379-9669-25b5e70c4b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071704144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3071704144
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2167751780
Short name T1001
Test name
Test status
Simulation time 11658087614 ps
CPU time 98.05 seconds
Started Aug 18 05:50:35 PM PDT 24
Finished Aug 18 05:52:13 PM PDT 24
Peak memory 235648 kb
Host smart-d10390bd-8e95-49c0-a54b-a2e40bf11764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167751780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2167751780
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1912428956
Short name T43
Test name
Test status
Simulation time 98268775745 ps
CPU time 455 seconds
Started Aug 18 05:50:44 PM PDT 24
Finished Aug 18 05:58:19 PM PDT 24
Peak memory 253036 kb
Host smart-a3bf2f5b-97e4-4f7e-8ab1-cdfe92310245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912428956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1912428956
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1729379885
Short name T842
Test name
Test status
Simulation time 1039232903 ps
CPU time 11.27 seconds
Started Aug 18 05:50:32 PM PDT 24
Finished Aug 18 05:50:44 PM PDT 24
Peak memory 224620 kb
Host smart-ce6e5791-d547-4b93-9904-1ddf963b6475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729379885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1729379885
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.4110932419
Short name T694
Test name
Test status
Simulation time 36302920101 ps
CPU time 247.03 seconds
Started Aug 18 05:50:34 PM PDT 24
Finished Aug 18 05:54:41 PM PDT 24
Peak memory 256236 kb
Host smart-529c2c83-9972-449d-a696-3b4d9f5a1af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110932419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.4110932419
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.461342091
Short name T856
Test name
Test status
Simulation time 2621162185 ps
CPU time 18.77 seconds
Started Aug 18 05:50:34 PM PDT 24
Finished Aug 18 05:50:53 PM PDT 24
Peak memory 232944 kb
Host smart-2a587390-7cdc-4e95-9b35-3aec5ce53262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461342091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.461342091
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4190687471
Short name T1008
Test name
Test status
Simulation time 537974853 ps
CPU time 9.95 seconds
Started Aug 18 05:50:35 PM PDT 24
Finished Aug 18 05:50:45 PM PDT 24
Peak memory 240852 kb
Host smart-5483bd7b-e4d3-4168-be47-07789e713c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190687471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4190687471
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3996644695
Short name T914
Test name
Test status
Simulation time 652597573 ps
CPU time 6.26 seconds
Started Aug 18 05:50:38 PM PDT 24
Finished Aug 18 05:50:45 PM PDT 24
Peak memory 240104 kb
Host smart-c95295d2-4c99-4073-8813-3a47fab06ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996644695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3996644695
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1502378520
Short name T766
Test name
Test status
Simulation time 1488144356 ps
CPU time 3.43 seconds
Started Aug 18 05:50:34 PM PDT 24
Finished Aug 18 05:50:38 PM PDT 24
Peak memory 233024 kb
Host smart-1b206823-7904-4526-9e93-0520027df650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502378520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1502378520
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3475684953
Short name T544
Test name
Test status
Simulation time 1183883733 ps
CPU time 6.6 seconds
Started Aug 18 05:50:38 PM PDT 24
Finished Aug 18 05:50:45 PM PDT 24
Peak memory 223248 kb
Host smart-36c5a612-67b6-4e75-9c0a-72bea19afcdf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3475684953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3475684953
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3118461364
Short name T179
Test name
Test status
Simulation time 37932530397 ps
CPU time 93.35 seconds
Started Aug 18 05:50:31 PM PDT 24
Finished Aug 18 05:52:05 PM PDT 24
Peak memory 250748 kb
Host smart-6737c941-5399-4969-9b6b-aef756568086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118461364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3118461364
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2912103811
Short name T634
Test name
Test status
Simulation time 10754114269 ps
CPU time 19.93 seconds
Started Aug 18 05:50:39 PM PDT 24
Finished Aug 18 05:50:59 PM PDT 24
Peak memory 216492 kb
Host smart-5cbb2960-0731-41db-81fa-cb4095520558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912103811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2912103811
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3828377532
Short name T535
Test name
Test status
Simulation time 126663518 ps
CPU time 1.26 seconds
Started Aug 18 05:50:34 PM PDT 24
Finished Aug 18 05:50:35 PM PDT 24
Peak memory 207868 kb
Host smart-4cd233e8-6ae0-403d-a492-20224d1894b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828377532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3828377532
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1670364479
Short name T718
Test name
Test status
Simulation time 254389539 ps
CPU time 1.39 seconds
Started Aug 18 05:50:27 PM PDT 24
Finished Aug 18 05:50:29 PM PDT 24
Peak memory 216428 kb
Host smart-36b38916-ba0d-483c-becb-05530106a960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670364479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1670364479
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1604623460
Short name T993
Test name
Test status
Simulation time 175568420 ps
CPU time 0.82 seconds
Started Aug 18 05:50:37 PM PDT 24
Finished Aug 18 05:50:37 PM PDT 24
Peak memory 206092 kb
Host smart-b9897dd2-778e-46f1-9881-4d1b90f24272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604623460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1604623460
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2354795052
Short name T759
Test name
Test status
Simulation time 3037493267 ps
CPU time 8.61 seconds
Started Aug 18 05:50:38 PM PDT 24
Finished Aug 18 05:50:47 PM PDT 24
Peak memory 232872 kb
Host smart-16cabab9-0e4a-4750-bca5-a2e8c7bb0ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354795052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2354795052
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1663519981
Short name T732
Test name
Test status
Simulation time 24281691 ps
CPU time 0.75 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:50:49 PM PDT 24
Peak memory 205764 kb
Host smart-afb4aa33-dcf0-4dda-9fcd-67d758bb81d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663519981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1663519981
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.323387724
Short name T165
Test name
Test status
Simulation time 208435806 ps
CPU time 4 seconds
Started Aug 18 05:50:47 PM PDT 24
Finished Aug 18 05:50:51 PM PDT 24
Peak memory 232808 kb
Host smart-30e96b78-3e66-48bc-bd9c-1cb11a23fd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323387724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.323387724
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3313872114
Short name T724
Test name
Test status
Simulation time 19056951 ps
CPU time 0.79 seconds
Started Aug 18 05:50:39 PM PDT 24
Finished Aug 18 05:50:40 PM PDT 24
Peak memory 205592 kb
Host smart-561aad19-47cc-47d0-8757-9a14cc91c6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313872114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3313872114
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1113970117
Short name T605
Test name
Test status
Simulation time 1177782761 ps
CPU time 23.54 seconds
Started Aug 18 05:50:45 PM PDT 24
Finished Aug 18 05:51:09 PM PDT 24
Peak memory 252384 kb
Host smart-6bb31511-cb4b-4f00-9345-0283b3180100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113970117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1113970117
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1011733496
Short name T455
Test name
Test status
Simulation time 15741367254 ps
CPU time 76.07 seconds
Started Aug 18 05:50:41 PM PDT 24
Finished Aug 18 05:51:57 PM PDT 24
Peak memory 249496 kb
Host smart-56869ab7-b802-42dd-8b06-bcc53065f1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011733496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1011733496
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3201309186
Short name T436
Test name
Test status
Simulation time 27442775463 ps
CPU time 125.97 seconds
Started Aug 18 05:50:47 PM PDT 24
Finished Aug 18 05:52:53 PM PDT 24
Peak memory 249372 kb
Host smart-1900e660-545f-431f-ab7b-a3dc12842902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201309186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3201309186
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2808586078
Short name T272
Test name
Test status
Simulation time 154662961 ps
CPU time 4.85 seconds
Started Aug 18 05:50:49 PM PDT 24
Finished Aug 18 05:50:54 PM PDT 24
Peak memory 224668 kb
Host smart-2f181a83-2a88-4351-9815-17a8e6d2b4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808586078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2808586078
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.232036428
Short name T384
Test name
Test status
Simulation time 30777192 ps
CPU time 0.83 seconds
Started Aug 18 05:50:46 PM PDT 24
Finished Aug 18 05:50:47 PM PDT 24
Peak memory 215828 kb
Host smart-679f53a2-8743-482f-974d-f3084f5ea982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232036428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.232036428
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.965605762
Short name T710
Test name
Test status
Simulation time 5130061289 ps
CPU time 13.18 seconds
Started Aug 18 05:50:43 PM PDT 24
Finished Aug 18 05:50:56 PM PDT 24
Peak memory 224684 kb
Host smart-fa4e5444-faaf-482f-8f96-5fc62baba537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965605762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.965605762
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2497878718
Short name T565
Test name
Test status
Simulation time 1997065872 ps
CPU time 2.25 seconds
Started Aug 18 05:50:37 PM PDT 24
Finished Aug 18 05:50:39 PM PDT 24
Peak memory 223020 kb
Host smart-de4cb098-809a-47d6-80cd-b38bcf26beca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497878718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2497878718
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.407284557
Short name T235
Test name
Test status
Simulation time 984517200 ps
CPU time 5.54 seconds
Started Aug 18 05:50:41 PM PDT 24
Finished Aug 18 05:50:47 PM PDT 24
Peak memory 232780 kb
Host smart-304968a5-3305-4f85-8880-c9dab4754b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407284557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.407284557
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.845367970
Short name T905
Test name
Test status
Simulation time 33076495 ps
CPU time 2.17 seconds
Started Aug 18 05:50:39 PM PDT 24
Finished Aug 18 05:50:41 PM PDT 24
Peak memory 232428 kb
Host smart-9d53d8f5-dbb8-4b84-8f88-f61b04554166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845367970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.845367970
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1895233768
Short name T326
Test name
Test status
Simulation time 238043180 ps
CPU time 5.23 seconds
Started Aug 18 05:50:37 PM PDT 24
Finished Aug 18 05:50:42 PM PDT 24
Peak memory 222676 kb
Host smart-5822967e-654a-4f4a-8ea2-03473eb64207
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1895233768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1895233768
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2213028829
Short name T140
Test name
Test status
Simulation time 147510329082 ps
CPU time 278.42 seconds
Started Aug 18 05:50:36 PM PDT 24
Finished Aug 18 05:55:14 PM PDT 24
Peak memory 249328 kb
Host smart-1b23c077-c6d9-4f3b-9f8f-95ef14dafbef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213028829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2213028829
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.910122850
Short name T393
Test name
Test status
Simulation time 62366055 ps
CPU time 0.75 seconds
Started Aug 18 05:50:36 PM PDT 24
Finished Aug 18 05:50:37 PM PDT 24
Peak memory 204720 kb
Host smart-5a7553e3-a78d-443c-bc9b-aac19cf77dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910122850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.910122850
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3216826239
Short name T396
Test name
Test status
Simulation time 4018763179 ps
CPU time 6.97 seconds
Started Aug 18 05:50:40 PM PDT 24
Finished Aug 18 05:50:47 PM PDT 24
Peak memory 216488 kb
Host smart-56f038ac-5171-47de-bab6-3cd569e18409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216826239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3216826239
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3223443442
Short name T963
Test name
Test status
Simulation time 695737354 ps
CPU time 1.72 seconds
Started Aug 18 05:50:37 PM PDT 24
Finished Aug 18 05:50:39 PM PDT 24
Peak memory 216468 kb
Host smart-ba389ec8-ff6a-47d9-89db-a9de39cd6d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223443442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3223443442
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3321209240
Short name T467
Test name
Test status
Simulation time 190228797 ps
CPU time 0.84 seconds
Started Aug 18 05:50:37 PM PDT 24
Finished Aug 18 05:50:38 PM PDT 24
Peak memory 206092 kb
Host smart-34281d4b-62bd-4fd6-a374-d1320628627d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321209240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3321209240
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3502666271
Short name T773
Test name
Test status
Simulation time 1110401259 ps
CPU time 8.86 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:50:57 PM PDT 24
Peak memory 232872 kb
Host smart-ad623243-eca8-4519-8f3f-04d411150385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502666271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3502666271
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.881388644
Short name T320
Test name
Test status
Simulation time 18312481 ps
CPU time 0.76 seconds
Started Aug 18 05:50:42 PM PDT 24
Finished Aug 18 05:50:43 PM PDT 24
Peak memory 204892 kb
Host smart-00e2b906-bd9d-465a-bba3-dc08a888819c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881388644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.881388644
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2213937481
Short name T668
Test name
Test status
Simulation time 320348239 ps
CPU time 4.91 seconds
Started Aug 18 05:50:40 PM PDT 24
Finished Aug 18 05:50:45 PM PDT 24
Peak memory 232832 kb
Host smart-1c4b2273-82fc-4d2c-a1ee-981e2b734711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213937481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2213937481
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1241893678
Short name T329
Test name
Test status
Simulation time 27701360 ps
CPU time 0.77 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:50:51 PM PDT 24
Peak memory 205856 kb
Host smart-d5829fe2-c3ec-4810-b31d-487c1ee83091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241893678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1241893678
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2652850988
Short name T373
Test name
Test status
Simulation time 15235983887 ps
CPU time 53.23 seconds
Started Aug 18 05:50:39 PM PDT 24
Finished Aug 18 05:51:32 PM PDT 24
Peak memory 252404 kb
Host smart-4a4d6ab7-278f-4124-a696-643e8caadb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652850988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2652850988
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3875537310
Short name T1011
Test name
Test status
Simulation time 22457383709 ps
CPU time 212.05 seconds
Started Aug 18 05:50:44 PM PDT 24
Finished Aug 18 05:54:16 PM PDT 24
Peak memory 249344 kb
Host smart-bc486ec5-7086-469c-8ffc-874be795ffb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875537310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3875537310
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4144079516
Short name T280
Test name
Test status
Simulation time 1535657491 ps
CPU time 24.12 seconds
Started Aug 18 05:50:45 PM PDT 24
Finished Aug 18 05:51:09 PM PDT 24
Peak memory 249204 kb
Host smart-10586049-69d4-4e9e-9da1-87dc846b73e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144079516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4144079516
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4129649713
Short name T632
Test name
Test status
Simulation time 237926863 ps
CPU time 3.39 seconds
Started Aug 18 05:50:44 PM PDT 24
Finished Aug 18 05:50:48 PM PDT 24
Peak memory 224620 kb
Host smart-3ff1bbec-18f2-4cdd-b305-ce562a68158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129649713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4129649713
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4024853506
Short name T608
Test name
Test status
Simulation time 18326126413 ps
CPU time 41.26 seconds
Started Aug 18 05:50:46 PM PDT 24
Finished Aug 18 05:51:27 PM PDT 24
Peak memory 224640 kb
Host smart-2a00151b-1005-4788-a7b2-73dcf754e762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024853506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4024853506
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2432050981
Short name T952
Test name
Test status
Simulation time 4651814265 ps
CPU time 10.51 seconds
Started Aug 18 05:50:40 PM PDT 24
Finished Aug 18 05:50:51 PM PDT 24
Peak memory 241016 kb
Host smart-99976ca2-86f6-4df6-9346-ee2382ed424a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432050981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2432050981
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.570163955
Short name T960
Test name
Test status
Simulation time 824702006 ps
CPU time 7.99 seconds
Started Aug 18 05:50:40 PM PDT 24
Finished Aug 18 05:50:48 PM PDT 24
Peak memory 249216 kb
Host smart-6f941ca8-942c-4723-ae1e-2a379594a9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570163955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.570163955
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1222636748
Short name T625
Test name
Test status
Simulation time 4145246019 ps
CPU time 21.83 seconds
Started Aug 18 05:50:35 PM PDT 24
Finished Aug 18 05:50:57 PM PDT 24
Peak memory 219440 kb
Host smart-a90eaca6-945c-4c7d-93dd-37345d9ae24f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1222636748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1222636748
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2127062416
Short name T1017
Test name
Test status
Simulation time 38578570076 ps
CPU time 213.87 seconds
Started Aug 18 05:50:38 PM PDT 24
Finished Aug 18 05:54:12 PM PDT 24
Peak memory 252608 kb
Host smart-2efd8f80-b4fe-445e-b6fe-fe599cdca056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127062416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2127062416
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.927775609
Short name T506
Test name
Test status
Simulation time 486056984 ps
CPU time 3.69 seconds
Started Aug 18 05:50:42 PM PDT 24
Finished Aug 18 05:50:46 PM PDT 24
Peak memory 216436 kb
Host smart-09e574c8-64c7-4e93-afdd-f09b4e34d3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927775609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.927775609
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2665464624
Short name T698
Test name
Test status
Simulation time 48624334 ps
CPU time 0.71 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:50:51 PM PDT 24
Peak memory 205688 kb
Host smart-2120dabe-be76-46b3-8a15-ec5069be4773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665464624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2665464624
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2195308037
Short name T863
Test name
Test status
Simulation time 34438167 ps
CPU time 1.74 seconds
Started Aug 18 05:50:44 PM PDT 24
Finished Aug 18 05:50:46 PM PDT 24
Peak memory 216460 kb
Host smart-3def84d6-2a9f-4645-ab0b-a09ed646fec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195308037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2195308037
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.332523832
Short name T500
Test name
Test status
Simulation time 79415592 ps
CPU time 0.91 seconds
Started Aug 18 05:50:46 PM PDT 24
Finished Aug 18 05:50:48 PM PDT 24
Peak memory 206084 kb
Host smart-7cfa146f-9ce2-4a0e-9d33-4bb2fafbb82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332523832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.332523832
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3949118080
Short name T365
Test name
Test status
Simulation time 107780668 ps
CPU time 2.14 seconds
Started Aug 18 05:50:57 PM PDT 24
Finished Aug 18 05:51:00 PM PDT 24
Peak memory 224212 kb
Host smart-eabfce97-57cb-4ec0-8921-105dd15b1b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949118080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3949118080
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4012333294
Short name T868
Test name
Test status
Simulation time 45762583 ps
CPU time 0.71 seconds
Started Aug 18 05:50:47 PM PDT 24
Finished Aug 18 05:50:48 PM PDT 24
Peak memory 205516 kb
Host smart-7200693c-aed8-479c-9ab2-94f5226de7a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012333294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4012333294
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.329501000
Short name T943
Test name
Test status
Simulation time 1600397613 ps
CPU time 9.53 seconds
Started Aug 18 05:50:47 PM PDT 24
Finished Aug 18 05:50:57 PM PDT 24
Peak memory 224568 kb
Host smart-089b3adf-a5d2-4d75-8ea4-ef5c3d098f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329501000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.329501000
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1870387574
Short name T660
Test name
Test status
Simulation time 101634029 ps
CPU time 0.76 seconds
Started Aug 18 05:50:56 PM PDT 24
Finished Aug 18 05:50:57 PM PDT 24
Peak memory 205860 kb
Host smart-2ff18ce3-d2d4-4142-b6fd-cd266e1be177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870387574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1870387574
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.758028600
Short name T443
Test name
Test status
Simulation time 3554785896 ps
CPU time 43.84 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:51:36 PM PDT 24
Peak memory 253564 kb
Host smart-b10c97d1-4c18-4abf-b019-74e877a11283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758028600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.758028600
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1704035280
Short name T893
Test name
Test status
Simulation time 13789301358 ps
CPU time 124.15 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:52:52 PM PDT 24
Peak memory 232996 kb
Host smart-f78858f7-f6ac-49c7-8892-09414cd15101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704035280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1704035280
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.303356789
Short name T796
Test name
Test status
Simulation time 332657554435 ps
CPU time 264.24 seconds
Started Aug 18 05:50:46 PM PDT 24
Finished Aug 18 05:55:11 PM PDT 24
Peak memory 254988 kb
Host smart-a4a9cff5-e96c-41c6-98d7-6ec5a7f80e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303356789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.303356789
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.865796281
Short name T61
Test name
Test status
Simulation time 2447369086 ps
CPU time 35.78 seconds
Started Aug 18 05:50:41 PM PDT 24
Finished Aug 18 05:51:17 PM PDT 24
Peak memory 232900 kb
Host smart-a7441aa5-bb12-416e-922e-f57cd6b512bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865796281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.865796281
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1712563338
Short name T898
Test name
Test status
Simulation time 26783155874 ps
CPU time 58.65 seconds
Started Aug 18 05:50:53 PM PDT 24
Finished Aug 18 05:51:51 PM PDT 24
Peak memory 256480 kb
Host smart-59140553-e50b-41ea-b9cb-e5544772153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712563338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1712563338
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4001802462
Short name T970
Test name
Test status
Simulation time 10155768292 ps
CPU time 18.63 seconds
Started Aug 18 05:50:39 PM PDT 24
Finished Aug 18 05:50:58 PM PDT 24
Peak memory 232888 kb
Host smart-db5580c7-b100-4294-93b1-f65e79f58ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001802462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4001802462
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1826351422
Short name T81
Test name
Test status
Simulation time 7438929266 ps
CPU time 43.87 seconds
Started Aug 18 05:50:45 PM PDT 24
Finished Aug 18 05:51:29 PM PDT 24
Peak memory 240844 kb
Host smart-ba67128f-ba25-4234-896e-3f1b26a1030b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826351422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1826351422
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2585024831
Short name T237
Test name
Test status
Simulation time 24387450581 ps
CPU time 35.98 seconds
Started Aug 18 05:50:47 PM PDT 24
Finished Aug 18 05:51:24 PM PDT 24
Peak memory 233900 kb
Host smart-9c298ecb-57bd-4d82-b402-63782006a01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585024831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2585024831
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.576744375
Short name T527
Test name
Test status
Simulation time 18285904923 ps
CPU time 17 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:51:09 PM PDT 24
Peak memory 235700 kb
Host smart-5aec623b-3468-4243-baf7-4b1d6e71be88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576744375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.576744375
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2512188430
Short name T1007
Test name
Test status
Simulation time 960163508 ps
CPU time 8.4 seconds
Started Aug 18 05:50:49 PM PDT 24
Finished Aug 18 05:50:58 PM PDT 24
Peak memory 222608 kb
Host smart-55980e5e-4983-4008-bbc6-2f077eb5650f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2512188430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2512188430
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1214109643
Short name T137
Test name
Test status
Simulation time 24573484151 ps
CPU time 77.17 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:52:05 PM PDT 24
Peak memory 249436 kb
Host smart-c8e82a6e-efb8-41b6-88f4-2790f25999b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214109643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1214109643
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2770391522
Short name T287
Test name
Test status
Simulation time 24138463388 ps
CPU time 33.37 seconds
Started Aug 18 05:50:38 PM PDT 24
Finished Aug 18 05:51:12 PM PDT 24
Peak memory 217788 kb
Host smart-c6c6d02e-f7d0-40cb-bca0-0d4f2821246c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770391522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2770391522
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.254809530
Short name T481
Test name
Test status
Simulation time 11774757252 ps
CPU time 12.06 seconds
Started Aug 18 05:50:53 PM PDT 24
Finished Aug 18 05:51:06 PM PDT 24
Peak memory 216504 kb
Host smart-307845a2-c3a6-4b37-9df3-00171dc0f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254809530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.254809530
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3304898269
Short name T340
Test name
Test status
Simulation time 24328801 ps
CPU time 0.91 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:50:51 PM PDT 24
Peak memory 206768 kb
Host smart-f340855a-57d4-41ab-9ff9-35f499ced2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304898269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3304898269
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1245242346
Short name T737
Test name
Test status
Simulation time 316171604 ps
CPU time 1.08 seconds
Started Aug 18 05:50:38 PM PDT 24
Finished Aug 18 05:50:39 PM PDT 24
Peak memory 206444 kb
Host smart-64da7091-9fcb-4baa-a581-941315dab4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245242346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1245242346
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2501303867
Short name T906
Test name
Test status
Simulation time 10844682306 ps
CPU time 33.26 seconds
Started Aug 18 05:50:39 PM PDT 24
Finished Aug 18 05:51:12 PM PDT 24
Peak memory 241056 kb
Host smart-483dd497-23d8-401c-ab64-ca169cb24cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501303867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2501303867
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2973607790
Short name T484
Test name
Test status
Simulation time 45084922 ps
CPU time 0.69 seconds
Started Aug 18 05:50:47 PM PDT 24
Finished Aug 18 05:50:48 PM PDT 24
Peak memory 205528 kb
Host smart-3334275f-4ccf-4fff-8623-3c712584d64e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973607790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2973607790
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.580698951
Short name T840
Test name
Test status
Simulation time 899822040 ps
CPU time 10.19 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:51:00 PM PDT 24
Peak memory 232824 kb
Host smart-f8b5038e-08bf-4eae-93d2-199d752b7549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580698951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.580698951
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4155169956
Short name T416
Test name
Test status
Simulation time 182979070 ps
CPU time 0.75 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:50:49 PM PDT 24
Peak memory 206592 kb
Host smart-da5b1782-8bc2-4ff5-af61-eab618c51d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155169956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4155169956
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1095126720
Short name T861
Test name
Test status
Simulation time 2099810516 ps
CPU time 14.32 seconds
Started Aug 18 05:50:54 PM PDT 24
Finished Aug 18 05:51:08 PM PDT 24
Peak memory 235468 kb
Host smart-ef568ff8-e2c5-4ffd-9045-cf0f342749b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095126720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1095126720
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2844414349
Short name T161
Test name
Test status
Simulation time 199730086310 ps
CPU time 262.85 seconds
Started Aug 18 05:50:45 PM PDT 24
Finished Aug 18 05:55:08 PM PDT 24
Peak memory 249396 kb
Host smart-d02d0344-8cc3-491a-9d21-b5f654c1a0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844414349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2844414349
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2497863329
Short name T75
Test name
Test status
Simulation time 20803431915 ps
CPU time 160.68 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:53:31 PM PDT 24
Peak memory 253104 kb
Host smart-46b04516-0a3f-484a-9c2d-e8fe6b38ee64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497863329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2497863329
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1168439534
Short name T939
Test name
Test status
Simulation time 915136502 ps
CPU time 5.57 seconds
Started Aug 18 05:50:47 PM PDT 24
Finished Aug 18 05:50:52 PM PDT 24
Peak memory 232816 kb
Host smart-c1c19b25-604e-4b20-9535-1ce325eb872c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168439534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1168439534
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3946211823
Short name T173
Test name
Test status
Simulation time 104198821062 ps
CPU time 388.42 seconds
Started Aug 18 05:50:51 PM PDT 24
Finished Aug 18 05:57:20 PM PDT 24
Peak memory 265892 kb
Host smart-47be629d-02b5-43c4-86c0-783d160936e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946211823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3946211823
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2522078925
Short name T709
Test name
Test status
Simulation time 2017790966 ps
CPU time 8.27 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:50:58 PM PDT 24
Peak memory 224632 kb
Host smart-57ff9350-baab-4df2-b7a9-55fad7d00b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522078925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2522078925
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3183696016
Short name T592
Test name
Test status
Simulation time 776618415 ps
CPU time 6.23 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:50:54 PM PDT 24
Peak memory 232824 kb
Host smart-df46b46e-8fc7-4d09-a072-6937005a32f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183696016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3183696016
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2798079563
Short name T459
Test name
Test status
Simulation time 71069800 ps
CPU time 2.48 seconds
Started Aug 18 05:50:46 PM PDT 24
Finished Aug 18 05:50:49 PM PDT 24
Peak memory 232468 kb
Host smart-1f703b80-619e-473b-9ba2-eabaadbfbd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798079563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2798079563
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3131644939
Short name T744
Test name
Test status
Simulation time 36433025017 ps
CPU time 29.79 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:51:22 PM PDT 24
Peak memory 232896 kb
Host smart-4fc1c614-62d9-42c3-93ad-b2ed610ad0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131644939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3131644939
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1593057004
Short name T361
Test name
Test status
Simulation time 1052708610 ps
CPU time 4.74 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:50:56 PM PDT 24
Peak memory 220364 kb
Host smart-65f2fe66-3b32-45bb-b70c-d6c81307f877
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1593057004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1593057004
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3346588921
Short name T546
Test name
Test status
Simulation time 58686552 ps
CPU time 1.01 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:50:51 PM PDT 24
Peak memory 215908 kb
Host smart-152c19f7-9e39-49fb-9b49-563757b3bd43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346588921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3346588921
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3866386781
Short name T281
Test name
Test status
Simulation time 5610736885 ps
CPU time 34.32 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:51:24 PM PDT 24
Peak memory 216520 kb
Host smart-a19561cf-b40b-4a1f-be68-31792729b6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866386781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3866386781
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.231874089
Short name T636
Test name
Test status
Simulation time 1004983818 ps
CPU time 7.3 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:50:59 PM PDT 24
Peak memory 216372 kb
Host smart-6fe2d0e4-c981-4918-b5b3-79965acaa6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231874089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.231874089
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1762930431
Short name T14
Test name
Test status
Simulation time 261402421 ps
CPU time 2.27 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:50:50 PM PDT 24
Peak memory 216488 kb
Host smart-ae24b5d9-8cc6-4ae8-80d7-bbbd697f8226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762930431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1762930431
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3270509049
Short name T314
Test name
Test status
Simulation time 282176220 ps
CPU time 0.9 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:50:49 PM PDT 24
Peak memory 206428 kb
Host smart-e013ff2d-ac25-4ff7-9e78-b1f7df180a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270509049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3270509049
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1957184722
Short name T231
Test name
Test status
Simulation time 4099133157 ps
CPU time 11.92 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:51:00 PM PDT 24
Peak memory 219264 kb
Host smart-203bae8a-d9f6-45bd-bcd9-87f72cf5586f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957184722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1957184722
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2821770207
Short name T363
Test name
Test status
Simulation time 14128856 ps
CPU time 0.74 seconds
Started Aug 18 05:50:51 PM PDT 24
Finished Aug 18 05:50:52 PM PDT 24
Peak memory 205484 kb
Host smart-7887fdb1-a4ef-424c-9aa3-012f419c27d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821770207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2821770207
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.183082070
Short name T965
Test name
Test status
Simulation time 178634391 ps
CPU time 3.09 seconds
Started Aug 18 05:50:47 PM PDT 24
Finished Aug 18 05:50:50 PM PDT 24
Peak memory 232820 kb
Host smart-1a1f24e0-3e53-4b53-9e7c-c1e06bc41184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183082070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.183082070
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1161134995
Short name T389
Test name
Test status
Simulation time 20477971 ps
CPU time 0.76 seconds
Started Aug 18 05:50:49 PM PDT 24
Finished Aug 18 05:50:49 PM PDT 24
Peak memory 206536 kb
Host smart-0341fe61-4d6e-4248-8ccb-3852824f201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161134995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1161134995
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3738497922
Short name T453
Test name
Test status
Simulation time 3088287574 ps
CPU time 27.97 seconds
Started Aug 18 05:50:51 PM PDT 24
Finished Aug 18 05:51:19 PM PDT 24
Peak memory 240340 kb
Host smart-f25aee22-9dc8-4f29-aaf8-fbb4c2fae390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738497922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3738497922
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3472098806
Short name T512
Test name
Test status
Simulation time 7890346580 ps
CPU time 65.1 seconds
Started Aug 18 05:51:02 PM PDT 24
Finished Aug 18 05:52:07 PM PDT 24
Peak memory 251480 kb
Host smart-5ea10996-9109-472b-9885-d04fe4763a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472098806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3472098806
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.268729829
Short name T491
Test name
Test status
Simulation time 1423292178 ps
CPU time 24.19 seconds
Started Aug 18 05:51:01 PM PDT 24
Finished Aug 18 05:51:25 PM PDT 24
Peak memory 238532 kb
Host smart-ac66474f-f74f-4b7c-883e-923f57fe05d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268729829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.268729829
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1750172784
Short name T711
Test name
Test status
Simulation time 20102051226 ps
CPU time 65.09 seconds
Started Aug 18 05:51:06 PM PDT 24
Finished Aug 18 05:52:11 PM PDT 24
Peak memory 236224 kb
Host smart-8a58b20f-99f1-46f1-8772-2d56527b3fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750172784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1750172784
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.4280610573
Short name T813
Test name
Test status
Simulation time 84806012633 ps
CPU time 180.77 seconds
Started Aug 18 05:51:03 PM PDT 24
Finished Aug 18 05:54:04 PM PDT 24
Peak memory 254168 kb
Host smart-63a3deab-d685-40ac-bc55-40e6890622da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280610573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.4280610573
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2656819500
Short name T620
Test name
Test status
Simulation time 2215919396 ps
CPU time 7.91 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:50:59 PM PDT 24
Peak memory 224728 kb
Host smart-3babc2a2-2aac-4e7c-9e56-4960bbc3164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656819500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2656819500
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3372978572
Short name T444
Test name
Test status
Simulation time 20226733103 ps
CPU time 53.11 seconds
Started Aug 18 05:50:51 PM PDT 24
Finished Aug 18 05:51:45 PM PDT 24
Peak memory 239396 kb
Host smart-c23a3113-d583-4257-8cce-8bb11c7394c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372978572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3372978572
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1137666141
Short name T181
Test name
Test status
Simulation time 904268254 ps
CPU time 3.04 seconds
Started Aug 18 05:50:51 PM PDT 24
Finished Aug 18 05:50:55 PM PDT 24
Peak memory 232868 kb
Host smart-1bef6074-fde8-4a9a-a7c6-4a897ef0055b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137666141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1137666141
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3724158250
Short name T311
Test name
Test status
Simulation time 646319334 ps
CPU time 2.28 seconds
Started Aug 18 05:50:53 PM PDT 24
Finished Aug 18 05:50:55 PM PDT 24
Peak memory 223824 kb
Host smart-fe259968-3617-4252-b25e-fe8b6be4707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724158250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3724158250
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3116743271
Short name T548
Test name
Test status
Simulation time 142254703 ps
CPU time 4.57 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:50:53 PM PDT 24
Peak memory 223176 kb
Host smart-80b675ec-7b4d-4200-b8f5-2ec8cf51b4b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3116743271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3116743271
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3511618518
Short name T17
Test name
Test status
Simulation time 10886962080 ps
CPU time 37.49 seconds
Started Aug 18 05:50:47 PM PDT 24
Finished Aug 18 05:51:25 PM PDT 24
Peak memory 232960 kb
Host smart-d13be772-f162-4916-a744-8da508708bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511618518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3511618518
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.439780658
Short name T928
Test name
Test status
Simulation time 3569671747 ps
CPU time 10.51 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:50:58 PM PDT 24
Peak memory 216520 kb
Host smart-dac9eac6-89ba-4489-9840-a4d4ea97ba44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439780658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.439780658
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2674495974
Short name T558
Test name
Test status
Simulation time 3483293537 ps
CPU time 9.27 seconds
Started Aug 18 05:50:53 PM PDT 24
Finished Aug 18 05:51:03 PM PDT 24
Peak memory 216532 kb
Host smart-6e379de7-b9db-4457-b1a1-03d0bfbb7435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674495974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2674495974
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3465087561
Short name T802
Test name
Test status
Simulation time 98168778 ps
CPU time 1.34 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:51:09 PM PDT 24
Peak memory 216488 kb
Host smart-891eed57-2c97-4941-b386-56a1bad47644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465087561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3465087561
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3731054781
Short name T871
Test name
Test status
Simulation time 68620120 ps
CPU time 0.78 seconds
Started Aug 18 05:50:51 PM PDT 24
Finished Aug 18 05:50:52 PM PDT 24
Peak memory 206076 kb
Host smart-6c8d8b4e-968d-475d-a81b-c51258f0c084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731054781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3731054781
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1975196753
Short name T783
Test name
Test status
Simulation time 86194315 ps
CPU time 2.76 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:50:55 PM PDT 24
Peak memory 232772 kb
Host smart-0397f105-bac3-490b-9506-79b1e05814e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975196753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1975196753
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3440970803
Short name T811
Test name
Test status
Simulation time 50835618 ps
CPU time 0.72 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:50:49 PM PDT 24
Peak memory 204884 kb
Host smart-a76139cb-88ee-4641-a95d-2738ff0fea64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440970803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3440970803
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.693070762
Short name T76
Test name
Test status
Simulation time 212801622 ps
CPU time 3.91 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:50:56 PM PDT 24
Peak memory 224628 kb
Host smart-c524dd09-803b-4b92-a001-e6c9a1d987b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693070762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.693070762
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3069304436
Short name T954
Test name
Test status
Simulation time 69021777 ps
CPU time 0.84 seconds
Started Aug 18 05:50:56 PM PDT 24
Finished Aug 18 05:50:57 PM PDT 24
Peak memory 206544 kb
Host smart-52f2d8de-972f-45ca-8743-ba7a0442d50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069304436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3069304436
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3739680293
Short name T6
Test name
Test status
Simulation time 38527445089 ps
CPU time 181.58 seconds
Started Aug 18 05:50:48 PM PDT 24
Finished Aug 18 05:53:49 PM PDT 24
Peak memory 272024 kb
Host smart-dfbd2797-f60f-488b-9ee8-1540392ca4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739680293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3739680293
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1787577509
Short name T770
Test name
Test status
Simulation time 5110428233 ps
CPU time 26.38 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:51:18 PM PDT 24
Peak memory 252320 kb
Host smart-0b0f0257-7fea-4160-80a6-1f079f5885b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787577509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1787577509
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3480503121
Short name T254
Test name
Test status
Simulation time 14689884906 ps
CPU time 119.54 seconds
Started Aug 18 05:50:53 PM PDT 24
Finished Aug 18 05:52:52 PM PDT 24
Peak memory 256508 kb
Host smart-cc7cc951-cec2-4785-98d6-b64be0d88c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480503121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3480503121
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.13121714
Short name T549
Test name
Test status
Simulation time 166826191 ps
CPU time 3.85 seconds
Started Aug 18 05:50:49 PM PDT 24
Finished Aug 18 05:50:53 PM PDT 24
Peak memory 234224 kb
Host smart-3d284a9a-0f80-4b35-926f-f42deaecf5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13121714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.13121714
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2157883268
Short name T191
Test name
Test status
Simulation time 37599158839 ps
CPU time 76.61 seconds
Started Aug 18 05:51:06 PM PDT 24
Finished Aug 18 05:52:23 PM PDT 24
Peak memory 256844 kb
Host smart-078b6ac2-8b33-4450-a630-3109e7f47b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157883268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2157883268
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.565979786
Short name T193
Test name
Test status
Simulation time 4468037596 ps
CPU time 10.38 seconds
Started Aug 18 05:50:47 PM PDT 24
Finished Aug 18 05:50:58 PM PDT 24
Peak memory 224712 kb
Host smart-34c2d06a-ddce-4893-9629-669077d2677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565979786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.565979786
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4037611518
Short name T520
Test name
Test status
Simulation time 13103608026 ps
CPU time 39.05 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:51:31 PM PDT 24
Peak memory 239392 kb
Host smart-5828d8dc-0d52-4e3b-8e8e-73a4c1236550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037611518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4037611518
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1249071411
Short name T899
Test name
Test status
Simulation time 105870783 ps
CPU time 2.58 seconds
Started Aug 18 05:51:00 PM PDT 24
Finished Aug 18 05:51:03 PM PDT 24
Peak memory 232872 kb
Host smart-edf5b362-560c-48c4-9295-097285af1a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249071411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1249071411
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.620741752
Short name T195
Test name
Test status
Simulation time 5829506132 ps
CPU time 12.92 seconds
Started Aug 18 05:50:57 PM PDT 24
Finished Aug 18 05:51:10 PM PDT 24
Peak memory 232880 kb
Host smart-26ed6774-145a-454f-96c7-06b0652a7808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620741752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.620741752
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.954334054
Short name T595
Test name
Test status
Simulation time 1276136749 ps
CPU time 6.09 seconds
Started Aug 18 05:50:54 PM PDT 24
Finished Aug 18 05:51:00 PM PDT 24
Peak memory 219328 kb
Host smart-579644a3-faed-4480-adfe-42a7386409f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=954334054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.954334054
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1862798627
Short name T138
Test name
Test status
Simulation time 17152502164 ps
CPU time 72.01 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:52:03 PM PDT 24
Peak memory 249368 kb
Host smart-5f0d1704-92bc-47b0-8383-71dafa83f771
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862798627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1862798627
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1603755040
Short name T761
Test name
Test status
Simulation time 2218810608 ps
CPU time 9.44 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:51:00 PM PDT 24
Peak memory 218136 kb
Host smart-e97c0fe7-7b68-4719-9391-4bc766325e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603755040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1603755040
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3747841906
Short name T583
Test name
Test status
Simulation time 1044070480 ps
CPU time 3.3 seconds
Started Aug 18 05:50:49 PM PDT 24
Finished Aug 18 05:50:52 PM PDT 24
Peak memory 216452 kb
Host smart-0c499cf5-3bbd-4f4e-a669-ceaa373f3898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747841906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3747841906
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.75894900
Short name T510
Test name
Test status
Simulation time 14058269 ps
CPU time 0.83 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:50:53 PM PDT 24
Peak memory 206864 kb
Host smart-9d8629b5-ff04-4fbb-9e76-d145a0038dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75894900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.75894900
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3872727165
Short name T541
Test name
Test status
Simulation time 134783916 ps
CPU time 0.79 seconds
Started Aug 18 05:50:54 PM PDT 24
Finished Aug 18 05:50:55 PM PDT 24
Peak memory 206088 kb
Host smart-4268ea28-60d9-4134-9a32-ba9fbe9a57e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872727165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3872727165
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.232739277
Short name T390
Test name
Test status
Simulation time 138688694 ps
CPU time 2.43 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:50:54 PM PDT 24
Peak memory 224680 kb
Host smart-c6a69361-c039-4bba-b041-901b5e602b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232739277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.232739277
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2599193949
Short name T1006
Test name
Test status
Simulation time 47143486 ps
CPU time 0.71 seconds
Started Aug 18 05:50:57 PM PDT 24
Finished Aug 18 05:50:58 PM PDT 24
Peak memory 205512 kb
Host smart-1f06bc24-023b-4e9d-aae9-e609b6bdb17a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599193949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2599193949
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4240327623
Short name T972
Test name
Test status
Simulation time 1261181685 ps
CPU time 8.94 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:51:17 PM PDT 24
Peak memory 232796 kb
Host smart-4c7322e6-00eb-4494-9fde-9738a2f8fe47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240327623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4240327623
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3110896510
Short name T656
Test name
Test status
Simulation time 50035544 ps
CPU time 0.78 seconds
Started Aug 18 05:50:51 PM PDT 24
Finished Aug 18 05:50:52 PM PDT 24
Peak memory 205548 kb
Host smart-af87d5ea-58ff-43ec-a6ea-bdcb1dd7a247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110896510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3110896510
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1047433852
Short name T347
Test name
Test status
Simulation time 5716034230 ps
CPU time 26.77 seconds
Started Aug 18 05:51:04 PM PDT 24
Finished Aug 18 05:51:31 PM PDT 24
Peak memory 239916 kb
Host smart-22abb9f1-2e6e-4f6e-b850-b3f918372193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047433852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1047433852
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.950966077
Short name T852
Test name
Test status
Simulation time 2232676251 ps
CPU time 43.86 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:51:36 PM PDT 24
Peak memory 252388 kb
Host smart-0432ae1f-9786-4553-801b-ab986615859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950966077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.950966077
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1908858943
Short name T941
Test name
Test status
Simulation time 21830011525 ps
CPU time 60.44 seconds
Started Aug 18 05:51:00 PM PDT 24
Finished Aug 18 05:52:01 PM PDT 24
Peak memory 232988 kb
Host smart-75693785-a219-4bf9-8fc4-fd0595633d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908858943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1908858943
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1459202692
Short name T306
Test name
Test status
Simulation time 107532891 ps
CPU time 3.15 seconds
Started Aug 18 05:51:01 PM PDT 24
Finished Aug 18 05:51:04 PM PDT 24
Peak memory 232944 kb
Host smart-11c101d6-cd8e-4a1a-a749-7da9593dbe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459202692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1459202692
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.755592391
Short name T267
Test name
Test status
Simulation time 26392470749 ps
CPU time 181.92 seconds
Started Aug 18 05:51:10 PM PDT 24
Finished Aug 18 05:54:12 PM PDT 24
Peak memory 251460 kb
Host smart-95946995-5e7e-45b4-b45d-3f71ca936477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755592391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.755592391
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1263129348
Short name T554
Test name
Test status
Simulation time 2490792414 ps
CPU time 3.74 seconds
Started Aug 18 05:51:02 PM PDT 24
Finished Aug 18 05:51:06 PM PDT 24
Peak memory 224684 kb
Host smart-4bb93747-3b91-461f-9c03-3430c40436fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263129348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1263129348
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1521709150
Short name T64
Test name
Test status
Simulation time 53244158189 ps
CPU time 99.43 seconds
Started Aug 18 05:51:09 PM PDT 24
Finished Aug 18 05:52:49 PM PDT 24
Peak memory 241040 kb
Host smart-bad24c13-e612-4696-a54f-2c24abd44527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521709150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1521709150
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3897104308
Short name T1016
Test name
Test status
Simulation time 50395201 ps
CPU time 1.97 seconds
Started Aug 18 05:51:05 PM PDT 24
Finished Aug 18 05:51:07 PM PDT 24
Peak memory 223812 kb
Host smart-65cfa8a6-8d22-4a5e-81b5-cf2991de6880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897104308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3897104308
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1519481139
Short name T839
Test name
Test status
Simulation time 204295276 ps
CPU time 2.18 seconds
Started Aug 18 05:51:09 PM PDT 24
Finished Aug 18 05:51:11 PM PDT 24
Peak memory 223256 kb
Host smart-3e83d689-24a2-4804-93a3-7c95a397a8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519481139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1519481139
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.366694482
Short name T341
Test name
Test status
Simulation time 137117464 ps
CPU time 3.34 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:50:56 PM PDT 24
Peak memory 220372 kb
Host smart-a4c0df35-940f-46b5-a922-19b74aac3e71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=366694482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.366694482
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3545316215
Short name T141
Test name
Test status
Simulation time 45121163 ps
CPU time 0.93 seconds
Started Aug 18 05:51:09 PM PDT 24
Finished Aug 18 05:51:10 PM PDT 24
Peak memory 206604 kb
Host smart-8b8fd897-f9f5-464a-af53-36ba81ac0bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545316215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3545316215
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1094283502
Short name T951
Test name
Test status
Simulation time 916665464 ps
CPU time 7.49 seconds
Started Aug 18 05:50:51 PM PDT 24
Finished Aug 18 05:50:58 PM PDT 24
Peak memory 216424 kb
Host smart-b33d65ac-9380-41eb-a4e3-824c4c74587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094283502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1094283502
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2282187821
Short name T461
Test name
Test status
Simulation time 283892574 ps
CPU time 2.31 seconds
Started Aug 18 05:51:00 PM PDT 24
Finished Aug 18 05:51:02 PM PDT 24
Peak memory 216392 kb
Host smart-4248de4d-7cb1-47b3-b3b3-19f93342933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282187821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2282187821
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1007148610
Short name T769
Test name
Test status
Simulation time 80756152 ps
CPU time 2.23 seconds
Started Aug 18 05:50:57 PM PDT 24
Finished Aug 18 05:50:59 PM PDT 24
Peak memory 216424 kb
Host smart-099b71f5-c47a-489f-a2fc-25e7d3eb369b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007148610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1007148610
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.783370588
Short name T383
Test name
Test status
Simulation time 52889227 ps
CPU time 0.85 seconds
Started Aug 18 05:50:51 PM PDT 24
Finished Aug 18 05:50:52 PM PDT 24
Peak memory 206088 kb
Host smart-7d19ba07-8252-4c8b-b6dd-33f18a2f9974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783370588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.783370588
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3388223914
Short name T404
Test name
Test status
Simulation time 1460411928 ps
CPU time 6.91 seconds
Started Aug 18 05:50:53 PM PDT 24
Finished Aug 18 05:51:00 PM PDT 24
Peak memory 239240 kb
Host smart-bf4847d9-14b2-4ed6-984c-da2ed310568b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388223914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3388223914
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2120084044
Short name T762
Test name
Test status
Simulation time 14700347 ps
CPU time 0.76 seconds
Started Aug 18 05:50:54 PM PDT 24
Finished Aug 18 05:50:55 PM PDT 24
Peak memory 204884 kb
Host smart-8f6ec8df-4ff7-48c3-8d5c-8ce866bc8be3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120084044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2120084044
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2269589098
Short name T211
Test name
Test status
Simulation time 64963297 ps
CPU time 2.66 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:51:11 PM PDT 24
Peak memory 232760 kb
Host smart-b037ab83-6856-4513-a0bd-e7d4e1815146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269589098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2269589098
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3769970310
Short name T650
Test name
Test status
Simulation time 20115666 ps
CPU time 0.76 seconds
Started Aug 18 05:50:52 PM PDT 24
Finished Aug 18 05:50:53 PM PDT 24
Peak memory 206928 kb
Host smart-3e23fff5-ad70-48d2-bb22-34e1305e652c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769970310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3769970310
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.4057718002
Short name T680
Test name
Test status
Simulation time 20150094 ps
CPU time 0.74 seconds
Started Aug 18 05:51:10 PM PDT 24
Finished Aug 18 05:51:11 PM PDT 24
Peak memory 215836 kb
Host smart-c82c8d7b-c556-4b02-84ec-f8791fc22d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057718002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.4057718002
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2310278256
Short name T391
Test name
Test status
Simulation time 7701466417 ps
CPU time 86.25 seconds
Started Aug 18 05:51:00 PM PDT 24
Finished Aug 18 05:52:26 PM PDT 24
Peak memory 257560 kb
Host smart-b8c99f83-ffb7-477c-8315-32aabf297e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310278256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2310278256
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1482807171
Short name T117
Test name
Test status
Simulation time 5581822477 ps
CPU time 60.85 seconds
Started Aug 18 05:51:10 PM PDT 24
Finished Aug 18 05:52:11 PM PDT 24
Peak memory 262096 kb
Host smart-45e9ea6e-9d22-4265-a68e-79143e7bcd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482807171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1482807171
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3779961735
Short name T753
Test name
Test status
Simulation time 190963398 ps
CPU time 3.76 seconds
Started Aug 18 05:51:04 PM PDT 24
Finished Aug 18 05:51:07 PM PDT 24
Peak memory 232880 kb
Host smart-89e3caeb-eb72-478a-8595-d4cd87a4057a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779961735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3779961735
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.4225389898
Short name T268
Test name
Test status
Simulation time 41758945821 ps
CPU time 113.61 seconds
Started Aug 18 05:50:53 PM PDT 24
Finished Aug 18 05:52:46 PM PDT 24
Peak memory 257500 kb
Host smart-8321113a-2157-4c36-b30f-d09a4640d96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225389898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.4225389898
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2683921723
Short name T517
Test name
Test status
Simulation time 260884381 ps
CPU time 4.58 seconds
Started Aug 18 05:51:02 PM PDT 24
Finished Aug 18 05:51:07 PM PDT 24
Peak memory 224524 kb
Host smart-c8201540-b271-4a5e-aec8-d91580b7195b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683921723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2683921723
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1827298638
Short name T218
Test name
Test status
Simulation time 5398544474 ps
CPU time 18.51 seconds
Started Aug 18 05:50:53 PM PDT 24
Finished Aug 18 05:51:11 PM PDT 24
Peak memory 224732 kb
Host smart-b8a8cf52-9a5c-4507-83a6-f281374f68b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827298638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1827298638
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3837515236
Short name T233
Test name
Test status
Simulation time 809492765 ps
CPU time 10.37 seconds
Started Aug 18 05:51:04 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 241052 kb
Host smart-eaaa4db8-2e2e-4115-8be9-e2475c018944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837515236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3837515236
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1998442535
Short name T167
Test name
Test status
Simulation time 1344896913 ps
CPU time 2.83 seconds
Started Aug 18 05:51:07 PM PDT 24
Finished Aug 18 05:51:09 PM PDT 24
Peak memory 224600 kb
Host smart-cba884c3-f846-4091-9dbb-b74bd5abc34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998442535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1998442535
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2192344922
Short name T581
Test name
Test status
Simulation time 658044226 ps
CPU time 4.15 seconds
Started Aug 18 05:51:03 PM PDT 24
Finished Aug 18 05:51:07 PM PDT 24
Peak memory 222668 kb
Host smart-cae4b40d-6415-4cf6-82e1-e6102f264927
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2192344922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2192344922
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3862823814
Short name T957
Test name
Test status
Simulation time 3422650228 ps
CPU time 29.23 seconds
Started Aug 18 05:50:50 PM PDT 24
Finished Aug 18 05:51:20 PM PDT 24
Peak memory 216564 kb
Host smart-1afb3022-afbd-4398-8191-dbdc9e4bd1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862823814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3862823814
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1036009955
Short name T319
Test name
Test status
Simulation time 382487081 ps
CPU time 2.71 seconds
Started Aug 18 05:51:04 PM PDT 24
Finished Aug 18 05:51:07 PM PDT 24
Peak memory 216444 kb
Host smart-d170cb48-e7da-4a30-aa8c-fd1a2fff9c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036009955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1036009955
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3458159702
Short name T765
Test name
Test status
Simulation time 241485913 ps
CPU time 1.28 seconds
Started Aug 18 05:51:03 PM PDT 24
Finished Aug 18 05:51:04 PM PDT 24
Peak memory 208228 kb
Host smart-3671354f-09b2-4967-9021-18e88ac824cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458159702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3458159702
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2653531623
Short name T590
Test name
Test status
Simulation time 211648626 ps
CPU time 0.98 seconds
Started Aug 18 05:51:02 PM PDT 24
Finished Aug 18 05:51:03 PM PDT 24
Peak memory 205616 kb
Host smart-5f04cfea-e673-43bf-b96d-d05377d2c355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653531623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2653531623
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3675361052
Short name T803
Test name
Test status
Simulation time 487279701 ps
CPU time 4.56 seconds
Started Aug 18 05:51:03 PM PDT 24
Finished Aug 18 05:51:07 PM PDT 24
Peak memory 224640 kb
Host smart-82393d43-3da1-4bb2-84e3-3e2741c1661b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675361052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3675361052
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2181478102
Short name T4
Test name
Test status
Simulation time 32360449 ps
CPU time 0.66 seconds
Started Aug 18 05:51:00 PM PDT 24
Finished Aug 18 05:51:01 PM PDT 24
Peak memory 204928 kb
Host smart-4f1dde25-6f1c-4fb0-a26f-48e3e9000777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181478102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2181478102
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4243508809
Short name T809
Test name
Test status
Simulation time 231548589 ps
CPU time 3.22 seconds
Started Aug 18 05:51:10 PM PDT 24
Finished Aug 18 05:51:13 PM PDT 24
Peak memory 232820 kb
Host smart-35e4b495-3b8c-4ec4-ad43-aa61833d6427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243508809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4243508809
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1626007815
Short name T622
Test name
Test status
Simulation time 17568187 ps
CPU time 0.77 seconds
Started Aug 18 05:50:59 PM PDT 24
Finished Aug 18 05:51:00 PM PDT 24
Peak memory 205808 kb
Host smart-6cb7bbdd-1666-4ab9-92c3-f8598d48982b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626007815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1626007815
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.4153708351
Short name T896
Test name
Test status
Simulation time 74991970373 ps
CPU time 81.63 seconds
Started Aug 18 05:51:10 PM PDT 24
Finished Aug 18 05:52:32 PM PDT 24
Peak memory 251932 kb
Host smart-083d46e6-7bf7-441b-9d7a-14c0d6429408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153708351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.4153708351
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2616457735
Short name T521
Test name
Test status
Simulation time 10623838547 ps
CPU time 31.72 seconds
Started Aug 18 05:51:00 PM PDT 24
Finished Aug 18 05:51:32 PM PDT 24
Peak memory 217796 kb
Host smart-44bda831-c382-4179-be25-331b0c68d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616457735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2616457735
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1509563493
Short name T446
Test name
Test status
Simulation time 24495799859 ps
CPU time 92.78 seconds
Started Aug 18 05:51:10 PM PDT 24
Finished Aug 18 05:52:43 PM PDT 24
Peak memory 248728 kb
Host smart-82e9bcd2-f68c-42cb-8b21-bd486109c7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509563493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1509563493
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1705833180
Short name T971
Test name
Test status
Simulation time 118976996792 ps
CPU time 315.86 seconds
Started Aug 18 05:51:10 PM PDT 24
Finished Aug 18 05:56:26 PM PDT 24
Peak memory 255872 kb
Host smart-37c623fb-6800-4752-a2bd-3630d8b6e377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705833180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1705833180
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.383893102
Short name T435
Test name
Test status
Simulation time 377583091 ps
CPU time 8.39 seconds
Started Aug 18 05:51:07 PM PDT 24
Finished Aug 18 05:51:15 PM PDT 24
Peak memory 224620 kb
Host smart-0085c0d2-a70a-41ab-820c-14ff2d438361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383893102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.383893102
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3955441579
Short name T630
Test name
Test status
Simulation time 132950387 ps
CPU time 2.88 seconds
Started Aug 18 05:51:02 PM PDT 24
Finished Aug 18 05:51:05 PM PDT 24
Peak memory 232776 kb
Host smart-185991bb-11a6-4615-8662-4b4923301652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955441579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3955441579
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3075514735
Short name T528
Test name
Test status
Simulation time 6193590002 ps
CPU time 6.99 seconds
Started Aug 18 05:51:12 PM PDT 24
Finished Aug 18 05:51:19 PM PDT 24
Peak memory 234184 kb
Host smart-0afaa1d7-803b-4a5b-a350-9ea712dfbf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075514735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3075514735
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.690036093
Short name T240
Test name
Test status
Simulation time 6204990573 ps
CPU time 22.18 seconds
Started Aug 18 05:51:03 PM PDT 24
Finished Aug 18 05:51:26 PM PDT 24
Peak memory 249304 kb
Host smart-14351614-93b4-4e04-ab4f-5ebc839d4117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690036093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.690036093
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.663183577
Short name T1015
Test name
Test status
Simulation time 16196933711 ps
CPU time 9.6 seconds
Started Aug 18 05:51:01 PM PDT 24
Finished Aug 18 05:51:10 PM PDT 24
Peak memory 220744 kb
Host smart-163b77ae-9a13-4dad-af42-af8e9a2cb584
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=663183577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.663183577
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3153160579
Short name T926
Test name
Test status
Simulation time 124964034135 ps
CPU time 614.43 seconds
Started Aug 18 05:51:09 PM PDT 24
Finished Aug 18 06:01:24 PM PDT 24
Peak memory 280140 kb
Host smart-60e10993-9a2c-42a5-91af-fb330ff2139c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153160579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3153160579
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1657250778
Short name T286
Test name
Test status
Simulation time 27705179077 ps
CPU time 40.83 seconds
Started Aug 18 05:51:02 PM PDT 24
Finished Aug 18 05:51:43 PM PDT 24
Peak memory 216516 kb
Host smart-a3cec201-bbd4-4582-8cd0-7877f7fbc0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657250778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1657250778
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3448463855
Short name T721
Test name
Test status
Simulation time 912203524 ps
CPU time 5.63 seconds
Started Aug 18 05:51:09 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 216356 kb
Host smart-7f50c6f2-62b3-427f-a3ce-2cc74abfa406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448463855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3448463855
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.88812566
Short name T539
Test name
Test status
Simulation time 65758996 ps
CPU time 1.89 seconds
Started Aug 18 05:51:00 PM PDT 24
Finished Aug 18 05:51:02 PM PDT 24
Peak memory 216404 kb
Host smart-88978338-4d9a-4fce-b1cf-47c158fdbad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88812566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.88812566
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1220331855
Short name T754
Test name
Test status
Simulation time 19187481 ps
CPU time 0.77 seconds
Started Aug 18 05:51:05 PM PDT 24
Finished Aug 18 05:51:06 PM PDT 24
Peak memory 206092 kb
Host smart-602aef84-4088-44e6-a2d3-46b6fb392284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220331855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1220331855
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4004218671
Short name T219
Test name
Test status
Simulation time 391945016 ps
CPU time 2.95 seconds
Started Aug 18 05:51:12 PM PDT 24
Finished Aug 18 05:51:15 PM PDT 24
Peak memory 232820 kb
Host smart-456e319e-e41a-4a01-9644-a13bc81d58d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004218671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4004218671
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1134287163
Short name T23
Test name
Test status
Simulation time 66237719 ps
CPU time 0.78 seconds
Started Aug 18 05:49:23 PM PDT 24
Finished Aug 18 05:49:24 PM PDT 24
Peak memory 204888 kb
Host smart-a52b5893-4ccd-4509-ad9b-a106798c4515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134287163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
134287163
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1165733219
Short name T553
Test name
Test status
Simulation time 1168314279 ps
CPU time 8.29 seconds
Started Aug 18 05:49:07 PM PDT 24
Finished Aug 18 05:49:15 PM PDT 24
Peak memory 224600 kb
Host smart-93ba5f63-444c-47ff-ac45-b8d9f635eb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165733219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1165733219
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3114611822
Short name T999
Test name
Test status
Simulation time 23700897 ps
CPU time 0.76 seconds
Started Aug 18 05:49:02 PM PDT 24
Finished Aug 18 05:49:03 PM PDT 24
Peak memory 206928 kb
Host smart-aef573a1-bb4d-4839-a2b0-e27a391f0cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114611822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3114611822
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1666474359
Short name T657
Test name
Test status
Simulation time 55887101364 ps
CPU time 114.21 seconds
Started Aug 18 05:49:02 PM PDT 24
Finished Aug 18 05:50:57 PM PDT 24
Peak memory 249952 kb
Host smart-81823d38-00a2-4743-aa8d-1c03ecf2b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666474359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1666474359
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3121249497
Short name T498
Test name
Test status
Simulation time 58145295 ps
CPU time 0.78 seconds
Started Aug 18 05:49:07 PM PDT 24
Finished Aug 18 05:49:08 PM PDT 24
Peak memory 216908 kb
Host smart-21a58230-4141-4c6a-b999-bf5fb80c07f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121249497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3121249497
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3738514884
Short name T222
Test name
Test status
Simulation time 113697200899 ps
CPU time 202.1 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:52:25 PM PDT 24
Peak memory 257556 kb
Host smart-7ae88677-34d7-4f8e-a4e3-3c520183f1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738514884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3738514884
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3789911960
Short name T10
Test name
Test status
Simulation time 1966291105 ps
CPU time 3.04 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:49:06 PM PDT 24
Peak memory 224624 kb
Host smart-3dfb68a2-e02b-4f13-8888-6b1ccb299f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789911960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3789911960
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1497142191
Short name T236
Test name
Test status
Simulation time 143628803734 ps
CPU time 176.82 seconds
Started Aug 18 05:49:03 PM PDT 24
Finished Aug 18 05:52:00 PM PDT 24
Peak memory 253036 kb
Host smart-085feb4f-1e22-4757-a662-f67942d62588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497142191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1497142191
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2822075667
Short name T1005
Test name
Test status
Simulation time 93177805 ps
CPU time 3.56 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:07 PM PDT 24
Peak memory 232832 kb
Host smart-f2ac2c26-1592-429f-bf4c-a53ec5086259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822075667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2822075667
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.837438029
Short name T819
Test name
Test status
Simulation time 19925553588 ps
CPU time 47.46 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 249308 kb
Host smart-0d5923ac-21b9-42c3-b19a-a7920a88dbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837438029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.837438029
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2348028520
Short name T49
Test name
Test status
Simulation time 15143804 ps
CPU time 0.99 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 217912 kb
Host smart-0a3d566c-967a-4bf3-b01e-ad0ca274b92c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348028520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2348028520
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.625535602
Short name T575
Test name
Test status
Simulation time 2925844435 ps
CPU time 10.11 seconds
Started Aug 18 05:49:05 PM PDT 24
Finished Aug 18 05:49:15 PM PDT 24
Peak memory 232824 kb
Host smart-367c0ef0-efa9-4b1c-9480-04d55dbb585c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625535602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
625535602
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.903771214
Short name T652
Test name
Test status
Simulation time 520661158 ps
CPU time 3.25 seconds
Started Aug 18 05:49:16 PM PDT 24
Finished Aug 18 05:49:19 PM PDT 24
Peak memory 224600 kb
Host smart-c040cf92-b17d-44b2-9bca-a5f3b8cf0fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903771214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.903771214
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3472073297
Short name T380
Test name
Test status
Simulation time 670364334 ps
CPU time 4.08 seconds
Started Aug 18 05:49:02 PM PDT 24
Finished Aug 18 05:49:07 PM PDT 24
Peak memory 222900 kb
Host smart-aaae509e-d891-4cdd-bc43-266ab543dcdd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3472073297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3472073297
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2288990310
Short name T60
Test name
Test status
Simulation time 138938727 ps
CPU time 1.01 seconds
Started Aug 18 05:49:11 PM PDT 24
Finished Aug 18 05:49:12 PM PDT 24
Peak memory 235504 kb
Host smart-fae8051b-7fb8-4e0d-9ae8-6b0af1badcc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288990310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2288990310
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1420074412
Short name T932
Test name
Test status
Simulation time 1021408930049 ps
CPU time 612.69 seconds
Started Aug 18 05:49:04 PM PDT 24
Finished Aug 18 05:59:17 PM PDT 24
Peak memory 272932 kb
Host smart-0bdf2a8c-61a7-480a-a5a0-f9f29b42b340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420074412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1420074412
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2476313699
Short name T901
Test name
Test status
Simulation time 918588777 ps
CPU time 4.67 seconds
Started Aug 18 05:49:02 PM PDT 24
Finished Aug 18 05:49:07 PM PDT 24
Peak memory 216444 kb
Host smart-962dd1e5-513c-4783-9eec-d576f4d3beb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476313699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2476313699
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3519377065
Short name T602
Test name
Test status
Simulation time 31422222431 ps
CPU time 10.42 seconds
Started Aug 18 05:49:00 PM PDT 24
Finished Aug 18 05:49:10 PM PDT 24
Peak memory 216492 kb
Host smart-4894dfea-b693-4846-a183-8dcc5b4b3b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519377065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3519377065
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2998095673
Short name T290
Test name
Test status
Simulation time 91043303 ps
CPU time 3.34 seconds
Started Aug 18 05:49:02 PM PDT 24
Finished Aug 18 05:49:06 PM PDT 24
Peak memory 216424 kb
Host smart-c9b0c011-87ae-4557-b7db-d3a04872a881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998095673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2998095673
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.394880556
Short name T679
Test name
Test status
Simulation time 13860797 ps
CPU time 0.71 seconds
Started Aug 18 05:49:01 PM PDT 24
Finished Aug 18 05:49:02 PM PDT 24
Peak memory 205436 kb
Host smart-830a9b52-4944-44e9-aee3-5963e84b5aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394880556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.394880556
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.890056176
Short name T831
Test name
Test status
Simulation time 930302746 ps
CPU time 3.72 seconds
Started Aug 18 05:49:09 PM PDT 24
Finished Aug 18 05:49:13 PM PDT 24
Peak memory 224672 kb
Host smart-7ab8ac08-ce6c-4d79-8920-7065b958186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890056176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.890056176
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2932502074
Short name T621
Test name
Test status
Simulation time 48235785 ps
CPU time 0.73 seconds
Started Aug 18 05:51:05 PM PDT 24
Finished Aug 18 05:51:05 PM PDT 24
Peak memory 204900 kb
Host smart-500c838d-e78f-417a-9d0e-f85b2a99342b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932502074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2932502074
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.715873637
Short name T797
Test name
Test status
Simulation time 44536562 ps
CPU time 2.22 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:51:10 PM PDT 24
Peak memory 224640 kb
Host smart-5c20a670-0af9-4ffc-8fb2-4065f69f1e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715873637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.715873637
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2834971360
Short name T935
Test name
Test status
Simulation time 20597251 ps
CPU time 0.82 seconds
Started Aug 18 05:51:05 PM PDT 24
Finished Aug 18 05:51:06 PM PDT 24
Peak memory 206436 kb
Host smart-7938b8d8-d555-4f5d-8383-c3eeddebbc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834971360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2834971360
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2057769612
Short name T266
Test name
Test status
Simulation time 242694260608 ps
CPU time 196.3 seconds
Started Aug 18 05:51:10 PM PDT 24
Finished Aug 18 05:54:27 PM PDT 24
Peak memory 257484 kb
Host smart-fdddf0ea-d3a4-496c-a128-a83cfd73186b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057769612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2057769612
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3118063633
Short name T786
Test name
Test status
Simulation time 3011722745 ps
CPU time 45.81 seconds
Started Aug 18 05:51:05 PM PDT 24
Finished Aug 18 05:51:51 PM PDT 24
Peak memory 239600 kb
Host smart-53d3a2a6-d950-43be-9f85-12ddddeb6246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118063633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3118063633
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1002640119
Short name T572
Test name
Test status
Simulation time 1452156101 ps
CPU time 33.45 seconds
Started Aug 18 05:51:04 PM PDT 24
Finished Aug 18 05:51:38 PM PDT 24
Peak memory 252144 kb
Host smart-18970f1c-1ffa-4704-b24f-9e2e7bf811e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002640119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1002640119
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1423730826
Short name T873
Test name
Test status
Simulation time 4903315295 ps
CPU time 12.86 seconds
Started Aug 18 05:51:02 PM PDT 24
Finished Aug 18 05:51:15 PM PDT 24
Peak memory 232888 kb
Host smart-d983f05f-820d-4e89-a850-814656e1cb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423730826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1423730826
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1169206096
Short name T432
Test name
Test status
Simulation time 2544337493 ps
CPU time 16.27 seconds
Started Aug 18 05:51:12 PM PDT 24
Finished Aug 18 05:51:28 PM PDT 24
Peak memory 251928 kb
Host smart-e07dcc1a-04e8-4e29-b0b4-72f4d8ff9b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169206096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1169206096
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2941376433
Short name T483
Test name
Test status
Simulation time 1162748251 ps
CPU time 9.09 seconds
Started Aug 18 05:51:00 PM PDT 24
Finished Aug 18 05:51:09 PM PDT 24
Peak memory 232840 kb
Host smart-6bb4ca28-b621-42f3-bad9-ed70827a4cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941376433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2941376433
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3899572188
Short name T238
Test name
Test status
Simulation time 630243629 ps
CPU time 13.54 seconds
Started Aug 18 05:51:13 PM PDT 24
Finished Aug 18 05:51:27 PM PDT 24
Peak memory 232728 kb
Host smart-18970843-63e3-4a9c-9977-057c37b662ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899572188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3899572188
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3579765494
Short name T197
Test name
Test status
Simulation time 4291976606 ps
CPU time 14.73 seconds
Started Aug 18 05:51:13 PM PDT 24
Finished Aug 18 05:51:28 PM PDT 24
Peak memory 224724 kb
Host smart-a1d6f785-1d06-4e14-85d8-3fc644762476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579765494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3579765494
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1183391934
Short name T47
Test name
Test status
Simulation time 358815563 ps
CPU time 5.43 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 224564 kb
Host smart-81394d44-be90-4b68-aa6a-2a29856921ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183391934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1183391934
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3757979837
Short name T359
Test name
Test status
Simulation time 268475526 ps
CPU time 3.33 seconds
Started Aug 18 05:51:10 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 219916 kb
Host smart-6caabe70-b3c4-436a-a7f2-06055db90485
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3757979837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3757979837
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2129131605
Short name T62
Test name
Test status
Simulation time 70577392 ps
CPU time 1.03 seconds
Started Aug 18 05:51:12 PM PDT 24
Finished Aug 18 05:51:13 PM PDT 24
Peak memory 207668 kb
Host smart-22f1fbc8-a076-4ca6-a77e-7bf001126035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129131605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2129131605
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2823838774
Short name T291
Test name
Test status
Simulation time 1546452052 ps
CPU time 19.46 seconds
Started Aug 18 05:51:05 PM PDT 24
Finished Aug 18 05:51:24 PM PDT 24
Peak memory 219928 kb
Host smart-de6736d9-f800-4103-863b-6330475d9af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823838774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2823838774
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.305185349
Short name T522
Test name
Test status
Simulation time 209535381 ps
CPU time 1.85 seconds
Started Aug 18 05:51:05 PM PDT 24
Finished Aug 18 05:51:07 PM PDT 24
Peak memory 208016 kb
Host smart-6edccca9-ad5b-45c6-a559-c5811fd01338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305185349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.305185349
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.322128198
Short name T804
Test name
Test status
Simulation time 253878470 ps
CPU time 4.1 seconds
Started Aug 18 05:51:12 PM PDT 24
Finished Aug 18 05:51:16 PM PDT 24
Peak memory 216452 kb
Host smart-18ef00d6-21a1-4cae-a0f0-9aa49d0c8983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322128198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.322128198
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.726017188
Short name T767
Test name
Test status
Simulation time 64103539 ps
CPU time 0.92 seconds
Started Aug 18 05:51:01 PM PDT 24
Finished Aug 18 05:51:03 PM PDT 24
Peak memory 206028 kb
Host smart-a1ee45c2-dfba-4faf-97f3-f137d0eb5bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726017188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.726017188
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1639482152
Short name T420
Test name
Test status
Simulation time 416166816 ps
CPU time 2.3 seconds
Started Aug 18 05:51:12 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 224048 kb
Host smart-7a5e7fcb-e2ad-44fb-a9a3-7b22ad307974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639482152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1639482152
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.534728545
Short name T53
Test name
Test status
Simulation time 12227465 ps
CPU time 0.7 seconds
Started Aug 18 05:51:13 PM PDT 24
Finished Aug 18 05:51:19 PM PDT 24
Peak memory 205576 kb
Host smart-7e2c09f6-cbc8-4d8a-b48a-172bd50aef69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534728545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.534728545
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1598581966
Short name T224
Test name
Test status
Simulation time 299821587 ps
CPU time 3.65 seconds
Started Aug 18 05:51:09 PM PDT 24
Finished Aug 18 05:51:13 PM PDT 24
Peak memory 224568 kb
Host smart-5858e3e9-c195-4c0c-865b-69541d6f2189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598581966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1598581966
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.345898790
Short name T412
Test name
Test status
Simulation time 60313459 ps
CPU time 0.76 seconds
Started Aug 18 05:51:06 PM PDT 24
Finished Aug 18 05:51:07 PM PDT 24
Peak memory 206540 kb
Host smart-55a69c81-894b-40fd-9f67-74b00e10be6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345898790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.345898790
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3974131259
Short name T883
Test name
Test status
Simulation time 432094913 ps
CPU time 9.98 seconds
Started Aug 18 05:51:03 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 232812 kb
Host smart-8af22bb4-0e7b-4faf-a722-4448d4155c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974131259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3974131259
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.929115626
Short name T793
Test name
Test status
Simulation time 9418392171 ps
CPU time 41.66 seconds
Started Aug 18 05:50:59 PM PDT 24
Finished Aug 18 05:51:41 PM PDT 24
Peak memory 254344 kb
Host smart-d9721464-e7f7-4a39-a3f8-e85af3888491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929115626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.929115626
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1034934786
Short name T364
Test name
Test status
Simulation time 155939469 ps
CPU time 2.93 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:51:11 PM PDT 24
Peak memory 232848 kb
Host smart-23ec166d-de35-419f-8b0c-332d77d409b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034934786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1034934786
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.945593153
Short name T716
Test name
Test status
Simulation time 57719784 ps
CPU time 1 seconds
Started Aug 18 05:51:01 PM PDT 24
Finished Aug 18 05:51:03 PM PDT 24
Peak memory 216044 kb
Host smart-b24c2c83-d57c-442c-b734-ed8f4c2b1dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945593153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.945593153
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2163800807
Short name T707
Test name
Test status
Simulation time 395587043 ps
CPU time 7.88 seconds
Started Aug 18 05:51:07 PM PDT 24
Finished Aug 18 05:51:15 PM PDT 24
Peak memory 224632 kb
Host smart-d8912a12-91b6-4575-8e26-26a625f16e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163800807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2163800807
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.522242529
Short name T756
Test name
Test status
Simulation time 28020287769 ps
CPU time 96.43 seconds
Started Aug 18 05:51:01 PM PDT 24
Finished Aug 18 05:52:38 PM PDT 24
Peak memory 252860 kb
Host smart-61d83f69-8335-4835-86e5-3422c65900f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522242529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.522242529
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2311801633
Short name T791
Test name
Test status
Simulation time 205067064 ps
CPU time 2.87 seconds
Started Aug 18 05:51:02 PM PDT 24
Finished Aug 18 05:51:05 PM PDT 24
Peak memory 232756 kb
Host smart-396523da-9492-426b-ae9a-b6fcdf7f1329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311801633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2311801633
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3854663676
Short name T734
Test name
Test status
Simulation time 245903778 ps
CPU time 4.75 seconds
Started Aug 18 05:51:02 PM PDT 24
Finished Aug 18 05:51:07 PM PDT 24
Peak memory 232808 kb
Host smart-3c823fe6-b9f5-4e87-9bda-e5d7dcc61626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854663676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3854663676
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4021417376
Short name T997
Test name
Test status
Simulation time 1555160920 ps
CPU time 8.86 seconds
Started Aug 18 05:51:11 PM PDT 24
Finished Aug 18 05:51:20 PM PDT 24
Peak memory 223056 kb
Host smart-7b90ab5d-1aee-4bce-8a11-dea13cbd9e86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4021417376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4021417376
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1365585616
Short name T285
Test name
Test status
Simulation time 41304147670 ps
CPU time 47.29 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:51:55 PM PDT 24
Peak memory 216500 kb
Host smart-e3edfbb0-087f-4130-aecd-67c710e80e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365585616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1365585616
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1470574117
Short name T478
Test name
Test status
Simulation time 5969464373 ps
CPU time 10.45 seconds
Started Aug 18 05:51:09 PM PDT 24
Finished Aug 18 05:51:20 PM PDT 24
Peak memory 216496 kb
Host smart-085edc79-3449-493a-b960-84886010f205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470574117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1470574117
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2862971768
Short name T296
Test name
Test status
Simulation time 92138282 ps
CPU time 2.06 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:51:10 PM PDT 24
Peak memory 216356 kb
Host smart-29228a2b-5a1e-46f6-b473-06bc46e50a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862971768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2862971768
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1545252695
Short name T948
Test name
Test status
Simulation time 45817127 ps
CPU time 0.74 seconds
Started Aug 18 05:51:02 PM PDT 24
Finished Aug 18 05:51:03 PM PDT 24
Peak memory 206076 kb
Host smart-2cec97a5-36f2-47e7-bc2a-107e1dd305ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545252695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1545252695
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.786458359
Short name T699
Test name
Test status
Simulation time 837256804 ps
CPU time 2.58 seconds
Started Aug 18 05:51:01 PM PDT 24
Finished Aug 18 05:51:04 PM PDT 24
Peak memory 224300 kb
Host smart-902f4c53-da9c-4db7-9400-a9bbfb9ff2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786458359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.786458359
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1749475031
Short name T996
Test name
Test status
Simulation time 35761583 ps
CPU time 0.73 seconds
Started Aug 18 05:51:13 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 204948 kb
Host smart-3db4f13f-f69b-4d2b-9472-41d3d4a747d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749475031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1749475031
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2468906727
Short name T708
Test name
Test status
Simulation time 881864333 ps
CPU time 9.82 seconds
Started Aug 18 05:51:09 PM PDT 24
Finished Aug 18 05:51:19 PM PDT 24
Peak memory 232840 kb
Host smart-f8d79f7b-58d9-43a2-91f0-1da2fdcaffab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468906727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2468906727
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.665209661
Short name T938
Test name
Test status
Simulation time 47241048 ps
CPU time 0.72 seconds
Started Aug 18 05:51:13 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 205488 kb
Host smart-1ce7643c-2c9b-4321-a61a-3abc3dd541c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665209661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.665209661
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3226727754
Short name T967
Test name
Test status
Simulation time 14377419758 ps
CPU time 33.6 seconds
Started Aug 18 05:51:20 PM PDT 24
Finished Aug 18 05:51:54 PM PDT 24
Peak memory 237900 kb
Host smart-21b6a70b-e648-42a2-91af-647c7a5f8c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226727754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3226727754
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.360504165
Short name T180
Test name
Test status
Simulation time 1851040552 ps
CPU time 49.64 seconds
Started Aug 18 05:51:13 PM PDT 24
Finished Aug 18 05:52:03 PM PDT 24
Peak memory 255696 kb
Host smart-6351ecb0-bb61-4042-a1b5-0f522466ca94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360504165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.360504165
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.4089174297
Short name T31
Test name
Test status
Simulation time 22099450578 ps
CPU time 266.02 seconds
Started Aug 18 05:51:07 PM PDT 24
Finished Aug 18 05:55:33 PM PDT 24
Peak memory 257444 kb
Host smart-8060f8f9-19ca-41aa-ae76-00a07cd39383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089174297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.4089174297
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3929895921
Short name T430
Test name
Test status
Simulation time 2516932271 ps
CPU time 8.94 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:51:17 PM PDT 24
Peak memory 232896 kb
Host smart-0c5adbd9-b834-4905-aea0-ae5ffba9de3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929895921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3929895921
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2216452636
Short name T186
Test name
Test status
Simulation time 8643360781 ps
CPU time 66.59 seconds
Started Aug 18 05:51:11 PM PDT 24
Finished Aug 18 05:52:17 PM PDT 24
Peak memory 256692 kb
Host smart-dcca90f5-29dd-42d9-ac77-24ff55b95b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216452636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2216452636
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2099163227
Short name T201
Test name
Test status
Simulation time 702575941 ps
CPU time 7.76 seconds
Started Aug 18 05:51:13 PM PDT 24
Finished Aug 18 05:51:21 PM PDT 24
Peak memory 224612 kb
Host smart-3bd9c7ea-8255-4693-ae79-117de5f2981d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099163227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2099163227
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4098449472
Short name T843
Test name
Test status
Simulation time 859681946 ps
CPU time 9.57 seconds
Started Aug 18 05:51:09 PM PDT 24
Finished Aug 18 05:51:18 PM PDT 24
Peak memory 232892 kb
Host smart-702102ff-2a60-452c-aeaa-3b295c03377f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098449472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4098449472
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3705856017
Short name T192
Test name
Test status
Simulation time 1041904435 ps
CPU time 7.24 seconds
Started Aug 18 05:51:07 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 224628 kb
Host smart-7eb0c345-f1a0-4366-af04-06e43545bb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705856017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3705856017
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2811678786
Short name T728
Test name
Test status
Simulation time 225894341 ps
CPU time 2.47 seconds
Started Aug 18 05:51:13 PM PDT 24
Finished Aug 18 05:51:15 PM PDT 24
Peak memory 224580 kb
Host smart-1caa4e99-635c-4212-950c-5ec0e8bf1497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811678786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2811678786
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2460050527
Short name T981
Test name
Test status
Simulation time 1726118124 ps
CPU time 8.34 seconds
Started Aug 18 05:51:10 PM PDT 24
Finished Aug 18 05:51:18 PM PDT 24
Peak memory 218812 kb
Host smart-babbfee3-ec88-4fc8-85b3-96af16649844
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2460050527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2460050527
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3106594169
Short name T116
Test name
Test status
Simulation time 10017028002 ps
CPU time 118.73 seconds
Started Aug 18 05:51:15 PM PDT 24
Finished Aug 18 05:53:14 PM PDT 24
Peak memory 249860 kb
Host smart-7a74fa72-40d2-467f-b7dc-fa61c3b7c7c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106594169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3106594169
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1092713855
Short name T533
Test name
Test status
Simulation time 2461317388 ps
CPU time 11.31 seconds
Started Aug 18 05:51:07 PM PDT 24
Finished Aug 18 05:51:18 PM PDT 24
Peak memory 216800 kb
Host smart-3c3b4357-351e-46df-b140-e14bb6e92052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092713855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1092713855
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2506986210
Short name T806
Test name
Test status
Simulation time 10760302 ps
CPU time 0.7 seconds
Started Aug 18 05:51:07 PM PDT 24
Finished Aug 18 05:51:08 PM PDT 24
Peak memory 205684 kb
Host smart-14bdb7db-b5bc-49f3-aa61-881ca6980cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506986210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2506986210
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1749397494
Short name T862
Test name
Test status
Simulation time 393421835 ps
CPU time 0.91 seconds
Started Aug 18 05:51:09 PM PDT 24
Finished Aug 18 05:51:10 PM PDT 24
Peak memory 207084 kb
Host smart-d90e8152-d9a5-42c8-9ace-b64113ded9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749397494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1749397494
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.63637859
Short name T497
Test name
Test status
Simulation time 40607968 ps
CPU time 0.75 seconds
Started Aug 18 05:51:14 PM PDT 24
Finished Aug 18 05:51:15 PM PDT 24
Peak memory 206088 kb
Host smart-d4590237-ea48-49e9-92d2-d591b11fd2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63637859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.63637859
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2254799095
Short name T764
Test name
Test status
Simulation time 664678307 ps
CPU time 7.48 seconds
Started Aug 18 05:51:12 PM PDT 24
Finished Aug 18 05:51:20 PM PDT 24
Peak memory 232872 kb
Host smart-21eb2abe-6282-4618-b48f-f710201a6914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254799095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2254799095
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2886109891
Short name T545
Test name
Test status
Simulation time 13932834 ps
CPU time 0.7 seconds
Started Aug 18 05:51:17 PM PDT 24
Finished Aug 18 05:51:18 PM PDT 24
Peak memory 204924 kb
Host smart-bafad559-23e1-4209-ada8-8e68cedac29b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886109891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2886109891
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.984211854
Short name T208
Test name
Test status
Simulation time 5242226385 ps
CPU time 12.84 seconds
Started Aug 18 05:51:24 PM PDT 24
Finished Aug 18 05:51:37 PM PDT 24
Peak memory 224676 kb
Host smart-af32f7eb-51da-4310-988d-e5aaa80bf126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984211854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.984211854
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.240600037
Short name T299
Test name
Test status
Simulation time 56311797 ps
CPU time 0.72 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:51:09 PM PDT 24
Peak memory 206520 kb
Host smart-8fe37efc-f781-482a-ad70-9031e13c8aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240600037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.240600037
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3341773121
Short name T423
Test name
Test status
Simulation time 1778767485 ps
CPU time 12.6 seconds
Started Aug 18 05:51:22 PM PDT 24
Finished Aug 18 05:51:35 PM PDT 24
Peak memory 224668 kb
Host smart-52c6012d-c3ae-4b21-8976-cbf2ed40bec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341773121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3341773121
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1969860483
Short name T876
Test name
Test status
Simulation time 12541542568 ps
CPU time 67.99 seconds
Started Aug 18 05:51:16 PM PDT 24
Finished Aug 18 05:52:24 PM PDT 24
Peak memory 257584 kb
Host smart-bf270104-1bbe-4f91-8c34-fa09b01c7827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969860483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1969860483
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3117556146
Short name T950
Test name
Test status
Simulation time 2302339878 ps
CPU time 59.89 seconds
Started Aug 18 05:51:27 PM PDT 24
Finished Aug 18 05:52:27 PM PDT 24
Peak memory 249552 kb
Host smart-182000cd-4edd-4245-842f-972def1e5a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117556146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3117556146
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2374295641
Short name T488
Test name
Test status
Simulation time 121832818429 ps
CPU time 173 seconds
Started Aug 18 05:51:17 PM PDT 24
Finished Aug 18 05:54:10 PM PDT 24
Peak memory 255572 kb
Host smart-926c76bb-853f-4265-a27c-b7748aad43d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374295641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2374295641
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1698478382
Short name T966
Test name
Test status
Simulation time 422829420 ps
CPU time 5.9 seconds
Started Aug 18 05:51:07 PM PDT 24
Finished Aug 18 05:51:13 PM PDT 24
Peak memory 232896 kb
Host smart-bfea6295-cdb5-4ced-bf6a-89f0c5a9c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698478382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1698478382
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2636743595
Short name T723
Test name
Test status
Simulation time 1617477717 ps
CPU time 10.25 seconds
Started Aug 18 05:51:11 PM PDT 24
Finished Aug 18 05:51:22 PM PDT 24
Peak memory 241044 kb
Host smart-c229ed1a-7a3f-41eb-a9ac-73602b8dc12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636743595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2636743595
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.293648448
Short name T424
Test name
Test status
Simulation time 1351826938 ps
CPU time 4.26 seconds
Started Aug 18 05:51:15 PM PDT 24
Finished Aug 18 05:51:19 PM PDT 24
Peak memory 232868 kb
Host smart-16d1c9f8-8361-467e-8da7-00c5bc6ce41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293648448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.293648448
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3524959607
Short name T601
Test name
Test status
Simulation time 306056647 ps
CPU time 2.99 seconds
Started Aug 18 05:51:17 PM PDT 24
Finished Aug 18 05:51:20 PM PDT 24
Peak memory 232812 kb
Host smart-65cb9b79-9759-4f79-a81b-2a517068444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524959607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3524959607
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.421740769
Short name T388
Test name
Test status
Simulation time 298471212 ps
CPU time 5.31 seconds
Started Aug 18 05:51:19 PM PDT 24
Finished Aug 18 05:51:25 PM PDT 24
Peak memory 223176 kb
Host smart-79fabdfc-bd6f-45b1-8910-4c924aae729e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=421740769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.421740769
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.962525244
Short name T543
Test name
Test status
Simulation time 3461447770 ps
CPU time 6.94 seconds
Started Aug 18 05:51:13 PM PDT 24
Finished Aug 18 05:51:20 PM PDT 24
Peak memory 216588 kb
Host smart-0190e365-0fcf-44f9-8b05-5351bdc4c4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962525244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.962525244
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3191837017
Short name T574
Test name
Test status
Simulation time 399088075 ps
CPU time 3.28 seconds
Started Aug 18 05:51:08 PM PDT 24
Finished Aug 18 05:51:12 PM PDT 24
Peak memory 216496 kb
Host smart-d68c6f22-c7fe-4f95-8a37-5650f0876244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191837017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3191837017
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.993249207
Short name T505
Test name
Test status
Simulation time 256748638 ps
CPU time 1.3 seconds
Started Aug 18 05:51:12 PM PDT 24
Finished Aug 18 05:51:13 PM PDT 24
Peak memory 216436 kb
Host smart-914931d7-25f5-4649-9ef2-929570778e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993249207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.993249207
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2441880673
Short name T909
Test name
Test status
Simulation time 203023763 ps
CPU time 0.73 seconds
Started Aug 18 05:51:14 PM PDT 24
Finished Aug 18 05:51:15 PM PDT 24
Peak memory 206088 kb
Host smart-b4815225-a70c-4994-9de5-61d2cb8cd2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441880673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2441880673
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2196213758
Short name T591
Test name
Test status
Simulation time 4500200343 ps
CPU time 17.86 seconds
Started Aug 18 05:51:13 PM PDT 24
Finished Aug 18 05:51:31 PM PDT 24
Peak memory 239720 kb
Host smart-ebfdf573-fca3-46b7-84be-b4078a2941f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196213758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2196213758
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2179858183
Short name T637
Test name
Test status
Simulation time 36243916 ps
CPU time 0.78 seconds
Started Aug 18 05:51:16 PM PDT 24
Finished Aug 18 05:51:17 PM PDT 24
Peak memory 204896 kb
Host smart-105e1fa1-dbbd-44dd-a487-6805ec3d4229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179858183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2179858183
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.953574072
Short name T305
Test name
Test status
Simulation time 58647738 ps
CPU time 2.39 seconds
Started Aug 18 05:51:19 PM PDT 24
Finished Aug 18 05:51:22 PM PDT 24
Peak memory 232508 kb
Host smart-4f07811e-6905-4b19-82af-cbf8f7c91cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953574072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.953574072
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3459000840
Short name T470
Test name
Test status
Simulation time 46136062 ps
CPU time 0.78 seconds
Started Aug 18 05:51:24 PM PDT 24
Finished Aug 18 05:51:25 PM PDT 24
Peak memory 206856 kb
Host smart-4313d3d7-07bd-4b7c-802a-0c70b94e5bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459000840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3459000840
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3165758046
Short name T322
Test name
Test status
Simulation time 23418319 ps
CPU time 0.76 seconds
Started Aug 18 05:51:22 PM PDT 24
Finished Aug 18 05:51:23 PM PDT 24
Peak memory 215820 kb
Host smart-59beb90b-b167-4d9d-b720-004fde76f87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165758046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3165758046
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.783324154
Short name T1014
Test name
Test status
Simulation time 12113334914 ps
CPU time 17.12 seconds
Started Aug 18 05:51:15 PM PDT 24
Finished Aug 18 05:51:33 PM PDT 24
Peak memory 217592 kb
Host smart-c64e778e-4cfa-48d1-ad7e-7879465aefd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783324154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.783324154
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.4230551491
Short name T577
Test name
Test status
Simulation time 47521822800 ps
CPU time 209.52 seconds
Started Aug 18 05:51:21 PM PDT 24
Finished Aug 18 05:54:50 PM PDT 24
Peak memory 249316 kb
Host smart-8c25263f-b36e-49de-9b1d-49f6bd3b3da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230551491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.4230551491
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1326225212
Short name T755
Test name
Test status
Simulation time 164976664 ps
CPU time 3.29 seconds
Started Aug 18 05:51:15 PM PDT 24
Finished Aug 18 05:51:19 PM PDT 24
Peak memory 233824 kb
Host smart-9dd8d45e-2949-42d8-abbd-34d82b53db91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326225212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1326225212
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1719442715
Short name T392
Test name
Test status
Simulation time 2739945979 ps
CPU time 27.89 seconds
Started Aug 18 05:51:19 PM PDT 24
Finished Aug 18 05:51:47 PM PDT 24
Peak memory 253584 kb
Host smart-6f8e8dd0-1e45-4990-92d0-bb7b4ca7fdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719442715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1719442715
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1955668837
Short name T413
Test name
Test status
Simulation time 1423590025 ps
CPU time 6.16 seconds
Started Aug 18 05:51:18 PM PDT 24
Finished Aug 18 05:51:25 PM PDT 24
Peak memory 232884 kb
Host smart-9020001a-0e61-4ddd-9703-8af2668eb104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955668837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1955668837
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2230905524
Short name T328
Test name
Test status
Simulation time 122709365 ps
CPU time 2.51 seconds
Started Aug 18 05:51:16 PM PDT 24
Finished Aug 18 05:51:18 PM PDT 24
Peak memory 232820 kb
Host smart-3343100e-79e3-4790-ae6c-e2f080ffd282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230905524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2230905524
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3257991970
Short name T841
Test name
Test status
Simulation time 219976161 ps
CPU time 3.3 seconds
Started Aug 18 05:51:19 PM PDT 24
Finished Aug 18 05:51:23 PM PDT 24
Peak memory 224580 kb
Host smart-c8595be9-3e77-48a1-b092-53eb419860bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257991970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3257991970
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3524833359
Short name T241
Test name
Test status
Simulation time 153012775 ps
CPU time 2.14 seconds
Started Aug 18 05:51:20 PM PDT 24
Finished Aug 18 05:51:22 PM PDT 24
Peak memory 224648 kb
Host smart-92f117e8-da7d-4cb9-9a6d-16e1503ba050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524833359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3524833359
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.604846018
Short name T7
Test name
Test status
Simulation time 89877804 ps
CPU time 4.1 seconds
Started Aug 18 05:51:18 PM PDT 24
Finished Aug 18 05:51:22 PM PDT 24
Peak memory 222604 kb
Host smart-4eafd49c-0d33-4c5a-bddf-bd4ca81f1e0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=604846018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.604846018
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1989444933
Short name T18
Test name
Test status
Simulation time 9808829481 ps
CPU time 182.91 seconds
Started Aug 18 05:51:21 PM PDT 24
Finished Aug 18 05:54:24 PM PDT 24
Peak memory 273656 kb
Host smart-1e03baa9-85d0-4dd6-bc37-1a639d08bc73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989444933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1989444933
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1064746055
Short name T350
Test name
Test status
Simulation time 30251731608 ps
CPU time 38.37 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:52:08 PM PDT 24
Peak memory 216508 kb
Host smart-14fe1cb4-1f9d-4db1-aa4d-5d28f8455089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064746055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1064746055
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3676759113
Short name T445
Test name
Test status
Simulation time 33641137808 ps
CPU time 19.34 seconds
Started Aug 18 05:51:16 PM PDT 24
Finished Aug 18 05:51:35 PM PDT 24
Peak memory 217600 kb
Host smart-713ba841-91ed-426b-abcf-3a399c29abe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676759113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3676759113
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1620464220
Short name T988
Test name
Test status
Simulation time 178144620 ps
CPU time 2.27 seconds
Started Aug 18 05:51:15 PM PDT 24
Finished Aug 18 05:51:18 PM PDT 24
Peak memory 216384 kb
Host smart-497cc026-40fc-4ba6-97f2-454a9142737f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620464220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1620464220
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1923578198
Short name T331
Test name
Test status
Simulation time 63713769 ps
CPU time 0.77 seconds
Started Aug 18 05:51:19 PM PDT 24
Finished Aug 18 05:51:20 PM PDT 24
Peak memory 206088 kb
Host smart-436c2b0e-7a73-4f51-bc8d-57c36337dbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923578198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1923578198
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3941770779
Short name T818
Test name
Test status
Simulation time 8992928337 ps
CPU time 18.4 seconds
Started Aug 18 05:51:13 PM PDT 24
Finished Aug 18 05:51:32 PM PDT 24
Peak memory 232956 kb
Host smart-eeb8c2ad-970c-415c-9936-9fc6245dd1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941770779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3941770779
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1243583390
Short name T729
Test name
Test status
Simulation time 48736610 ps
CPU time 0.73 seconds
Started Aug 18 05:51:26 PM PDT 24
Finished Aug 18 05:51:27 PM PDT 24
Peak memory 205512 kb
Host smart-44f9387d-cfcc-43df-8e16-8d62849972c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243583390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1243583390
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3203608057
Short name T225
Test name
Test status
Simulation time 734933480 ps
CPU time 4.93 seconds
Started Aug 18 05:51:36 PM PDT 24
Finished Aug 18 05:51:46 PM PDT 24
Peak memory 224676 kb
Host smart-f9b7befe-adde-4d62-bfba-c6ad6ac56d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203608057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3203608057
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.221316734
Short name T674
Test name
Test status
Simulation time 47261384 ps
CPU time 0.72 seconds
Started Aug 18 05:51:20 PM PDT 24
Finished Aug 18 05:51:21 PM PDT 24
Peak memory 205548 kb
Host smart-981d362d-aaf5-4ebe-89ad-83fb474dc3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221316734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.221316734
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4128668748
Short name T845
Test name
Test status
Simulation time 3667950074 ps
CPU time 61.24 seconds
Started Aug 18 05:51:25 PM PDT 24
Finished Aug 18 05:52:26 PM PDT 24
Peak memory 257428 kb
Host smart-70303a85-69d4-437a-9f75-0b79a97b1ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128668748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4128668748
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.406121199
Short name T885
Test name
Test status
Simulation time 5210785342 ps
CPU time 104.4 seconds
Started Aug 18 05:51:32 PM PDT 24
Finished Aug 18 05:53:17 PM PDT 24
Peak memory 253552 kb
Host smart-5c524427-d799-406b-8b99-9fb0fc7244ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406121199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.406121199
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2218325327
Short name T691
Test name
Test status
Simulation time 41650647964 ps
CPU time 163.54 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:54:15 PM PDT 24
Peak memory 238532 kb
Host smart-98e1907b-3a50-4863-b68f-9be8076d80fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218325327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2218325327
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3465893408
Short name T275
Test name
Test status
Simulation time 305610657 ps
CPU time 5.73 seconds
Started Aug 18 05:51:30 PM PDT 24
Finished Aug 18 05:51:36 PM PDT 24
Peak memory 224644 kb
Host smart-9ae6e6e4-ad87-425c-bd2e-fd7d2be49994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465893408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3465893408
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.200278985
Short name T466
Test name
Test status
Simulation time 13046150077 ps
CPU time 31.4 seconds
Started Aug 18 05:51:21 PM PDT 24
Finished Aug 18 05:51:52 PM PDT 24
Peak memory 250748 kb
Host smart-626459dc-6f04-42e6-9835-404ddf377f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200278985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.200278985
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3003308416
Short name T228
Test name
Test status
Simulation time 2525766544 ps
CPU time 12.26 seconds
Started Aug 18 05:51:19 PM PDT 24
Finished Aug 18 05:51:31 PM PDT 24
Peak memory 224688 kb
Host smart-65e9a4f3-0ab1-45b7-a014-00aa843140b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003308416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3003308416
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.279955977
Short name T386
Test name
Test status
Simulation time 2347422116 ps
CPU time 27.17 seconds
Started Aug 18 05:51:23 PM PDT 24
Finished Aug 18 05:51:50 PM PDT 24
Peak memory 232908 kb
Host smart-6045d3fd-8623-4c4c-b20b-cfe319eaebc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279955977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.279955977
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2237626970
Short name T685
Test name
Test status
Simulation time 5857643474 ps
CPU time 8.83 seconds
Started Aug 18 05:51:16 PM PDT 24
Finished Aug 18 05:51:25 PM PDT 24
Peak memory 224696 kb
Host smart-e33f0da6-944f-4d43-b421-1ae99143335a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237626970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2237626970
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2589645281
Short name T713
Test name
Test status
Simulation time 10154309220 ps
CPU time 18.22 seconds
Started Aug 18 05:51:18 PM PDT 24
Finished Aug 18 05:51:36 PM PDT 24
Peak memory 233168 kb
Host smart-0a6febe9-6c26-4cb2-9609-9f829765e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589645281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2589645281
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.748021456
Short name T542
Test name
Test status
Simulation time 4852626375 ps
CPU time 13.51 seconds
Started Aug 18 05:51:21 PM PDT 24
Finished Aug 18 05:51:35 PM PDT 24
Peak memory 219164 kb
Host smart-ac54f3ba-bb66-4efc-9d58-cc4a2c11859c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=748021456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.748021456
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.617602780
Short name T29
Test name
Test status
Simulation time 675634312 ps
CPU time 10.62 seconds
Started Aug 18 05:51:19 PM PDT 24
Finished Aug 18 05:51:29 PM PDT 24
Peak memory 216856 kb
Host smart-9def2987-d9ee-46f4-b1fd-0564874813e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617602780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.617602780
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1086051716
Short name T310
Test name
Test status
Simulation time 1433834728 ps
CPU time 8.84 seconds
Started Aug 18 05:51:21 PM PDT 24
Finished Aug 18 05:51:30 PM PDT 24
Peak memory 216404 kb
Host smart-d30366fd-88ef-47c3-87d9-acb0a789810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086051716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1086051716
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.517541242
Short name T344
Test name
Test status
Simulation time 103070748 ps
CPU time 1.07 seconds
Started Aug 18 05:51:25 PM PDT 24
Finished Aug 18 05:51:26 PM PDT 24
Peak memory 208040 kb
Host smart-f242a7b8-2afb-4eac-8bbf-3a14fd0e4f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517541242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.517541242
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2368444581
Short name T612
Test name
Test status
Simulation time 47235451 ps
CPU time 0.67 seconds
Started Aug 18 05:51:19 PM PDT 24
Finished Aug 18 05:51:20 PM PDT 24
Peak memory 205616 kb
Host smart-f784f4d0-1a4e-48f2-8a06-161d850f66c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368444581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2368444581
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.504337494
Short name T230
Test name
Test status
Simulation time 119338405 ps
CPU time 2.56 seconds
Started Aug 18 05:51:24 PM PDT 24
Finished Aug 18 05:51:27 PM PDT 24
Peak memory 224556 kb
Host smart-953f3490-fea5-44cc-ba37-95ae7bb79a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504337494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.504337494
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2115610980
Short name T750
Test name
Test status
Simulation time 14299668 ps
CPU time 0.71 seconds
Started Aug 18 05:51:34 PM PDT 24
Finished Aug 18 05:51:34 PM PDT 24
Peak memory 204880 kb
Host smart-1005a30d-41f8-4236-927c-84f93ab4407e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115610980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2115610980
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1841256955
Short name T712
Test name
Test status
Simulation time 149861112 ps
CPU time 2.58 seconds
Started Aug 18 05:51:21 PM PDT 24
Finished Aug 18 05:51:23 PM PDT 24
Peak memory 224676 kb
Host smart-f4f7a073-c4a4-4176-9cdd-3c123eb4df13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841256955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1841256955
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2710837417
Short name T900
Test name
Test status
Simulation time 59935967 ps
CPU time 0.76 seconds
Started Aug 18 05:51:25 PM PDT 24
Finished Aug 18 05:51:26 PM PDT 24
Peak memory 205556 kb
Host smart-1fa893c3-07b9-4723-8038-82ed70192f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710837417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2710837417
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.835386937
Short name T185
Test name
Test status
Simulation time 452113869764 ps
CPU time 567.59 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 06:00:59 PM PDT 24
Peak memory 271924 kb
Host smart-a30582fd-97e3-496d-bfcf-a4926666a6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835386937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.835386937
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.394185661
Short name T746
Test name
Test status
Simulation time 51654451512 ps
CPU time 79.98 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:52:49 PM PDT 24
Peak memory 232984 kb
Host smart-73291eac-b9e8-4785-9989-c5f5b9198aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394185661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.394185661
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1380192152
Short name T706
Test name
Test status
Simulation time 20385477596 ps
CPU time 70.17 seconds
Started Aug 18 05:51:24 PM PDT 24
Finished Aug 18 05:52:34 PM PDT 24
Peak memory 262888 kb
Host smart-350f72bb-f1f4-4085-9b8a-d50db4663bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380192152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1380192152
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1146570478
Short name T274
Test name
Test status
Simulation time 2558632225 ps
CPU time 44.05 seconds
Started Aug 18 05:51:23 PM PDT 24
Finished Aug 18 05:52:07 PM PDT 24
Peak memory 238924 kb
Host smart-2787bd5e-a6cf-4dd7-a893-41dd8b942d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146570478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1146570478
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4117152081
Short name T492
Test name
Test status
Simulation time 26059965554 ps
CPU time 170.05 seconds
Started Aug 18 05:51:32 PM PDT 24
Finished Aug 18 05:54:23 PM PDT 24
Peak memory 237992 kb
Host smart-5a44a553-1535-497f-a695-d15718011c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117152081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4117152081
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2622394006
Short name T52
Test name
Test status
Simulation time 227850524 ps
CPU time 4.82 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:51:36 PM PDT 24
Peak memory 224656 kb
Host smart-c77a7a95-85dc-4dcf-8639-b252e952c878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622394006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2622394006
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1395352288
Short name T760
Test name
Test status
Simulation time 622042843 ps
CPU time 5.57 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:51:36 PM PDT 24
Peak memory 224652 kb
Host smart-13c2c4d4-c887-428d-975a-395f8794306a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395352288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1395352288
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2028055920
Short name T977
Test name
Test status
Simulation time 3993640911 ps
CPU time 13.6 seconds
Started Aug 18 05:51:22 PM PDT 24
Finished Aug 18 05:51:36 PM PDT 24
Peak memory 232872 kb
Host smart-1123eb4d-ad4c-47b7-b8ff-56f6f7265ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028055920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2028055920
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.450759108
Short name T80
Test name
Test status
Simulation time 118077362 ps
CPU time 2.35 seconds
Started Aug 18 05:51:23 PM PDT 24
Finished Aug 18 05:51:25 PM PDT 24
Peak memory 224636 kb
Host smart-977d4726-1495-446e-b032-7943332157f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450759108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.450759108
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1351853549
Short name T513
Test name
Test status
Simulation time 72716940 ps
CPU time 3.65 seconds
Started Aug 18 05:51:20 PM PDT 24
Finished Aug 18 05:51:24 PM PDT 24
Peak memory 222692 kb
Host smart-5790bef2-9578-4dbe-8e6b-7f40c3152967
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1351853549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1351853549
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1042950197
Short name T139
Test name
Test status
Simulation time 46236194534 ps
CPU time 205.28 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:54:56 PM PDT 24
Peak memory 257060 kb
Host smart-f4de1143-db16-405f-9e93-11cbc909eec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042950197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1042950197
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3758215473
Short name T969
Test name
Test status
Simulation time 5393175696 ps
CPU time 35.81 seconds
Started Aug 18 05:51:33 PM PDT 24
Finished Aug 18 05:52:09 PM PDT 24
Peak memory 216572 kb
Host smart-e89db8d5-6f0e-4df7-8b93-e6b2a345f098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758215473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3758215473
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.79727655
Short name T695
Test name
Test status
Simulation time 825224212 ps
CPU time 5.21 seconds
Started Aug 18 05:51:32 PM PDT 24
Finished Aug 18 05:51:38 PM PDT 24
Peak memory 216464 kb
Host smart-bdf9644b-ae08-483a-a9c0-968368d9f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79727655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.79727655
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1931123465
Short name T825
Test name
Test status
Simulation time 123363829 ps
CPU time 1.8 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:51:33 PM PDT 24
Peak memory 216356 kb
Host smart-f7a755ec-cdaa-4a92-bf77-e615897b86ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931123465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1931123465
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.337363509
Short name T693
Test name
Test status
Simulation time 45935862 ps
CPU time 0.77 seconds
Started Aug 18 05:51:22 PM PDT 24
Finished Aug 18 05:51:23 PM PDT 24
Peak memory 206056 kb
Host smart-94906ddb-35e2-4eee-9ea8-4f45bcee7847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337363509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.337363509
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2013331348
Short name T582
Test name
Test status
Simulation time 618945566 ps
CPU time 6.56 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:51:37 PM PDT 24
Peak memory 240944 kb
Host smart-9418cbd1-8df7-483b-bbdd-f49c0f9ad98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013331348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2013331348
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.485786250
Short name T719
Test name
Test status
Simulation time 30747309 ps
CPU time 0.72 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:51:30 PM PDT 24
Peak memory 205504 kb
Host smart-344ad7f6-7e41-4fc8-9307-0ee04b59af6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485786250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.485786250
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1883120075
Short name T65
Test name
Test status
Simulation time 542184099 ps
CPU time 6.66 seconds
Started Aug 18 05:51:25 PM PDT 24
Finished Aug 18 05:51:32 PM PDT 24
Peak memory 224608 kb
Host smart-7c6cb3bc-8a20-45b2-aa4f-6fc10607903c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883120075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1883120075
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1902880389
Short name T816
Test name
Test status
Simulation time 37621521 ps
CPU time 0.77 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:51:32 PM PDT 24
Peak memory 206840 kb
Host smart-16e210fc-01e7-4626-b90f-95767c1aea28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902880389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1902880389
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.913608994
Short name T826
Test name
Test status
Simulation time 60070704487 ps
CPU time 437.29 seconds
Started Aug 18 05:51:34 PM PDT 24
Finished Aug 18 05:58:51 PM PDT 24
Peak memory 260708 kb
Host smart-da14fb32-d028-44cd-94a9-665828d14a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913608994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.913608994
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.254698152
Short name T975
Test name
Test status
Simulation time 11077593914 ps
CPU time 122.62 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:53:34 PM PDT 24
Peak memory 257464 kb
Host smart-17234582-bc44-40c4-9f5a-7e53d93e9b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254698152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.254698152
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2575723413
Short name T663
Test name
Test status
Simulation time 22873208493 ps
CPU time 177.5 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:54:29 PM PDT 24
Peak memory 250916 kb
Host smart-5770ec18-5eea-459b-aa93-634fc39147a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575723413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2575723413
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.378325905
Short name T127
Test name
Test status
Simulation time 107756608 ps
CPU time 4.44 seconds
Started Aug 18 05:51:23 PM PDT 24
Finished Aug 18 05:51:28 PM PDT 24
Peak memory 241024 kb
Host smart-374e1406-2155-4e38-ad6b-84ddd257b3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378325905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.378325905
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3369343586
Short name T239
Test name
Test status
Simulation time 19406350647 ps
CPU time 49.6 seconds
Started Aug 18 05:51:24 PM PDT 24
Finished Aug 18 05:52:13 PM PDT 24
Peak memory 249340 kb
Host smart-a8ef9bcf-6585-45a1-ade2-3434a5b3fe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369343586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3369343586
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2651100648
Short name T245
Test name
Test status
Simulation time 1467691096 ps
CPU time 16.76 seconds
Started Aug 18 05:51:24 PM PDT 24
Finished Aug 18 05:51:41 PM PDT 24
Peak memory 224636 kb
Host smart-024094b4-b74e-4fff-9bb8-068571faec03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651100648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2651100648
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3983277880
Short name T199
Test name
Test status
Simulation time 17647562282 ps
CPU time 34.6 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:52:06 PM PDT 24
Peak memory 249564 kb
Host smart-6f38312a-64a8-4569-bb50-90ae41fb91e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983277880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3983277880
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2860290295
Short name T473
Test name
Test status
Simulation time 603319191 ps
CPU time 2.39 seconds
Started Aug 18 05:51:32 PM PDT 24
Finished Aug 18 05:51:35 PM PDT 24
Peak memory 232764 kb
Host smart-6ce6d0fd-f6c5-4b31-b4a1-207d62e5acb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860290295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2860290295
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3744316207
Short name T523
Test name
Test status
Simulation time 450249222 ps
CPU time 3.23 seconds
Started Aug 18 05:51:32 PM PDT 24
Finished Aug 18 05:51:35 PM PDT 24
Peak memory 224660 kb
Host smart-aa50ea63-ca02-41fc-836b-d23d31e96594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744316207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3744316207
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2485973548
Short name T742
Test name
Test status
Simulation time 1772750631 ps
CPU time 8.78 seconds
Started Aug 18 05:51:34 PM PDT 24
Finished Aug 18 05:51:43 PM PDT 24
Peak memory 222692 kb
Host smart-7168723c-ff9e-4027-909b-aa4af3e11807
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2485973548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2485973548
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.4232380377
Short name T450
Test name
Test status
Simulation time 18297939705 ps
CPU time 118.18 seconds
Started Aug 18 05:51:32 PM PDT 24
Finished Aug 18 05:53:30 PM PDT 24
Peak memory 255208 kb
Host smart-58c28b88-7d80-4152-aaf3-3fe58d915c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232380377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.4232380377
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3242894206
Short name T468
Test name
Test status
Simulation time 71882175766 ps
CPU time 43.25 seconds
Started Aug 18 05:51:30 PM PDT 24
Finished Aug 18 05:52:14 PM PDT 24
Peak memory 216488 kb
Host smart-a313fce0-5078-403c-8b4a-1091833198df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242894206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3242894206
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1137514690
Short name T1003
Test name
Test status
Simulation time 722269468 ps
CPU time 6.57 seconds
Started Aug 18 05:51:32 PM PDT 24
Finished Aug 18 05:51:38 PM PDT 24
Peak memory 216344 kb
Host smart-0fa652c7-576c-4903-9e01-65046355bb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137514690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1137514690
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1166587920
Short name T618
Test name
Test status
Simulation time 23371881 ps
CPU time 1.15 seconds
Started Aug 18 05:51:23 PM PDT 24
Finished Aug 18 05:51:24 PM PDT 24
Peak memory 208224 kb
Host smart-f646345a-d6aa-420f-afef-63e3b3acf51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166587920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1166587920
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.792729371
Short name T372
Test name
Test status
Simulation time 50685042 ps
CPU time 0.88 seconds
Started Aug 18 05:51:24 PM PDT 24
Finished Aug 18 05:51:25 PM PDT 24
Peak memory 206064 kb
Host smart-cd0e035a-befe-418b-83c4-5b7c4400504e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792729371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.792729371
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2474478351
Short name T5
Test name
Test status
Simulation time 536183972 ps
CPU time 6.88 seconds
Started Aug 18 05:51:35 PM PDT 24
Finished Aug 18 05:51:42 PM PDT 24
Peak memory 232864 kb
Host smart-48be9379-86ed-4653-ab39-804c1b3ae138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474478351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2474478351
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.4231936623
Short name T526
Test name
Test status
Simulation time 10684790 ps
CPU time 0.7 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:51:32 PM PDT 24
Peak memory 204912 kb
Host smart-3e0cc991-42ea-418c-ab1b-e1177f26a2cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231936623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4231936623
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.302731938
Short name T336
Test name
Test status
Simulation time 1061016763 ps
CPU time 11.04 seconds
Started Aug 18 05:51:35 PM PDT 24
Finished Aug 18 05:51:46 PM PDT 24
Peak memory 224604 kb
Host smart-106c0637-accb-4499-a1a6-a7310f487513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302731938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.302731938
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3254706258
Short name T779
Test name
Test status
Simulation time 231937635 ps
CPU time 0.78 seconds
Started Aug 18 05:51:28 PM PDT 24
Finished Aug 18 05:51:29 PM PDT 24
Peak memory 206560 kb
Host smart-905d3425-7e10-4ff9-b211-fa8721c6238b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254706258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3254706258
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.639713023
Short name T752
Test name
Test status
Simulation time 11420085119 ps
CPU time 107.4 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:53:19 PM PDT 24
Peak memory 250556 kb
Host smart-710c524d-8479-49ad-879a-eeaf7f8f8164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639713023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.639713023
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3002769557
Short name T725
Test name
Test status
Simulation time 28616609042 ps
CPU time 73.65 seconds
Started Aug 18 05:51:34 PM PDT 24
Finished Aug 18 05:52:47 PM PDT 24
Peak memory 252440 kb
Host smart-633ca369-a89c-482d-8934-0e091173e28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002769557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3002769557
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2741206477
Short name T70
Test name
Test status
Simulation time 23757594273 ps
CPU time 144.19 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:53:53 PM PDT 24
Peak memory 255576 kb
Host smart-b707effa-8d3c-468c-801e-fb99b10eba11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741206477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2741206477
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3142092391
Short name T125
Test name
Test status
Simulation time 225274111 ps
CPU time 6.53 seconds
Started Aug 18 05:51:34 PM PDT 24
Finished Aug 18 05:51:41 PM PDT 24
Peak memory 232900 kb
Host smart-5bd81e83-d6cb-4400-8c63-f042eb283a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142092391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3142092391
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3904712483
Short name T850
Test name
Test status
Simulation time 14017339455 ps
CPU time 106.2 seconds
Started Aug 18 05:51:32 PM PDT 24
Finished Aug 18 05:53:18 PM PDT 24
Peak memory 250348 kb
Host smart-a3a11717-a1d4-4e49-bf2a-9cf606a338fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904712483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3904712483
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2057612266
Short name T169
Test name
Test status
Simulation time 4701459878 ps
CPU time 51.53 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:52:22 PM PDT 24
Peak memory 224684 kb
Host smart-4665427f-daef-439e-8b9d-2c835168f78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057612266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2057612266
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.7657981
Short name T213
Test name
Test status
Simulation time 7793918200 ps
CPU time 42.01 seconds
Started Aug 18 05:51:35 PM PDT 24
Finished Aug 18 05:52:17 PM PDT 24
Peak memory 233900 kb
Host smart-b2f8d36c-6047-406b-927b-6d21f99073e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7657981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.7657981
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2388132556
Short name T815
Test name
Test status
Simulation time 33603631 ps
CPU time 2.53 seconds
Started Aug 18 05:51:32 PM PDT 24
Finished Aug 18 05:51:35 PM PDT 24
Peak memory 232832 kb
Host smart-0cba6ac8-8417-4e3e-9b8e-f736596858e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388132556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2388132556
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1555069383
Short name T223
Test name
Test status
Simulation time 553946420 ps
CPU time 2.72 seconds
Started Aug 18 05:51:38 PM PDT 24
Finished Aug 18 05:51:41 PM PDT 24
Peak memory 232836 kb
Host smart-652926c4-41ac-436a-a4a2-0a38c6892c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555069383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1555069383
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1851754503
Short name T123
Test name
Test status
Simulation time 491503407 ps
CPU time 4.14 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:51:33 PM PDT 24
Peak memory 223332 kb
Host smart-77c5aaec-c2dc-452d-bf1b-daf4db40f958
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1851754503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1851754503
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1330985530
Short name T810
Test name
Test status
Simulation time 220451522 ps
CPU time 0.94 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:51:30 PM PDT 24
Peak memory 205884 kb
Host smart-6fe9070a-159b-49c7-a04d-1694de55f4ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330985530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1330985530
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3665988903
Short name T561
Test name
Test status
Simulation time 10240267684 ps
CPU time 19.85 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:51:49 PM PDT 24
Peak memory 216488 kb
Host smart-90761bbf-7c48-4545-ad85-d435f1e5ae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665988903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3665988903
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.805827552
Short name T902
Test name
Test status
Simulation time 1784928586 ps
CPU time 1.86 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:51:31 PM PDT 24
Peak memory 207144 kb
Host smart-6eeb3873-0128-4163-a226-ea4af77e7577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805827552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.805827552
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2013142449
Short name T462
Test name
Test status
Simulation time 15301459 ps
CPU time 0.82 seconds
Started Aug 18 05:51:30 PM PDT 24
Finished Aug 18 05:51:31 PM PDT 24
Peak memory 206716 kb
Host smart-07e0306e-3327-4bbd-8d81-a520e7a121e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013142449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2013142449
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.370417220
Short name T687
Test name
Test status
Simulation time 116370308 ps
CPU time 0.95 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:51:30 PM PDT 24
Peak memory 206056 kb
Host smart-68a6ec1e-3c31-407b-9409-ccc0a7705922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370417220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.370417220
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3253458399
Short name T780
Test name
Test status
Simulation time 54870532 ps
CPU time 2.53 seconds
Started Aug 18 05:51:33 PM PDT 24
Finished Aug 18 05:51:36 PM PDT 24
Peak memory 232804 kb
Host smart-cfef384a-4d7d-4a0c-a032-4e24b51e7f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253458399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3253458399
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3704340195
Short name T525
Test name
Test status
Simulation time 30788476 ps
CPU time 0.7 seconds
Started Aug 18 05:51:30 PM PDT 24
Finished Aug 18 05:51:31 PM PDT 24
Peak memory 205516 kb
Host smart-e0e336d8-179e-46f9-8432-d9c35077ce20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704340195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3704340195
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3562553206
Short name T772
Test name
Test status
Simulation time 573260134 ps
CPU time 8.56 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:51:37 PM PDT 24
Peak memory 224676 kb
Host smart-6dfefea5-ca70-4c02-92b5-05e0b4cb0a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562553206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3562553206
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3476009417
Short name T877
Test name
Test status
Simulation time 47658057 ps
CPU time 0.79 seconds
Started Aug 18 05:51:33 PM PDT 24
Finished Aug 18 05:51:34 PM PDT 24
Peak memory 206572 kb
Host smart-f4535f0b-5f8f-4418-8d88-296372a616da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476009417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3476009417
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.552963444
Short name T864
Test name
Test status
Simulation time 56511195444 ps
CPU time 150.79 seconds
Started Aug 18 05:51:34 PM PDT 24
Finished Aug 18 05:54:10 PM PDT 24
Peak memory 266564 kb
Host smart-c6252f98-68b0-489e-91bc-3757ddf7e2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552963444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.552963444
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1499683563
Short name T164
Test name
Test status
Simulation time 48285827902 ps
CPU time 474.63 seconds
Started Aug 18 05:51:35 PM PDT 24
Finished Aug 18 05:59:29 PM PDT 24
Peak memory 257168 kb
Host smart-f56ca26d-3d93-4c93-808b-6d25cf4e57c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499683563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1499683563
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1114909311
Short name T40
Test name
Test status
Simulation time 37079409114 ps
CPU time 28.13 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:51:59 PM PDT 24
Peak memory 232988 kb
Host smart-0d0b0a13-685f-4d79-bf96-8a4674c13a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114909311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1114909311
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2012253788
Short name T278
Test name
Test status
Simulation time 1954505452 ps
CPU time 16.32 seconds
Started Aug 18 05:51:31 PM PDT 24
Finished Aug 18 05:51:48 PM PDT 24
Peak memory 224664 kb
Host smart-4e683c36-fc18-4f02-8ed3-63669728de61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012253788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2012253788
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.4109709014
Short name T176
Test name
Test status
Simulation time 35862649191 ps
CPU time 120.64 seconds
Started Aug 18 05:51:32 PM PDT 24
Finished Aug 18 05:53:33 PM PDT 24
Peak memory 241096 kb
Host smart-a438ee06-37ec-4f73-aeee-3b2ef88163a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109709014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.4109709014
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1749933704
Short name T421
Test name
Test status
Simulation time 4374079743 ps
CPU time 19.58 seconds
Started Aug 18 05:51:34 PM PDT 24
Finished Aug 18 05:51:54 PM PDT 24
Peak memory 224620 kb
Host smart-37534ca5-4c7d-47aa-b112-ac7147243f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749933704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1749933704
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3052429388
Short name T983
Test name
Test status
Simulation time 31017504106 ps
CPU time 94.34 seconds
Started Aug 18 05:51:37 PM PDT 24
Finished Aug 18 05:53:12 PM PDT 24
Peak memory 240464 kb
Host smart-b2bca876-9f2d-486b-b38c-55158dda25ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052429388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3052429388
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2599839697
Short name T263
Test name
Test status
Simulation time 1415883477 ps
CPU time 6.34 seconds
Started Aug 18 05:51:34 PM PDT 24
Finished Aug 18 05:51:40 PM PDT 24
Peak memory 241012 kb
Host smart-59664fc5-fe4e-41c9-9bc2-f3b587b07cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599839697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2599839697
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.559635964
Short name T524
Test name
Test status
Simulation time 1902156867 ps
CPU time 5.58 seconds
Started Aug 18 05:51:34 PM PDT 24
Finished Aug 18 05:51:40 PM PDT 24
Peak memory 232888 kb
Host smart-0431b192-ef1d-410a-88fb-c8fc951010ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559635964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.559635964
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1629653960
Short name T916
Test name
Test status
Simulation time 735574286 ps
CPU time 6.75 seconds
Started Aug 18 05:51:33 PM PDT 24
Finished Aug 18 05:51:40 PM PDT 24
Peak memory 223128 kb
Host smart-808b883a-314d-4f12-8f55-15b7677d2023
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1629653960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1629653960
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.352671032
Short name T16
Test name
Test status
Simulation time 15788198724 ps
CPU time 137.68 seconds
Started Aug 18 05:51:35 PM PDT 24
Finished Aug 18 05:53:53 PM PDT 24
Peak memory 266000 kb
Host smart-7b3455e9-02a1-4170-9184-095213dc04ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352671032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.352671032
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1079668863
Short name T426
Test name
Test status
Simulation time 22241177079 ps
CPU time 33.18 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:52:03 PM PDT 24
Peak memory 216444 kb
Host smart-30bd5e1f-4ab0-4485-a832-7fd3ee7d5a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079668863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1079668863
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1333139879
Short name T337
Test name
Test status
Simulation time 643593291 ps
CPU time 2.75 seconds
Started Aug 18 05:51:36 PM PDT 24
Finished Aug 18 05:51:39 PM PDT 24
Peak memory 216440 kb
Host smart-236409f3-66a8-4286-9f4c-0a3ac1c4b5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333139879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1333139879
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2133760790
Short name T409
Test name
Test status
Simulation time 147063975 ps
CPU time 1.89 seconds
Started Aug 18 05:51:30 PM PDT 24
Finished Aug 18 05:51:32 PM PDT 24
Peak memory 216488 kb
Host smart-4b7203c3-fc2f-4ceb-ac39-e7d765e6f772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133760790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2133760790
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.180244464
Short name T934
Test name
Test status
Simulation time 88846787 ps
CPU time 0.82 seconds
Started Aug 18 05:51:32 PM PDT 24
Finished Aug 18 05:51:33 PM PDT 24
Peak memory 206080 kb
Host smart-96490c4f-35e7-4229-a7d5-092c07b962fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180244464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.180244464
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.972708977
Short name T701
Test name
Test status
Simulation time 1625007579 ps
CPU time 8.1 seconds
Started Aug 18 05:51:29 PM PDT 24
Finished Aug 18 05:51:37 PM PDT 24
Peak memory 241032 kb
Host smart-503de466-9d4a-47f4-9e8a-3c78f8d1c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972708977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.972708977
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3830342585
Short name T782
Test name
Test status
Simulation time 58152257 ps
CPU time 0.69 seconds
Started Aug 18 05:49:19 PM PDT 24
Finished Aug 18 05:49:20 PM PDT 24
Peak memory 205476 kb
Host smart-6bf188ac-d652-4272-bfd2-9b21bcf9fadc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830342585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
830342585
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4209874760
Short name T166
Test name
Test status
Simulation time 144603590 ps
CPU time 2.27 seconds
Started Aug 18 05:49:10 PM PDT 24
Finished Aug 18 05:49:12 PM PDT 24
Peak memory 224632 kb
Host smart-f4c98d0b-4896-4d62-aaa6-1a9035cf15d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209874760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4209874760
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1551220843
Short name T370
Test name
Test status
Simulation time 13157088 ps
CPU time 0.72 seconds
Started Aug 18 05:49:11 PM PDT 24
Finished Aug 18 05:49:12 PM PDT 24
Peak memory 205476 kb
Host smart-a1b0577a-7b4d-48f7-91a4-73092a624703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551220843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1551220843
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3282866669
Short name T619
Test name
Test status
Simulation time 5683074884 ps
CPU time 33.62 seconds
Started Aug 18 05:49:18 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 252124 kb
Host smart-65b9b912-063d-4f30-be9f-2388d0bfa6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282866669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3282866669
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2048570773
Short name T645
Test name
Test status
Simulation time 18640809254 ps
CPU time 232.15 seconds
Started Aug 18 05:49:11 PM PDT 24
Finished Aug 18 05:53:03 PM PDT 24
Peak memory 266388 kb
Host smart-3fb419de-209d-4775-9588-2209d1a042d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048570773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2048570773
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3082525545
Short name T119
Test name
Test status
Simulation time 56918478074 ps
CPU time 603.69 seconds
Started Aug 18 05:49:13 PM PDT 24
Finished Aug 18 05:59:17 PM PDT 24
Peak memory 264156 kb
Host smart-fa151876-ce57-4dfe-a29c-db93773b809e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082525545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3082525545
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1519089213
Short name T358
Test name
Test status
Simulation time 249097795 ps
CPU time 6.7 seconds
Started Aug 18 05:49:16 PM PDT 24
Finished Aug 18 05:49:23 PM PDT 24
Peak memory 232828 kb
Host smart-723fc329-b048-4d30-b9ac-22efc3791490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519089213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1519089213
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3632293754
Short name T210
Test name
Test status
Simulation time 30713669276 ps
CPU time 88.51 seconds
Started Aug 18 05:49:11 PM PDT 24
Finished Aug 18 05:50:40 PM PDT 24
Peak memory 252960 kb
Host smart-15ca9391-7783-4f2a-a496-460b7fc0da27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632293754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3632293754
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.771227063
Short name T776
Test name
Test status
Simulation time 4235152451 ps
CPU time 10.61 seconds
Started Aug 18 05:49:12 PM PDT 24
Finished Aug 18 05:49:23 PM PDT 24
Peak memory 228692 kb
Host smart-cdb1c624-35b2-49b5-afea-aad2cf00105b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771227063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.771227063
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.79566027
Short name T979
Test name
Test status
Simulation time 46053484 ps
CPU time 2.7 seconds
Started Aug 18 05:49:09 PM PDT 24
Finished Aug 18 05:49:12 PM PDT 24
Peak memory 232852 kb
Host smart-fba5d377-8d0d-41d0-925e-be83d01c51c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79566027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.79566027
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.298888580
Short name T964
Test name
Test status
Simulation time 132428197 ps
CPU time 1.08 seconds
Started Aug 18 05:49:17 PM PDT 24
Finished Aug 18 05:49:18 PM PDT 24
Peak memory 217940 kb
Host smart-9f48f16a-9c73-40a2-9ace-30d1e27624d0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298888580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.298888580
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2505080076
Short name T465
Test name
Test status
Simulation time 76714827 ps
CPU time 2.48 seconds
Started Aug 18 05:49:16 PM PDT 24
Finished Aug 18 05:49:19 PM PDT 24
Peak memory 232824 kb
Host smart-3c9b0d84-9e29-4216-bad7-b32d0cbdedc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505080076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2505080076
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1133216992
Short name T858
Test name
Test status
Simulation time 435821794 ps
CPU time 2.08 seconds
Started Aug 18 05:49:13 PM PDT 24
Finished Aug 18 05:49:15 PM PDT 24
Peak memory 223208 kb
Host smart-99aae167-405b-40c4-96d1-063d8d550999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133216992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1133216992
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2346455484
Short name T579
Test name
Test status
Simulation time 6019341516 ps
CPU time 7.55 seconds
Started Aug 18 05:49:13 PM PDT 24
Finished Aug 18 05:49:21 PM PDT 24
Peak memory 220416 kb
Host smart-7fa4762e-94bb-41a1-9695-ca3d65481956
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2346455484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2346455484
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4073359723
Short name T1009
Test name
Test status
Simulation time 134280602605 ps
CPU time 364.16 seconds
Started Aug 18 05:49:09 PM PDT 24
Finished Aug 18 05:55:13 PM PDT 24
Peak memory 253144 kb
Host smart-a2179726-b4b5-418c-9c52-219c993aefd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073359723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4073359723
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2429921359
Short name T670
Test name
Test status
Simulation time 8780344068 ps
CPU time 42.41 seconds
Started Aug 18 05:49:10 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 216476 kb
Host smart-f8e1df1d-5908-4554-8985-83012d4551ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429921359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2429921359
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3150157896
Short name T2
Test name
Test status
Simulation time 2516579682 ps
CPU time 3.11 seconds
Started Aug 18 05:49:09 PM PDT 24
Finished Aug 18 05:49:12 PM PDT 24
Peak memory 216512 kb
Host smart-125f367b-a43a-4de6-bbc1-8ba38cdfecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150157896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3150157896
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.930704060
Short name T415
Test name
Test status
Simulation time 84286799 ps
CPU time 1.38 seconds
Started Aug 18 05:49:15 PM PDT 24
Finished Aug 18 05:49:17 PM PDT 24
Peak memory 216380 kb
Host smart-c22e81a9-e435-408a-a283-ec42dd02237d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930704060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.930704060
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1013527133
Short name T559
Test name
Test status
Simulation time 88447241 ps
CPU time 0.96 seconds
Started Aug 18 05:49:22 PM PDT 24
Finished Aug 18 05:49:23 PM PDT 24
Peak memory 206060 kb
Host smart-25e9049d-9d5d-425b-92e8-2a8b462fb4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013527133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1013527133
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3534024635
Short name T585
Test name
Test status
Simulation time 3360926727 ps
CPU time 15.64 seconds
Started Aug 18 05:49:26 PM PDT 24
Finished Aug 18 05:49:42 PM PDT 24
Peak memory 232912 kb
Host smart-fecfe9e4-32c4-47dd-900d-a9fd740eeca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534024635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3534024635
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2232903420
Short name T962
Test name
Test status
Simulation time 15607348 ps
CPU time 0.73 seconds
Started Aug 18 05:49:10 PM PDT 24
Finished Aug 18 05:49:11 PM PDT 24
Peak memory 205448 kb
Host smart-a9faafc7-88d2-456d-96d4-7da281f370fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232903420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
232903420
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2088142909
Short name T162
Test name
Test status
Simulation time 398186037 ps
CPU time 2.83 seconds
Started Aug 18 05:49:14 PM PDT 24
Finished Aug 18 05:49:17 PM PDT 24
Peak memory 232808 kb
Host smart-adeb0164-e09a-49d8-bc6d-c0ab08ed6eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088142909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2088142909
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1275230944
Short name T982
Test name
Test status
Simulation time 38004145 ps
CPU time 0.72 seconds
Started Aug 18 05:49:08 PM PDT 24
Finished Aug 18 05:49:09 PM PDT 24
Peak memory 206572 kb
Host smart-7b198fa7-b8bf-47f5-ada5-19354bf47ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275230944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1275230944
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.165884814
Short name T867
Test name
Test status
Simulation time 634280170 ps
CPU time 12.01 seconds
Started Aug 18 05:49:09 PM PDT 24
Finished Aug 18 05:49:21 PM PDT 24
Peak memory 249744 kb
Host smart-7e48c077-dcf1-4188-8833-6beab2fc1dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165884814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.165884814
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1887570562
Short name T1029
Test name
Test status
Simulation time 527144327355 ps
CPU time 211.3 seconds
Started Aug 18 05:49:10 PM PDT 24
Finished Aug 18 05:52:41 PM PDT 24
Peak memory 256680 kb
Host smart-c3dfde73-ea50-45fc-91fe-adfa9d6a8043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887570562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1887570562
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2371386987
Short name T255
Test name
Test status
Simulation time 4587245941 ps
CPU time 66.82 seconds
Started Aug 18 05:49:16 PM PDT 24
Finished Aug 18 05:50:23 PM PDT 24
Peak memory 256604 kb
Host smart-b2df6132-02ef-46d9-a80e-456ddd077cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371386987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2371386987
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3597176875
Short name T366
Test name
Test status
Simulation time 100575750 ps
CPU time 2.79 seconds
Started Aug 18 05:49:18 PM PDT 24
Finished Aug 18 05:49:21 PM PDT 24
Peak memory 232732 kb
Host smart-8f8ff10a-209b-4327-bb35-77a537fdedaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597176875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3597176875
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.983919600
Short name T36
Test name
Test status
Simulation time 8328921213 ps
CPU time 56.6 seconds
Started Aug 18 05:49:16 PM PDT 24
Finished Aug 18 05:50:13 PM PDT 24
Peak memory 249292 kb
Host smart-2603cff3-104b-4aa0-96e6-b2a8efaf87d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983919600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
983919600
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2035646354
Short name T394
Test name
Test status
Simulation time 108415625 ps
CPU time 2.27 seconds
Started Aug 18 05:49:08 PM PDT 24
Finished Aug 18 05:49:10 PM PDT 24
Peak memory 224556 kb
Host smart-a613e55e-0cf6-4101-afd5-765c31dea652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035646354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2035646354
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3153044372
Short name T968
Test name
Test status
Simulation time 194884802 ps
CPU time 3.82 seconds
Started Aug 18 05:49:18 PM PDT 24
Finished Aug 18 05:49:22 PM PDT 24
Peak memory 232848 kb
Host smart-d4db85a4-dead-4660-8444-b3278c09558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153044372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3153044372
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.4009993069
Short name T661
Test name
Test status
Simulation time 32051100 ps
CPU time 1.05 seconds
Started Aug 18 05:49:17 PM PDT 24
Finished Aug 18 05:49:18 PM PDT 24
Peak memory 216696 kb
Host smart-64a19fbe-80f6-499d-ba88-f19e1135b567
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009993069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.4009993069
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1269423074
Short name T913
Test name
Test status
Simulation time 31591603070 ps
CPU time 17.96 seconds
Started Aug 18 05:49:10 PM PDT 24
Finished Aug 18 05:49:28 PM PDT 24
Peak memory 224700 kb
Host smart-782a5f0c-c6fb-449f-b52c-16148e0dfddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269423074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1269423074
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1026746789
Short name T844
Test name
Test status
Simulation time 1639470563 ps
CPU time 7.1 seconds
Started Aug 18 05:49:15 PM PDT 24
Finished Aug 18 05:49:22 PM PDT 24
Peak memory 224648 kb
Host smart-e58215b8-699a-4b73-b253-3ec6fbfbbf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026746789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1026746789
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2952399078
Short name T836
Test name
Test status
Simulation time 3252602956 ps
CPU time 6.06 seconds
Started Aug 18 05:49:12 PM PDT 24
Finished Aug 18 05:49:18 PM PDT 24
Peak memory 219584 kb
Host smart-3ac83469-8901-43b5-8c0c-45edef47e964
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2952399078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2952399078
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2781615320
Short name T284
Test name
Test status
Simulation time 43660398159 ps
CPU time 20.87 seconds
Started Aug 18 05:49:20 PM PDT 24
Finished Aug 18 05:49:41 PM PDT 24
Peak memory 216464 kb
Host smart-371e859c-a5f6-4237-8002-5cf0682fbada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781615320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2781615320
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1573070721
Short name T1004
Test name
Test status
Simulation time 254385962 ps
CPU time 1.86 seconds
Started Aug 18 05:49:17 PM PDT 24
Finished Aug 18 05:49:19 PM PDT 24
Peak memory 216260 kb
Host smart-6525e3a3-054b-4d1b-9237-362ba52484ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573070721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1573070721
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1932443968
Short name T406
Test name
Test status
Simulation time 56427180 ps
CPU time 1.42 seconds
Started Aug 18 05:49:12 PM PDT 24
Finished Aug 18 05:49:14 PM PDT 24
Peak memory 216424 kb
Host smart-0bae5284-58c6-421d-a894-2ca071f02c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932443968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1932443968
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.219426575
Short name T557
Test name
Test status
Simulation time 82184646 ps
CPU time 0.91 seconds
Started Aug 18 05:49:10 PM PDT 24
Finished Aug 18 05:49:11 PM PDT 24
Peak memory 207100 kb
Host smart-304a9a30-a644-4fd4-835f-c3f3b3eebd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219426575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.219426575
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2941184792
Short name T848
Test name
Test status
Simulation time 3539969047 ps
CPU time 12.88 seconds
Started Aug 18 05:49:10 PM PDT 24
Finished Aug 18 05:49:22 PM PDT 24
Peak memory 240764 kb
Host smart-34192223-0436-4c53-bbad-b1f1a82e805b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941184792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2941184792
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2115615151
Short name T597
Test name
Test status
Simulation time 13380092 ps
CPU time 0.73 seconds
Started Aug 18 05:49:17 PM PDT 24
Finished Aug 18 05:49:18 PM PDT 24
Peak memory 204900 kb
Host smart-c2f3e3bd-17ab-4316-9d18-e23c7a9594b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115615151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
115615151
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3209573604
Short name T536
Test name
Test status
Simulation time 114190755 ps
CPU time 2.07 seconds
Started Aug 18 05:49:20 PM PDT 24
Finished Aug 18 05:49:22 PM PDT 24
Peak memory 224152 kb
Host smart-dd807d42-b5b6-451a-ae55-122c56cd86cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209573604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3209573604
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2669669283
Short name T889
Test name
Test status
Simulation time 98401940 ps
CPU time 0.72 seconds
Started Aug 18 05:49:15 PM PDT 24
Finished Aug 18 05:49:16 PM PDT 24
Peak memory 205520 kb
Host smart-c31781c0-a07b-4f5d-a220-5a52b2a6d160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669669283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2669669283
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.208227841
Short name T476
Test name
Test status
Simulation time 3213251035 ps
CPU time 19.01 seconds
Started Aug 18 05:49:17 PM PDT 24
Finished Aug 18 05:49:36 PM PDT 24
Peak memory 249212 kb
Host smart-51305b5e-43fb-4e8b-b824-ffb664ba9b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208227841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.208227841
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3165822241
Short name T785
Test name
Test status
Simulation time 6445623873 ps
CPU time 77.95 seconds
Started Aug 18 05:49:21 PM PDT 24
Finished Aug 18 05:50:39 PM PDT 24
Peak memory 251588 kb
Host smart-7a320bbe-5d54-4d99-9229-9fbc55d88cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165822241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3165822241
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.269453320
Short name T504
Test name
Test status
Simulation time 12975068139 ps
CPU time 55.96 seconds
Started Aug 18 05:49:17 PM PDT 24
Finished Aug 18 05:50:14 PM PDT 24
Peak memory 233920 kb
Host smart-67f49a73-acc8-4fc8-98e4-6048c123d4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269453320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
269453320
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1285975825
Short name T768
Test name
Test status
Simulation time 1925143730 ps
CPU time 30.94 seconds
Started Aug 18 05:49:16 PM PDT 24
Finished Aug 18 05:49:47 PM PDT 24
Peak memory 232860 kb
Host smart-97040131-47a8-41c6-b2a8-441d3d527df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285975825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1285975825
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.865168663
Short name T940
Test name
Test status
Simulation time 53241539172 ps
CPU time 98.47 seconds
Started Aug 18 05:49:23 PM PDT 24
Finished Aug 18 05:51:01 PM PDT 24
Peak memory 249440 kb
Host smart-493ddfb2-4b62-490d-b78f-335354007582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865168663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
865168663
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4119628476
Short name T986
Test name
Test status
Simulation time 2032885822 ps
CPU time 12.93 seconds
Started Aug 18 05:49:19 PM PDT 24
Finished Aug 18 05:49:32 PM PDT 24
Peak memory 224644 kb
Host smart-526316a2-ed6c-4a21-b18a-cdee0e57708f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119628476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4119628476
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.988402930
Short name T440
Test name
Test status
Simulation time 1018733066 ps
CPU time 7.65 seconds
Started Aug 18 05:49:18 PM PDT 24
Finished Aug 18 05:49:26 PM PDT 24
Peak memory 235940 kb
Host smart-0f4d5ebc-86ce-4f9f-847f-2033c8bf95ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988402930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.988402930
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.844925794
Short name T897
Test name
Test status
Simulation time 35875483 ps
CPU time 1.09 seconds
Started Aug 18 05:49:10 PM PDT 24
Finished Aug 18 05:49:11 PM PDT 24
Peak memory 216644 kb
Host smart-d2d99a30-7716-4d6a-8c65-54a62616557e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844925794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.844925794
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2650952288
Short name T244
Test name
Test status
Simulation time 7701133244 ps
CPU time 12.94 seconds
Started Aug 18 05:49:18 PM PDT 24
Finished Aug 18 05:49:31 PM PDT 24
Peak memory 224864 kb
Host smart-f3940bbc-7ce3-40b5-8756-8ec4a51226a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650952288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2650952288
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2269696868
Short name T530
Test name
Test status
Simulation time 54408219 ps
CPU time 2.02 seconds
Started Aug 18 05:49:15 PM PDT 24
Finished Aug 18 05:49:17 PM PDT 24
Peak memory 223036 kb
Host smart-6b893fc0-9f2d-4dde-a27f-d7c83cda228c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269696868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2269696868
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2058063046
Short name T330
Test name
Test status
Simulation time 4252255400 ps
CPU time 13.71 seconds
Started Aug 18 05:49:22 PM PDT 24
Finished Aug 18 05:49:35 PM PDT 24
Peak memory 222116 kb
Host smart-bc59cee1-2aaa-4eb5-80ac-12e4630719d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2058063046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2058063046
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2397016342
Short name T649
Test name
Test status
Simulation time 125879778 ps
CPU time 0.82 seconds
Started Aug 18 05:49:16 PM PDT 24
Finished Aug 18 05:49:17 PM PDT 24
Peak memory 206924 kb
Host smart-462b5523-7219-49cb-8535-34e0df1f00c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397016342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2397016342
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4136239244
Short name T733
Test name
Test status
Simulation time 531967377 ps
CPU time 4.01 seconds
Started Aug 18 05:49:27 PM PDT 24
Finished Aug 18 05:49:31 PM PDT 24
Peak memory 216340 kb
Host smart-93e174c8-dc3c-47fe-815d-56eff940199e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136239244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4136239244
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3328704720
Short name T395
Test name
Test status
Simulation time 940756959 ps
CPU time 1.96 seconds
Started Aug 18 05:49:16 PM PDT 24
Finished Aug 18 05:49:18 PM PDT 24
Peak memory 208028 kb
Host smart-fdc8289d-4040-4946-9652-6da588a03438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328704720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3328704720
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3906031590
Short name T677
Test name
Test status
Simulation time 73415136 ps
CPU time 1.38 seconds
Started Aug 18 05:49:20 PM PDT 24
Finished Aug 18 05:49:21 PM PDT 24
Peak memory 208236 kb
Host smart-9b6cc451-8ad7-494d-8015-96e4f98c1caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906031590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3906031590
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.921982260
Short name T911
Test name
Test status
Simulation time 54602164 ps
CPU time 0.71 seconds
Started Aug 18 05:49:17 PM PDT 24
Finished Aug 18 05:49:17 PM PDT 24
Peak memory 206064 kb
Host smart-f9608bce-47ae-426d-b8fc-da364d32063d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921982260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.921982260
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1502526712
Short name T931
Test name
Test status
Simulation time 8790617067 ps
CPU time 16.27 seconds
Started Aug 18 05:49:15 PM PDT 24
Finished Aug 18 05:49:32 PM PDT 24
Peak memory 232904 kb
Host smart-5ebf8bc1-57ae-4931-9964-22e86f74f316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502526712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1502526712
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1572508689
Short name T933
Test name
Test status
Simulation time 22705530 ps
CPU time 0.69 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:49:33 PM PDT 24
Peak memory 204836 kb
Host smart-2ad3ffb5-c3ea-4df9-97fd-52527ef77883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572508689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
572508689
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2843417583
Short name T875
Test name
Test status
Simulation time 962160747 ps
CPU time 10.49 seconds
Started Aug 18 05:49:21 PM PDT 24
Finished Aug 18 05:49:32 PM PDT 24
Peak memory 224656 kb
Host smart-09010325-4bfd-4f89-b698-88839b66babe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843417583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2843417583
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.279989233
Short name T587
Test name
Test status
Simulation time 46874146 ps
CPU time 0.74 seconds
Started Aug 18 05:49:21 PM PDT 24
Finished Aug 18 05:49:21 PM PDT 24
Peak memory 205560 kb
Host smart-ba6847fb-b1fa-4f0e-b20d-10b853ea2dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279989233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.279989233
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4176638177
Short name T745
Test name
Test status
Simulation time 4421267009 ps
CPU time 22.31 seconds
Started Aug 18 05:49:17 PM PDT 24
Finished Aug 18 05:49:40 PM PDT 24
Peak memory 237564 kb
Host smart-6b00026e-dcac-404c-a8f2-07ea679a2ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176638177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4176638177
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.705858129
Short name T448
Test name
Test status
Simulation time 2039779456 ps
CPU time 46.33 seconds
Started Aug 18 05:49:21 PM PDT 24
Finished Aug 18 05:50:07 PM PDT 24
Peak memory 257472 kb
Host smart-87739a1e-fc97-4513-b491-e251dd1873f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705858129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.705858129
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1070840637
Short name T182
Test name
Test status
Simulation time 30146747946 ps
CPU time 101.79 seconds
Started Aug 18 05:49:32 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 253712 kb
Host smart-f5803b13-eec3-496d-aa40-a33a65cef4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070840637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1070840637
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.286053799
Short name T271
Test name
Test status
Simulation time 7826571353 ps
CPU time 62.48 seconds
Started Aug 18 05:49:21 PM PDT 24
Finished Aug 18 05:50:24 PM PDT 24
Peak memory 232824 kb
Host smart-05bd07a4-de7d-48a2-863d-8eb8b8504adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286053799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.286053799
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2375649724
Short name T919
Test name
Test status
Simulation time 86534356282 ps
CPU time 117.44 seconds
Started Aug 18 05:49:16 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 249352 kb
Host smart-d61be395-f1ba-4f45-8851-46214e6496e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375649724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2375649724
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2796133644
Short name T998
Test name
Test status
Simulation time 8071074051 ps
CPU time 15.48 seconds
Started Aug 18 05:49:18 PM PDT 24
Finished Aug 18 05:49:33 PM PDT 24
Peak memory 232952 kb
Host smart-879bb9a4-2fcc-4238-8ebb-548b7c708d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796133644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2796133644
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.745605340
Short name T309
Test name
Test status
Simulation time 168329359 ps
CPU time 2.24 seconds
Started Aug 18 05:49:21 PM PDT 24
Finished Aug 18 05:49:23 PM PDT 24
Peak memory 224576 kb
Host smart-a921d370-c8ce-4a1d-b5dd-747a63c97b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745605340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.745605340
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3894682953
Short name T659
Test name
Test status
Simulation time 29525478 ps
CPU time 1.06 seconds
Started Aug 18 05:49:24 PM PDT 24
Finished Aug 18 05:49:25 PM PDT 24
Peak memory 217996 kb
Host smart-b2dbc036-625c-4cad-b334-17943b6d68f1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894682953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3894682953
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3230770970
Short name T397
Test name
Test status
Simulation time 17392879137 ps
CPU time 13.6 seconds
Started Aug 18 05:49:24 PM PDT 24
Finished Aug 18 05:49:37 PM PDT 24
Peak memory 240968 kb
Host smart-4b84b1cd-a22e-4bd1-9fc9-20364c9cadde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230770970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3230770970
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.651585090
Short name T508
Test name
Test status
Simulation time 1059893174 ps
CPU time 5.48 seconds
Started Aug 18 05:49:16 PM PDT 24
Finished Aug 18 05:49:21 PM PDT 24
Peak memory 224608 kb
Host smart-5e4670a4-3021-4020-a700-b55fdf0bd068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651585090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.651585090
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2619525378
Short name T50
Test name
Test status
Simulation time 133631502 ps
CPU time 3.29 seconds
Started Aug 18 05:49:24 PM PDT 24
Finished Aug 18 05:49:28 PM PDT 24
Peak memory 222764 kb
Host smart-f740ac99-7010-45c6-9254-225b8a2682b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2619525378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2619525378
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1679468518
Short name T992
Test name
Test status
Simulation time 276160181753 ps
CPU time 685.11 seconds
Started Aug 18 05:49:21 PM PDT 24
Finished Aug 18 06:00:47 PM PDT 24
Peak memory 290200 kb
Host smart-1c5bb724-a3e6-4ddc-9bbe-e2c38278abe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679468518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1679468518
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2003800962
Short name T799
Test name
Test status
Simulation time 1835303013 ps
CPU time 30.84 seconds
Started Aug 18 05:49:24 PM PDT 24
Finished Aug 18 05:49:55 PM PDT 24
Peak memory 216504 kb
Host smart-1e8f68ef-1d9c-4504-bc77-ec412373397c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003800962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2003800962
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3071337842
Short name T345
Test name
Test status
Simulation time 7747697430 ps
CPU time 24.51 seconds
Started Aug 18 05:49:24 PM PDT 24
Finished Aug 18 05:49:49 PM PDT 24
Peak memory 216500 kb
Host smart-edf8aadd-891a-442d-aec0-fdee2f21765d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071337842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3071337842
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4104588346
Short name T289
Test name
Test status
Simulation time 34519208 ps
CPU time 1.14 seconds
Started Aug 18 05:49:15 PM PDT 24
Finished Aug 18 05:49:16 PM PDT 24
Peak memory 208184 kb
Host smart-d254e4cc-2f0e-41cb-93a1-bd25020847b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104588346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4104588346
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4148283171
Short name T604
Test name
Test status
Simulation time 39774791 ps
CPU time 0.79 seconds
Started Aug 18 05:49:22 PM PDT 24
Finished Aug 18 05:49:23 PM PDT 24
Peak memory 206028 kb
Host smart-f94a2d47-1052-4317-9d08-c6b59358ab01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148283171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4148283171
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2333394999
Short name T735
Test name
Test status
Simulation time 7491961237 ps
CPU time 15.19 seconds
Started Aug 18 05:49:28 PM PDT 24
Finished Aug 18 05:49:43 PM PDT 24
Peak memory 228716 kb
Host smart-3f4de101-9a99-4de0-bc77-6d189e2c593f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333394999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2333394999
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.802669903
Short name T562
Test name
Test status
Simulation time 30662657 ps
CPU time 0.72 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:49:35 PM PDT 24
Peak memory 205876 kb
Host smart-ebdc7818-59ef-4b71-85da-829f063a77dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802669903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.802669903
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2292403245
Short name T920
Test name
Test status
Simulation time 8067221378 ps
CPU time 18.75 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:49:52 PM PDT 24
Peak memory 232792 kb
Host smart-7084a3a5-978f-47cc-b1c9-9ff5f277a25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292403245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2292403245
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3267558474
Short name T606
Test name
Test status
Simulation time 68579329 ps
CPU time 0.79 seconds
Started Aug 18 05:49:17 PM PDT 24
Finished Aug 18 05:49:18 PM PDT 24
Peak memory 206592 kb
Host smart-89d3832a-94d7-4e27-9779-6adf592a7f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267558474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3267558474
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2472736339
Short name T401
Test name
Test status
Simulation time 17153717908 ps
CPU time 131.36 seconds
Started Aug 18 05:49:23 PM PDT 24
Finished Aug 18 05:51:34 PM PDT 24
Peak memory 249324 kb
Host smart-4089c83f-5ad5-4386-a6b6-38e990b8f08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472736339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2472736339
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.706625178
Short name T778
Test name
Test status
Simulation time 16589541350 ps
CPU time 58.33 seconds
Started Aug 18 05:49:34 PM PDT 24
Finished Aug 18 05:50:33 PM PDT 24
Peak memory 234680 kb
Host smart-4a78718c-7e3a-4339-999e-40409afc1ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706625178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.706625178
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3386143941
Short name T989
Test name
Test status
Simulation time 57947174331 ps
CPU time 145.64 seconds
Started Aug 18 05:49:33 PM PDT 24
Finished Aug 18 05:51:59 PM PDT 24
Peak memory 255092 kb
Host smart-f5609374-f2ee-495e-b0ea-98a3908f16fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386143941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3386143941
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.597870412
Short name T849
Test name
Test status
Simulation time 7783283657 ps
CPU time 62.26 seconds
Started Aug 18 05:49:16 PM PDT 24
Finished Aug 18 05:50:18 PM PDT 24
Peak memory 241092 kb
Host smart-56c4116d-cfe9-4028-8a02-4ef294be3067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597870412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.597870412
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.10018122
Short name T908
Test name
Test status
Simulation time 9477761797 ps
CPU time 16.26 seconds
Started Aug 18 05:49:22 PM PDT 24
Finished Aug 18 05:49:38 PM PDT 24
Peak memory 235788 kb
Host smart-4f08bd48-f921-448c-bb49-b2ab78a84b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10018122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.10018122
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.188657188
Short name T624
Test name
Test status
Simulation time 673540783 ps
CPU time 6.78 seconds
Started Aug 18 05:49:20 PM PDT 24
Finished Aug 18 05:49:27 PM PDT 24
Peak memory 224608 kb
Host smart-a6cd8732-7251-442b-92ee-cd25737ebefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188657188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.188657188
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4158846089
Short name T881
Test name
Test status
Simulation time 1097344751 ps
CPU time 9.47 seconds
Started Aug 18 05:49:28 PM PDT 24
Finished Aug 18 05:49:38 PM PDT 24
Peak memory 224584 kb
Host smart-ee902a7a-f61d-4956-ad59-ce73f56bfcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158846089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4158846089
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.857396930
Short name T509
Test name
Test status
Simulation time 15409258 ps
CPU time 0.98 seconds
Started Aug 18 05:49:24 PM PDT 24
Finished Aug 18 05:49:25 PM PDT 24
Peak memory 217992 kb
Host smart-321c374d-f97a-4dc8-a9c8-ca8f2c63960a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857396930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.857396930
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1338445409
Short name T371
Test name
Test status
Simulation time 6655324887 ps
CPU time 9.9 seconds
Started Aug 18 05:49:23 PM PDT 24
Finished Aug 18 05:49:33 PM PDT 24
Peak memory 249284 kb
Host smart-78b5057c-af2f-42e1-b614-113ceaad16e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338445409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1338445409
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2705134744
Short name T247
Test name
Test status
Simulation time 122509944 ps
CPU time 4.19 seconds
Started Aug 18 05:49:22 PM PDT 24
Finished Aug 18 05:49:27 PM PDT 24
Peak memory 232764 kb
Host smart-d20b2fc3-fb4f-4f19-aaf2-1c7540a774b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705134744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2705134744
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2814773664
Short name T382
Test name
Test status
Simulation time 3070399850 ps
CPU time 14.43 seconds
Started Aug 18 05:49:24 PM PDT 24
Finished Aug 18 05:49:39 PM PDT 24
Peak memory 219056 kb
Host smart-22b08ef7-daa6-4e50-b3ad-a338504a5ee9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2814773664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2814773664
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1001937892
Short name T118
Test name
Test status
Simulation time 67376441344 ps
CPU time 681.13 seconds
Started Aug 18 05:49:26 PM PDT 24
Finished Aug 18 06:00:47 PM PDT 24
Peak memory 281524 kb
Host smart-bcc0401f-f6c5-491f-b88f-6a17f0b99f6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001937892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1001937892
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.300290887
Short name T451
Test name
Test status
Simulation time 6314756065 ps
CPU time 7.47 seconds
Started Aug 18 05:49:18 PM PDT 24
Finished Aug 18 05:49:26 PM PDT 24
Peak memory 216700 kb
Host smart-428a20a9-f45d-4388-9aa4-2332da38bb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300290887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.300290887
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4035383988
Short name T904
Test name
Test status
Simulation time 6614651935 ps
CPU time 15.64 seconds
Started Aug 18 05:49:18 PM PDT 24
Finished Aug 18 05:49:34 PM PDT 24
Peak memory 216528 kb
Host smart-bcbf71c2-ca8a-40b8-9a76-9f5b66ccae79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035383988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4035383988
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4029606788
Short name T980
Test name
Test status
Simulation time 271406936 ps
CPU time 2.11 seconds
Started Aug 18 05:49:23 PM PDT 24
Finished Aug 18 05:49:25 PM PDT 24
Peak memory 216428 kb
Host smart-f65ec7e6-4cd5-47de-9e0d-614450a1ba48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029606788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4029606788
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2247282621
Short name T307
Test name
Test status
Simulation time 242752563 ps
CPU time 0.91 seconds
Started Aug 18 05:49:20 PM PDT 24
Finished Aug 18 05:49:21 PM PDT 24
Peak memory 206100 kb
Host smart-13cfded5-ce42-4902-b6f9-28e252332293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247282621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2247282621
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3885772084
Short name T551
Test name
Test status
Simulation time 1494514088 ps
CPU time 3.2 seconds
Started Aug 18 05:49:27 PM PDT 24
Finished Aug 18 05:49:30 PM PDT 24
Peak memory 232796 kb
Host smart-d05e01de-5af5-435f-a17b-6a0ffd885a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885772084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3885772084
Directory /workspace/9.spi_device_upload/latest
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